Internet design method for AI processor hardware component and medium

Abstract

The invention discloses an Internet design method for AI processor hardware components and a medium. The method comprises the following steps: acquiring a logic routing data path in an internet design of an AI processor hardware component; determining a target data path set through a preset reachable path generation method according to the logic routing data path; generating a path solving mathematical model through a preset joint constraint condition in combination with the target data path set, and solving the path solving mathematical model to obtain an optimized data path set; and feeding back the optimized data path set, and completing the internet design of the hardware component of the AI processor according to the optimized data path set. The problem that an AI processor hardware component interconnection network design method mainly depends on the design experience of an architector is solved, the efficiency and accuracy of the interconnection network design of the hardware component are improved, the manpower cost and material resources are saved, and the flexibility of the interconnection network design of the hardware component is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of processor hardware component processing, and in particular, to an interconnection network design method and medium for AI processor hardware components. Background Art

[0002] With the rapid development of artificial intelligence technology, the number of parameters in deep learning models has increased exponentially, posing higher requirements for the computing power of AI (Artificial Intelligence) processors. That is, through the upgrade of semiconductor processes, more and more computing cores are integrated inside a single processor to achieve greater computing power density and lower energy consumption in order to obtain better computing energy efficiency. In the face of the exponential increase in the number of hardware components inside AI processors, the interconnection requirements between hardware components have increased exponentially. However, it is obviously impossible and unreasonable to establish a full interconnection channel between all hardware components. Therefore, for the interconnection of the system architecture, it is necessary to consider the optimal physical connection and routing strategies to achieve the design goal of meeting the best interconnection performance with the least resources.

[0003] In the process of implementing the present invention, the inventors found that the prior art has the following defects: Currently, the design method of the interconnection network for AI processor hardware components mainly relies on the design experience of architects. The architects define the interconnection rules between hardware components based on past design practices and subjective judgments. According to the project experience of designing multiple generations of processors, to ensure the stability and reliability of the interconnection architecture, a large amount of manpower, equipment, and time are required to iteratively generate a stagewise mature solution, and this iterative improvement will continue until before tape-out. The disadvantage of this method is that it overly relies on the personal experience and intuition of architects. Moreover, when facing tasks that exceed the complexity boundary of human execution, it becomes increasingly difficult for humans to complete the processor tape-out without errors within the limited project execution time. Once there are shortfalls or omissions in the performance of the interconnection system, it will lead to the failure of the processor tape-out, wasting the costs of manpower and material resources. Summary of the Invention

[0004] The present invention provides an interconnection network design method and medium for AI processor hardware components to improve the efficiency and accuracy of the interconnection network design of hardware components, saving manpower costs and material resources.

[0005] According to one aspect of the present invention, there is provided an interconnection network design method for AI processor hardware components, which includes:

[0006] In the interconnection network design of AI processor hardware components, obtain a logical routing data path; wherein, the logical routing data path is the only routing data path between MST and SLV;

[0007] Among them, in the interconnection network design of AI processor hardware components, it includes at least one MST, at least one SLV, and at least one intermediate node; where MST is the initiator of data transfer requests between hardware components; SLV is the server of data transfer requests between hardware components, and MST reaches SLV through one or more intermediate nodes to perform data transfer;

[0008] According to the logical routing data path, through a preset reachable path generation method, a target data path set is determined;

[0009] Through preset joint constraint conditions, combined with the target data path set, a path-solving mathematical model is generated, and the path-solving mathematical model is solved to obtain an optimized data path set;

[0010] The optimized data path set is fed back, and the interconnection network design of AI processor hardware components is completed according to the optimized data path set.

[0011] According to another aspect of the present invention, an interconnection network design device for AI processor hardware components is provided, which includes:

[0012] A logical routing data path acquisition module, used to acquire the logical routing data path in the interconnection network design of AI processor hardware components;

[0013] Among them, the logical routing data path is the only routing data path between MST and SLV;

[0014] Among them, in the interconnection network design of AI processor hardware components, it includes at least one MST, at least one SLV, and at least one intermediate node; where MST is the initiator of data transfer requests between hardware components; SLV is the server of data transfer requests between hardware components, and MST reaches SLV through one or more intermediate nodes to perform data transfer;

[0015] A target data path set determination module, used to determine a target data path set according to the logical routing data path through a preset reachable path generation method;

[0016] An optimized data path set determination module, used to generate a path-solving mathematical model through preset joint constraint conditions, combined with the target data path set, and solve the path-solving mathematical model to obtain an optimized data path set;

[0017] An optimized data path set feedback module, used to feed back the optimized data path set and complete the interconnection network design of AI processor hardware components according to the optimized data path set.

[0018] According to another aspect of the present invention, there is provided an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the method for designing an interconnection network for AI processor hardware components according to any embodiment of the present invention is implemented.

[0019] According to another aspect of the present invention, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the method for designing an interconnection network for AI processor hardware components according to any embodiment of the present invention when executed.

[0020] In the technical solution of the embodiment of the present invention, in the design of the interconnection network of AI processor hardware components, logical routing data paths are obtained; according to the logical routing data paths, a target data path set is determined by a pre-set reachable path generation method; a path-solving mathematical model is generated by combining the target data path set with pre-set joint constraint conditions, and the path-solving mathematical model is solved to obtain an optimized data path set; the optimized data path set is fed back, and the interconnection network design of AI processor hardware components is completed according to the optimized data path set. The problem that the method for designing the interconnection network of AI processor hardware components mainly depends on the design experience of architects is solved, the efficiency and accuracy of the interconnection network design of hardware components are improved, the labor cost and material resources are saved, and the flexibility of the interconnection network design of hardware components is improved.

[0021] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings without creative efforts based on these drawings.

[0023] Figure 1 is a flowchart of a method for designing an interconnection network for AI processor hardware components according to Embodiment 1 of the present invention;

[0024] Figure 2 is a detailed flowchart of a method for designing an interconnection network for AI processor hardware components according to Embodiment 2 of the present invention;

[0025] Figure 3It is a schematic structural diagram of an interconnection network design device for AI processor hardware components provided in Embodiment 3 of the present invention;

[0026] Figure 4 It is a schematic structural diagram of an electronic device provided in Embodiment 4 of the present invention;

[0027] Figure 5 It is a specific schematic structural diagram of the interconnection network architecture in the method provided in Embodiment 1 of the present invention. Detailed implementation manners

[0028] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0029] It should be noted that the terms "target", "current", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily need to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0030] Embodiment 1

[0031] Figure 1 This is a flowchart of a method for designing an interconnection network for AI processor hardware components provided in Embodiment 1 of the present invention. This embodiment is applicable to the case where the AI processor hardware components are interconnected through the interconnection network design. This method can be executed by an interconnection network design device for AI processor hardware components, and the interconnection network design device for AI processor hardware components can be implemented in the form of hardware and / or software.

[0032] Correspondingly, as Figure 1 shown, the method includes:

[0033] S110. In the interconnection network design of AI processor hardware components, obtain the logical routing data path.

[0034] Among them, the logical routing data path is the only routing data path between the MST and the SLV.

[0035] Among them, in the interconnection network design of the AI processor hardware components, it includes at least one MST, at least one SLV, and at least one intermediate node; among them, the MST is the initiator of the data transfer request between the hardware components; the SLV is the server of the data transfer request between the hardware components, and the MST reaches the SLV through one or more intermediate nodes to perform data transfer.

[0036] In this embodiment, when the request sent from the MST accesses the SLV, it will pass through one or more intermediate nodes. Among them, the intermediate node is the node of the data transfer path. Each intermediate node has the function of sending the request or reply received from one port out from another port to realize routing. Multiple intermediate nodes are combined to form a node cluster (NodeCluster, NC), forming an intermediate layer network that works together.

[0037] In the hardware architecture, when the request sent from the MST accesses the SLV, it will pass through a common node cluster and finally reach the slave device. The node cluster contains all the intermediate nodes participating in the data transfer path, and the specific definition is: , where represents the th intermediate node, is the total number of nodes. The role of the node cluster is to centrally manage and optimize the intermediate node resources in the data transfer path to ensure that the data request can be efficiently and reliably transmitted to the target slave device.

[0038] In this embodiment, an accessible data transfer path from the MST to the SLV in the hardware architecture is the data path. The data path is defined by the physical connection definition and the logical routing definition together.

[0039] Specifically, for the physical connection definition, it defines the connection relationships of all physical entities in the system, specifically including: the entity category is the complete set of all MSTs, SLVs, and intermediate nodes; the link specification is the explicit declaration of the links allowed for communication between all entities.

[0040] Specifically, the logical routing definition is based on the physical connection definition, and sets a unique and definite data path for each pair of MST and SLV, which comes from the data path expression file, that is, the interconnection definition. Specifically, for each and each , there is a unique routing data path, that is, the logical routing data path. For example: is and The only routing data path between them. This ensures the uniqueness and determinacy of the data path, providing a clear basis for the subsequent optimization of the interconnection network design.

[0041] In the actual interconnection network architecture, it includes 16 MSTs, 24 SLVs, and 180 intermediate nodes. Due to the complexity of the actual interconnection network architecture, it is difficult to completely describe the interconnection details. This article can demonstrate the specific optimization process through the following example.

[0042] Exemplarily, assume that the interconnection network architecture includes 2 MSTs (M1 and M2), 3 SLVs (S1, S2, and S3), and 2 intermediate nodes (Node1, Node2). The link relationships between all nodes, that is, the specific logical routing data paths are: .

[0043] S120. According to the logical routing data path, through a preset reachable path generation method, determine the target data path set.

[0044] Among them, the reachable path generation method can be a method for generating all reachable paths between different MSTs and SLVs. The target data path set can be a set containing multiple reachable paths.

[0045] Optionally, the step of determining the target data path set according to the logical routing data path through a preset reachable path generation method includes: screening the logical routing data path to determine the target logical routing data path to be optimized; transforming the target logical routing data path through a preset hardware component interconnection network graph structure transformation method to obtain the target logical routing data path graph structure; and determining the target data path set according to the target logical routing data path graph structure through a preset reachable path generation method.

[0046] Among them, the hardware component interconnection network graph structure transformation method can be a graph structure generated according to the target logical routing data path, that is, it can generate the target logical routing data path graph structure according to the logical routing data path. Specifically, Figure 5 This is the specific structure schematic diagram of the interconnection network architecture in the first embodiment of the present invention, which is generated according to the logical routing data path.

[0047] Optionally, according to the target logical routing data path graph structure, a target data path set is determined through a preset reachable path generation method, including: through the preset reachable path generation method, traversing the target logical routing data path graph structure to obtain all reachable paths from each MST through different intermediate nodes to each SLV, and obtaining each of the reachable paths; wherein, the target logical routing data path graph includes a directional connection relationship path graph of each MST passing through different intermediate nodes to the corresponding SLV; combining each of the reachable paths to determine a target data path set.

[0048] In this embodiment, after generating the target logical routing data path graph structure, it is necessary to traverse the target logical routing data path graph structure to obtain all reachable paths from each MST through different intermediate nodes to each SLV, obtain each reachable path, and further obtain a target data path set.

[0049] Continuing the previous example, assume the obtained reachable paths include: , that is, a target data path set is obtained.

[0050] S130. Generate a path solution mathematical model by combining the target data path set through preset joint constraint conditions, and solve the path solution mathematical model to obtain an optimized data path set.

[0051] Among them, the joint constraint conditions may include link capacity constraint, path selection constraint, and link flow constraint.

[0052] Among them, the link capacity is the maximum value of the number of times a link can be selected or passed through; the link flow is the number of times a link can be selected or passed through; wherein, the link capacity constraint is that the flow of each link cannot exceed the link capacity; the path selection constraint is that the number of path selections is restricted in the reachable paths from each MST to the SLV; the link flow constraint is the relationship between the link flow and the number of paths selecting this link.

[0053] In this embodiment, the target data path set can be constrained according to the joint constraint conditions. The constraints can be set as follows: the flow of each link cannot exceed the link capacity; the number of path selections in the reachable paths from each MST to the SLV is 1; the link flow is equal to the number of paths selecting this link. Further, a path solution mathematical model is obtained according to the joint constraint conditions, and then solved to obtain an optimized data path set.

[0054] The advantages of such a setting are as follows: it can make full use of the link capacity, minimize the number of selected links, and shorten the length of the data path as much as possible, so as to better meet the requirements of data path optimization and improve the flexibility of data path optimization.

[0055] S140. Feedback the optimized data path set and implement the interconnection network design of the AI processor hardware components according to the optimized data path set.

[0056] Optionally, the feedback of the optimized data path set and the implementation of the interconnection network design of the AI processor hardware components according to the optimized data path set include: deleting the unnecessary paths in the direction connection relationship path diagram corresponding to each reachable path according to the received optimized data path set to obtain an optimized direction connection relationship path diagram; and completing the interconnection network design of the AI processor hardware components according to the optimized direction connection relationship path diagram.

[0057] Among them, the direction connection relationship path diagram can be a path diagram obtained by combining the reachable paths in the target data path set. The paths in the optimized data path set are included in the reachable paths corresponding to the target data path set.

[0058] In this embodiment, after obtaining the optimized data path set, the paths in the optimized data path set can be matched with the paths in the direction connection relationship path diagram. If the match is successful, the path is retained; if the match is unsuccessful, the path is deleted.

[0059] Further, after traversing and deleting the unnecessary paths, an optimized direction connection relationship path diagram can be obtained, and the interconnection network design of the AI processor hardware components can be completed according to the optimized direction connection relationship path diagram.

[0060] The advantage of such a setting is that the optimized data path can be more intuitively displayed through the optimized direction connection relationship path diagram, which is more convenient for implementing the interconnection network design of the AI processor hardware components.

[0061] In the technical solution of the embodiment of the present invention, in the interconnection network design of AI processor hardware components, logical routing data paths are obtained; according to the logical routing data paths, a target data path set is determined by a preset reachable path generation method; a path solution mathematical model is generated by combining the target data path set with preset joint constraint conditions, and the path solution mathematical model is solved to obtain an optimized data path set; the optimized data path set is fed back, and the interconnection network design of AI processor hardware components is completed according to the optimized data path set. The problem that the interconnection network design method of AI processor hardware components mainly depends on the design experience of architects is solved, the efficiency and accuracy of the interconnection network design of hardware components are improved, the labor cost and material resources are saved, and the flexibility of the interconnection network design of hardware components is improved.

[0062] Embodiment 2

[0063] Figure 2 A detailed flowchart of an interconnection network design method for AI processor hardware components is provided for the second embodiment of the present invention. This embodiment is refined based on the above embodiments. In this embodiment, the process of generating a path solution mathematical model by combining the target data path set with preset joint constraint conditions and solving the path solution mathematical model to obtain an optimized data path set is further refined.

[0064] Correspondingly, as Figure 2 shown, the method includes:

[0065] S210. In the interconnection network design of AI processor hardware components, obtain logical routing data paths.

[0066] S220. According to the logical routing data paths, determine a target data path set by a preset reachable path generation method.

[0067] S230. Generate a path solution mathematical model by combining the target data path set with link capacity constraints, path selection constraints, and link flow constraints.

[0068] In this embodiment, specifically, the path solution mathematical model generated by combining the target data path set with link capacity constraints, path selection constraints, and link flow constraints is: ; where i represents the intermediate node i on the link; j represents the intermediate node j on the link; represents the traffic from the intermediate node i to the intermediate node j on the link; represents the indicator variable indicating whether the link from the intermediate node i to the intermediate node j is selected; represents the total number of SLVs; An influence parameter indicating the adjustment of the number of selected links; An influence parameter indicating the adjustment of the data path length; Indicates the data path; An indicator variable indicating whether the data path is selected; Indicates the length of the data path; M represents the set of MSTs; S represents the set of SLVs; m represents an MST in the set of MSTs; s represents an SLV in the set of SLVs; Indicates from to a complete path; Indicates from to all complete paths; Indicates a path passing through the link starting from the intermediate node i and ending at the intermediate node j; b represents the size of the number of path selections in the reachable paths from each MST to the SLV; Indicates the number of path selections in the reachable paths from each MST to the SLV.

[0069] Among them, for the meaning is: the link traffic is equal to the number of paths selecting this link, that is, the number of times the link is selected is the sum of the number of paths passing through this link among all . For the meaning is: for any path from to there is exactly one.

[0070] Continuing the previous example, for the link capacity constraint, it can be set that the traffic of each link cannot exceed the link capacity. For the path selection constraint, it can be set that the number of path selections in the reachable paths from each MST to the SLV is 1. For the link traffic constraint, it can be set that the link traffic is equal to the number of paths selecting this link.

[0071] Furthermore, the maximum capacity of each link can be defined as the number of SLVs. It can be set that the total number of SLVs is 3, that is, the link capacity is 3. Correspondingly, through the link capacity constraint, path selection constraint, and link traffic constraint, combined with the target data path set, a path solution mathematical model is generated as: .

[0072] S240. By using a pre-set mixed integer optimizer to solve the path solution mathematical model, an optimized data path set is obtained.

[0073] Among them, the mixed integer optimizer is an optimizer that can perform solution processing on the path solution mathematical model.

[0074] In this embodiment, it is possible to perform a solution process to obtain an optimized data path set corresponding to the jointly constrained conditions set above. Additionally, different constraint condition setting operations can be performed on the jointly constrained conditions to generate different optimized data path sets.

[0075] S250. Feed back the optimized data path set and implement the interconnection network design of the AI processor hardware components according to the optimized data path set.

[0076] Continuing from the previous example, in the actual interconnection network architecture, there are 16 MSTs, 24 SLVs, and 180 intermediate nodes. Through the above interconnection network design method, the average link utilization rate can be improved, the physical resource scheduling efficiency can be significantly optimized; the average path length is also optimized, the number of active links is reduced, and the number of intermediate nodes is synchronously reduced, achieving an intensive deployment of hardware resources.

[0077] The technical solution of the embodiment of the present invention, in the interconnection network design of the AI processor hardware components, obtains the logical routing data path; according to the logical routing data path, determines a target data path set through a pre-set reachable path generation method; generates a path solution mathematical model through link capacity constraints, path selection constraints, and link flow constraints, combined with the target data path set; solves the path solution mathematical model through a pre-set mixed integer optimizer to obtain an optimized data path set; feeds back the optimized data path set and implements the interconnection network design of the AI processor hardware components according to the optimized data path set. It improves the average link utilization rate, significantly optimizes the physical resource scheduling efficiency, achieves an intensive deployment of hardware resources, improves the efficiency and accuracy of the interconnection network design of the hardware components, and saves labor costs and material resources.

[0078] Embodiment III

[0079] Figure 3 It is a schematic structural diagram of an interconnection network design device for AI processor hardware components provided in Embodiment III of the present invention. The interconnection network design device for AI processor hardware components provided in this embodiment can be implemented through software and / or hardware, and can be configured in a terminal device or a server to implement an interconnection network design method for AI processor hardware components in the embodiment of the present invention. As Figure 3 shown, the device includes: a logical routing data path acquisition module 310, a target data path set determination module 320, an optimized data path set determination module 330, and an optimized data path set feedback module 340.

[0080] Among them, the logical routing data path acquisition module 310 is used to acquire the logical routing data path in the interconnection network design of the AI processor hardware components;

[0081] Among them, the logical routing data path is the only routing data path between the MST and the SLV;

[0082] Among them, in the interconnection network design of the AI processor hardware components, it includes at least one MST, at least one SLV, and at least one intermediate node; among them, the MST is the initiator of the data transfer request between the hardware components; the SLV is the server of the data transfer request between the hardware components, and the MST reaches the SLV through one or more intermediate nodes to perform data transfer;

[0083] The target data path set determination module 320 is used to determine the target data path set according to the logical routing data path through a preset reachable path generation method;

[0084] The optimized data path set determination module 330 is used to generate a path solution mathematical model by combining the target data path set with preset joint constraint conditions, and solve the path solution mathematical model to obtain the optimized data path set;

[0085] The optimized data path set feedback module 340 is used to feedback the optimized data path set and complete the interconnection network design of the AI processor hardware components according to the optimized data path set.

[0086] The technical solution of the embodiment of the present invention is to acquire the logical routing data path in the interconnection network design of the AI processor hardware components; determine the target data path set according to the logical routing data path through a preset reachable path generation method; generate a path solution mathematical model by combining the target data path set with preset joint constraint conditions, and solve the path solution mathematical model to obtain the optimized data path set; feedback the optimized data path set and complete the interconnection network design of the AI processor hardware components according to the optimized data path set. It solves the problem that the interconnection network design method of the AI processor hardware components mainly depends on the design experience of the architect, improves the efficiency and accuracy of the interconnection network design of the hardware components, saves labor costs and material resources, and improves the flexibility of the interconnection network design of the hardware components.

[0087] Based on the above embodiments, the target data path set determination module 320 may specifically include: a target logical routing data path determination unit, configured to determine a target logical routing data path to be optimized by screening the logical routing data path; a target logical routing data path graph structure determination unit, configured to transform the target logical routing data path through a pre-set hardware component interconnection network graph structure transformation method to obtain a target logical routing data path graph structure; a target data path set determination unit, configured to determine a target data path set according to the target logical routing data path graph structure through a pre-set reachable path generation method.

[0088] Based on the above embodiments, the target data path set determination unit may specifically be configured to: traverse the target logical routing data path graph structure through a pre-set reachable path generation method, obtain all reachable paths from each MST passing through different intermediate nodes to each SLV, and obtain each of the reachable paths; wherein, the target logical routing data path graph includes a directional connection relationship path graph of each MST passing through different intermediate nodes to the corresponding SLV; combine each of the reachable paths to determine a target data path set.

[0089] Based on the above embodiments, the joint constraint conditions include: link capacity constraint, path selection constraint, and link traffic constraint; wherein, the link capacity is the maximum value of the number of times a link can be selected or passed through; the link traffic is the number of times a link can be selected or passed through; wherein, the link capacity constraint is that the traffic of each link cannot exceed the link capacity; the path selection constraint is that the number of path selections is constrained in the reachable paths from each MST to the SLV; the link traffic constraint is the relationship between the link traffic and the number of paths selecting the link.

[0090] Based on the above embodiments, the optimized data path set determination module 330 may specifically be configured to:

[0091] Generate a path solution mathematical model by combining the link capacity constraint, path selection constraint, and link traffic constraint with the target data path set as ;

[0092] wherein, i represents the intermediate node i on the link; j represents the intermediate node j on the link; represents the traffic from the intermediate node i to the intermediate node j on the link; represents an indicator variable indicating whether the link from the intermediate node i to the intermediate node j is selected; represents the total number of SLVs; represents an influence parameter for adjusting the number of selected links; An influence parameter indicating the adjustment of the data path length; Indicates the data path; An indication variable indicating whether the data path is selected; Indicates the length of the data path; M represents the set of MSTs; S represents the set of SLVs; m represents an MST in the set of MSTs; S represents an SLV in the set of SLVs; Indicates from to A complete path; Indicates from to All complete paths; Indicates a path passing through a link starting from intermediate node i and ending at intermediate node j; b represents the magnitude of the number of path selections in the reachable paths from each MST to SLV; Indicates the number of path selections in the reachable paths from each MST to SLV.

[0093] Based on the above embodiments, the optimized data path set determination module 330 may specifically be used to: solve the path solution mathematical model through a pre-set mixed integer optimizer to obtain an optimized data path set.

[0094] Based on the above embodiments, the optimized data path set feedback module 340 may specifically be used to: delete the unnecessary paths in the direction connection relationship path diagrams corresponding to the reachable paths according to the received optimized data path set to obtain an optimized direction connection relationship path diagram; complete the interconnection network design of the AI processor hardware components according to the optimized direction connection relationship path diagram.

[0095] The interconnection network design device for AI processor hardware components provided by the embodiments of the present invention can execute the interconnection network design method for AI processor hardware components provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method.

[0096] Embodiment Four

[0097] Figure 4FIG. shows a schematic structural diagram of an electronic device 10 that can be used to implement Embodiment 4 of the present invention. The electronic device is intended to represent various forms of digital computers, such as, for example, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, for example, personal digital processors, cellular telephones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0098] As Figure 4 shown, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc. The memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0099] Multiple components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0100] The processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the interconnection network design method for AI processor hardware components.

[0101] In some embodiments, a method for designing an interconnection network for AI processor hardware components can be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by the processor 11, one or more steps of the above-described method for designing an interconnection network for AI processor hardware components can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the method for designing an interconnection network for AI processor hardware components by any other suitable means (e.g., by means of firmware).

[0102] The method includes: in the design of the interconnection network of AI processor hardware components, obtaining a logical routing data path; wherein, the logical routing data path is the only routing data path between the MST and the SLV; wherein, in the design of the interconnection network of AI processor hardware components, it includes at least one MST, at least one SLV, and at least one intermediate node; wherein, the MST is the initiator of the data transfer request between hardware components; the SLV is the server of the data transfer request between hardware components, and the MST reaches the SLV through one or more intermediate nodes to perform data transfer; according to the logical routing data path, by a preset reachable path generation method, determining a set of target data paths; by preset combined constraint conditions, combining the set of target data paths, generating a path-solving mathematical model, and solving the path-solving mathematical model to obtain an optimized set of data paths; feeding back the optimized set of data paths, and implementing the design of the interconnection network of AI processor hardware components according to the optimized set of data paths.

[0103] The various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a dedicated or general-purpose programmable processor, and can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0104] A computer program for implementing the method of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer programs are executed by the processor, the functions / operations specified in the flowchart and / or block diagram are implemented. The computer programs can be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0105] In the context of the present invention, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0106] In order to provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0107] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), blockchain network, and the Internet.

[0108] A computing system can include a client and a server. The client and the server are generally remote from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, and solves the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services.

[0109] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0110] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

[0111] Example Five

[0112] Embodiment 5 of the present invention further provides a computer-readable storage medium, and the computer-readable instructions are used to execute a method for designing an interconnection network for AI processor hardware components when executed by a computer processor. The method includes: in the design of the interconnection network for AI processor hardware components, obtaining a logical routing data path; wherein, the logical routing data path is the only routing data path between the MST and the SLV; wherein, in the design of the interconnection network for AI processor hardware components, it includes at least one MST, at least one SLV, and at least one intermediate node; wherein, the MST is the initiator of the data transfer request between hardware components; the SLV is the server of the data transfer request between hardware components, and the MST reaches the SLV through one or more intermediate nodes to perform data transfer; according to the logical routing data path, by a pre-set reachable path generation method, determining a set of target data paths; by a pre-set combined constraint condition, combining the set of target data paths, generating a path-solving mathematical model, and solving the path-solving mathematical model to obtain an optimized set of data paths; feeding back the optimized set of data paths, and implementing the design of the interconnection network for AI processor hardware components according to the optimized set of data paths.

[0113] Of course, the computer-executable instructions of a computer-readable storage medium provided by the embodiments of the present invention are not limited to the method operations described above, and can also execute related operations in the design of the interconnection network for AI processor hardware components provided by any embodiment of the present invention.

[0114] Through the above description of the embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software and necessary general hardware. Of course, it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as a floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk, or optical disc of a computer, etc., including several instructions for causing a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0115] It should be noted that in the above embodiments of the interconnection network design for the hardware components of the AI processor, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of mutual distinction and do not limit the protection scope of the present invention.

[0116] The above specific implementation manners do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for designing an interconnection network for AI processor hardware components, characterized in that Including: In the interconnection network design of AI processor hardware components, obtain the logical routing data path; wherein, the logical routing data path is the only routing data path between MST and SLV; Wherein, in the interconnection network design of AI processor hardware components, it includes at least one MST, at least one SLV and at least one intermediate node; wherein, MST is the initiator of data transfer requests between hardware components; SLV is the server of data transfer requests between hardware components, and MST reaches SLV through one or more intermediate nodes to perform data transfer; According to the logical routing data path, determine the target data path set through a preset reachable path generation method; Through preset joint constraint conditions, combine with the target data path set to generate a path solution mathematical model, and solve the path solution mathematical model to obtain an optimized data path set; Feedback the optimized data path set, and implement the interconnection network design of AI processor hardware components according to the optimized data path set.

2. The method according to claim 1, characterized in that, The step of determining the target data path set through a preset reachable path generation method according to the logical routing data path includes: Determine the target logical routing data path to be optimized by screening the logical routing data path; Transform the target logical routing data path through a preset hardware component interconnection network graph structure transformation method to obtain the target logical routing data path graph structure; According to the target logical routing data path graph structure, determine the target data path set through a preset reachable path generation method.

3. The method according to claim 2, characterized in that, The step of determining the target data path set through a preset reachable path generation method according to the target logical routing data path graph structure includes: Traverse the target logical routing data path graph structure through a preset reachable path generation method to obtain all reachable paths from each MST passing through different intermediate nodes to each SLV, and obtain each of the reachable paths; Wherein, the target logical routing data path graph includes a direction connection relationship path graph of each MST passing through different intermediate nodes to the corresponding SLV; Combine each of the reachable paths to determine the target data path set.

4. The method according to claim 3, wherein The joint constraint conditions include: link capacity constraint, path selection constraint and link flow constraint; Wherein, the link capacity is the maximum value of the number of times a link can be selected or passed through; the link flow is the number of times a link can be selected or passed through; Wherein, the link capacity constraint is that the flow of each link cannot exceed the link capacity; the path selection constraint is that the number of path selections is restricted in the reachable paths from each MST to SLV; the link flow constraint is the relationship between the link flow and the number of paths selecting this link.

5. The method according to claim 4, characterized in that, The step of generating a path solution mathematical model by combining with the target data path set through preset joint constraint conditions includes: By combining the link capacity constraint, path selection constraint, and link flow constraint with the target data path set, a mathematical model for path solving is generated as ; Among them, i represents the intermediate node i on the link; j represents the intermediate node j on the link; represents the traffic from the intermediate node i to the intermediate node j on the link; represents an indicator variable indicating whether the link from the intermediate node i to the intermediate node j is selected; represents the total number of SLVs; represents the influence parameter for adjusting the number of selected links; represents the influence parameter for adjusting the length of the data path; represents the data path; represents an indicator variable indicating whether the data path is selected; represents the length of the data path; M represents the set of MSTs; S represents the set of SLVs; m represents an MST in the set of MSTs; s represents an SLV in the set of SLVs; represents from to a complete path; represents from to all complete paths; represents a path passing through the link starting from the intermediate node i and ending at the intermediate node j; b represents the magnitude of the number of path selections in the reachable paths from each MST to the SLV; represents the number of path selections in the reachable paths from each MST to the SLV.

6. The method according to claim 5, wherein The step of solving the path solution mathematical model to obtain an optimized data path set includes: Solve the mathematical model of the path through a pre-set mixed integer optimizer to obtain an optimized data path set.

7. The method according to claim 6, wherein Feedback the optimized data path set and implement the interconnection network design of the AI processor hardware components according to the optimized data path set, including: Delete the unnecessary paths in the direction connection relationship path diagram corresponding to each reachable path according to the received optimized data path set to obtain an optimized direction connection relationship path diagram; Complete the interconnection network design of the AI processor hardware components according to the optimized direction connection relationship path diagram.

8. An interconnection network design device for AI processor hardware components, characterized in that Including: A logical routing data path acquisition module, used to acquire a logical routing data path in the interconnection network design of the AI processor hardware components; Wherein, the logical routing data path is the only routing data path between the MST and the SLV; Wherein, in the interconnection network design of the AI processor hardware components, it includes at least one MST, at least one SLV and at least one intermediate node; wherein, the MST is the initiator of the data transfer request between the hardware components; the SLV is the server of the data transfer request between the hardware components, and the MST reaches the SLV through one or more intermediate nodes to perform data transfer; A target data path set determination module, used to determine a target data path set according to the logical routing data path through a preset reachable path generation method; An optimized data path set determination module, used to generate a path solution mathematical model by combining a preset joint constraint condition with the target data path set, and solve the path solution mathematical model to obtain an optimized data path set; An optimized data path set feedback module, used to feedback the optimized data path set and implement the interconnection network design of the AI processor hardware components according to the optimized data path set.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements an interconnection network design method for AI processor hardware components as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the processor to implement an interconnection network design method for AI processor hardware components as described in any one of claims 1-7 when executed.

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