An interconnection network design method and medium for AI processor hardware components

Abstract

The present invention discloses an interconnection network design method and medium for AI processor hardware components. By obtaining a logical routing data path in the interconnection network design of the AI processor hardware components; determining a target data path set based on the logical routing data path through a pre-set reachable path generation method; generating a path solving mathematical model based on the pre-set joint constraint conditions and the target data path set, and solving the path solving mathematical model to obtain an optimized data path set; feeding back the optimized data path set, and completing the interconnection network design of the AI processor hardware components based on the optimized data path set. This solves the problem that the interconnection network design method of the AI processor hardware components mainly relies on the design experience of the architect, improves the efficiency and accuracy of the interconnection network design of the hardware components, saves labor costs and material resources, and improves the flexibility of the interconnection network design of the hardware components.

Description

Technical Field

[0001] The present invention relates to the field of processor hardware component processing technology, and in particular to an interconnection network design method and medium for AI processor hardware components. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, the number of parameters in deep learning models is growing exponentially, placing higher demands on the computing power of AI (artificial intelligence) processors. This requires integrating more and more computing cores within a single processor through semiconductor process upgrades, achieving greater computing density and lower energy consumption for better computing efficiency. Faced with the surge in the number of hardware components within AI processors, the demand for interconnection between these components is increasing exponentially. Establishing fully interconnected channels between all hardware components is clearly impossible and irrational. This necessitates considering optimal physical connections and routing strategies for system architecture interconnection to achieve the design goal of achieving the best possible interconnection performance with the least resources.

[0003] In the process of realizing the present invention, the inventors discovered that the existing technology has the following defects: the current industry's method for designing interconnection networks for AI processor hardware components mainly relies on the design experience of architects, who define the interconnection rules between hardware components based on previous design practices and subjective judgment. According to the project experience of multiple generations of processor designs, the stability and reliability of the interconnection architecture requires a large amount of manpower, equipment, and time to iteratively generate phased mature solutions. This iterative improvement will continue until tape-out. The disadvantage of this method is that it over-relies on the architect's personal experience and intuition. Moreover, when faced with task execution complexity exceeding the human limit, it becomes increasingly difficult for humans to complete processor tape-out with zero errors within the limited project execution time. Once the performance of the interconnection system has shortcomings or omissions, the processor tape-out will fail, wasting manpower and material resources. Summary of the Invention

[0004] The present invention provides an interconnection network design method and medium for AI processor hardware components, so as to improve the efficiency and accuracy of the interconnection network design of hardware components and save manpower costs and material resources.

[0005] According to one aspect of the present invention, a method for designing an interconnection network for AI processor hardware components is provided, comprising:

[0006] In an interconnection network design of AI processor hardware components, a logical routing data path is obtained; wherein the logical routing data path is a unique routing data path between the MST and the SLV;

[0007] The interconnection network design of AI processor hardware components includes at least one MST, at least one SLV, and at least one intermediate node. The MST is the initiator of data transfer requests between hardware components; the SLV is the service provider of data transfer requests between hardware components. The MST reaches the SLV through one or more intermediate nodes to perform data transfer.

[0008] According to the logical routing data path, a target data path set is determined by a preset reachable path generation method;

[0009] By combining the preset joint constraint conditions with the target data path set, a path solving mathematical model is generated, and the path solving mathematical model is solved to obtain an optimized data path set;

[0010] The optimized data path set is fed back, and the interconnection network design of the AI processor hardware components is completed based on the optimized data path set.

[0011] According to another aspect of the present invention, there is provided an interconnection network design apparatus for AI processor hardware components, comprising:

[0012] A logical routing data path acquisition module is used to obtain the logical routing data path in the interconnection network design of the AI processor hardware components;

[0013] Wherein, the logical routing data path is the only routing data path between the MST and the SLV;

[0014] The interconnection network design of AI processor hardware components includes at least one MST, at least one SLV, and at least one intermediate node. The MST is the initiator of data transfer requests between hardware components; the SLV is the service provider of data transfer requests between hardware components. The MST reaches the SLV through one or more intermediate nodes to perform data transfer.

[0015] a target data path set determination module, configured to determine a target data path set according to the logical routing data path and by a preset reachable path generation method;

[0016] An optimized data path set determination module is used to generate a path solving mathematical model based on pre-set joint constraints and a target data path set, and solve the path solving mathematical model to obtain an optimized data path set;

[0017] The optimized data path set feedback module is used to provide feedback on the optimized data path set and complete the interconnection network design of the AI processor hardware components based on the optimized data path set.

[0018] According to another aspect of the present invention, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the method for designing an interconnection network for AI processor hardware components as described in any embodiment of the present invention is implemented.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the interconnection network design method for AI processor hardware components described in any embodiment of the present invention when executed.

[0020] The technical solution of the embodiment of the present invention is to obtain a logical routing data path in the interconnection network design of the AI processor hardware component; determine a target data path set based on the logical routing data path through a pre-set reachable path generation method; generate a path solving mathematical model based on the pre-set joint constraint conditions and the target data path set, and solve the path solving mathematical model to obtain an optimized data path set; provide feedback on the optimized data path set, and complete the interconnection network design of the AI processor hardware component based on the optimized data path set. This solves the problem that the interconnection network design method of the AI processor hardware component mainly relies on the design experience of the architect, improves the efficiency and accuracy of the interconnection network design of the hardware component, saves labor costs and material resources, and improves the flexibility of the interconnection network design of the hardware component.

[0021] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 This is a flowchart of a method for designing an interconnection network for AI processor hardware components according to the first embodiment of the present invention;

[0024] Figure 2 This is a detailed flowchart of a method for designing an interconnection network for AI processor hardware components according to the second embodiment of the present invention;

[0025] Figure 31 is a schematic diagram of the structure of an interconnection network design device for AI processor hardware components according to the third embodiment of the present invention;

[0026] Figure 4 This is a schematic structural diagram of an electronic device provided according to a fourth embodiment of the present invention;

[0027] Figure 5 It is a schematic diagram of the specific structure of the Internet network architecture in the method provided according to the first embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "target", "current", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0030] Example 1

[0031] Figure 1 A flowchart of a method for designing an interconnection network for AI processor hardware components is provided for the first embodiment of the present invention. This embodiment is applicable to situations where AI processor hardware components are interconnected through interconnection network design. The method can be performed by an apparatus for designing an interconnection network for AI processor hardware components, which can be implemented in the form of hardware and / or software.

[0032] Correspondingly, such as Figure 1 As shown, the method includes:

[0033] S110. In an interconnection network design of AI processor hardware components, obtain a logical routing data path.

[0034] The logical routing data path is the only routing data path between the MST and the SLV.

[0035] The interconnection network design of the AI processor hardware components includes at least one MST, at least one SLV, and at least one intermediate node. The MST is the initiator of data transfer requests between hardware components. The SLV is the server of data transfer requests between hardware components. The MST reaches the SLV through one or more intermediate nodes to transfer data.

[0036] In this embodiment, requests from the MST to the SLV pass through one or more intermediate nodes. These nodes are nodes in the data transport path. Each intermediate node is capable of routing requests or replies received from one port and forwarding them out another port. Multiple intermediate nodes are combined to form a NodeCluster (NC), forming a collaborative middle-layer network.

[0037] In the hardware architecture, requests from the MST to access the SLV will pass through a common node cluster and ultimately reach the slave device. The node cluster includes all intermediate nodes involved in the data transfer path, specifically defined as: ,in, Indicates the Intermediate nodes, The node cluster is used to centrally manage and optimize the intermediate node resources in the data transfer path, ensuring that data requests can be efficiently and reliably delivered to the target slave device.

[0038] In this embodiment, a data path is a reachable data transport path from the MST to the SLV in the hardware architecture. The data path definition is composed of a physical connection definition and a logical routing definition.

[0039] Specifically, for the physical connection definition, the connection relationship of all physical entities in the system is defined, including: the entity category is the complete set of all MSTs, SLVs and intermediate nodes; the link specification is an explicit declaration of the links that allow communication between all entities.

[0040] Specifically, the logical routing definition is based on the physical connection definition, and sets a unique and fixed data path for each pair of MST and SLV, which comes from the data path expression file, that is, the interconnection definition. and each , there is a unique routing data path, also known as a logical routing data path, for example: for and This ensures the uniqueness and certainty of the data path, providing a clear basis for subsequent interconnection network design optimization.

[0041] The actual internetwork architecture includes 16 MSTs, 24 SLVs, and 180 intermediate nodes. Because the actual internetwork architecture is complex and difficult to fully describe in detail, this article uses the following example to illustrate the specific optimization process.

[0042] For example, assume that the internetwork architecture includes two MSTs (M1 and M2), three SLVs (S1, S2, and S3), and two intermediate nodes (Node1 and Node2). The link relationships between all nodes, i.e., the logical routing data paths, are as follows: .

[0043] S120 : Determine a target data path set according to the logical routing data path using a preset reachable path generation method.

[0044] The reachable path generation method may be a method for generating all reachable paths between different MSTs and SLVs. The target data path set may be a set containing multiple reachable paths.

[0045] Optionally, the target data path set is determined based on the logical routing data path through a preset reachable path generation method, including: determining the target logical routing data path that needs to be optimized by screening the logical routing data path; transforming the target logical routing data path through a preset hardware component interconnection network graph structure transformation method to obtain a target logical routing data path graph structure; and determining the target data path set based on the target logical routing data path graph structure through a preset reachable path generation method.

[0046] Among them, the method for converting the hardware component interconnection network graph structure can be a graph structure generated according to the target logical routing data path, that is, the target logical routing data path graph structure can be generated according to the logical routing data path. Specifically, Figure 5 A specific structural diagram of the Internet network architecture in the method is provided for the first embodiment of the present invention, which is generated according to the logical routing data path.

[0047] Optionally, the target data path set is determined based on the target logical routing data path graph structure through a preset reachable path generation method, including: traversing the target logical routing data path graph structure through a preset reachable path generation method to obtain all reachable paths from each MST through different intermediate nodes to each SLV, and obtaining each of the reachable paths; wherein the target logical routing data path graph includes a directional connection relationship path graph for each MST through different intermediate nodes to reach the corresponding SLV; and combining each of the reachable paths to determine the target data path set.

[0048] In this embodiment, after generating the target logical routing data path graph structure, it is necessary to traverse the target logical routing data path graph structure to obtain all reachable paths from each MST through different intermediate nodes to each SLV, obtain each reachable path, and further obtain the target data path set.

[0049] Continuing with the previous example, assume that the reachable paths obtained include: , that is, the target data path set is obtained.

[0050] S130 , generating a path solving mathematical model by combining the preset joint constraint conditions with the target data path set, and solving the path solving mathematical model to obtain an optimized data path set.

[0051] The joint constraints may include link capacity constraints, path selection constraints, and link flow constraints.

[0052] The link capacity is the maximum number of times a link can be selected or passed; the link flow is the number of times a link can be selected or passed; the link capacity constraint is that the flow of each link cannot exceed the link capacity; the path selection constraint is that the number of path selections in each reachable path from MST to SLV is constrained; and the link flow constraint is the relationship between the link flow and the number of paths that select the link.

[0053] In this embodiment, the target data path set can be constrained according to the joint constraint conditions. The constraint can be set as follows: the flow of each link cannot exceed the link capacity; in each reachable path from MST to SLV, the number of path selections is 1; the link flow is equal to the number of paths that select the link. Further, based on the joint constraint conditions, a path solution mathematical model is obtained, and then the solution is performed to obtain the optimized data path set.

[0054] The advantage of this setting is that it can fully utilize the link capacity, minimize the number of selected links, and shorten the length of the data path as much as possible, thereby better meeting the requirements of data path optimization and improving the flexibility of data path optimization.

[0055] S140: Feedback the optimized data path set, and complete the interconnection network design of the AI processor hardware components based on the optimized data path set.

[0056] Optionally, the optimized data path set is fed back, and the interconnection network design of the AI processor hardware components is completed according to the optimized data path set, including: according to the received optimized data path set, deleting unnecessary paths in the directional connection relationship path graph corresponding to each of the reachable paths to obtain an optimized directional connection relationship path graph; and completing the interconnection network design of the AI processor hardware components according to the optimized directional connection relationship path graph.

[0057] The directional connection relationship path graph may be a path graph obtained by combining the reachable paths in the target data path set, and the paths in the optimized data path set are included in the reachable paths corresponding to the target data path set.

[0058] In this embodiment, after obtaining the optimized data path set, the paths in the optimized data path set can be matched with the paths in the directional connection relationship path graph. If the match is successful, the path is retained; if the match is unsuccessful, the path is deleted.

[0059] Furthermore, after the traversal is completed and unnecessary paths are deleted, an optimized direction connection relationship path graph can be obtained, and the interconnection network design of the AI processor hardware components can be completed based on the optimized direction connection relationship path graph.

[0060] The advantage of this setting is that the optimized data path can be more intuitively displayed through the optimization direction connection relationship path diagram, which can make it easier to implement the interconnection network design of AI processor hardware components.

[0061] The technical solution of the embodiment of the present invention is to obtain a logical routing data path in the interconnection network design of the AI processor hardware component; determine a target data path set based on the logical routing data path through a pre-set reachable path generation method; generate a path solving mathematical model based on the pre-set joint constraint conditions and the target data path set, and solve the path solving mathematical model to obtain an optimized data path set; provide feedback on the optimized data path set, and complete the interconnection network design of the AI processor hardware component based on the optimized data path set. This solves the problem that the interconnection network design method of the AI processor hardware component mainly relies on the design experience of the architect, improves the efficiency and accuracy of the interconnection network design of the hardware component, saves labor costs and material resources, and improves the flexibility of the interconnection network design of the hardware component.

[0062] Example 2

[0063] Figure 2 A detailed flow chart of a method for designing an interconnection network for AI processor hardware components is provided for the second embodiment of the present invention. This embodiment is based on and further refines the above embodiments. In this embodiment, the path solving mathematical model is generated by combining the preset joint constraints with the target data path set, and the optimized data path set obtained by solving the path solving mathematical model is further refined.

[0064] Correspondingly, such as Figure 2 As shown, the method includes:

[0065] S210. In an interconnection network design of AI processor hardware components, obtain a logical routing data path.

[0066] S220 : Determine a target data path set according to the logical routing data path using a preset reachable path generation method.

[0067] S230 , generating a path solving mathematical model by combining link capacity constraints, path selection constraints, and link flow constraints with a target data path set.

[0068] In this embodiment, the path solving mathematical model may be generated by combining the link capacity constraint, the path selection constraint, and the link flow constraint with the target data path set: ; Where i represents the intermediate node i on the link; j represents the intermediate node j on the link; represents the traffic from intermediate node i to intermediate node j on the link; An indicator variable indicating whether the link from intermediate node i to intermediate node j is selected; Indicates the total number of SLVs; Indicates the influencing parameter for adjusting the number of selected links; Indicates the influencing parameter for adjusting the data path length; Represents the data path; An indicator variable indicating whether the data path is selected; Indicates the length of the data path; M indicates the set of MSTs; S indicates the set of SLVs; m indicates an MST in the set of MSTs; S indicates an SLV in the set of SLVs; Indicates from arrive A complete path; Indicates from arrive The complete path of the whole represents a path that passes through a link starting from intermediate node i and ending at intermediate node j; b represents the number of path choices in each reachable path from MST to SLV; Indicates the number of path selections in each reachable path from MST to SLV.

[0069] Among them, for The meaning of is: the link flow is equal to the number of paths that select the link, that is, the link The number of selected The sum of the number of paths passing through the link. The meaning is: for any arrive There is only one path.

[0070] Continuing with the previous example, the link capacity constraint can be set such that the traffic on each link cannot exceed the link capacity. The path selection constraint can be set such that the number of paths selected from each MST to SLV is 1. The link flow constraint can be set such that the link flow is equal to the number of paths that select that link.

[0071] Furthermore, the maximum capacity of each link can be defined as the number of SLVs. The total number of SLVs can be set to 3, which means the link capacity is 3. Accordingly, by combining the link capacity constraint, path selection constraint, and link flow constraint with the target data path set, the path solution mathematical model is generated as follows: .

[0072] S240 , solving the path solving mathematical model through a preset mixed integer optimizer to obtain an optimized data path set.

[0073] Among them, the mixed integer optimizer can be an optimizer that solves the path solution mathematical model.

[0074] In this embodiment, Performing a solution process, obtaining an optimized data path set corresponding to the above-set joint constraint conditions. In addition, different constraint condition setting operations can be performed on the joint constraint conditions to generate different optimized data path sets.

[0075] S250: Feedback the optimized data path set, and complete the interconnection network design of the AI processor hardware components based on the optimized data path set.

[0076] Continuing with the previous example, in an actual internetwork architecture, including 16 MSTs, 24 SLVs, and 180 intermediate nodes, the above internetwork design approach improves average link utilization and significantly optimizes physical resource scheduling efficiency. It also optimizes average path length, reduces the number of active links, and simultaneously reduces the number of intermediate nodes, achieving intensive deployment of hardware resources.

[0077] The technical solution of the embodiment of the present invention is to obtain a logical routing data path in the interconnection network design of the AI processor hardware components; determine the target data path set based on the logical routing data path through a pre-set reachable path generation method; generate a path solving mathematical model by combining the target data path set with link capacity constraints, path selection constraints, and link flow constraints; solve the path solving mathematical model through a pre-set mixed integer optimizer to obtain an optimized data path set; feed back the optimized data path set, and complete the interconnection network design of the AI processor hardware components based on the optimized data path set. This improves the average link utilization, significantly optimizes the physical resource scheduling efficiency, achieves intensive deployment of hardware resources, improves the efficiency and accuracy of the interconnection network design of the hardware components, and saves manpower costs and material resources.

[0078] Example 3

[0079] Figure 3 This is a schematic diagram of the structure of an interconnection network design device for AI processor hardware components provided in the third embodiment of the present invention. The interconnection network design device for AI processor hardware components provided in this embodiment can be implemented through software and / or hardware, and can be configured in a terminal device or server to implement an interconnection network design method for AI processor hardware components in the embodiment of the present invention. Figure 3 As shown, the apparatus includes: a logical routing data path acquisition module 310 , a target data path set determination module 320 , an optimized data path set determination module 330 and an optimized data path set feedback module 340 .

[0080] The logical routing data path acquisition module 310 is used to obtain the logical routing data path in the interconnection network design of the AI processor hardware components;

[0081] Wherein, the logical routing data path is the only routing data path between the MST and the SLV;

[0082] The interconnection network design of AI processor hardware components includes at least one MST, at least one SLV, and at least one intermediate node. The MST is the initiator of data transfer requests between hardware components; the SLV is the service provider of data transfer requests between hardware components. The MST reaches the SLV through one or more intermediate nodes to perform data transfer.

[0083] a target data path set determination module 320, configured to determine a target data path set according to the logical routing data path and using a preset reachable path generation method;

[0084] The optimized data path set determination module 330 is configured to generate a path solving mathematical model based on pre-set joint constraints and a target data path set, and solve the path solving mathematical model to obtain an optimized data path set;

[0085] The optimized data path set feedback module 340 is used to provide feedback on the optimized data path set and complete the interconnection network design of the AI processor hardware components based on the optimized data path set.

[0086] The technical solution of the embodiment of the present invention is to obtain a logical routing data path in the interconnection network design of the AI processor hardware component; determine a target data path set based on the logical routing data path through a pre-set reachable path generation method; generate a path solving mathematical model based on the pre-set joint constraint conditions and the target data path set, and solve the path solving mathematical model to obtain an optimized data path set; provide feedback on the optimized data path set, and complete the interconnection network design of the AI processor hardware component based on the optimized data path set. This solves the problem that the interconnection network design method of the AI processor hardware component mainly relies on the design experience of the architect, improves the efficiency and accuracy of the interconnection network design of the hardware component, saves labor costs and material resources, and improves the flexibility of the interconnection network design of the hardware component.

[0087] Based on the above embodiments, the target data path set determination module 320 may specifically include: a target logical routing data path determination unit, configured to determine a target logical routing data path that needs to be optimized by screening the logical routing data paths; a target logical routing data path graph structure determination unit, configured to transform the target logical routing data paths by a preset hardware component interconnection network graph structure transformation method to obtain a target logical routing data path graph structure; and a target data path set determination unit, configured to determine a target data path set based on the target logical routing data path graph structure by a preset reachable path generation method.

[0088] Based on the above embodiments, the target data path set determination unit can be specifically used to: traverse the target logical routing data path graph structure through a preset reachable path generation method, obtain all reachable paths from each MST through different intermediate nodes to each SLV, and obtain each of the reachable paths; wherein the target logical routing data path graph includes a directional connection relationship path graph for each MST through different intermediate nodes to reach the corresponding SLV; and combine the reachable paths to determine the target data path set.

[0089] Based on the above embodiments, the joint constraint conditions include: link capacity constraint, path selection constraint, and link flow constraint; wherein the link capacity is the maximum number of times a link can be selected or passed; the link flow is the number of times a link can be selected or passed; wherein the link capacity constraint is that the flow of each link cannot exceed the link capacity; the path selection constraint is that in each reachable path from MST to SLV, the number of path selections is constrained; and the link flow constraint is the relationship between the link flow and the number of paths that select the link.

[0090] Based on the above embodiments, the optimized data path set determination module 330 may be specifically configured to:

[0091] By combining the link capacity constraint, path selection constraint and link flow constraint with the target data path set, the path solution mathematical model is generated as ;

[0092] Where i represents the intermediate node i on the link; j represents the intermediate node j on the link; represents the traffic from intermediate node i to intermediate node j on the link; An indicator variable indicating whether the link from intermediate node i to intermediate node j is selected; Indicates the total number of SLVs; Indicates the influencing parameter for adjusting the number of selected links; Indicates the influencing parameter for adjusting the data path length; Represents the data path; An indicator variable indicating whether the data path is selected; Indicates the length of the data path; M indicates the set of MSTs; S indicates the set of SLVs; m indicates an MST in the set of MSTs; S indicates an SLV in the set of SLVs; Indicates from arrive A complete path; Indicates from arrive The complete path of the whole represents a path that passes through a link starting from intermediate node i and ending at intermediate node j; b represents the number of path choices in each reachable path from MST to SLV; Indicates the number of path selections in each reachable path from MST to SLV.

[0093] On the basis of the above embodiments, the optimized data path set determination module 330 can be specifically used to solve the mathematical model of the path through a pre-set mixed integer optimizer. Solve and obtain the optimized data path set.

[0094] Based on the above embodiments, the optimized data path set feedback module 340 can be specifically used to: delete unnecessary paths in the directional connection relationship path graph corresponding to each of the reachable paths according to the received optimized data path set, to obtain an optimized directional connection relationship path graph; and complete the interconnection network design of the AI processor hardware components according to the optimized directional connection relationship path graph.

[0095] The interconnection network design device for AI processor hardware components provided in an embodiment of the present invention can execute the interconnection network design method for AI processor hardware components provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0096] Example 4

[0097] Figure 4A schematic diagram of the structure of an electronic device 10 that can be used to implement the fourth embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0098] like Figure 4 As shown, electronic device 10 includes at least one processor 11 and memory, such as read-only memory (ROM) 12 and random access memory (RAM) 13, communicatively connected to at least one processor 11. The memory stores computer programs executable by the at least one processor. Processor 11 can perform various appropriate actions and processes based on the computer programs stored in ROM 12 or loaded from storage unit 18 into RAM 13. RAM 13 can also store various programs and data required for the operation of electronic device 10. Processor 11, ROM 12, and RAM 13 are interconnected via bus 14. An input / output (I / O) interface 15 is also connected to bus 14.

[0099] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0100] Processor 11 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any other suitable processor, controller, microcontroller, etc. Processor 11 executes the various methods and processes described above, such as the interconnection network design method for AI processor hardware components.

[0101] In some embodiments, the interconnection network design method for AI processor hardware components can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the interconnection network design method for AI processor hardware components described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to execute the interconnection network design method for AI processor hardware components by any other appropriate means (for example, by means of firmware).

[0102] The method includes: obtaining a logical routing data path in an interconnection network design of AI processor hardware components; wherein the logical routing data path is a unique routing data path between an MST and an SLV; wherein the interconnection network design of the AI processor hardware components includes at least one MST, at least one SLV, and at least one intermediate node; wherein the MST is the initiator of a data transfer request between hardware components; the SLV is the server of a data transfer request between hardware components, and the MST reaches the SLV through one or more intermediate nodes to transfer data; according to the logical routing data path, a target data path set is determined by a preset reachable path generation method; according to preset joint constraints, a path solution mathematical model is generated in combination with the target data path set, and the path solution mathematical model is solved to obtain an optimized data path set; the optimized data path set is fed back, and the interconnection network design of the AI processor hardware components is completed according to the optimized data path set.

[0103] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0104] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0105] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or apparatus. A computer-readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media may include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0106] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device that has: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0107] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0108] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0109] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0110] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

[0111] Example 5

[0112] A fifth embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable instructions, when executed by a computer processor, are used to perform a method for designing an interconnection network for AI processor hardware components. The method comprises: obtaining a logical routing data path in the interconnection network design of the AI processor hardware components; wherein the logical routing data path is a unique routing data path between an MST and an SLV; wherein the interconnection network design of the AI processor hardware components includes at least one MST, at least one SLV, and at least one intermediate node; wherein the MST is the initiator of data transfer requests between hardware components; the SLV is the service provider of data transfer requests between hardware components, and the MST reaches the SLV through one or more intermediate nodes to perform data transfer; based on the logical routing data path, determining a target data path set using a preset reachable path generation method; generating a path solution mathematical model based on preset joint constraints and the target data path set, and solving the path solution mathematical model to obtain an optimized data path set; providing feedback on the optimized data path set, and completing the interconnection network design of the AI processor hardware components based on the optimized data path set.

[0113] Of course, the computer-readable storage medium provided in an embodiment of the present invention has computer-executable instructions that are not limited to the method operations described above, but can also execute related operations in the Internet network design for AI processor hardware components provided in any embodiment of the present invention.

[0114] Through the above description of the embodiments, those skilled in the art can clearly understand that the present invention can be implemented with the help of software and necessary general-purpose hardware. Of course, it can also be implemented with hardware, but in many cases the former is a better embodiment. Based on this understanding, the technical solution of the present invention, or the part that contributes to the existing technology, can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as a computer floppy disk, read-only memory (ROM), random access memory (RAM), flash memory (FLASH), hard disk or optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments of the present invention.

[0115] It is worth noting that in the above-mentioned embodiment of the interconnection network design for AI processor hardware components, the various units and modules included are only divided according to functional logic, but are not limited to the above-mentioned division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present invention.

[0116] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A method for designing an interconnection network for AI processor hardware components, characterized in that: include: In an interconnection network design of AI processor hardware components, a logical routing data path is obtained; wherein the logical routing data path is a unique routing data path between the MST and the SLV; The interconnection network design of AI processor hardware components includes at least one MST, at least one SLV, and at least one intermediate node. The MST is the initiator of data transfer requests between hardware components; the SLV is the service provider of data transfer requests between hardware components. The MST reaches the SLV through one or more intermediate nodes to perform data transfer. According to the logical routing data path, a target data path set is determined by a preset reachable path generation method; By combining the preset joint constraint conditions with the target data path set, a path solving mathematical model is generated, and the path solving mathematical model is solved to obtain an optimized data path set; Feedback of the optimized data path set is performed, and an interconnection network design of the AI processor hardware components is completed based on the optimized data path set; The joint constraints include: link capacity constraints, path selection constraints, and link flow constraints; Among them, link capacity is the maximum number of times a link can be selected or passed; link flow is the number of times a link can be selected or passed; The link capacity constraint is that the traffic of each link cannot exceed the link capacity; the path selection constraint is that the number of path selections in each reachable path from MST to SLV is constrained; and the link flow constraint is the relationship between the link flow and the number of paths that select the link.

2. The method according to claim 1, characterized in that The step of determining a target data path set according to the logical routing data path by using a preset reachable path generation method includes: By screening the logical routing data paths, determining a target logical routing data path that needs to be optimized; The target logical routing data path is converted by a preset hardware component interconnection network graph structure conversion method to obtain a target logical routing data path graph structure; According to the target logical routing data path graph structure, a target data path set is determined through a preset reachable path generation method.

3. The method according to claim 2, characterized in that The step of determining a target data path set based on the target logical routing data path graph structure and using a preset reachable path generation method includes: By using a preset reachable path generation method, the target logical routing data path graph structure is traversed to obtain all reachable paths from each MST through different intermediate nodes to each SLV, thereby obtaining each reachable path; The target logical routing data path diagram includes a directional connection relationship path diagram of each MST passing through different intermediate nodes to reach the corresponding SLV; The reachable paths are combined to determine a target data path set.

4. The method according to claim 3, characterized in that The method of generating a path solving mathematical model by combining the preset joint constraint conditions with the target data path set includes: By combining the link capacity constraint, path selection constraint and link flow constraint with the target data path set, the path solution mathematical model is generated as ; Where i represents the intermediate node i on the link; j represents the intermediate node j on the link; represents the traffic from intermediate node i to intermediate node j on the link; An indicator variable indicating whether the link from intermediate node i to intermediate node j is selected; Indicates the total number of SLVs; Indicates the influencing parameter for adjusting the number of selected links; Indicates the influencing parameter for adjusting the data path length; Represents the data path; Indicates the length of the data path; M indicates the set of MSTs; S indicates the set of SLVs; m indicates an MST in the set of MSTs; S indicates an SLV in the set of SLVs; Indicates from arrive A complete path; Indicates from arrive The complete path of the whole; represents a path that passes through a link starting from intermediate node i and ending at intermediate node j; b represents the number of path choices in each reachable path from MST to SLV; Indicates the number of path selections in each reachable path from MST to SLV.

5. The method according to claim 4, characterized in that Solving the path solving mathematical model to obtain an optimized data path set includes: Solve the mathematical model for the path using a pre-set mixed integer optimizer Solve and obtain the optimized data path set.

6. The method according to claim 5, characterized in that Feedback of the optimized data path set and completion of the interconnection network design of the AI processor hardware components based on the optimized data path set include: According to the received optimized data path set, unnecessary paths in the directional connection relationship path graph corresponding to each of the reachable paths are deleted to obtain an optimized directional connection relationship path graph; The interconnection network design of the AI processor hardware components is completed according to the optimization direction connection relationship path diagram.

7. An interconnection network design device for AI processor hardware components, characterized in that: include: A logical routing data path acquisition module is used to obtain the logical routing data path in the interconnection network design of the AI processor hardware components; Wherein, the logical routing data path is the only routing data path between the MST and the SLV; The interconnection network design of AI processor hardware components includes at least one MST, at least one SLV, and at least one intermediate node. The MST is the initiator of data transfer requests between hardware components; the SLV is the service provider of data transfer requests between hardware components. The MST reaches the SLV through one or more intermediate nodes to perform data transfer. a target data path set determination module, configured to determine a target data path set according to the logical routing data path and by a preset reachable path generation method; An optimized data path set determination module is used to generate a path solving mathematical model based on pre-set joint constraints and a target data path set, and solve the path solving mathematical model to obtain an optimized data path set; An optimized data path set feedback module, configured to provide feedback on the optimized data path set and implement interconnection network design of AI processor hardware components based on the optimized data path set; The joint constraints include: link capacity constraints, path selection constraints, and link flow constraints; Among them, link capacity is the maximum number of times a link can be selected or passed; link flow is the number of times a link can be selected or passed; The link capacity constraint is that the traffic of each link cannot exceed the link capacity; the path selection constraint is that the number of path selections in each reachable path from MST to SLV is constrained; and the link flow constraint is the relationship between the link flow and the number of paths that select the link.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that: When the processor executes the computer program, it implements an interconnection network design method for AI processor hardware components according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement an interconnection network design method for AI processor hardware components according to any one of claims 1 to 6 when executed.

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