Chip reliability test method, device, system and electronic equipment

Abstract

The embodiment of the present application provides a chip reliability test method, device, system and electronic equipment, which relates to the field of chip reliability testing technology. The method includes: determining a test project model according to the chip type of the chip to be tested and the characteristics of the test project, wherein the test project model includes the test project for the chip to be tested, the test cost of the test project and the probability of occurrence of the project result of the test project that can determine the overall test result; establishing a test project data table according to the test project model; quantitatively evaluating the test projects in the test project data table based on the entropy weight method to obtain the comprehensive index corresponding to the test project; selecting test projects in different time stages based on the greedy algorithm and the comprehensive index to generate a test plan. The implementation method provided by this application improves the scientific nature of the test plan design.

Description

Technical Field

[0001] The present application relates to the technical field of chip reliability testing, and in particular to a chip reliability testing method, a chip reliability testing device, a chip reliability testing system, an electronic device, a storage medium, and a computer program product. Background Art

[0002] Reliability testing is an important means of improving the reliability of chip products. Different test types can be performed at different stages of a chip's lifecycle to enhance product quality and reliability. Experience shows that different chip types are susceptible to different types of defects under different test conditions. For example, the pins of SOP-packaged chips are susceptible to damage from electrostatic testing due to their large package size and high supply voltage, but are less susceptible to voltage stress failure during latch-up testing. The same chip also exhibits different propensity to induce the same defect under different test conditions. For example, the highly accelerated temperature and humidity life test (HAST) can induce stress migration defects within a shorter test cycle, while the high-temperature operating life (HTOL) test requires a longer test cycle. Furthermore, if both tests are performed simultaneously, further HTOL testing may be unnecessary or unnecessary after the HAST test reveals a defect. Therefore, the appropriate arrangement of test items plays a crucial role in promptly detecting product defects, improving test efficiency, and reducing the waste of test resources.

[0003] For example, the test items outlined in the "T / CIE 073-2020 Industrial High-Reliability Integrated Circuit Evaluation Part 8: Microcontrollers (MCUs)" standard include 11 test items, distributed across different phases and scenarios, and resulting in a high test workload. This indicates that different test items, in different phases and scenarios, can induce significant variations in defect types and test workload.

[0004] Existing technologies are based on tradition or personal experience, and lack scientific planning for multiple test projects for products. There is a certain degree of arbitrariness and uncertainty, and there is no relevant software tool support. Based on relevant research data, standards, and test experience, the test cycle, test cost, and probability of triggering defects for different test projects are different. The main shortcomings of traditional test project arrangements are: First, the arrangement of test projects depends largely on the experience of test personnel and the idle status of equipment, which is uncertain and arbitrary; second, the probability of different test projects triggering defects on different chips is not fully considered, and there is a waste of resources caused by carrying out multiple test projects at the same time; third, there is a lack of professional tool software support for test project selection and test sequence arrangement. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a chip reliability test method, device, system and electronic equipment. In order to address the problems of arbitrariness, uncertainty and lack of systematic planning in traditional test schemes or methods, the defect characteristics of different chips and the probability of defects stimulated by test stress are combined, while also considering the test cycle and test economic cost, so as to at least solve some of the problems in the background technology.

[0006] In order to achieve the above-mentioned purpose, a chip reliability test method is provided in the present application, including: determining a test item model according to the chip type of the chip to be tested and the characteristics of the test items, the test item model including the test items for the chip to be tested, the test costs of the test items and the probability of occurrence of the project results of the test items that can determine the overall test results; establishing a test item data table according to the test item model, the items in the test item data table are determined according to the contents in the test item model, and the values ​​in the test item data table are determined according to historical data; quantitatively evaluating the test items in the test item data table based on the entropy weight method to obtain comprehensive indicators corresponding to the test items; selecting test items in different time stages based on the greedy algorithm and the comprehensive indicators to generate a test plan.

[0007] Optionally, the test cost of the test project includes a test period and a test economic cost; and the project result capable of determining the overall test result includes: detecting at least one defect among a plurality of defects that cause the overall test result to be unqualified.

[0008] Optionally, the items in the test item data table are determined according to the content in the test item model, including: row names of the test item data table are set in correspondence with the test items;

[0009] The column names of the test item data table include: test cost of the test item and the corresponding probabilities of various defects.

[0010] Optionally, the values ​​in the test item data table are determined based on historical data, including: the values ​​in the test item data table are determined based on mathematical statistics of historical data, or the values ​​in the test item data table are determined based on expert experience based on historical data.

[0011] Optionally, the test items in the test item data table are quantitatively evaluated based on the entropy weight method to obtain comprehensive indicators corresponding to the test items, including: converting the data in the test item data table into a first matrix; preprocessing the first matrix to obtain a preprocessed matrix, each column of the preprocessed matrix represents an indicator; calculating the proportion of each value under each item in the preprocessed matrix to obtain an indicator proportion matrix; calculating the entropy value of each indicator according to the indicator proportion matrix; calculating the information entropy redundancy of each indicator according to the entropy value; obtaining the weight of each indicator according to the information entropy redundancy; and obtaining the comprehensive indicator corresponding to the test item according to the data in the test item data table and the weight.

[0012] Optionally, the first matrix is ​​preprocessed to obtain a preprocessed matrix, including: performing correlation consistency processing and occurrence probability summation processing on the data in the first matrix to obtain a second matrix, each column of the second matrix represents an indicator; performing data normalization processing on the indicators in the second matrix to obtain a third matrix, and using the third matrix as the preprocessed matrix.

[0013] Optionally, based on the greedy algorithm and the comprehensive index, test items of different time stages are selected to generate a test plan, including: dividing the test plan into several time stages, each time stage is used to execute a test item of a chip to be tested; starting from the first time stage, the following steps are executed in each time stage: selecting the test item with the largest comprehensive index of each chip to be tested that has not been included in the test plan as the test item to be selected; if the test item to be selected meets the implementation conditions, the test item to be selected is included in the test plan of the current time stage; after executing the above steps in the several time stages, the test plan is obtained.

[0014] Optionally, the implementation condition includes: the test equipment executing the test item is in an idle state.

[0015] The present application also provides a chip reliability testing device, which includes: a model determination module, which is used to determine the test item model according to the chip type of the chip to be tested and the characteristics of the test items, wherein the test item model includes the test items for the chip to be tested, the test costs of the test items, and the probability of occurrence of the project results of the test items that can determine the overall test results; a data table establishment module, which is used to establish a test item data table according to the test item model, wherein the items in the test item data table are determined according to the contents in the test item model, and the values ​​in the test item data table are determined according to historical data; an indicator calculation module, which is used to quantitatively evaluate the test items in the test item data table based on the entropy weight method to obtain the comprehensive indicators corresponding to the test items; and a scheme generation module, which is used to select test items of different time stages based on the greedy algorithm and the comprehensive indicators to generate a test scheme.

[0016] Optionally, the test cost of the test project includes a test period and a test economic cost; and the project result capable of determining the overall test result includes: detecting at least one defect among a plurality of defects that cause the overall test result to be unqualified.

[0017] Optionally, the items in the test item data table are determined according to the content in the test item model, including: the row names of the test item data table are set corresponding to the test items; the column names of the test item data table include: the test cost of the test item and the corresponding probabilities of multiple defects.

[0018] Optionally, the values ​​in the test item data table are determined based on historical data, including: the values ​​in the test item data table are determined based on mathematical statistics of historical data, or the values ​​in the test item data table are determined based on expert experience based on historical data.

[0019] Optionally, the test items in the test item data table are quantitatively evaluated based on the entropy weight method to obtain comprehensive indicators corresponding to the test items, including: converting the data in the test item data table into a first matrix; preprocessing the first matrix to obtain a preprocessed matrix, each column of the preprocessed matrix represents an indicator; calculating the proportion of each value under each item in the preprocessed matrix to obtain an indicator proportion matrix; calculating the entropy value of each indicator according to the indicator proportion matrix; calculating the information entropy redundancy of each indicator according to the entropy value; obtaining the weight of each indicator according to the information entropy redundancy; and obtaining the comprehensive indicator corresponding to the test item according to the data in the test item data table and the weight.

[0020] Optionally, the first matrix is ​​preprocessed to obtain a preprocessed matrix, including: performing correlation consistency processing and occurrence probability summation processing on the data in the first matrix to obtain a second matrix, each column of the second matrix represents an indicator; performing data normalization processing on the indicators in the second matrix to obtain a third matrix, and using the third matrix as the preprocessed matrix.

[0021] Optionally, based on the greedy algorithm and the comprehensive index, test items of different time stages are selected to generate a test plan, including: dividing the test plan into several time stages, each time stage is used to execute a test item of a chip to be tested; starting from the first time stage, the following steps are executed in each time stage: selecting the test item with the largest comprehensive index of each chip to be tested that has not been included in the test plan as the test item to be selected; if the test item to be selected meets the implementation conditions, the test item to be selected is included in the test plan of the current time stage; after executing the above steps in the several time stages, the test plan is obtained.

[0022] Optionally, the implementation condition includes: the test equipment executing the test item is in an idle state.

[0023] This application also provides an electronic device comprising: at least one processor; and a memory connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the at least one processor implements the aforementioned chip reliability test method by executing the instructions stored in the memory.

[0024] The present application also provides a machine-readable storage medium, which stores instructions. When the instructions are executed by a processor, the processor is configured to execute the aforementioned chip reliability test method.

[0025] The present application also provides a computer program product, comprising a computer program, which implements the aforementioned chip reliability test method when executed by a processor.

[0026] The above technical solution has the following beneficial effects:

[0027] Compared with traditional schemes or traditional methods, the chip reliability test method proposed in this application fully considers the characteristics of chip product defects and test items that trigger defects, and proposes a theoretical method of giving priority to test items with the shortest test cycle, lowest cost, and high defect triggering probability to carry out tests. It greatly improves the scientific nature of the test scheme design, and has obvious improvements in improving test efficiency and reducing test costs compared with traditional methods.

[0028] Other features and advantages of the embodiments of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present application but do not constitute a limitation on the embodiments of the present application. In the accompanying drawings:

[0030] Figure 1 The following schematically shows a schematic diagram of a solution idea according to an embodiment of the present application;

[0031] Figure 2 Schematically shows a schematic diagram of the steps of a chip reliability test method according to an embodiment of the present application;

[0032] Figure 3 The following schematically shows a schematic structural diagram of a chip reliability test device according to an embodiment of the present application;

[0033] Figure 4 Schematically shows the architecture of a chip reliability test system according to an embodiment of the present application;

[0034] Figure 5 The internal structure of an electronic device according to an embodiment of the present application is schematically shown. DETAILED DESCRIPTION

[0035] The following describes the specific implementation of the embodiment of the present application in detail with reference to the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the embodiment of the present application and is not intended to limit the embodiment of the present application.

[0036] In response to various problems in the background technology, the present application proposes a chip reliability test method, device, system and electronic equipment, which generate test plans based on entropy weight method and greedy algorithm. Figure 1 The schematic diagram of the scheme idea according to the embodiment of the present application is shown schematically. Figure 1 As shown, the solution ideas of this application mainly include: first, based on the chip type and the characteristics of the test project, the test project modeling is carried out, and the established model includes attributes such as the test project cycle, test cost, and different defect probabilities; then, based on the test project model, a test project data table is created, and the data of the data table is set according to the expert experience method; then, based on the entropy weight method, the comprehensive index of the set test project data table is calculated to obtain the test project comprehensive index data table; finally, based on the data in the test project comprehensive index data table and the greedy algorithm, the test projects are selected in stages to generate the test plan.

[0037] Figure 2 The following schematically shows the steps of the chip reliability test method according to the embodiment of the present application. Figure 2As shown, a chip reliability test method, the method comprising:

[0038] S01. Determine a test item model based on the chip type and test item characteristics of the chip to be tested, wherein the test item model includes test items for the chip to be tested, test costs of the test items, and the probability of occurrence of test results of the test items that can determine the overall test results;

[0039] S02. Establishing a test item data table according to the test item model, wherein the items in the test item data table are determined according to the content of the test item model, and the values ​​in the test item data table are determined according to historical data;

[0040] S03. Quantitatively evaluate the test items in the test item data table based on the entropy weight method to obtain comprehensive indicators corresponding to the test items;

[0041] S04. Selecting test items in different time periods based on the greedy algorithm and the comprehensive indicators to generate a test plan.

[0042] Through the above implementation, compared to traditional schemes or methods, this embodiment fully considers the characteristics of chip product defects and the defects triggered by test items, providing scientific and effective tool support for the generation of test plans, conforming to the objective laws of chip testing, and significantly improving the scientific nature of chip testing test plans. At the same time, this embodiment uses mathematical methods to propose a theoretical method for prioritizing the selection of test items with the shortest test cycle, lowest cost, and highest defect triggering probability for testing. This solves the problem of traditional methods lacking tool support, greatly improves the scientific nature of test plan design, and improves test efficiency and reduces test costs compared to traditional methods.

[0043] In some embodiments of the present application, step S01 determines the test project model based on the chip type and test project characteristics of the chip to be tested, including: based on practical experience, the probability of different types of chip products stimulating defects under different test projects is related to the package type, device scale, package size, product maturity, and application scenario. For example, the SOP package is large in size, has protruding pins, and generally has a higher supply voltage than the BGA package, which is susceptible to ESD test projects to produce breakdown defects, but is less prone to latch-up failures than other packages; the BGA package is not susceptible to electrostatic damage, but has a high integration level and a low supply voltage, such as 1.2V, which is prone to latch-up failures caused by latch-up test projects. Different types of chips are prone to different degrees of defect susceptibility under different test projects. Based on the chip type, the appropriate test project sequence is selected for testing to achieve twice the result with half the effort and economic efficiency. The main factors affecting the order or selection of test projects are the test cycle, that is, the time required to perform the test; the economic cost of the test, that is, the cost required to perform the test; and different defect stimuli, such as breakdown probability, latch-up probability, and carrier degradation probability. During the test process, if breakdown failure, latch-up failure, carrier degradation failure, or other failures occur, the overall test result of the chip under test will be judged as unqualified, and no further testing is required. Therefore, from a practical engineering perspective, we hope to prioritize test items with short test cycles, low test costs, and high defect probabilities. This will help us discover product defects as quickly as possible, terminate the test early, or avoid the need to continue other tests, thereby improving test efficiency and reducing test costs.

[0044] In some embodiments of the present application, the items in the test item data table are determined based on the content of the test item model, including: the row names of the test item data table are set to correspond to the test items; the column names of the test item data table include: the test cost of the test item and the corresponding probabilities of various defects. For example, the content of the test item model includes: serial number, test item, test cycle, test economic cost, probability of triggering defect 1, probability of triggering defect 2, probability of triggering defect 3, etc. This results in the test item data table shown below.

[0045]

[0046] In some embodiments of the present application, the values ​​in the above-mentioned test item data table are determined based on historical data, including: the values ​​in the test item data table are determined based on mathematical statistical results of historical data, or the values ​​in the test item data table are determined based on expert experience based on historical data.

[0047] In some embodiments of the present application, a quantitative evaluation of the test items in the test item data table is performed based on an entropy weight method to obtain a comprehensive index corresponding to the test item, including: converting the data in the test item data table into a first matrix; preprocessing the first matrix to obtain a preprocessed matrix, wherein each column of the preprocessed matrix represents an index; calculating the proportion of each value under each item in the preprocessed matrix to the index to obtain an index proportion matrix; calculating the entropy value of each index based on the index proportion matrix; calculating the information entropy redundancy of each index based on the entropy value; obtaining a weight for each index based on the information entropy redundancy; and obtaining a comprehensive index corresponding to the test item based on the data in the test item data table and the weights. For example, assume there are n test item samples, each with m indicators, including test cycle, test economic cost, and multiple defect probability indicators. The specific values ​​of each indicator can be obtained or set using expert experience or based on historical statistical data, thereby constructing the sample index data into an n×m matrix, namely, the first matrix.

[0048] In some optional steps, the test sample data is preprocessed. First, the inverse of the test cycle index is obtained; second, the inverse of the test economic cost is obtained; the purpose is to change the correlation between the value and the comprehensive index from negative correlation to positive correlation, so that the correlation is consistent. Third, the summation of multiple defect probabilities is performed, the purpose of which is to reduce the dimension of the matrix, thereby transforming the first matrix from n×m to n×3 matrix A n×3 , which is the second matrix.

[0049] Let x ij is the i-th test item and the j-th indicator, i=1,...,n, j=1,2,3, then the matrix A n×3 As shown below:

[0050]

[0051] Normalize the sample indicators. Because the units of the test cycle, test economic cost, and defect probability indicators are different, normalization is required to ensure the uniformity of the dimensions. This implementation adopts the forward indicator method for data normalization, as shown below:

[0052]

[0053] Then generate the index normalization matrix B n×3 , that is, the third matrix, is as follows:

[0054]

[0055] The proportion of the i-th sample value under the j-th item to the indicator is calculated by the following formula: ij :

[0056]

[0057] Then generate the index proportion matrix, recorded as C n×3 , as shown below:

[0058]

[0059] The entropy value of the j-th indicator is calculated by the following formula:

[0060]

[0061] Where k=1 / ln( n )>0, satisfying e j ≥0.

[0062] The information entropy redundancy d is calculated by the following formula j :

[0063]

[0064] The weight of each indicator is calculated using the following formula:

[0065]

[0066] The comprehensive score of each sample is calculated using the following formula:

[0067]

[0068] w j For the j The weight of the indicator, S i This is the comprehensive index of the i-th test item. Adding this comprehensive index to the aforementioned test item data table will generate a test item comprehensive index data table, as shown in the following table.

[0069]

[0070] To facilitate the subsequent selection of test items based on comprehensive indicators, the above-mentioned test item comprehensive indicator data table can be sorted based on the comprehensive indicators. The sorting is preferably in descending order. The sorting method can be selected from the sorting methods in the prior art. For example, if the bubble sort method is selected, n×(n-1) / 2 rounds of bubble sort are required to achieve descending order based on the comprehensive indicators.

[0071] In some embodiments of the present application, test items of different time stages are selected based on the greedy algorithm and the comprehensive index to generate a test plan, including: dividing the test plan into several time stages, each time stage is used to execute one test item of a chip to be tested; starting from the first time stage, each time stage performs the following steps: selecting the test item with the largest comprehensive index that has not been included in the test plan for each chip to be tested as the test item to be selected; if the test item to be selected meets the implementation conditions, the test item to be selected is included in the test plan of the current time stage; after the above steps are performed in the several time stages, the test plan is obtained. The implementation conditions include: the test equipment executing the test item is in an idle state. During the actual engineering test of the chip, it is impossible to only carry out one test item for one chip product to be tested, and multiple test items for multiple products are often carried out at the same time.

[0072] This embodiment proposes a test plan generation method based on a greedy algorithm, which includes two parts: data preparation and plan generation. Data preparation refers to the aforementioned test project comprehensive index data table. Assume that there are n chip products to be tested that need to be tested, and each chip product to be tested requires m test items. Then, a test project comprehensive index data table for n chip products to be tested can be established, that is, the test project data table settings for each product are completed according to the aforementioned steps, and the m comprehensive index calculations of the test project data table for each product are completed, and a test project comprehensive index data table for different chip products to be tested is established. Plan generation includes: the test plan can be divided into several time stages, a test project for different products is selected in each stage, and the comprehensive index of the test project is maximized.

[0073] The solution generation part can be implemented by following the steps below:

[0074] The Phase 1 plan creation process includes:

[0075] Step 1: Select the test item that is not included in the test plan and has the largest comprehensive index from the test item comprehensive index data table of the first chip product to be tested, and determine whether the test equipment for this test item is available. If it is available, it will be included in the test plan in sequence; if it is busy, it will not be included in the first phase test plan for the time being;

[0076] Step 2: Select the test item that is not included in the test plan and has the largest comprehensive index from the test item comprehensive index data table of the second chip product to be tested, and determine whether the test equipment for this test item is available. If it is available, include it in the test plan in sequence; if it is busy, temporarily exclude it from the first phase test plan; ......

[0077] Step n: Select the test item that is not included in the test plan and has the largest comprehensive index from the test item comprehensive index data table of the nth chip product to be tested, and determine whether the test equipment for the test item is idle. If it is idle, include it in the test plan in sequence; if it is busy, it will not be included in the first phase test plan for the time being.

[0078] The Phase 2 protocol creation process includes repeating steps 1 to n in Phase 1 to generate a Phase 2 trial protocol.

[0079] The process of creating the n-th phase plan includes: repeating step 1 to step n of the first phase to generate the n-th phase test plan.

[0080] The n-stage test plans are sequentially combined to form a test plan for n chip products to be tested. Engineers can carry out each test project in stages according to the test plan.

[0081] Thus, the implementation method of this application not only supports the planning and arrangement of multiple test projects for one chip product, but also supports the planning and arrangement of multiple test projects for multiple chip products. Compared with traditional methods, it has greater flexibility and applicability, greatly improving the orderliness and efficiency of test projects.

[0082] Based on the same inventive concept, this application also provides a chip reliability test device, Figure 3 The schematic diagram of the structure of the chip reliability test device according to the embodiment of the present application is shown. Figure 3 As shown, the device includes: a model determination module, which is used to determine the test item model according to the chip type of the chip to be tested and the characteristics of the test items, wherein the test item model includes the test items for the chip to be tested, the test costs of the test items, and the probability of occurrence of the project results of the test items that can determine the overall test results; a data table establishment module, which is used to establish a test item data table according to the test item model, wherein the items in the test item data table are determined according to the contents in the test item model, and the values ​​in the test item data table are determined according to historical data; an indicator calculation module, which is used to quantitatively evaluate the test items in the test item data table based on the entropy weight method to obtain the comprehensive indicators corresponding to the test items; and a scheme generation module, which is used to select test items in different time stages based on the greedy algorithm and the comprehensive indicators to generate a test scheme.

[0083] In some optional embodiments of the present application, the test cost of the test project includes the test cycle and the test economic cost; the project results that can determine the overall test results include: detecting at least one defect among the multiple defects that cause the overall test results to be unqualified.

[0084] In some optional embodiments of the present application, the items in the test project data table are determined according to the content in the test project model, including: the row names of the test project data table are set corresponding to the test projects; the column names of the test project data table include: the test cost of the test project and the corresponding probabilities of multiple defects.

[0085] In some optional embodiments of the present application, the values ​​in the test item data table are determined based on historical data, including: the values ​​in the test item data table are determined based on mathematical statistical results of historical data, or the values ​​in the test item data table are determined based on expert experience based on historical data.

[0086] In some optional embodiments of the present application, the test items in the test item data table are quantitatively evaluated based on the entropy weight method to obtain comprehensive indicators corresponding to the test items, including: converting the data in the test item data table into a first matrix; preprocessing the first matrix to obtain a preprocessed matrix, each column of the preprocessed matrix represents an indicator; calculating the proportion of each value under each item in the preprocessed matrix to obtain an indicator proportion matrix; calculating the entropy value of each indicator according to the indicator proportion matrix; calculating the information entropy redundancy of each indicator according to the entropy value; obtaining the weight of each indicator according to the information entropy redundancy; and obtaining the comprehensive indicator corresponding to the test item according to the data in the test item data table and the weight.

[0087] In some optional embodiments of the present application, the first matrix is ​​preprocessed to obtain a preprocessed matrix, including: performing correlation consistency processing and occurrence probability summation processing on the data in the first matrix to obtain a second matrix, each column of the second matrix represents an indicator; performing data normalization processing on the indicators in the second matrix to obtain a third matrix, and using the third matrix as the preprocessed matrix.

[0088] In some optional embodiments of the present application, test items of different time stages are selected based on the greedy algorithm and the comprehensive index to generate a test plan, including: dividing the test plan into several time stages, each time stage is used to execute one test item of a chip to be tested; starting from the first time stage, the following steps are executed in each time stage: selecting the test item with the largest comprehensive index of each chip to be tested that has not been included in the test plan as the test item to be selected; if the test item to be selected meets the implementation conditions, the test item to be selected is included in the test plan of the current time stage; after executing the above steps in the several time stages, the test plan is obtained.

[0089] In some optional implementations of the present application, the implementation condition includes: the test equipment executing the test item is in an idle state.

[0090] The specific definition of each functional module in the above-mentioned chip reliability test device can be found in the definition of the chip reliability test method above, which will not be repeated here. Each module in the above-mentioned system can be implemented in whole or in part by software, hardware and their combination. The above-mentioned modules can be embedded in or independent of the processor in the electronic device in the form of hardware, or can be stored in the memory of the electronic device in the form of software, so that the processor can call and execute the operations corresponding to the above modules. It also solves the problem that the traditional method has no tool support, greatly improves the scientific nature of the test scheme design, significantly improves the test efficiency and reduces the test cost.

[0091] In order to facilitate the operation and implementation of the aforementioned chip reliability test method or chip reliability test device, the embodiments of the present application further propose a chip reliability test system. Figure 4 The schematic diagram of the chip reliability test system according to the embodiment of the present application is shown schematically. Figure 4 As shown, the chip reliability test system includes at least four layers: model, data, function, and service. It is built on the operating system OS, database DB, and other basic software. The model layer includes at least the test project information model, product information model, test project comprehensive indicator model, test plan model, etc., which are used to create data tables. The data layer includes at least the test project information data table, product information data table, test project comprehensive indicator data table, and test plan data table. The function layer includes at least the test project setting, product information setting, test plan information setting, test plan generation, etc. The service layer includes at least the test plan configuration service entrance and the test plan query service entrance.

[0092] The main workflow of the aforementioned chip reliability test system includes: data preparation, which primarily involves creating models and data tables to prepare for setting up information such as test items, chip products, and test plans. Information setup involves setting up test item information based on product type information and expert experience through the test plan configuration service portal. Plan generation involves first calculating test item indicators using the entropy weight method; then, using a greedy algorithm, test plans are generated in stages. Plan querying involves searching for corresponding test plans based on product type through the test plan query service portal.

[0093] As a software implementation, the chip reliability test system shares the aforementioned advantages, while also boasting a clear architectural hierarchy and comprehensive functionality, providing a software foundation for implementing the aforementioned chip reliability tests. This implementation proposes a software system design architecture and workflow, addressing the lack of tool support for traditional test plan generation methods and contributing significantly to improving test management.

[0094] In some embodiments of the present application, an electronic device is further provided, comprising: at least one processor; a memory connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the at least one processor executes the aforementioned chip reliability test method. Its internal structure diagram can be as follows Figure 5 shown. Figure 5 The internal structure diagram of an electronic device according to an embodiment of the present application is schematically shown. The electronic device includes a processor A01, a network interface A02, a memory (not shown in the figure) and a database (not shown in the figure) connected via a system bus. Among them, the processor A01 of the electronic device is used to provide computing and control capabilities. The memory of the electronic device includes an internal memory A03 and a non-volatile storage medium A04. The non-volatile storage medium A04 stores an operating system B01, a computer program B02 and a database (not shown in the figure). The internal memory A03 provides an environment for the operation of the operating system B01 and the computer program B02 in the non-volatile storage medium A04. The network interface A02 of the electronic device is used to communicate with an external terminal through a network connection. When the computer program B02 is executed by the processor A01, a chip reliability test method is implemented.

[0095] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the electronic device to which the solution of the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0096] In one embodiment provided in the present application, a machine-readable storage medium is provided. The machine-readable storage medium stores instructions. When the instructions are executed by a processor, the processor is configured to execute the aforementioned chip reliability test method.

[0097] In one embodiment provided in the present application, a computer program product is provided, including a computer program, which implements the aforementioned chip reliability test method when executed by a processor.

[0098] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0099] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0100] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0102] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0103] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0104] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can be implemented using any method or technology to store information. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change RAM (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media such as modulated data signals and carrier waves.

[0105] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0106] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A chip reliability test method, characterized in that: The method includes: Determine a test item model based on the chip type and test item characteristics of the chip to be tested, wherein the test item model includes test items for the chip to be tested, test costs of the test items, and the probability of occurrence of test results of the test items that can determine the overall test results; the test costs of the test items include the test cycle and the test economic cost; the test results that can determine the overall test results include: detection of at least one defect among multiple defects that cause the overall test results to fail; Establishing a test item data table according to the test item model, wherein the items in the test item data table are determined according to the content of the test item model, and the values ​​in the test item data table are determined according to historical data; Performing a quantitative evaluation on the test items in the test item data table based on the entropy weight method to obtain comprehensive indicators corresponding to the test items; Based on the greedy algorithm and the comprehensive index, test items of different time stages are selected to generate a test plan, including: dividing the test plan into several time stages, each time stage is used to execute one test item of a chip to be tested; starting from the first time stage, the following steps are executed in each time stage: selecting the test item with the largest comprehensive index of each chip to be tested that has not been included in the test plan as the test item to be selected; if the test item to be selected meets the implementation conditions, the test item to be selected is included in the test plan of the current time stage; after executing the above steps in the several time stages, the test plan is obtained.

2. The method according to claim 1, characterized in that The items in the test item data table are determined according to the contents of the test item model, including: The row names of the test item data table are set corresponding to the test items; The column names of the test item data table include: test cost of the test item and the corresponding probabilities of various defects.

3. The method according to claim 1, characterized in that The values ​​in the test item data table are determined based on historical data, including: The values ​​in the test item data table are determined based on the mathematical statistics of historical data, or The values ​​in the test item data table are determined based on expert experience based on historical data.

4. The method according to claim 1, wherein Based on the entropy weight method, the test items in the test item data table are quantitatively evaluated to obtain the comprehensive indicators corresponding to the test items, including: Converting the data in the test item data table into a first matrix; Preprocessing the first matrix to obtain a preprocessed matrix, wherein each column of the preprocessed matrix represents an indicator; Calculate the proportion of each value under each item in the preprocessed matrix to the indicator to obtain an indicator proportion matrix; Calculate the entropy value of each indicator according to the indicator weight matrix; Calculate the information entropy redundancy of each indicator according to the entropy value; Obtaining the weight of each indicator according to the information entropy redundancy; The comprehensive index corresponding to the test item is obtained according to the data in the test item data table and the weight.

5. The method according to claim 4, characterized in that Preprocessing the first matrix to obtain a preprocessed matrix includes: Performing correlation consistency processing and probability summation processing on the data in the first matrix to obtain a second matrix, wherein each column of the second matrix represents an indicator; The indicators in the second matrix are subjected to data normalization processing to obtain a third matrix, and the third matrix is ​​used as the preprocessed matrix.

6. The method according to claim 1, characterized in that The implementation conditions include: The test equipment executing the test item is in an idle state.

7. A chip reliability test device, characterized in that: The device includes: a model determination module, configured to determine a test item model based on the chip type and test item characteristics of the chip to be tested, wherein the test item model includes a test item for the chip to be tested, a test cost of the test item, and a probability of occurrence of a test result of the test item that can determine the overall test result; the test cost of the test item includes a test cycle and a test economic cost; and the test result that can determine the overall test result includes: detection of at least one defect among multiple defects that cause the overall test result to fail; a data table establishment module, configured to establish a test item data table according to the test item model, wherein the items in the test item data table are determined according to the content in the test item model, and the values ​​in the test item data table are determined according to historical data; an index calculation module, configured to quantitatively evaluate the test items in the test item data table based on an entropy weight method to obtain comprehensive indicators corresponding to the test items; and A scheme generation module is used to select test items in different time stages based on a greedy algorithm and the comprehensive indicators to generate a test scheme, including: dividing the test scheme into several time stages, each time stage is used to execute one test item for a chip to be tested; starting from the first time stage, each time stage executes the following steps: selecting the test item with the largest comprehensive indicator that has not been included in the test scheme for each chip to be tested as the test item to be selected; if the test item to be selected meets the implementation conditions, the test item to be selected is included in the test scheme of the current time stage; after executing the above steps in the several time stages, the test scheme is obtained.

8. The device according to claim 7, characterized in that The items in the test item data table are determined according to the contents of the test item model, including: The row names of the test item data table are set corresponding to the test items; The column names of the test item data table include: test cost of the test item and the corresponding probabilities of various defects.

9. The device according to claim 7, characterized in that The values ​​in the test item data table are determined based on historical data, including: The values ​​in the test item data table are determined based on the mathematical statistics of historical data, or The values ​​in the test item data table are determined based on expert experience based on historical data.

10. The device according to claim 7, characterized in that Based on the entropy weight method, the test items in the test item data table are quantitatively evaluated to obtain the comprehensive indicators corresponding to the test items, including: Converting the data in the test item data table into a first matrix; Preprocessing the first matrix to obtain a preprocessed matrix, wherein each column of the preprocessed matrix represents an indicator; Calculate the proportion of each value under each item in the preprocessed matrix to the indicator to obtain an indicator proportion matrix; Calculate the entropy value of each indicator according to the indicator weight matrix; Calculate the information entropy redundancy of each indicator according to the entropy value; Obtaining the weight of each indicator according to the information entropy redundancy; The comprehensive index corresponding to the test item is obtained according to the data in the test item data table and the weight.

11. The device according to claim 10, characterized in that Preprocessing the first matrix to obtain a preprocessed matrix includes: Performing correlation consistency processing and probability summation processing on the data in the first matrix to obtain a second matrix, wherein each column of the second matrix represents an indicator; The indicators in the second matrix are subjected to data normalization processing to obtain a third matrix, and the third matrix is ​​used as the preprocessed matrix.

12. The device according to claim 7, characterized in that The implementation conditions include: The test equipment executing the test item is in an idle state.

13. A chip reliability test system, used to implement the chip reliability test method according to any one of claims 1 to 6, characterized in that: The system comprises: A model layer, comprising at least a test item model, a product information model, a test item comprehensive indicator model, and a test plan model. The models in the model layer are used to create a data table. A data layer, comprising at least a test project information data table, a product information data table, a test project comprehensive index data table, and a test plan data table; Functional layer, which at least includes test item setting, product information setting, test plan information setting, and test plan generation; The service layer includes at least a test plan configuration service entry and a test plan query service entry.

14. An electronic device, characterized in that: include: at least one processor; a memory connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the at least one processor implements the steps of the chip reliability test method according to any one of claims 1 to 6 by executing the instructions stored in the memory.

15. A computer-readable storage medium having a computer program / instruction stored thereon, characterized in that: When the computer program / instructions are executed by a processor, the steps of the chip reliability test method according to any one of claims 1 to 6 are implemented. 16 . A computer program product comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the chip reliability test method according to claim 1 .

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