Circuit segmentation method and device

Abstract

The invention provides a circuit segmentation method and device, and the method comprises the steps: obtaining an instantiation tree corresponding to a circuit and a circuit segmentation configuration input by a user, the instantiation tree comprises the weight of a node, the weight of the node is used for indicating the time consumed for processing a circuit module corresponding to the node, and the instantiation tree comprises the weight of the node; the circuit segmentation configuration comprises the number N of processing cores for performing parallel synthesis on the circuit; n segmentation block groups corresponding to the circuit are determined according to an instantiation tree and the circuit segmentation configuration, each segmentation block group comprises at least one first segmentation block, the first segmentation block comprises at least one node, the N segmentation block groups are in one-to-one correspondence with the N processing cores, and the difference value of the weights of any two segmentation block groups in the N segmentation block groups does not exceed a preset threshold value, the weight of the segmentation block group is the sum of the weights of the nodes included in the segmentation block group. According to the method provided by the invention, the efficiency of circuit segmentation parallel optimization and / or the PPA optimization effect can be improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular, to a circuit splitting method and apparatus. Background Art

[0002] Circuit power consumption, performance, and area (PPA) are core metrics that concern developers and users of electronic design automation (EDA) tools. However, according to Moore's Law, as the chip scale increases year by year, EDA tools need to process circuits of larger scale. In addition to PPA, the running time of EDA tools is also a key factor in improving the work efficiency of EDA users, which is related to chip engineers obtaining timely feedback on the results of tool runs and the chip's time to market. In addition, the efficiency optimization of EDA tools themselves can indirectly improve PPA.

[0003] To efficiently process large-scale circuits, multi-core parallel acceleration has become a common method for improving the running efficiency of EDA tools. Among them, circuit splitting parallel optimization is the most commonly used acceleration method because of its small development volume and adaptability to various backend synthesis algorithms. Through the circuit splitting method, the entire ultra-large circuit can be split into multiple split blocks, and then the hardware resources can be independently and parallelly called to optimize the multiple split blocks. Therefore, how to split the circuit greatly affects the efficiency of parallel optimization and the netlist PPA. Summary of the Invention

[0004] This application provides a circuit splitting method and apparatus, which can improve the efficiency of circuit splitting parallel optimization.

[0005] In a first aspect, a circuit splitting method is provided. The method includes: obtaining an instantiation tree corresponding to the circuit and a circuit splitting configuration input by a user, where the instantiation tree includes weights of nodes, and the weights of the nodes are used to indicate the time expected to be consumed for processing the circuit modules corresponding to the nodes, and the circuit splitting configuration includes the number N of processing cores for parallel synthesis of the circuit, and N is an integer greater than 1; determining, according to the instantiation tree and the circuit splitting configuration, N split block groups corresponding to the circuit, each split block group including at least one first split block, the first split block including at least one of the nodes, the N split block groups corresponding one-to-one to the N processing cores, and the difference between the weights of any two split block groups among the N split block groups not exceeding a preset threshold, and the weight of the split block group including the sum of the weights of the nodes included in the split block group.

[0006] The present application provides a circuit splitting method, which can determine N load-balanced splitting block groups for N processing cores, improve the load balance degree and utilization rate of multi-cores, and further improve the efficiency of parallel optimization of circuit splitting. At the same time, it is not necessary for the user to specify the number of splitting parts and a large number of hyperparameters in advance, improving the user experience.

[0007] It should be understood that the instantiation tree is used to represent circuit modules and the hierarchical relationship between each circuit module. Optionally, the instantiation tree may further include the weights of the edges between nodes, and the weights of the edges between nodes are used to indicate the tightness of the dependency relationship between the circuit modules corresponding to the nodes. Exemplarily, the weight of each node can be predicted by a circuit learner, and the weights of the edges between nodes can be obtained by analyzing the instantiation relationship of the instantiation tree.

[0008] Optionally, the weight of the splitting block group can be the sum of the weights of the nodes included in the splitting block group, or it can also be the sum of the weights of the nodes included in the splitting block group and the weights of the edges between nodes.

[0009] Optionally, the circuit splitting configuration input by the user may further include any one or more of the number of splitting iterations, the splitting target priority or weight, and the sub-chip prior information. The splitting target priority or weight can be used to indicate whether PPA is prioritized or the parallel synthesis efficiency is prioritized, and the sub-chip prior information includes the chip-level structure that has been defined when designing the chip.

[0010] Each first splitting block is a part of the instantiation tree, and each processing core is used to process the corresponding splitting block group.

[0011] In combination with the first aspect, in some implementation manners of the first aspect, determining the N splitting block groups corresponding to the circuit includes: determining a plurality of the first splitting blocks corresponding to the circuit; and determining the N splitting block groups according to the plurality of the first splitting blocks.

[0012] Exemplarily, after obtaining a plurality of first splitting blocks, these first splitting blocks can be randomly divided into N splitting block groups, and then the total time for N processing cores to perform parallel synthesis on the N splitting block groups is estimated. Repeat this random grouping operation multiple times until a certain division of N splitting block groups is found, such that the total time for N processing cores to perform parallel synthesis on the N splitting block groups meets the requirements, for example, the grouping with the minimum total time for N processing cores to perform parallel synthesis on N splitting block groups among M random groupings.

[0013] The present application provides a circuit splitting method, which can determine N load-balanced splitting block groups for N processing cores, improve the load balance degree and utilization rate of multi-cores, and further improve the efficiency of parallel optimization of circuit splitting.

[0014] In combination with the first aspect, in some implementations of the first aspect, determining the multiple first segmentation blocks corresponding to the circuit includes: determining a first segmentation front corresponding to the circuit, where the first segmentation front is used to segment the instantiation tree into the multiple first segmentation blocks.

[0015] The first segmentation front includes a set of nodes near the bottom layer of the instantiation tree on the segmentation boundary that segments the instantiation tree into the multiple first segmentation blocks. The first segmentation block is a subtree in the instantiation tree with the nodes included in the first segmentation front as the root nodes.

[0016] This application provides a circuit segmentation method, which can determine multiple first segmentation blocks through the segmentation front corresponding to the instantiation tree, simplifies the representation method of the segmentation blocks, and reduces the storage space required by the method of this application.

[0017] In combination with the first aspect, in some implementations of the first aspect, determining the first segmentation front corresponding to the circuit includes: obtaining multiple historical segmentation fronts and the metrics corresponding to each historical segmentation front in the multiple historical segmentation fronts, where the metrics include any one or more of the scale balance degree of the multiple circuit segmentation blocks corresponding to the historical segmentation front, the sum of the multiple cutting edges of the instantiation tree corresponding to the historical segmentation front, the total time expected for parallel synthesis of the multiple circuit segmentation blocks corresponding to the historical segmentation front, the expected overall synthesis process time corresponding to the historical segmentation front, the time expected to be processed by the backend physical design tool corresponding to the historical segmentation front, and the circuit power performance area (PPA) corresponding to the historical segmentation front; determining the first segmentation front corresponding to the circuit according to the multiple historical segmentation fronts and the metrics corresponding to each historical segmentation front, where the first segmentation front is one of the multiple historical segmentation fronts.

[0018] The expected overall synthesis process time includes the total sum of the expected preprocessing, parallel synthesis, and postprocessing times.

[0019] Exemplarily, among multiple historical splitting fronts, the historical splitting front with the optimal corresponding metric can be selected as the first splitting front. For example, the higher the scale balance degree of the multiple circuit splitting blocks corresponding to the historical splitting front, the higher the possibility that the N splitting block groups corresponding to the N processing cores are balanced. The historical splitting front with the highest scale balance degree of the multiple circuit splitting blocks is selected as the first splitting front. The smaller the sum of the multiple cutting edges of the instantiation tree corresponding to the historical splitting front, the lower the dependency relationship between different splitting blocks. The historical splitting front with the smallest sum of the cutting edges is selected as the first splitting front. The less the total time expected for parallel synthesis of the multiple circuit splitting blocks corresponding to the historical splitting front, the less time consumed by the N processing cores to process the N splitting block groups. The historical splitting front with the least total time for parallel synthesis of the multiple circuit splitting blocks is selected as the first splitting front. Similarly, the historical splitting front with the least expected total synthesis process time, the least expected time processed by the backend physical design tool, and the optimal PPA can be selected as the first splitting front.

[0020] Optionally, the first splitting front can also be selected by synthesizing any combination of the above multiple metrics. For example, the historical splitting front with a relatively small total time for parallel synthesis of the multiple circuit splitting blocks and a relatively small sum of the multiple cutting edges is selected as the first splitting front.

[0021] This application provides a circuit splitting method, which can select the optimal splitting front according to different metrics corresponding to the splitting front, improve the load balance degree and utilization rate of multiple cores, and further improve the efficiency of parallel optimization of circuit splitting.

[0022] In combination with the first aspect, in some implementation manners of the first aspect, before determining the first splitting front corresponding to the circuit, the method further includes: obtaining the first splitting front, which is obtained by adjusting the second splitting front corresponding to the circuit, and the second splitting front is used to split the instantiation tree into multiple second splitting blocks.

[0023] This application provides a circuit splitting method, which can obtain multiple splitting fronts by continuously adjusting the splitting front, and then select the splitting front with the optimal metrics, which can improve the load balance degree and utilization rate of multiple cores, and further improve the efficiency of parallel optimization of circuit splitting.

[0024] In connection with the first aspect, in some implementations of the first aspect, obtaining the first segmentation front includes: obtaining the second segmentation front, where the second segmentation front includes a set of nodes near the bottom layer of the instantiation tree on the segmentation boundary that divides the instantiation tree into the multiple second segmentation blocks; determining a third segmentation block, where the third segmentation block is the segmentation block with the largest weight among the multiple second segmentation blocks; and replacing a first node in the second segmentation front with the next layer of nodes in the instantiation tree having the first node as the root node to obtain the first segmentation front, where the first node is the root node of the third segmentation block.

[0025] It should be understood that the weight of a segmentation block can be the sum of the weights of the nodes included in the segmentation block, or it can also be the sum of the weights of the nodes and the weights of the edges between the nodes in the segmentation block.

[0026] Exemplarily, the second segmentation front includes nodes N2, N3, N4, and N5. The third segmentation block where N3 is located is the segmentation block with the largest weight among the multiple second segmentation blocks. The next layer of nodes having N3 as the root node includes N9 to N13, then the first segmentation front includes nodes N2, N9 to N13, N4, and N5.

[0027] This application provides a circuit segmentation method. Multiple segmentation fronts can be obtained by continuously adjusting the segmentation front, and then the segmentation front with the optimal index can be selected, which can improve the load balancing degree and utilization rate of multiple cores, and further improve the efficiency of parallel optimization of circuit segmentation.

[0028] In connection with the first aspect, in some implementations of the first aspect, the multiple first segmentation blocks are multiple segmentation blocks after duplicate removal processing.

[0029] In a possible implementation, after the circuit segmentation front and structure are known, duplicate removal processing can be performed on the first segmentation blocks according to the names of the instances, etc., so as to reduce the total time for N processing cores to process tasks.

[0030] In connection with the first aspect, in some implementations of the first aspect, obtaining the instantiation tree corresponding to the circuit includes: obtaining the circuit high-level description file corresponding to the circuit; constructing the abstract syntax tree (AST) corresponding to the circuit according to the circuit high-level description file; and determining the instantiation tree according to the AST and a circuit learner, where the circuit learner is used to predict the weights of the nodes.

[0031] Optionally, the instantiation tree can also be directly determined according to the circuit high-level description file and the circuit learner. The circuit high-level description file includes, but is not limited to, verilog, intermediate representation (IR), etc.

[0032] Exemplarily, the high-level circuit description can be input into a lexical analyzer. The lexical analyzer will split the input code into individual lexical units (tokens), such as keywords, identifiers, operators, etc. Next, the lexical units are passed to a syntax analyzer for syntax analysis. The syntax analyzer constructs an abstract syntax tree according to the language's syntax rules. It can organize the lexical units into a tree structure, representing the structure and hierarchical relationship of the code.

[0033] The root node of the instantiation tree represents the top-level module of the entire design. A root node of the instantiation tree can be created according to the structure of the AST. Starting from the root node of the AST, traversal can be performed, for example, using traversal algorithms such as depth-first search or breadth-first search. According to the type and attributes of the AST nodes, processing is carried out, and corresponding instantiation tree nodes are created to represent the modules in the AST until the traversal is completed to obtain the instantiation tree.

[0034] Exemplarily, a circuit learner can be used to predict the weights of the instantiation tree nodes. The input of the circuit learner can be the circuit module-level AST with bit-width information (bit width), and the output is the comprehensive load corresponding to each module. The comprehensive load represents the time expected to process the circuit module corresponding to the node.

[0035] This application provides a circuit partitioning method. An instantiation tree can be obtained through a high-level circuit description file and a circuit learner, which is convenient for guiding and scheduling subsequent circuit partitioning.

[0036] In a second aspect, a computer device is provided. The device includes: an acquisition module, configured to acquire the instantiation tree corresponding to the circuit and the circuit partitioning configuration input by a user. The instantiation tree includes the weights of nodes, and the weights of the nodes are used to indicate the time expected to process the circuit module corresponding to the nodes. The circuit partitioning configuration includes the number N of processing cores for parallel synthesis of the circuit, and N is an integer greater than 1; a processing module, configured to determine N partitioning block groups corresponding to the circuit according to the instantiation tree and the circuit partitioning configuration. Each of the N partitioning block groups includes at least one first partitioning block, and the first partitioning block includes at least one of the nodes. The N partitioning block groups correspond one-to-one to the N processing cores, and the difference between the weights of any two of the N partitioning block groups does not exceed a preset threshold. The weight of the partitioning block group includes the sum of the weights of the nodes included in the partitioning block group.

[0037] In combination with the second aspect, in some implementation manners of the second aspect, the processing module is specifically configured to: determine a plurality of the first partitioning blocks corresponding to the circuit; and determine the N partitioning block groups according to the plurality of the first partitioning blocks.

[0038] In combination with the second aspect, in some implementations of the second aspect, the processing module is specifically configured to: determine a first splitting front corresponding to the circuit, where the first splitting front is used to split the instantiation tree into the multiple first splitting blocks.

[0039] In combination with the second aspect, in some implementations of the second aspect, the processing module is specifically configured to: obtain a plurality of historical splitting fronts and metrics corresponding to each historical splitting front in the plurality of historical splitting fronts, where the metrics include any one or more of the scale balance degree of the multiple circuit splitting blocks corresponding to the historical splitting front, the sum of the multiple cutting edges of the instantiation tree corresponding to the historical splitting front, the total time expected for parallel synthesis of the multiple circuit splitting blocks corresponding to the historical splitting front, the expected overall synthesis process time corresponding to the historical splitting front, the time expected for the back-end physical design tool to process the historical splitting front, and the circuit power consumption performance area PPA corresponding to the historical splitting front; determine the first splitting front corresponding to the circuit according to the plurality of historical splitting fronts and the metrics corresponding to each historical splitting front, where the first splitting front is one of the plurality of historical splitting fronts.

[0040] In combination with the second aspect, in some implementations of the second aspect, the obtaining module is further configured to obtain the first splitting front, where the first splitting front is obtained by adjusting a second splitting front corresponding to the circuit, and the second splitting front is used to split the instantiation tree into multiple second splitting blocks.

[0041] In combination with the second aspect, in some implementations of the second aspect, the obtaining module is specifically configured to: obtain the second splitting front, where the second splitting front includes a set of nodes near the bottom layer of the instantiation tree on the splitting boundary for splitting the instantiation tree into the multiple second splitting blocks; determine a third splitting block, where the third splitting block is the splitting block with the largest weight among the multiple second splitting blocks; replace a first node in the second splitting front with a node in the next layer of the instantiation tree with the first node as the root node to obtain the first splitting front, where the first node is the root node of the third splitting block.

[0042] In combination with the second aspect, in some implementations of the second aspect, the multiple first splitting blocks are multiple splitting blocks after duplicate removal processing.

[0043] In combination with the second aspect, in some implementations of the second aspect, the obtaining module is specifically configured to: obtain a circuit high-level description file corresponding to the circuit; construct an AST corresponding to the circuit according to the circuit high-level description file; determine the instantiation tree according to the AST and a circuit learner, where the circuit learner is used to predict the weight of the node.

[0044] The beneficial effects of the second aspect and any possible implementation manner of the second aspect correspond to those of the first aspect and any possible implementation manner of the first aspect, and thus will not be elaborated herein.

[0045] In a third aspect, an embodiment of the present application provides a computer device, which includes a processor for coupling with a memory, reading and executing instructions and / or program codes in the memory to execute the first aspect or any possible implementation manner of the first aspect.

[0046] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium storing program codes, which cause a computer to execute the first aspect or any possible implementation manner of the first aspect when the computer-readable storage medium runs on the computer.

[0047] In a fifth aspect, an embodiment of the present application provides a computer program product, which includes computer program codes that cause the computer to execute the first aspect or any possible implementation manner of the first aspect when the computer program codes run on the computer. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 FIG. is an exemplary flowchart of a circuit segmentation method provided by an embodiment of the present application.

[0049] Figure 2 FIG. is a schematic diagram of a segmentation front provided by an embodiment of the present application.

[0050] Figure 3 FIG. is an exemplary flowchart of parallel logic synthesis for circuit segmentation provided by an embodiment of the present application.

[0051] Figure 4 FIG. is a schematic diagram of multi-core loads corresponding to different segmentation fronts provided by an embodiment of the present application.

[0052] Figure 5 FIG. is a schematic diagram of instantiation tree segmentation provided by an embodiment of the present application.

[0053] Figure 6 FIG. is another exemplary flowchart of parallel logic synthesis for circuit segmentation provided by an embodiment of the present application.

[0054] Figure 7 FIG. is an exemplary flowchart of another circuit instantiation tree segmentation method provided by an embodiment of the present application.

[0055] Figure 8 FIG. is a schematic diagram of a segmentation front 710 provided by an embodiment of the present application.

[0056] Figure 9 It is a schematic diagram of an AST structure provided by an embodiment of the present application.

[0057] Figure 10 It is a schematic diagram of a cut-off front 720 provided by an embodiment of the present application.

[0058] Figure 11 It is a structural example diagram of a computer device provided by an embodiment of the present application.

[0059] Figure 12 It is a structural example diagram of another computer device provided by an embodiment of the present application.

[0060] Figure 13 It is an example diagram of a computer program product provided by an embodiment of the present application. Detailed implementation manners

[0061] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present application, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0062] In the embodiments of the present application, words such as "exemplary" and "for example" are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" in the present application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of the word "exemplary" is intended to present concepts in a specific manner.

[0063] The business scenarios described in the embodiments of the present application are for more clearly illustrating the technical solutions in the embodiments of the present application, and do not constitute a limitation on the technical solutions provided by the embodiments of the present application. Those of ordinary skill in the art can know that with the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0064] Referring to "one embodiment" or "some embodiments" etc. described in this specification means that specific features, structures or characteristics described in combination with the embodiment are included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. appearing in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0065] In this application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: including the case where A exists alone, A and B exist simultaneously, and B exists alone, where A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after. "At least one (item)" or its similar expression refers to any combination of these items, including any combination of single item or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, and c can be single or multiple.

[0066] To facilitate the understanding of the embodiments of this application, some definitions involved in this application are briefly described first.

[0067] 1. Electronic Design Automation (EDA): It refers to a design method that uses computer-aided design software to complete the functional design, synthesis, verification, physical design (including layout, wiring, layout, design rule checking, etc.) of large-scale integrated circuit chips.

[0068] 2. Operator: The basic unit of circuit function.

[0069] 3. Instance tree: A tree-like structure used to represent the design hierarchy in chip design. It describes the hierarchical relationship between various modules in the design, where each node represents an instance of a module. An instance is a uniquely identified (copied) module. After the module definition is designed, it may be called multiple times, and each call will create a unique instance point on the instance tree.

[0070] 4. Partition frontier: A set of nodes at the bottom layer on a cut boundary that can divide the circuit into non-overlapping parts during partitioning.

[0071] 5. Logic synthesis: A key step in the chip design process that converts high-level logical descriptions into low-level gate-level netlists or Boolean function representations.

[0072] 6. Subchip: Refers to a relatively small functional area or sub-module within a larger chip (referred to as the main chip or mother chip).

[0073] Circuit power consumption, performance, and area (PPA) are core metrics that concern developers and users of electronic design automation (EDA) tools. However, according to Moore's Law, as the scale of chips increases year by year, EDA tools need to process circuits of a larger scale. In addition to PPA, the running time (efficiency) of EDA tools is also a key factor in improving the work efficiency of EDA users, which is related to chip engineers obtaining timely feedback on the results of tool runs and the time to market of chips. Moreover, the efficiency optimization of EDA tools themselves can indirectly improve PPA.

[0074] To efficiently process large-scale circuits, multi-core parallel acceleration has become a common method to improve the running efficiency of EDA tools. Among them, circuit partitioning parallel optimization is the most commonly used acceleration method because of its small development volume and adaptability to various backend synthesis algorithms. Through the circuit partitioning method, the entire super-large circuit can be divided into multiple partition blocks, and then the hardware resources can be independently and parallelly invoked to optimize these multiple partition blocks. Therefore, the balance degree among the partition blocks processed by each processing core greatly affects the parallelism and efficiency of parallel optimization.

[0075] The circuit partitioning method provided in this application is based on the circuit hierarchical structure. It can automatically optimize the number of partitions according to the number of parallel cores, the predicted circuit synthesis load, and the total load after analog parallel task scheduling, improve the load balance degree and multi-core utilization rate, and greatly improve the user experience. At the same time, the circuit partitioning method provided in this application can estimate the impact of partitioning on the netlist PPA, optimize the netlist partitioning for comprehensive load balance and PPA optimization, and improve the PPA optimization effect of the netlist.

[0076] Figure 1 It is an exemplary flowchart of a circuit partitioning method provided by an embodiment of this application.

[0077] 110. Obtain the instantiation tree corresponding to the circuit and the circuit partitioning configuration input by the user.

[0078] The instantiation tree includes the weights of nodes, and the weights of nodes are used to indicate the time expected to be consumed for processing the circuit modules corresponding to the nodes. The circuit partitioning configuration includes the number N of processing cores for parallel synthesis of the circuit, and N is an integer greater than 1.

[0079] It should be understood that the instantiation tree is used to represent the circuit modules and the hierarchical relationship between each circuit module. Optionally, the instantiation tree may further include the weights of the edges between nodes, and the weights of the edges between nodes are used to indicate the tightness of the dependency relationship between the circuit modules corresponding to the nodes. Exemplarily, the weight of each node can be predicted according to a circuit learner, and the weight of the edge between nodes can be obtained by analyzing the instantiation relationship of the instantiation tree.

[0080] Optionally, the circuit splitting configuration input by the user may further include any one or more of the number of splitting iterations, the splitting target priority or weight, and the prior information of the sub-chip. The splitting target priority or weight can be used to indicate whether PPA is prioritized or the parallel synthesis efficiency is prioritized, for example. The prior information of the sub-chip includes the chip-level structure that has been defined when designing the chip.

[0081] 120. Determine N splitting block groups corresponding to the circuit.

[0082] Based on the instantiation tree and the circuit splitting configuration, N splitting block groups corresponding to the circuit can be determined. Each splitting block group includes at least one first splitting block, and the first splitting block includes at least one node of the instantiation tree. The N splitting block groups correspond one-to-one to N processing cores, and the difference in weights between any two of the N splitting block groups does not exceed a preset threshold. The weight of a splitting block group is the sum of the weights of the nodes included in the splitting block group.

[0083] Each first splitting block is a part of the instantiation tree, and each processing core is used to process the corresponding splitting block group. The fact that the difference in weights between any two of the N splitting block groups does not exceed a preset threshold means that the load of each processing core is balanced, and the time for each processing core to process the corresponding splitting block group is basically equal.

[0084] Optionally, the weight of a splitting block group can be the sum of the weights of the nodes included in the splitting block group, or it can also be the sum of the weights of the nodes and the weights between the nodes included in the splitting block group.

[0085] Figure 2 It is a schematic diagram of a splitting front provided by an embodiment of the present application.

[0086] Exemplarily, a certain instantiation tree includes nodes N1 to N19. Among them, N1 is located in the first layer, N2 to N5 are located in the second layer, and N6 to N19 are located in the third layer. The numbers in the nodes represent the weights of the nodes. For example, the weight of N1 is 20, and the weight of N2 is 10. This weight can be regarded as the time expected to be consumed for processing the module represented by the node. The splitting front refers to the set of nodes on the bottom layer of a non-intersecting splitting boundary when splitting the circuit. For example Figure 2 The shown splitting front includes nodes N2, N9 to N13, N4, N16 to N19. Figure 2The shown splitting front splits the circuit into a top-level block and a split-level block. N1, N3, and N5 belong to the top-level block, and N2, N4, N6 to N19 belong to the split-level block. Both the top-level block and the split-level block can be regarded as the corresponding split blocks of the circuit. Among them, the subtrees with the nodes included in the splitting front as the root nodes belong to different split-level blocks. For example, N2, N6 to N8 belong to the first split-level block, N9 belongs to the second split-level block, N10 belongs to the third split-level block, N11 belongs to the fourth split-level block, N12 belongs to the fifth split-level block, N13 belongs to the sixth split-level block, N4, N14, and N15 belong to the seventh split-level block, N16 belongs to the eighth split-level block, N17 belongs to the ninth split-level block, N18 belongs to the tenth split-level block, and N19 belongs to the eleventh split-level block.

[0087] Figure 3 It is an exemplary flowchart of performing logic synthesis in parallel for circuit splitting provided by an embodiment of the present application.

[0088] 310. Convert the high-level circuit description into an abstract syntax tree (AST).

[0089] The high-level circuit description is a method for abstracting and describing the behavior and function of a circuit. It is a high-level description used in circuit design to illustrate the function and operation of the circuit without involving the specific gate-level circuit implementation. Exemplarily, through register transfer level (RTL) design, a circuit can be described, including the flow of data, the execution of operations, and the change of states. RTL design can be represented by a hardware description language (HDL) such as Verilog or very-high-speed integrated circuit hardware description language (VHDL), and can be converted into a gate-level netlist through a synthesis tool for subsequent physical design and implementation.

[0090] Exemplarily, the high-level circuit description can be input into a lexical analyzer. The lexical analyzer will split the input code into individual lexical units (tokens), such as keywords, identifiers, operators, etc. Next, the lexical units are passed to a syntax analyzer for syntax analysis. The syntax analyzer constructs an abstract syntax tree according to the syntax rules of the language. It can organize the lexical units into a tree structure representing the structure and hierarchical relationship of the code.

[0091] 320. Establish an instantiation tree according to the abstract syntax tree.

[0092] The root node of the instantiation tree represents the top-level module of the entire design, and the root node of the instantiation tree can be created according to the structure of the AST. Starting from the root node of the AST, traversal can be performed, for example, using traversal algorithms such as depth-first search or breadth-first search, and processing according to the type and attributes of the AST nodes. Correspondingly, instantiation tree nodes are created to represent the modules in the AST until the traversal is completed, and the instantiation tree is obtained.

[0093] 330, predict the weights of the instantiation tree nodes and / or edges.

[0094] In the embodiments of the present application, a circuit learner is used to predict the weights of the instantiation tree nodes. The weight of a node can represent the comprehensive load of the circuit module corresponding to the node. The comprehensive load represents the time expected to process the circuit module corresponding to the node. Optionally, in some possible implementation manners, the weight of the node can also represent the predicted PPA impact of the circuit module corresponding to the node. By analyzing the instantiation relationship of the instantiation tree, the weights of the edges for estimating the PPA impact can be obtained. The weights of the edges between nodes are used to indicate the tightness of the dependency relationship between the circuit modules corresponding to the nodes.

[0095] Exemplarily, the input of the circuit learner can be a circuit module-level AST with bit-width information (bit width), and the output is the comprehensive load corresponding to each module. The AST contains various combinational and sequential expressions, such as unary operators, binary operators, single-bit (bit) operators, multi-bit operators, always blocks, etc. The always block is a syntax in Verilog used to describe combinational logic and sequential logic. Under the given backend synthesis setting conditions, the circuit high-level syntax tree representation composed of these expressions has determined the comprehensive load, PPA, etc. of the circuit. Therefore, theoretically, taking the AST as the input before synthesis can predict the circuit comprehensive load and PPA.

[0096] The feature extraction of the circuit AST representation can generally be divided into two categories: graph structure representation learning and vector feature representation learning.

[0097] Graph structure representation learning refers to learning the representation of nodes or graphs from graph structure data. In a graph structure, data is organized in the form of nodes and edges. Nodes represent entities, and edges represent the relationships between nodes. Common graph structure representation learning methods include graph convolutional networks (GCN), graph sample and aggregated (GraphSAGE), graph attention networks (GAT), etc. These methods construct the representation vectors of nodes by iteratively aggregating the neighbor information of nodes.

[0098] Vector feature representation learning refers to learning the representation of data from feature data in vector form. In vector feature representation learning, data is represented in the form of vectors, and each dimension corresponds to a feature. Common vector feature representation learning methods include decision tree (DT), multiple layer perceptron (MLP), principal component analysis (PCA), Autoencoder, etc. In some possible implementation manners, multiple features that can characterize the circuit characteristics and are related to the prediction target can be defined according to experience. Taking the prediction of the comprehensive load as an example, when traversing the AST, the distribution of circuit nodes of various bit widths and / or types can be counted, such as unary single-bit operators, unary multi-bit operators, binary single-bit operators, binary multi-bit operators, and other operators. Unary single-bit operators include bitwiseAnd, bitwiseOr, etc., unary multi-bit operators include plus, minus, bitwiseNot, etc., binary single-bit operators include equality, greaterThanEqual, etc., binary multi-bit operators include add, multiply, subtract, etc., and other operators include elementSelect, conditional, etc.

[0099] The use of the circuit learner includes two parts: offline training and online inference. To train the circuit learner, data pairs between the module-level circuit AST and the comprehensive load can be collected, and the data pairs can be saved when the comprehensive software runs in the module-parallel synthesis mode. After collecting a large number of AST-comprehensive load data pairs of different circuits, define the circuit learner model type and hyperparameters, and then train the model. After the model is trained, it is stored in a fixed location or uploaded to the model version repository for subsequent online inference. When the model is put into operation, given a new AST structure, the circuit learner extracts vectorized circuit features online, and then loads and infers the prediction model to obtain the comprehensive load prediction result of the module.

[0100] In the circuit splitting method provided by this application, the circuit learner has stronger robustness for predicting instantiated tree nodes and boundary weights. Because the splitting front evaluation index includes the sum of the weights of the splitting blocks composed of multiple nodes. If the prediction error satisfies the normal distribution, the expectation of the sum of the prediction errors of multiple nodes will be close to 0.

[0101] 340, split the instantiated tree.

[0102] In the embodiments of the present application, a circuit splitter is used to split the instantiation tree, so that the synthesis load of the split blocks processed by each processing core among multiple processing cores performing parallel synthesis is as balanced as possible, thereby improving the efficiency of parallel optimization.

[0103] Figure 4 It is a schematic diagram of the multi-core load corresponding to different split fronts provided by the embodiments of the present application.

[0104] Exemplarily, the processing tool includes two computing cores, core 1 and core 2. The split front 1 splits the circuit into three split blocks 1, 2, and 3. The split block 1 includes modules M1, M3, and M4. The split block 2 includes module M2 and module Top. The split block 3 includes module 5. Core 1 corresponds to processing the first split block group, and the first split block group includes split block 1 and split block 2. Core 2 corresponds to processing the second split block group, and the second split block group includes split block 3. Generally speaking, the time for parallel synthesis of the multiple split blocks corresponding to the split front 1 on core 1 and core 2 is about 90. The split front 2 splits the circuit into three split blocks 4, 5, and 6. The split block 4 includes modules M1, M3, and M4. The split block 5 includes module Top. The split block 6 includes module M2 and module 5. Core 1 corresponds to processing the third split block group, and the third split block group includes split block 4 and split block 5. Core 2 corresponds to processing the fourth split block group, and the fourth split block group includes split block 6. Generally speaking, the time for parallel synthesis of the multiple split blocks corresponding to the split front 2 on core 1 and core 2 is about 70. It can be seen that the splitting method of the split front 2 compared with the split front 1 can make the synthesis load of the split blocks processed by each processing core among multiple processing cores performing parallel synthesis as balanced as possible, thereby improving the efficiency of parallel optimization.

[0105] The input of the circuit splitter is an instantiation tree with node and / or edge weights. Among them, each node is a unique instantiated instance, and the edges between nodes represent instantiation relationships. It should be understood that an instance is a uniquely identified module. After the module definition is designed, it may be called multiple times, and each call will build a unique instance point on the instantiation tree.

[0106] The node weight is the prediction result of the circuit learner, and the weight of the edge for estimating the PPA impact can be obtained by analyzing the instantiation relationship. The present application provides a splitting method that can dynamically adjust the split front and automatically optimize the split front of the circuit instantiation tree according to the number of parallel cores of the processing tool, improve the synthesis load balance and multi-core utilization rate, and does not require the user to specify a large number of split algorithm parameters, which can improve the automation degree of the split algorithm and the user experience.

[0107] Figure 5 It is a schematic diagram of instantiation tree splitting provided by the embodiments of the present application. Node N1 is connected to Figure 3The top-level node of the illustrated instantiation tree corresponds to N1, N2 corresponds to the node of Module 1, N3 corresponds to the node of Module 2, N4 corresponds to the node of Module 3, N5 corresponds to the node of Module 4, and N6 corresponds to the node of Module 5. The weight of node N1 is 20, the weight of node N2 is 10, the weight of node N3 is 30, the weight of node N4 is 20, the weight of node N5 is 20, and the weight of node N6 is 50. The weight between N1 and N2 is 2, the weight between N1 and N3 is 9, the weight between N2 and N4 is 8, the weight between N2 and N5 is 9, and the weight between N3 and N6 is 1.

[0108] According to the selected cut front, the instantiation tree can be divided into multiple balanced cut blocks. It should be understood that the more balanced the estimated load between multiple cut blocks, the more likely the actual synthesis load of the cut blocks processed by each processing core in the parallel synthesis will be balanced, thereby improving the efficiency of parallel optimization. Figure 5 The shown cut front includes node N2 and node N6. This cut front divides the instantiation tree into three cut blocks. Among them, N1 and N3 are in the first cut block, N2, N4, and N5 are in the second cut block, and N6 is in the third cut block. It can be seen that the synthesis load of the first cut block is 20 + 30 = 50, the synthesis load of the second cut block is 10 + 20 + 20 = 50, and the synthesis load of the third cut block is 50. This cut front divides the instantiation tree into three balanced cut blocks, which can improve the efficiency of parallel optimization. At the same time, when selecting the cut front, the weights between nodes can also be considered, and edges with smaller weights are preferably selected for cutting. For example, Figure 5 The weights of the edges cut by the shown cut front are 2 and 1 respectively, which can reduce the dependence between different cut blocks and reduce the impact of cutting on the netlist PPA.

[0109] 350, schedule subtasks.

[0110] According to the estimated time for multiple processing cores to perform parallel synthesis on the cut blocks, each cut block can be assigned to multiple available processing cores so that they can process different subtasks simultaneously, and the synthesis load of each processing core for processing subtasks is balanced. Such a subtask can be, for example, logic synthesis. This parallel processing can maximize the computing power of the multi-core processor and accelerate the overall processing speed. Exemplarily, the order of scheduling subtasks can be determined according to the dependency relationship and synthesis load between the cut blocks. Such a task division can improve the efficiency of parallel optimization. In some possible implementation manners, the load on each processor can also be balanced as much as possible according to the size and processing complexity of the cut blocks. If some cut blocks are larger or more complex than other cut blocks, they can be assigned to processors with higher performance to ensure overall load balance.

[0111] In a possible implementation, after knowing the slicing frontiers and structures of the circuit, the sliced blocks can be de-duplicated according to the names of the instances, etc. Exemplarily, Module 3 and Module 4 have the same function, which means that only one of Module 3 and Module 4 can be selected for processing, thereby reducing the total time for task execution.

[0112] 360, perform logic synthesis to generate a gate-level netlist.

[0113] Through logic synthesis, the design can be transformed from a high-level RTL description to a low-level gate-level netlist representation, enabling subsequent steps such as physical design, placement and routing, and verification to be carried out. RTL synthesis and Bit synthesis in the logic synthesis process are respectively responsible for RTL-level and bit-level circuit logic optimization and technology mapping to obtain better design metrics such as performance, power consumption, and area.

[0114] Figure 6 is an exemplary flowchart of another method for performing logic synthesis in parallel with circuit slicing provided by an embodiment of the present application. Figure 6 and Figure 3 correspond to steps 380 and 390 of

[0115] 380, train the circuit learner.

[0116] Exemplarily, the circuit learner can be offline trained according to the circuit representation and synthesis load data pair saved offline, and then the circuit learner can be used for online inference to predict the synthesis load of the new circuit representation.

[0117] 390, optimize the circuit slicer.

[0118] Optionally, the circuit slicer can also be optimized according to the execution order of multiple subtasks to improve the prediction accuracy and slicing efficiency of the multi-core load after parallel scheduling of the actual tasks by the slicing. Optionally, the PPA optimization effect after slicing can also be estimated to improve the PPA optimization effect of the slicing.

[0119] In a possible implementation, after knowing the circuit slicing frontiers and structures, the sliced blocks can be de-duplicated according to the names of the instances, etc. Exemplarily, Module 13 and Module 14 in the sliced block 12 have the same function, which means that only one of Module 13 and Module 14 can be selected for processing. Therefore, an embodiment of the present application can also select to optimize the circuit slicer according to the order after parallel scheduling of the de-duplicated slicing tasks.

[0120] Figure 7 is an exemplary flowchart of another circuit instantiation tree slicing method provided by an embodiment of the present application.

[0121] 610, obtain the circuit slicing configuration.

[0122] Exemplarily, the circuit splitting configuration specified by the user can be obtained in the software interface or the configuration file. The circuit splitting configuration includes the number of parallel synthesis cores. Optionally, it can also include any one or more of the number of splitting iterations, the priority or weight of the splitting target, and the prior information of the sub-chip. The number of parallel synthesis cores is the number of processing cores for parallel synthesis of the circuit. The priority or weight of the splitting target can be used to indicate whether PPA is prioritized or the parallel synthesis efficiency is prioritized. The prior information of the sub-chip includes the chip-level structure that has been defined during the design of the chip.

[0123] 620, obtain the weight prediction result.

[0124] Obtain the weight prediction of the module. Optionally, the weight prediction result of the boundary between modules can also be obtained. The weight of the module can be predicted using a circuit learner, and the weight of the boundary between modules can be obtained by analyzing the instantiation relationship of the instantiation tree.

[0125] 630, construct and initialize the instantiation tree.

[0126] Construct the circuit instantiation tree structure and initialize the instantiation tree with the prediction result of step 620.

[0127] It should be understood that the execution order of 620 and 630 is only an example. It is also possible to construct the instantiation tree first and then obtain the weight prediction result. This example should not be construed as a limitation to the present application.

[0128] 640, initialize the splitting front.

[0129] Figure 8 It is a schematic diagram of a splitting front 710 provided by an embodiment of the present application. The splitting front 710 is a splitting front initialized by an instantiation tree. The splitting front 710 includes nodes N2, N3, N4, and N5. The splitting front 710 splits the circuit into a top-level block and a split-level block. N1 belongs to the top-level block, and N2 to N19 belong to the split-level block. Among them, the subtrees with the nodes included in the splitting front 710 as the root nodes belong to different split-level blocks. For example, N2, N6 to N8 belong to the first split-level block, N3, N9 to N13 belong to the second split-level block, N4, N14, and N15 belong to the third split-level block, and N5, N16 to N19 belong to the fourth split-level block.

[0130] Optionally, the prior information specified by the user can also be used as the initialization of the splitting front. The above example should not be construed as a limitation to the present application.

[0131] 650, adjust the splitting front.

[0132] Adjusting the current splitting front can obtain a new splitting front. In one possible implementation, from the multiple splitting blocks corresponding to the current splitting front, the splitting block with the largest weight can be selected, and the node M belonging to the current splitting front in the splitting block with the largest weight is moved to the top-level block. The new splitting front can be regarded as replacing the original node M with the next-level nodes with node M as the root node in the current splitting front, that is, splitting the subtree with node M as the root node into multiple subtrees with the next-level nodes of node M as the root nodes.

[0133] Figure 9 It is a schematic diagram of an AST structure provided by an embodiment of the present application. A node will have a large number of small nodes. During the process of dynamically moving down the splitting front, a large number of small splitting blocks will be generated. These small splitting blocks have little impact on the synthesis efficiency, and a large number of nodes can be deduplicated when tasks are dispatched. Therefore, small splitting blocks can be ignored, and key attention can be paid to the splitting blocks with larger weights.

[0134] Exemplarily, the current splitting front is splitting front 710, and splitting front 710 includes nodes N2, N3, N4, and N5. N2, N6 to N8 belong to the first split layer block, N3, N9 to N13 belong to the second split layer block, N4, N14, and N15 belong to the third split layer block, and N5, N16 to N19 belong to the fourth split layer block. The weight of the first split layer block corresponding to splitting front 710 is 10 + 10 + 10 + 10 = 40, the weight of the second split layer block is 10 + 50 + 45 + 40 + 44 + 51 = 240, the weight of the third split layer block is 10 + 20 + 15 = 45, and the weight of the fourth split layer block is 10 + 40 + 39 + 52 + 51 = 192. The weight of the second split layer block is the largest. Move node N3 to the top-level block to adjust and obtain a new splitting front 720. Figure 10 It is a schematic diagram of a splitting front 720 provided by an embodiment of the present application. Splitting front 720 includes nodes N2, N9 to N13, N4, and N5, and can be regarded as replacing the original node N3 with the next-level nodes with node N3 as the root node in the original splitting front 710. At this time, splitting front 720 splits the circuit into a top-level block and split layer blocks. N1 and N3 belong to the top-level block, and N2, N4 to N19 belong to the split layer blocks. Among them, the subtrees with the nodes included in splitting front 720 as the root nodes belong to different split layer blocks respectively. For example, N2, N6 to N8 belong to the first split layer block, N9 belongs to the second split layer block, N10 belongs to the third split layer block, N11 belongs to the fourth split layer block, N12 belongs to the fifth split layer block, N13 belongs to the sixth split layer block, N4, N14, and N15 belong to the seventh split layer block, and N5, N16 to N19 belong to the eighth split layer block.

[0135] By analogy, by continuously adjusting the segmentation front from top to bottom, multiple segmentation fronts and multiple segmentation blocks corresponding to the segmentation fronts can be obtained.

[0136] It should be understood that taking the sum of the node weights in the segmentation block as the weight of the segmentation block in the above example is only an example. It is also possible to take the sum of the node weights and the boundary weights between nodes in the segmentation block as the weight of the segmentation block. At the same time, in the above example, selecting the node M belonging to the current segmentation front in the segmentation block with the largest weight and moving it to the top-level block is only one possible implementation method. In other possible implementation methods, it is also possible to select the node M belonging to the current segmentation front in the segmentation block with the second largest weight, the third largest weight, or randomly, and the above example should not be construed as a limitation to this application.

[0137] Optionally, other strategies can also be used to select the points to be segmented, or feasible segmentation fronts can be completely randomly generated. For example, edges with smaller boundary weights between nodes can be first selected as the cutting edges to generate segmentation blocks.

[0138] 660, evaluate the current segmentation front.

[0139] Evaluate the indicators corresponding to the current segmentation front. Exemplarily, the balance degree of the scales of the segmentation blocks corresponding to the segmentation front, the sum of all boundary weights of the segmentation blocks, the total time of parallel synthesis after estimating the scheduling subtasks, the estimated total time of the entire synthesis process, the overall time processed by the backend physical design tool, the synthesis PPA, etc. can be evaluated, either any one or multiple of them. Among them, the estimated total time of the entire synthesis process includes the sum of the estimated preprocessing, parallel synthesis, and postprocessing times.

[0140] In one possible implementation method, after the circuit segmentation front and structure are known, the segmentation blocks can be de-duplicated according to the names of the instances, etc. Therefore, the embodiments of this application can also select the total time of parallel synthesis after estimating the scheduling subtasks of the de-duplicated segmentation blocks as the indicator of the segmentation front.

[0141] Exemplarily, the top-level balance degree, the segmentation layer balance degree, and the total balance degree corresponding to the current segmentation front can be calculated. It should be understood that the segmentation difficulties of different ASTs are different. ASTs with more balanced structures and smaller variances of node weights are usually easier to segment. Therefore, for a specific AST, the embodiments of this application can monitor and record the segmentation front corresponding to the current minimum imbalance degree.

[0142] 665, save the current segmentation front.

[0143] Save the current segmentation front and the corresponding indicators to the historical segmentation front set.

[0144] 670, determine whether the termination condition is satisfied.

[0145] If the preset termination condition is satisfied, step 680 is executed; otherwise, step 650 is executed again. Exemplarily, it is possible to determine whether to terminate or prematurely terminate the adjustment and optimization of the partitioning front according to the number of partitioning times and the historical partitioning index sequence. Determining whether the termination condition is satisfied according to the historical partitioning index sequence includes, but is not limited to, determining whether the termination condition is satisfied according to indicators such as the estimated load change curve, relative gain, and partitioning weight change curve.

[0146] 680. Select the optimal partitioning front.

[0147] According to the partitioning fronts and corresponding indicators saved in the historical partitioning front set, select the optimal partitioning front as the output. The selection criteria include, but are not limited to, the optimal load balance degree, the optimal estimated parallel comprehensive total time, the optimal estimated parallel comprehensive total time, the score of the optimal cutting edge weight, the optimal multi-objective score calculated according to the user-specified priority or weight, etc.

[0148] Optionally, embodiments of the present application may also choose to visualize the historical partitioning front or the historical partitioning result.

[0149] The circuit partitioning method proposed in the present application adopts a top-down partitioning process and can dynamically adjust the partitioning front. That is, by moving the root node in the most time-consuming partitioning block on the partitioning front to the top-level partitioning block, the most time-consuming partitioning block is split into multiple less time-consuming partitioning blocks, so that the time consumption of multiple partitioning blocks of the instantiation tree is as balanced as possible, and thus the time consumption of the partitioning blocks corresponding to each processing core is as balanced as possible. At the same time, the circuit partitioning method proposed in the present application can automatically optimize the partitioning front of the circuit instantiation tree according to the number of parallel cores, improving the load balance degree and multi-core utilization rate. Without the need for the user to specify a large number of partitioning algorithm parameters, the automation degree of the partitioning method and the user experience are improved.

[0150] The circuit partitioning method provided by the present application can improve the load balance degree of ultra-large-scale circuit partitioning, improve the partitioning robustness, increase the parallel synthesis efficiency by an average of 51.4%, and the end-to-end overall synthesis efficiency by 32.5%, with basically no deterioration of the synthesis efficiency. At the same time, the circuit partitioning method provided by the present application can effectively reduce the sub-circuit scale, facilitating the verification of the functional correctness of the netlist before and after synthesis.

[0151] The circuit partitioning method provided by this application can predict the back-end EDA tool load and PPA based on the high-level circuit representation before executing the EDA tool, realizing ultra-large-scale circuit partitioning that takes into account both load balancing and PPA, and can be used to accelerate various EDA logic synthesis tools, including but not limited to application specific integrated circuit (ASIC), field-programmable gate array (FPGA), emulation (EMU) synthesis, etc. In addition, after circuit partitioning, the logic synthesis and physical design of each block can also be executed in parallel. Therefore, the circuit partitioning method provided by this application can also be used to accelerate the entire EDA process.

[0152] The above describes the circuit partitioning method according to the embodiments of this application. The following will separately describe Figure 11 and Figure 12 the apparatuses and devices according to the embodiments of this application.

[0153] The embodiments of this application also provide a computer storage medium, in which program instructions are stored. When the program is executed, it may include some or all of the steps of the circuit partitioning method in the corresponding embodiments such as Figure 1 , Figure 3 , Figure 6 and Figure 7 .

[0154] Figure 11 FIG. 1100 is a structural example diagram of a computer device 1100 provided by the embodiments of this application. The computer device 1100 includes an acquisition module 1110 and a processing module 1120. The acquisition module 1110 and the processing module 1120 can be implemented by software, hardware, or a combination of both. The computer device 1100 can be an EDA software tool or a related module or device installed with the tool.

[0155] Among them, the acquisition module 1110 is used to acquire the instantiation tree corresponding to the circuit and the circuit partitioning configuration input by the user, so as to execute Figure 1 110 in the Figure 6 method and

[0156] 610 in Figure 1 . Figure 3 . Figure 6 The processing module 1120 is used to execute some or all of the steps in the Figure 7 method according to the instantiation tree and the circuit partitioning configuration, and determine N cut block groups corresponding to the circuit.

[0157] Figure 12FIG. 0 is a structural example diagram of another computer device 1200 provided by an embodiment of the present application. The computer device 1200 includes a processor 1202, a communication interface 1203, and a memory 1204. An example of the computer device 1200 is a computing device, such as a server for performing EDA simulation.

[0158] The method disclosed in the above embodiment of the present application can be applied to or implemented by the processor 1202. The processor 1202 may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. In the implementation process, the steps of the above method may be completed by the integrated logic circuit in the hardware of the processor 1202 or the instructions in the form of software. The various methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed and completed by a hardware decoding processor, or executed and completed by a combination of hardware and software modules in the decoding processor.

[0159] The memory 1204 can be a volatile memory, a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory of the methods described herein is intended to include but not be limited to these and any other suitable types of memory.

[0160] Communication can occur between the processor 1202, the memory 1204, and the communication interface 1203 via a bus. Executable code is stored in the memory 1204, and the processor 1202 reads the executable code in the memory 1204 to execute the corresponding method. Other software modules required for running processes, such as an operating system, can also be included in the memory 1204. The operating system can be LINUX TM , UNIX TM , WINDOWS TM and so on.

[0161] For example, the executable code in the memory 1204 is used to implement Figure 1 , Figure 3 , Figure 6 and Figure 7 the methods shown, and the processor 1202 reads the executable code in the memory 1204 to execute Figure 1 , Figure 3 , Figure 6 and Figure 7 the methods shown.

[0162] In some embodiments of the present application, the disclosed method may be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or encoded on other non-transitory media or articles. Figure 13 A conceptual partial view of an example computer program product arranged in accordance with at least some of the embodiments presented herein is schematically shown, the example computer program product including a computer program for executing a computer process on a computing device. In one embodiment, the example computer program product 1300 is provided using a signal-bearing medium 1301. The signal-bearing medium 1301 may include one or more program instructions 1302 which, when run by one or more processors, may provide the functions or portions of the functions described above for Figure 1 , Figure 3 , Figure 6 and Figure 7 shown in the methods. Thus, for example, with reference to Figure 1 , Figure 3 , Figure 6 and Figure 7 shown in the embodiments, one or more of the features therein may be carried out by one or more instructions associated with the signal-bearing medium 1301.

[0163] In some examples, the signal-bearing medium 1301 may include a computer-readable medium 1303, such as but not limited to, a hard disk drive, a compact disk (CD), a digital video disk (DVD), a digital tape, a memory, a read-only memory (ROM), or a random access memory (RAM), and so on. In some embodiments, the signal-bearing medium 1301 may include a computer-recordable medium 1304, such as but not limited to, a memory, a read / write (R / W) CD, an R / W DVD, and so on. In some embodiments, the signal-bearing medium 1301 may include a communication medium 1305, such as but not limited to, a digital and / or analog communication medium (e.g., an optical fiber cable, a waveguide, a wired communication link, a wireless communication link, and so on). Thus, for example, the signal-bearing medium 1301 may be conveyed by a wireless form of the communication medium 1305 (e.g., a wireless communication medium compliant with the IEEE 802.11 standard or other transmission protocols). One or more program instructions 1302 may be, for example, computer-executable instructions or logic implementation instructions. In some examples, the foregoing computing device may be configured to provide various operations, functions, or actions in response to the program instructions 1302 communicated to the computing device via one or more of the computer-readable medium 1303, the computer-recordable medium 1304, and / or the communication medium 1305. It should be understood that the arrangements described herein are for illustrative purposes only. Thus, those skilled in the art will understand that other arrangements and other elements (e.g., machines, interfaces, functions, sequences, and groups of functions, etc.) can be used instead, and some elements may be omitted altogether depending on the desired results. Additionally, many of the elements described can be implemented as discrete or distributed components, or as functional entities combined with other components in any suitable combination and location.

[0164] Those of ordinary skill in the art can realize that the units and method steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Skilled artisans can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0165] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the devices and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0166] In several embodiments provided by this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical or other forms.

[0167] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they can be located in one place, or they can be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0168] In addition, in each embodiment of this application, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0169] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of this application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0170] As described above, the above are only the specific implementation manners of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A circuit segmentation method, characterized in that, Including: Obtain the instantiation tree corresponding to the circuit and the circuit partitioning configuration input by the user. The instantiation tree includes the weights of nodes, and the weight of a node is used to indicate the time expected to be consumed for processing the circuit module corresponding to the node. The circuit partitioning configuration includes the number N of processing cores for parallel synthesis of the circuit, and N is an integer greater than 1; According to the instantiation tree and the circuit partitioning configuration, determine N partitioning block groups corresponding to the circuit. Each partitioning block group includes at least one first partitioning block, and the first partitioning block includes at least one of the nodes. The N partitioning block groups correspond one-to-one to the N processing cores, and the difference in weights between any two of the N partitioning block groups does not exceed a preset threshold. The weight of a partitioning block group includes the sum of the weights of the nodes included in the partitioning block group.

2. The method according to claim 1, wherein The determining the N partitioning block groups corresponding to the circuit includes: Determine a plurality of the first partitioning blocks corresponding to the circuit; Determine the N partitioning block groups according to the plurality of the first partitioning blocks.

3. The method according to claim 2, characterized in that The determining the plurality of the first partitioning blocks corresponding to the circuit includes: Determine a first partitioning front corresponding to the circuit, and the first partitioning front is used to divide the instantiation tree into the plurality of the first partitioning blocks.

4. The method according to claim 3, wherein The determining the first partitioning front corresponding to the circuit includes: Obtain a plurality of historical partitioning fronts and the metrics corresponding to each historical partitioning front among the plurality of historical partitioning fronts. The metrics include any one or more of the scale balance degree of the plurality of circuit partitioning blocks corresponding to the historical partitioning front, the sum of the plurality of cutting edges of the instantiation tree corresponding to the historical partitioning front, the total time expected for parallel synthesis of the plurality of circuit partitioning blocks corresponding to the historical partitioning front, the expected overall synthesis process time corresponding to the historical partitioning front, the time expected to be processed by the backend physical design tool corresponding to the historical partitioning front, and the circuit power consumption performance area PPA corresponding to the historical partitioning front; According to the plurality of historical partitioning fronts and the metrics corresponding to each historical partitioning front, determine the first partitioning front corresponding to the circuit, and the first partitioning front is one of the plurality of historical partitioning fronts.

5. The method according to claim 3 or 4, characterized in that, Before the determining the first partitioning front corresponding to the circuit, the method further includes: Obtain the first partitioning front, and the first partitioning front is obtained by adjusting a second partitioning front corresponding to the circuit. The second partitioning front is used to divide the instantiation tree into a plurality of second partitioning blocks.

6. The method according to claim 5, characterized in that, The obtaining the first partitioning front includes: Obtain the second partitioning front, and the second partitioning front includes a set of nodes on the cutting boundary that divides the instantiation tree into the plurality of second partitioning blocks and is close to the bottom layer of the instantiation tree; Determine a third partitioning block, and the third partitioning block is the partitioning block with the largest weight among the plurality of second partitioning blocks; Replace a first node in the second partitioning front with a node in the next layer of the instantiation tree with the first node as the root node to obtain the first partitioning front, and the first node is the root node of the third partitioning block.

7. The method according to any one of claims 2 to 6, characterized in that, The multiple first segmentation blocks are multiple segmentation blocks after duplicate removal processing.

8. The method according to any one of claims 1 to 7, characterized in that, The obtaining of the instantiation tree corresponding to the circuit includes: Obtaining a high-level circuit description file corresponding to the circuit; Constructing an abstract syntax tree AST corresponding to the circuit according to the high-level circuit description file; Determining the instantiation tree according to the AST and a circuit learner, where the circuit learner is used to predict the weights of the nodes.

9. A computer device, characterized in that, Including: An obtaining module, configured to obtain the instantiation tree corresponding to the circuit and a circuit segmentation configuration input by a user. The instantiation tree includes the weights of nodes, and the weights of the nodes are used to indicate the time consumed for processing the circuit modules corresponding to the nodes. The circuit segmentation configuration includes the number N of processing cores for parallel synthesis of the circuit, and N is an integer greater than 1; A processing module, configured to determine N segmentation block groups corresponding to the circuit according to the instantiation tree and the circuit segmentation configuration. Each segmentation block group includes at least one first segmentation block, and the first segmentation block includes at least one of the nodes. The N segmentation block groups correspond one-to-one to N processing cores, and the difference between the weights of any two of the N segmentation block groups does not exceed a preset threshold. The weight of a segmentation block group includes the sum of the weights of the nodes included in the segmentation block group.

10. The device according to claim 9, characterized in that, The processing module is specifically configured to: Determine multiple first segmentation blocks corresponding to the circuit; Determine the N segmentation block groups according to the multiple first segmentation blocks.

11. The device according to claim 10, characterized in that, The processing module is specifically configured to: Determine a first segmentation frontier corresponding to the circuit, where the first segmentation frontier is used to segment the instantiation tree into the multiple first segmentation blocks.

12. The device according to claim 11, characterized in that, The processing module is specifically configured to: Obtain multiple historical segmentation frontiers and metrics corresponding to each historical segmentation frontier among the multiple historical segmentation frontiers. The metrics include any one or more of the scale balance degree of multiple circuit segmentation blocks corresponding to the historical segmentation frontier, the sum of multiple cutting edges of the instantiation tree corresponding to the historical segmentation frontier, the total time expected for parallel synthesis of the multiple circuit segmentation blocks corresponding to the historical segmentation frontier, the expected comprehensive full-process time corresponding to the historical segmentation frontier, the time expected to be processed by a backend physical design tool corresponding to the historical segmentation frontier, and the circuit power consumption performance area PPA corresponding to the historical segmentation frontier; Determine the first segmentation frontier corresponding to the circuit according to the multiple historical segmentation frontiers and the metrics corresponding to each historical segmentation frontier, where the first segmentation frontier is one of the multiple historical segmentation frontiers.

13. The device according to claim 11 or 12, characterized in that, The obtaining module is further configured to obtain the first segmentation frontier, where the first segmentation frontier is obtained by adjusting a second segmentation frontier corresponding to the circuit, and the second segmentation frontier is used to segment the instantiation tree into multiple second segmentation blocks.

14. The device according to claim 13, characterized in that, The obtaining module is specifically configured to: Obtain the second segmentation frontier, where the second segmentation frontier includes a set of nodes on the segmentation boundary that is close to the bottom layer of the instantiation tree when the instantiation tree is segmented into the multiple second segmentation blocks. Determine the third split block, where the third split block is the split block with the largest weight among the multiple second split blocks; Replace the first node in the second split front with the next-level node in the instantiated tree with the first node as the root node to obtain the first split front, where the first node is the root node of the third split block.

15. The device according to any one of claims 10 to 14, characterized in that The multiple first split blocks are multiple split blocks after duplicate removal processing.

16. The device according to any one of claims 9 to 15, characterized in that The obtaining module is specifically configured to: Obtain the high-level circuit description file corresponding to the circuit; Construct the abstract syntax tree AST corresponding to the circuit according to the high-level circuit description file; Determine the instantiated tree according to the AST and the circuit learner, where the circuit learner is used to predict the weight of the node.

17. A computer device, characterized in that, Include: A processor, which is used to be coupled with a memory, read and execute instructions and / or program codes in the memory to execute the method according to any one of claims 1-8.

18. A computer-readable medium, characterized in that, The computer-readable medium stores computer program codes, and when the computer program codes are run on a computer, the computer is caused to execute the method according to any one of claims 1-8.

19. A computer program product, characterized in that, The computer program product includes computer program codes, and when the computer program codes are run on a computer, the computer is caused to execute the method according to any one of claims 1-8.

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