Defect analysis method based on wafer image overlay, electronic equipment, storage medium and program product

Abstract

The invention provides a defect analysis method based on wafer image overlay, electronic equipment, a storage medium and a program product. Relates to the technical field of image processing. The method comprises the following steps: obtaining a plurality of wafer images; extracting calibration features on each wafer image; performing alignment processing on the plurality of wafer images based on the calibration features to obtain a plurality of aligned wafer images; according to a preset superposition rule, carrying out superposition operation on the plurality of aligned wafer images to obtain a superposed image; extracting defect features on the superposed image; and according to the defect characteristics, analyzing in combination with the state information of each part in the working process in the production process to obtain factors causing defects. According to the method, the wafer image is subjected to superposition processing, and defect analysis is carried out based on the superposed image, so that factors of defect generation can be accurately positioned, the occurrence frequency and the distribution rule of the defects can be counted, and the reliability of a defect detection result is improved.

Description

Technical Field

[0001] The present application relates to the field of image processing technology, and in particular, to a defect analysis method, an electronic device, a storage medium, and a program product based on wafer image superposition diagrams. Background Art

[0002] In the field of industrial manufacturing, for example, in the process of wafer production, the process is complex. In order to ensure production quality, wafer images need to be collected at multiple nodes during the production process to provide data for subsequent defect detection.

[0003] The purpose of defect analysis is to mine and analyze the defect information and other production information of the product to find and locate the causes of product defects. Specifically, locate the production process where the defect occurs, and even which specific device, or which raw material, which process parameter, which production personnel, and a series of production factors.

[0004] Currently, defect analysis is to compare multiple images through manual experience to determine the root cause of the defect. This method relying on manual analysis, on the one hand, depends on human experience. If the experience is insufficient, the accurate cause of the defect cannot be determined; on the other hand, people can only compare and analyze the characteristics of the general area by feeling, and the accuracy is not enough; when there are thousands of pictures, it is very difficult for people to perform a full-scale comparison analysis, and some defect information may be overlooked, resulting in inaccurate defect analysis. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a defect analysis method, an electronic device, a storage medium, and a program product based on wafer image superposition diagrams to improve the accuracy of defect analysis.

[0006] In a first aspect, the embodiments of the present application provide a defect analysis method based on wafer image superposition diagrams, including: Obtain multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes, or images of different wafers in the same production process; Extract the calibration features on each wafer image, where the calibration features are the features used for positioning when aligning multiple wafer images; Align the multiple wafer images based on the calibration features to obtain the aligned multiple wafer images; Perform a superposition operation on the aligned multiple wafer images according to a preset superposition rule to obtain a superposition image; Extract the defect features on the superposition image; Analyze according to the defect features, combined with the state information of each component during the working process in the production process, to obtain the factors causing the defects.

[0007] In the embodiments of the present application, since different production processes may introduce different types of defects, therefore, by performing an overlay process on the images of the same wafer in different production processes and then performing defect analysis based on the superimposed image, the specific process link where the defect occurs can be identified more accurately, and thus the source of the defect can be accurately located. And by analyzing the superimposed images of different wafers in the same production process, the frequency and distribution law of the defect occurrence can be statistically analyzed, which can reduce the probability of misjudgment caused by accidental factors of a single wafer and improve the reliability of the defect detection result.

[0008] In a possible implementation manner of the first aspect, the image type of the wafer image is an AOI image; the defect information of the wafer image, where the defect information includes the defect type and the defect position; the superimposed image includes a first single-defect superimposed image; according to a preset superimposing rule, performing a superimposing operation on the aligned multiple wafer images to obtain a superimposed image, including: Based on the defect type, extracting defect images containing a single defect type from the wafer images; For the defect images of the same defect type, counting the number of first defect images with defects at the same pixel position; Generating a first single-defect superimposed image according to the number of first defect images.

[0009] In the embodiments of the present application, defect images containing a single defect type are extracted from the wafer images based on the defect type, so that subsequent defect analysis can focus on specific types of defects and can clearly reflect the frequency of a certain defect at each pixel position, providing data support for accurately locating high-defect-risk areas.

[0010] In a possible implementation manner of the first aspect, the superimposed image further includes a multi-defect superimposed image, and the method further includes: Counting the number of second defect images with a first target defect type at the same pixel position in the first single-defect superimposed image, and generating a multi-defect superimposed image according to the number of second defect images; where the first target defect type is all defect types or some defect types selected from all defect types.

[0011] In the embodiments of the present application, when superimposing images of a single defect, by counting the number of second defect images with a first target defect type at the same pixel position, the severity of the defect can be more accurately quantified.

[0012] In a possible implementation manner of the first aspect, generating a first single-defect superimposed image according to the number of first defect images includes: Determining the color parameter corresponding to the pixel position according to the number of first defect images corresponding to each pixel position; Render a first single-defect superposition image based on color parameters.

[0013] In an exemplary embodiment of the present application, based on the number of defective images at each pixel position, corresponding colors are used for rendering, so that the defect distribution of the first single-defect superposition image is more intuitively displayed.

[0014] In a possible implementation manner of the first aspect, the image type of the wafer image is an AOI image; the defect information of the wafer image includes the defect type and the defect position; the superposition image includes a second single-defect superposition image; according to a preset superposition rule, multiple aligned wafer images are superposed to obtain a superposition image, including: Extract defect images containing a single defect type from the wafer image based on the defect type; Perform grid division on the defect images corresponding to each defect type to obtain multiple grid images; For each defect type, count the number of defective chips contained in each grid image in the corresponding defect image; According to the number of defective chips contained in each grid image obtained by statistics, calculate the superposition value corresponding to the grid images at the same position in multiple defect images of the same defect type according to a preset superposition algorithm, and generate a second single-defect superposition image based on the superposition value.

[0015] In a possible implementation manner of the first aspect, the superposition image further includes a second multi-defect superposition image, and the method further includes: Count the number of chips with a second target defect type on the same grid image in the second single-defect superposition image, and generate a second multi-defect superposition image according to the number of chips; wherein, the second target defect type is all defect types or some defect types selected from all defect types.

[0016] In an exemplary embodiment of the present application, by counting the number of defective chips contained in each grid image, the number of defects can be quantified, which helps to compare the defect densities in different regions; the second single-defect superposition images corresponding to the second target defect types are superposed again to obtain the final superposition image. This enables the simultaneous observation of the distributions of multiple defect types on the entire wafer, facilitating the analysis of whether there is an associated distribution between different defect types.

[0017] In a possible implementation manner of the first aspect, the image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter values at each pixel position of the wafer; according to a preset superposition rule, multiple aligned wafer images are superposed to obtain a superposition image, including: Perform superposition calculations on the target measurement parameter values at the same pixel position in multiple wafer images according to a preset superposition algorithm to obtain a first superposition parameter value; the preset superposition algorithm includes summation, mean calculation, variance calculation, and standard deviation calculation; Generate a superposition image based on the first superposition parameter value.

[0018] In the embodiments of the present application, by performing superposition calculations on multiple wafer mapping images generated based on the target measurement parameter values at each pixel position according to a preset superposition algorithm, a first superposition parameter value can be obtained, thereby realizing the precise quantification of the target measurement parameter values. The generated superposition image can intuitively display the overall distribution and variation of the wafer measurement parameters.

[0019] In a possible implementation manner of the first aspect, the image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter values of the wafer at each pixel position; according to a preset superposition rule, perform a superposition operation on the aligned multiple wafer images to obtain a superposition image, including: Divide each wafer image into grids to obtain multiple second grid images corresponding to each wafer image; Calculate the mean value of the target measurement parameter values within each second grid image to obtain the parameter mean value corresponding to each second grid image; According to a preset superposition algorithm, perform superposition calculations on the parameter mean values of the second grid images at the same position of multiple wafer images to obtain a second superposition parameter value; Generate a superposition image based on the second superposition parameter value.

[0020] In the embodiments of the present application, after dividing the wafer image into grids, the target measurement parameter values within each second grid image are calculated as a mean value to represent the parameter level of the grid. On the one hand, the defect situation of each grid area of the wafer can be obtained, and on the other hand, the data processing volume is reduced.

[0021] In a possible implementation manner of the first aspect, the superposition rule includes: The parameters in the wafer image participating in the superposition operation; The preset superposition algorithm corresponding to the superposition operation; The rendering rule of the superposition image.

[0022] In the embodiments of the present application, by setting the superposition rule, when performing image superposition for different analysis purposes and data characteristics, the superposition is performed according to the preset superposition rule, clarifying the parameter selection, superposition algorithm, and rendering rule participating in the superposition operation, making the entire superposition process highly targeted and more clearly and intuitively presented to the staff.

[0023] In a possible implementation of the first aspect, before performing the superposition operation on the aligned multiple wafer images according to the preset superposition rule, the method further includes: If the wafer image contains line defects, intercept the line defect image from the image of the wafer according to the position of the line defects; Extract the skeleton of the line defect from the line defect image to obtain a skeleton image; Correspondingly, performing the superposition operation on the aligned multiple wafer images according to the preset superposition rule includes: Performing the superposition operation on the skeleton images according to the preset superposition rule.

[0024] In the embodiments of the present application, after superimposing multiple defective wafer images, the defects may cover the entire wafer image, making it difficult to analyze information such as the position and trend of the defects. Therefore, before superimposing, the skeleton of the defects in each wafer image can be extracted first to obtain a skeleton image containing the defect skeletons, and then the skeleton images can be superimposed to facilitate subsequent defect analysis.

[0025] In a possible implementation of the first aspect, analyzing according to the defect characteristics and combining the state information of each component in the production process to obtain the factors causing the defects includes: Analyzing according to the defect characteristics and combining the state information of each component in the production process to obtain the process information and component information causing the defects.

[0026] In the embodiments of the present application, the presence of defects and the positions of the defects on a single wafer image are accidental. By superimposing multiple wafer images, the distribution of the defects becomes dense, and then the defect characteristics can be extracted, and the causes of the defects can be analyzed based on the defect characteristics.

[0027] In a possible implementation of the first aspect, the defect characteristics include the distribution characteristics of pin mark defects. Analyzing according to the defect characteristics and combining the state information of each component in the production process includes: Obtaining the minimum distance between the pin marks in the superimposed image according to the distribution characteristics of the pin mark defects; wherein, the pin mark defects are caused by the abnormal working state of the probes during the production of the wafers; Determining the process information and probe information causing the pin mark defects according to the minimum distance and the actual distance between the probes in each production process.

[0028] In the embodiments of the present application, since the actual distances between the probes corresponding to different production processes are different, after superimposing multiple wafer images, the minimum distance between the pin marks in the wafer image can be found, and based on the minimum distance, the production process information and probe information causing the pin mark defects can be quickly located, which is convenient for subsequent maintenance.

[0029] In a possible implementation of the first aspect, according to a preset superposition rule, perform a superposition operation on multiple aligned wafer images to obtain a superposed image, including: For the case where multiple wafer images are images of the same wafer under different processes, superpose the wafer image corresponding to the current process with the wafer images before the current process to obtain the process superposed image corresponding to the current process; According to the defect characteristics, analyze in combination with the state information of each component in the production process during operation to obtain the factors causing the defects, including: Calculate the difference degree between the process superposed images corresponding to adjacent processes; Determine the process information where the defect appears based on the difference degree, and / or determine the evolution information of the defect along with the production process.

[0030] In the embodiments of the present application, by superposing the wafer image corresponding to the current process with the previous wafer images and calculating the difference degree between the process superposed images corresponding to adjacent processes, the influence of the current process on the wafer can be clearly observed. If new defect characteristics appear in the superposed image, it can be accurately determined that these defects are generated in the current process.

[0031] In a second aspect, an embodiment of the present application provides a defect analysis device based on wafer image superposition, including: An image acquisition module, configured to acquire multiple wafer images; the multiple wafer images are images of the same wafer corresponding to different production processes, or images of different wafers in the same production process; A feature extraction module, configured to extract the calibration features on each wafer image, and the calibration features are features used for positioning when aligning multiple wafer images; An image alignment module, configured to perform an alignment process on multiple wafer images based on the calibration features to obtain multiple aligned wafer images; An image superposition module, configured to perform a superposition operation on multiple aligned wafer images according to a preset superposition rule to obtain a superposed image; A defect feature extraction module, configured to extract the defect features on the superposed image; A defect analysis module, configured to analyze according to the defect features in combination with the state information of each component in the production process during operation to obtain the factors causing the defects.

[0032] In a third aspect, an embodiment of the present application provides an electronic device, including: a processor, a memory, and a bus, where: The processor and the memory communicate with each other through the bus; The memory stores program instructions executable by the processor, and the processor can execute the method of the first aspect by calling the program instructions.

[0033] In a fourth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium, including: The non-transitory computer-readable storage medium stores computer instructions, and the computer instructions cause the computer to execute the methods in various possible implementation manners of the first aspect.

[0034] In a fifth aspect, an embodiment of the present application provides a computer program product, including computer program instructions. When the computer program instructions are read and run by a processor, the methods in various possible implementation manners of the first aspect are executed.

[0035] In the embodiment of the present application, after aligning each wafer image and then performing overlay analysis, the correlation analysis of all defects on the image is completed at one time, with lower complexity; and multiple colors are used to distinguish the number of defects after overlay, which is more intuitive. It not only considers the correlation of a single type of defect, but also considers the unified correlation of all defects. When the image resolutions are different, the method of grid division and then overlay can be used to uniformly consider the data within each grid, which is more effective for defect analysis and can better assist relevant personnel in defect analysis.

[0036] Other features and advantages of the present application will be described in the subsequent specification, and part of them will become obvious from the specification, or can be understood by implementing the embodiments of the present application. The objectives and other advantages of the present application can be achieved and obtained through the structures specifically pointed out in the written specification, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 It is a schematic flowchart of a defect analysis method based on wafer image overlay provided by an embodiment of the present application; Figure 2 It is a schematic diagram of a wafer image provided by an embodiment of the present application; Figure 3 It is an example diagram of grid division provided by an embodiment of the present application; Figure 4 It is an example diagram of a mapping image provided by an embodiment of the present application; Figure 5 It is three defect area diagrams provided by an embodiment of the present application; Figure 6 Three skeleton diagrams provided by the embodiments of the present application; Figure 7 A schematic diagram of direct image overlay provided by the embodiments of the present application; Figure 8 A schematic diagram after image overlay through the skeleton image provided by the embodiments of the present application; Figure 9 Three schematic diagrams of needle mark defects provided by the embodiments of the present application; Figure 10 A schematic diagram after superimposing multiple wafer images provided by the embodiments of the present application; Figure 11 A schematic diagram of the structure of a defect analysis device based on wafer image overlay provided by the embodiments of the present application; Figure 12 A schematic diagram of the physical structure of an electronic device provided by the embodiments of the present application. Detailed implementation manners

[0039] Next, embodiments of the technical solutions of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to illustrate the technical solutions of the present application more clearly, so they are only examples and cannot be used to limit the protection scope of the present application.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above drawings are intended to cover non-exclusive inclusion.

[0041] In the description of the embodiments of the present application, technical terms such as "first" and "second" are only used to distinguish different objects and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present application, "a plurality of" means more than two unless otherwise specifically defined.

[0042] Referring to "embodiments" herein means that specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of this application. The phrase appears in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0043] In the description of the embodiments of the present application, the term "and / or" is merely an association relationship describing associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the associated objects before and after.

[0044] In the description of the embodiments of the present application, the term "a plurality of" refers to two or more (including two). Similarly, "a plurality of groups" refers to two or more groups (including two groups), and "a plurality of pieces" refers to two or more pieces (including two pieces).

[0045] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific situations.

[0046] In advanced manufacturing fields such as photovoltaic and semiconductor chips, the low product yield is the main factor restricting the profits of enterprises and hindering the development of enterprises. The production and manufacturing process is long and the process is complex. From raw materials to intermediate products and then to final products, defects may occur in each production process, and the accumulation of defects in each link leads to a low final yield. There are two sources of product defects, one is caused by accidental factors, and the other is caused by abnormal factors. Accidental factors are inherent, always present, have a small impact on quality but are difficult to eliminate. Abnormal factors sometimes appear and sometimes do not appear, have a greater impact on quality and are easy to eliminate, and abnormal factors often cause batch quality problems.

[0047] The purpose of defect analysis is to search for and locate the causes of product defects by mining and analyzing the defect information and other production information of the product. Specifically, locate the process where the defect occurs, and even which specific equipment, or which raw material, which process parameter and other production elements. Furthermore, the subsequent maintenance can be carried out according to the causes of the defects to improve the product yield.

[0048] For wafer production, multiple production processes are required, and each production process may produce defects. To conduct quality inspection on the production processes, image acquisition devices can be set in the production processes to acquire the wafer images after each production process is completed. Since there are many production processes, a large number of wafer images will be obtained after a wafer is completed, and the production line will operate continuously. Therefore, a large number of wafer images will also be generated in each production process. When the types and quantities of wafer defects are numerous, analyzing the defects manually based on experience is inefficient and prone to overlooking key points, resulting in low accuracy.

[0049] To solve the above technical problems, the embodiments of the present application provide a defect analysis method based on wafer image superposition. Before defect analysis, multiple images are subjected to superposition processing according to a preset superposition rule to obtain a superimposed image, and then wafer defect analysis is performed based on the superimposed image. By analyzing the defects in the superimposed image, the correlation between defects can be obtained, which is convenient for judging whether a certain defect often appears at the same position and for timely investigation.

[0050] Figure 1 The flowchart of a defect analysis method based on wafer image superposition provided by the embodiments of the present application is shown as Figure 1 shown, and the method includes: Step 101: Obtain multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes or images of different wafers in the same production process; Step 102: Extract the calibration features on each wafer image, where the calibration features are the features used for positioning when aligning multiple wafer images; Step 103: Align the multiple wafer images based on the calibration features to obtain the aligned multiple wafer images; Step 104: Perform a superposition operation on the aligned multiple wafer images according to a preset superposition rule to obtain a superimposed image; Step 105: Extract the defect features on the superimposed image; Step 106: Analyze according to the defect features in combination with the state information of each component in the production process during operation to obtain the factors causing the defects.

[0051] Among them, in step 101, the wafer will go through multiple production processes, such as oxidation, lithography, etching, doping, metallization, etc. When each key process is completed, an optical detection device (such as an optical microscope, a scanning electron microscope, etc.) is used to image the wafer to obtain the wafer image under this process. For example, after the lithography process, an image of the wafer surface is taken to observe the formation of the lithography pattern; after the etching process, the wafer image is taken again to check the etching depth and shape, etc.

[0052] Due to various factors in the wafer manufacturing process (such as raw material differences, equipment fluctuations, process parameter changes, etc.), there may be differences between different wafers. By analyzing the images of the same process on multiple wafers, the stability and consistency of this process on different wafers can be evaluated, and potential batch quality problems can be detected in a timely manner.

[0053] In step 102, the calibration feature is a feature used to align multiple wafer images. Usually, patterns or marks with obvious position features on the wafer and relatively stable in different processes are selected. For example, in the chip arrangement pattern on the wafer, the corner points, center points of the chips, or specific alignment marks (such as alignment marks, overlay marks, etc.) can be selected as calibration features. These calibration features have clear boundaries and easily recognizable shapes in the wafer image, facilitating subsequent image alignment operations.

[0054] Figure 2 A schematic diagram of a wafer image provided by an embodiment of the present application is shown as Figure 2 shown. There is a flat edge on each wafer image. Therefore, this flat edge can be used as a calibration feature. There are also depressions on both sides of the flat edge. The flat edge and the two depressions can also be used together as calibration features. These calibration features have clear boundaries and easily recognizable shapes in the wafer image, facilitating subsequent image alignment operations. Additionally, Figure 2 also shows 2 squares and 5 dots. These are all calibration points on the wafer image and can also be used as calibration features for subsequent alignment. It should be noted that Figure 2 the calibration features on are only examples. In fact, the number and positions of the squares and dots can be set on the wafer according to actual situations, and the embodiments of the present application do not make specific limitations in this regard. Moreover, the wafer images can also be aligned only based on the squares or only based on the dots.

[0055] Image processing algorithms can be used to extract calibration features from wafer images. Among them, the image processing algorithms can include algorithms based on edge detection (such as the Canny edge detection algorithm), algorithms based on corner detection (such as the Harris corner detection algorithm), and algorithms based on template matching, etc. Through these algorithms, the positions of the calibration features can be accurately located in the wafer image, providing accurate reference points for subsequent image alignment.

[0056] In addition, the image acquisition devices set in different production processes may adopt different acquisition precisions, which are manifested as different resolutions on the wafer images. Therefore, it is necessary to unify the image resolution. For example, for high-resolution images, adjacent data can be merged according to the coordinate granularity of low-resolution images (specifically, the average value or the maximum or minimum value can be taken according to business needs) to unify to the low resolution. Or the low-resolution images can be adjusted to images with the same resolution as the high-resolution images through interpolation and other methods, and then image alignment can be performed.

[0057] It should be noted that for the wafer image being an AOI image, before alignment, the wafer image can be preprocessed. Specifically, the specific preprocessing operations include at least one of the following: (1) Convert the wafer image into a grayscale image; (2) Binarize the grayscale image using a threshold segmentation algorithm; (3) Invert the image; (4) Perform a closing operation on the AOI image; (5) Find the maximum value of the minimum bounding rectangle after binarization.

[0058] For example: (1), (2), and (5) can be selected from the above-listed preprocessing operations for preprocessing, or (1), (2), (4), and (5) preprocessing can be performed on the wafer image, etc.

[0059] During alignment, the four corner points of the minimum bounding rectangle can be found, and the largest circular contour area in the original image can be perspective-transformed into a rectangular area of a fixed size. The width and height of the perspective transformation are the width and height of the largest circular contour area in the original image. After perspective transformation, the circular contour areas of all AOI images are aligned to the same-sized rectangular area and the flat sides will also be aligned.

[0060] In step 103, for the image acquisition devices of the same process, it is possible that due to the external environment, the image acquisition devices shift, resulting in the inability of multiple wafer images collected by the same image acquisition device to completely overlap. For the image acquisition devices of different processes, their device parameters may be different, resulting in different information such as image resolution in the collected images, and it is impossible to directly perform overlay processing on multiple wafer images. It is necessary to align multiple wafer images first and then perform overlay processing.

[0061] According to the extracted calibration features, a spatial correspondence relationship is established between multiple wafer images, that is, by calculating the geometric transformation relationship (such as translation, rotation, scaling, etc.) between the calibration features in different images, the obtained multiple wafer images are aligned in spatial positions. For example, if one wafer image has undergone translation and / or rotation relative to another image, the translated and / or rotated image can be made to coincide with other wafer images through alignment processing.

[0062] When aligning multiple wafer images based on calibration features, a suitable alignment algorithm can be adopted. For example, a matching-based alignment algorithm can be used. This alignment algorithm determines the geometric transformation relationship by matching the calibration features between different images. In addition, an alignment algorithm based on image content similarity can also be used, or first locate through Hough transform and then perform alignment in a perspective alignment manner, etc.

[0063] In step 104, multiple overlay rules can be preset according to different analysis requirements. The overlay rules can include: (1) Parameters involved in the overlay operation in the wafer image; Different overlay rules can be set for the parameters of different overlay operations. Among them, the parameters involved in the overlay operation can refer to the measurement parameters of the mapping image participating in the overlay, or the defect types in the AOI image. The defect types are for the possible multiple types of defects in the wafer image. By setting the overlay rules, the defect types participating in the overlay can be determined. The measurement parameter refers to a wafer image formed by a certain measurement parameter in the mapping data of the wafer, and the overlay process is performed on this wafer image.

[0064] (2) The preset overlay algorithm corresponding to the overlay operation; The overlay algorithm can include summation, mean, variance, and standard deviation, etc. Among them, the summation algorithm can be used to statistically analyze the cumulative effect of defects in multiple wafer images. The mean algorithm can affect the average level of defects. The variance and standard deviation algorithms can evaluate the dispersion degree and stability of defects. For example, to understand the overall distribution of defects on the wafer surface after a certain production process, the mean algorithm can be used for the overlay operation to obtain an overlay image reflecting the average defect quantity distribution.

[0065] (3) The rendering rule of the overlay image; The rendering rule refers to the correspondence between the number of defects and the color rendered into the overlaid image.

[0066] It should be understood that in actual overlay, any one or more of the above overlay rules can be adopted. For example, the parameters involved in the overlay operation and the overlay algorithm can be selected without color rendering, or all three of the above rules can be adopted.

[0067] When superimposing multiple wafer images, for wafer images of the same wafer under different production processes, they can be superimposed one by one in the order of the production processes. For wafer images of different wafers under the same production process, they can be superimposed one by one in the order in which the wafers are completed under this production process. It is also possible to superimpose all the wafer images participating in the superposition at one time. Moreover, when superimposing wafer images, it is possible to superimpose only a certain type of defect on the wafer image. Therefore, the superimposed image obtained by superimposing the wafer images can be a single-defect superimposed image; it is also possible to superimpose several types of defects on the wafer image, or superimpose all the defects on the wafer image. At this time, the obtained superimposed image is a multi-defect superimposed image. It can be understood that when performing image superposition, it is also possible to first superimpose a single defect to obtain a single-defect superimposed image, and then superimpose the single-defect superimposed image again to obtain a multi-defect superimposed image. Therefore, the superimposed image can include a single-defect superimposed image and a multi-defect superimposed image.

[0068] In step 105, after obtaining the superimposed image, the superimposed image can be analyzed. Since the superimposed image synthesizes the information of multiple wafer images, the defective area will show characteristics that are significantly different from the surrounding normal areas in the superimposed image. Therefore, the defective features on the superimposed image can be extracted. For example: in the superimposed image, if the color or gray value of a certain area is significantly different from the surrounding areas, it indicates that there may be a defect in this area. In addition, according to the coordinate information in the superimposed image, the position of the defect on the wafer image can be located, providing a data basis for the subsequent analysis of the cause of the defect.

[0069] When analyzing wafer defects, the type of the defect can also be determined. That is, according to the performance characteristics of different types of defects in the superimposed image, the defects can be classified. For example, according to characteristics such as the shape, size, and distribution law of the defects, the defects are classified into different types such as particle contamination, scratch, pattern missing, pattern short circuit, and hidden crack. At the same time, by analyzing the defective area in the superimposed image, the severity of the defect can be evaluated. For example, parameters such as the area, depth, and height of the defective area are calculated and compared with the pre-set defect tolerance standard to determine whether the defect will affect the performance and quality of the wafer.

[0070] In step 106, in combination with the status information of each component in the production process during operation (such as process parameters, equipment status, raw material quality, etc.), the factors causing defects are analyzed. By analyzing the distribution law and evolution trend of defects in the superimposed image, the key process or factors leading to defects can be found. For example, if it is found that the scratch defects on the wafer surface increase significantly after a certain process, the process parameters of this process (such as etching depth, photoresist coating uniformity, etc.) and the equipment operation status (such as tool wear, conveyor belt vibration, etc.) can be analyzed in depth, and targeted optimization measures can be taken, such as adjusting process parameters, improving the equipment maintenance plan, etc., so as to reduce the generation of defects and improve the yield rate of wafers.

[0071] In the embodiments of the present application, since different production processes may introduce different types of defects, therefore, the images of the same wafer in different production processes are subjected to an overlay process, and then defect analysis is performed based on the superimposed image, which can more accurately identify the specific process link where the defect occurs, and then accurately locate the defect source. And for the analysis after overlaying the images of different wafers in the same production process, the frequency and distribution law of the occurrence of defects can be counted, which can reduce the probability of misjudgment caused by accidental factors of a single wafer and improve the reliability of the defect detection result.

[0072] On the basis of the above embodiments, the image types of the wafer images may include AOI images and mapping images. In the case where the image type of the wafer image is an AOI image; the wafer image includes defect information, and the defect information includes defect type and defect location; the superimposed image includes a first single-defect superimposed image; according to a preset superimposing rule, multiple aligned wafer images are subjected to a superimposing operation to obtain a superimposed image, including: Based on the defect type, defect images containing a single defect type are extracted from the wafer image; For the defect images of the same defect type, the number of first defect images with defects at the same pixel position is counted, and a first single-defect superimposed image is generated according to the number of first defect images.

[0073] In the specific implementation process, the automatic optical inspection (AOI) technology plays a key role in wafer inspection. The AOI system scans and images the wafer surface through a high-resolution camera, and can capture various subtle defect features. These defect features can be identified and classified into different defect types, such as scratches, hidden cracks, cutting lines, etc. after being processed by image processing and analysis algorithms.

[0074] Before performing overlay, defect recognition can be pre - carried out on each wafer image to determine whether each pixel point in the wafer image contains a defect. If a defect is contained, the defect type is further determined. In a wafer image, there may be multiple defect types, but there is only one defect type at one pixel point.

[0075] For overlay of a single defect type, for example: to perform overlay processing on the defect type of pin marks, defects of the pin mark defect type can be extracted from multiple wafer images to form a defect image containing only pin mark defects. It can also be understood as removing other defects except pin mark defects in the wafer image. It can be understood that if there are no pin mark defects in some wafer images, these wafer images do not participate in the subsequent overlay processing.

[0076] After obtaining the defect image containing a single defect type, when performing overlay, the number of the first defect images with defects at the same pixel position in multiple defect images can be counted, and the counted number of the first defect images can be stored at the corresponding pixel position to obtain the first single - defect overlay image. It can be understood that overlay can be performed on each defect type according to the above - mentioned overlay method to obtain a single - defect overlay image corresponding to the defect type, that is, the overlay image.

[0077] It should be noted that before extracting the defect image containing a single defect type, the color space of the aligned AOI image can be converted from RGB to HSV. The reason is that in the RGB color space, color is jointly determined by the R, G, and B channels, and in the HSV space, color is determined by the H channel alone, S represents saturation, and V represents brightness. Therefore, after converting to the HSV color space, it is convenient for backend developers to perform color settings.

[0078] Based on the above - mentioned embodiments, the overlay image also includes the first multi - defect overlay image. After obtaining the single - defect overlay image, some or all of the single - defect overlay images corresponding to the defect types can be selected from multiple defect types for re - overlay. The overlay method is similar to the overlay method of a single defect type, that is, the number of the second defect images with defects at the same pixel position in the first single - defect overlay images corresponding to multiple defect types is counted, the defect parameter corresponding to each pixel position is obtained according to a preset overlay algorithm (such as summation), and the first multi - defect overlay image is generated based on the defect parameter.

[0079] In another embodiment, when performing overlay on an image with multiple defect types, it is also possible not to perform re - overlay on the basis of the first single - defect overlay image, but to directly perform overlay on the obtained wafer image containing multiple defect types. The specific operation method is as follows: Extract multiple defect types to be involved in subsequent superposition from the obtained wafer images to obtain wafer images with multiple defect types, or remove the defect types that do not need to be involved in subsequent superposition from the obtained wafer images to obtain wafer images with multiple defect types. It can be understood that the multiple defect types involved in subsequent superposition can be all the defect types included in the wafer images, or multiple defect types selected from all the defect types, which can be specifically set according to actual needs, and the embodiments of the present application do not make specific limitations on this. If a certain wafer image does not contain any of the defect types to be involved in subsequent superposition, then this wafer image will be removed and not participate in subsequent superposition. In addition, the obtained images with multiple defect types may contain all the defect types in all the third target defect types, or may contain some of the defect types in the third target defect types, or may only contain one defect type in the third target defect types. For example: for wafer image 1, its included defect types are defect A, defect B, defect C, defect D, and defect E; the defect types included in wafer image 2 are defect A, defect B, and defect C; the defect types included in wafer image 3 are defect C, defect D, and defect E. Assume that the third target defect types include defect A, defect B, and defect C. Then, the image with multiple defect types obtained after defect extraction from wafer image 1 contains defect A, defect B, and defect C; the image with multiple defect types obtained after defect extraction from wafer image 2 contains defect B and defect C; the image with multiple defect types obtained after defect extraction from wafer image 3 contains defect C.

[0080] After obtaining the images with multiple defect types, superimpose the obtained multiple images with multiple defect types. Specifically, count the number of defects at the same pixel position in multiple wafer images with multiple defect types, store the number of defects at this pixel position, and obtain a superimposed image. It is also possible to perform color rendering according to the number of defects to obtain a superimposed image.

[0081] The embodiments of the present application extract defect images containing a single defect type from wafer images based on defect types, enabling subsequent defect analysis to focus on specific types of defects and clearly reflecting the frequency of a certain defect at each pixel position, providing data support for accurately locating high-defect-risk areas. In addition, through the comprehensive superposition of multiple defect types, the correlation between different defect types can also be discovered.

[0082] Based on the above embodiments, generate a first single-defect superimposed image according to the number of first defect images, including: Determine the color parameters corresponding to the pixel position according to the number of first defect images corresponding to each pixel position; Render and generate a first single-defect superimposed image based on the color parameters.

[0083] In a specific implementation process, after obtaining the first single-defect superimposed image, in order to more intuitively display the distribution of defects, a correspondence relationship can be established between the number of first defect images at each pixel position and the rendering color.

[0084] Color models can include the RGB (Red, Green, Blue) model and the HSV (Hue, Saturation, Value) model, etc. For example, if the RGB model is selected, various colors can be represented by combinations of different red, green, and blue color channels. For the first single-defect superimposed image, a color in a unified color system (such as the red color system) can be selected to represent the correspondence between the number of first defect images at each pixel position and the color. For example, the lighter the red color, the fewer the number of first defect images at the corresponding pixel position, and the darker the red color, the more the number of first defect images at the corresponding pixel position. Of course, different color systems can also be used to represent the correspondence between the number of first defect images at each pixel position and the color. For example, when the number of first defect images is small, the corresponding color is light blue (RGB value: (0, 191, 255)); when the number is medium, the corresponding color is green (RGB value: (0, 255, 0)); when the number is large, the corresponding color is yellow (RGB value: (255, 255, 0)); when the number is very large, the corresponding color is red (RGB value: (255, 0, 0)). This mapping rule can intuitively reflect the frequency of defect occurrence, and the more the number, the more prominent the color.

[0085] In addition, a grayscale image can also be used for color rendering, and a correspondence relationship is established between the grayscale value and the number of first defect images. For example: the smaller the grayscale value, the more the number of first defect images at the corresponding pixel position, and the larger the grayscale value, the fewer the number of first defect images at the corresponding pixel position. Or, the larger the grayscale value, the more the number of first defect images at the corresponding pixel position, and the smaller the grayscale value, the fewer the number of first defect images at the corresponding pixel position.

[0086] Similarly, the superimposed image obtained after superimposing multiple defect type images can also be rendered using a similar color rendering method as above, which will not be elaborated here.

[0087] Based on the number of defective images at each pixel position in the embodiments of the present application, corresponding colors are used for rendering, making the defect distribution of the first single-defect superimposed image more intuitively displayed.

[0088] Based on the above embodiments, the image type of the wafer image is an AOI image; the defect information of the wafer image, where the defect information includes the defect type and the defect position; the superimposed image includes a second single-defect superimposed image; according to a preset superimposing rule, multiple aligned wafer images are superimposed to obtain a superimposed image, including: Extract defect images containing a single type of defect from the wafer image based on the defect type; Perform grid division on the defect images corresponding to each defect type to obtain multiple grid images; For each defect type, count the number of defective chips contained in each grid image in the corresponding defect image; According to the number of defective chips contained in each grid image obtained by statistics, calculate the superposition value corresponding to the grid images at the same position in multiple defect images of the same defect type according to a preset superposition algorithm, and generate a second single-defect superposition image based on the superposition value.

[0089] In the specific implementation process, before performing image superposition, defect recognition can be pre-performed on each wafer image to determine whether each pixel point in the wafer image contains a defect. If a defect is contained, the defect type is further determined. In a wafer image, a wafer image may have multiple defect types, but there is only one defect type at one pixel point.

[0090] For single-defect type image superposition, for example: to perform image superposition processing on pin mark defects as the defect type, defects of the pin mark type can be extracted from multiple wafer images to form defect images containing only pin mark defects. It can also be understood as removing other defects except pin mark defects in the wafer image. It can be understood that if there are no pin mark defects in some wafer images, these wafer images do not participate in the subsequent image superposition processing.

[0091] After obtaining the defect images containing a single defect type, grid division can be performed according to a preset size. For example: the size of the grid can be 20 pixel points, or 30 pixel points, or grid division can also be performed according to the chip size. For example: each grid can contain 5 chips or 10 chips, etc. The size of the grid can be specifically set according to actual needs, and the embodiments of the present application do not make specific limitations in this regard. In addition, the defect image can also be divided according to a preset number of grids. The number of grids can be set according to actual needs, and the embodiments of the present application do not make specific limitations in this regard. In the grid images obtained after grid division, each grid can include multiple chips. It should be noted that the grid division method for each wafer image should be consistent. Figure 3 This is an example diagram of grid division provided by the embodiments of the present application, Figure 3 where the black dots in the wafer image are used to represent defect information. In actual applications, Figure 3 it can be represented by a color image, and different colors represent the number of defects contained at the position of the pixel point. It should be noted that, Figure 3 the grids in the background part do not participate in the subsequent superposition calculation.

[0092] When performing overlay processing on a grid image of a defect type, the number of defective chips contained in each grid can be counted. It should be noted that a defective chip can be determined by judging whether there is a defect at the pixel position where the chip is located. If there is a defect, the chip can be determined as a defective chip.

[0093] According to the number of defective chips contained in each grid image obtained by statistics, the overlay value corresponding to the grid images at the same position in multiple defective images of the same defect type is calculated according to a preset overlay algorithm. The preset overlay algorithm can include summation, mean, variance, standard deviation, etc. For example, if the mean algorithm is selected, for multiple defective images of the same defect type (such as scratches), calculate the average value of the number of defective chips contained in each image at each grid position as the overlay value of this grid position.

[0094] The overlay value can be stored as a defect attribute of this grid, or it can be represented by colors. That is, a second single-defect overlay image is generated according to the set color rendering rules. A color coding method can be adopted, and different colors are assigned according to the magnitude of the overlay value. For example, areas with lower overlay values are represented by green, indicating fewer defective chips; areas with medium overlay values are represented by yellow, indicating a moderate number of defective chips; areas with higher overlay values are represented by red, indicating a large number of defective chips. In this way, the overlay value of each grid is converted into color information, and the second single-defect overlay image is drawn to intuitively display the distribution and severity of the same defect type in multiple wafer images.

[0095] In another embodiment, the overlay image can also include a second multi-defect overlay image. After obtaining the second single-defect overlay image, the second single-defect overlay images corresponding to multiple defect types can be overlaid again. In the embodiments of the present application, the defect types selected for re-overlay are called second target defect types. The second curve target defects can be all the defect types contained in multiple wafer images, or at least two defect types selected from all the defect types.

[0096] When performing image overlay of multiple defect types, re-overlay can be performed according to the second single-defect overlay image storing the overlay value. The overlay method is similar to the above-mentioned wafer image overlay method for a single defect, that is, the number of defective chips contained in the same grid in the second single-defect overlay images corresponding to the second target defect types is overlaid and calculated according to a preset overlay algorithm to obtain a second multi-defect overlay image.

[0097] The second single defect superposition images corresponding to the second target defect type are superimposed again to obtain the final superimposed image. The second target defect type can be all defect types or some defect types selected from all defect types. For example, particle contamination and scratches are selected as the second target defect types, and their corresponding second single defect superposition images are superimposed again. During the superposition process, transparency superposition can be used so that the distribution of different defect types can be simultaneously presented in the final superimposed image. The final superimposed image can comprehensively display the distribution of multiple defect types on the entire wafer, providing comprehensive and intuitive visual information for wafer defect analysis, helping technicians to quickly locate defect areas, analyze the causes and evolution of defects, and take corresponding measures to optimize the production process and improve wafer quality.

[0098] In another embodiment, when overlaying images of multiple defect types, it is also possible not to overlay again on the basis of the second single defect overlay image, but to overlay directly on the obtained wafer image containing multiple defect types. The specific operation method is as follows: Extract multiple defect types that are to be involved in subsequent superposition from the obtained wafer image to obtain a wafer image with multiple defect types, or remove defect types that do not need to be involved in subsequent superposition from the obtained wafer image to obtain a wafer image with multiple defect types. It is understandable that if a certain wafer image does not contain any defect type that is to be involved in subsequent superposition, the wafer image is removed and does not participate in subsequent superposition. Then, the wafer image with multiple defect types is gridded to obtain a grid image, and the multiple grid images with multiple defect types obtained are superimposed. Specifically, the number of defective chips contained in the same grid in multiple wafer images with multiple defect types is counted, and the number of defective chips contained is stored in the grid as a defect attribute of the grid to obtain a superimposed image. Color rendering can also be performed according to the number of defects to obtain a superimposed image.

[0099] The embodiment of the present application counts the number of defective chips in each grid image so that the number of defects can be quantified, which helps to compare the defect density in different areas; the second single defect overlay images corresponding to the second target defect type are overlaid again to obtain the final overlay image. This makes it possible to observe the distribution of multiple defect types on the entire wafer at the same time, which is convenient for analyzing whether there is a correlation distribution between different defect types.

[0100] On the basis of the above embodiment, when the image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter value of the wafer at each pixel point position; according to the preset superposition rule, the aligned multiple wafer images are superimposed to obtain a superimposed image, including: Perform superposition calculations on the target measurement parameter values at the same pixel position in multiple wafer images according to a preset superposition algorithm to obtain a first superposition parameter value; the preset superposition algorithm includes summation, mean, variance, and standard deviation calculations. Generate a superposition image based on the first superposition parameter value.

[0101] In a specific implementation process, obtain the csv dataset of the mapping that needs to be superposed. The csv dataset can include several to thousands of data, which is specifically determined according to the actual scenario. The csv dataset is chip data obtained by using some measurement means during the chip production process, such as current data, voltage data, etc.

[0102] According to the superposition requirements, select the corresponding target measurement parameters from the csv data, extract the target measurement parameters corresponding to each pixel position in the csv dataset, and plot them at the corresponding pixel positions to obtain the mapping. Therefore, the mapping image is generated based on the target measurement parameter values at each pixel position of the wafer. Figure 4 This is an example diagram of the mapping image provided by the embodiment of the present application. The black dots in the figure are used to represent defect information. In practical applications, Figure 4 It can be represented by a color map, and different colors represent the number of defects at that pixel position.

[0103] After obtaining the mapping image, perform a superposition operation on multiple mapping images according to a preset superposition rule. The preset superposition algorithm includes various mathematical calculation methods, such as mean calculation, variance calculation, and standard deviation calculation.

[0104] Among them, the mean calculation algorithm: Calculate the average value of the target measurement parameter values at the same pixel position in multiple wafer images. This method can reflect the average physical parameter level of multiple wafers at this position, help to understand the overall parameter distribution of the wafers during the production process, and eliminate the influence of individual differences. For example, when analyzing the reflectivity of a batch of wafers, calculating the mean can obtain the average reflectivity of the batch of wafers at each position, which is used to evaluate the stability of the production process.

[0105] The variance and standard deviation calculation algorithms: Measure the degree of dispersion of the target measurement parameter values by calculating the variance and standard deviation. The larger the variance and standard deviation, the greater the fluctuation of the physical parameters of different wafers at the same pixel position. This is very important for evaluating the uniformity and stability of the production process. For example, in the control of the doping concentration of wafers, if the variance of the doping concentration in a certain area is large, it indicates that the doping process in this area is unstable and the process needs to be optimized.

[0106] The corresponding color can be rendered according to the first superposition parameter value at each pixel position, so that a superposition image representing the distribution of the first superposition parameter value through different colors can be obtained. When rendering, the standard value of the target measurement parameter can be preset. The more it deviates from the standard value, the deeper the color is used to represent it. Thus, the abnormal positions on the wafer image can be determined through the colors in the superposition image.

[0107] In the embodiment of the present application, by superimposing and calculating multiple wafer mapping images generated based on the target measurement parameter values at each pixel position according to a preset superposition algorithm, the first superposition parameter value can be obtained, thereby realizing the accurate quantification of the target measurement parameter value. The generated superposition image can intuitively display the overall distribution and change of the wafer measurement parameters.

[0108] Based on the above embodiments, the image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter values of the wafer at each pixel position; according to the preset superposition rule, multiple aligned wafer images are superimposed to obtain a superposition image, including: Each wafer image is divided into grids to obtain multiple second grid images corresponding to each wafer image; Calculate the mean value of the target measurement parameter values within each second grid image to obtain the parameter mean value corresponding to each second grid image; According to the preset superposition algorithm, superimpose and calculate the parameter mean values of the second grid images at the same position of multiple wafer images to obtain the second superposition parameter value; Generate a superposition image according to the second superposition parameter value.

[0109] In the specific implementation process, after obtaining the mapping image, the mapping image is divided into grids according to the coordinate positions to obtain the second grid images. The size of the grids can be determined according to the requirements and the resolution of the wafer image. For example, a wafer image of 2048×2048 pixels is divided into 64×64 grids, and the size of each grid image is 32×32 pixels.

[0110] Calculate the mean value of the target measurement parameter values within each grid to obtain the parameter mean value corresponding to each grid. According to the preset superposition rule, superimpose the parameters of multiple mapping images under the same grid to obtain the second superposition parameter value of each grid object.

[0111] After obtaining the second superposition parameter value, the second superposition parameter value can be stored as an attribute of the corresponding grid under the grid to obtain a superposition image. It is also possible to render the corresponding color for the corresponding grid according to the second superposition parameter value to obtain a superposition image.

[0112] In the embodiments of the present application, after dividing the wafer image into grids, the target measurement parameter value in each second grid image is calculated as an average value to represent the parameter level of the grid. On the one hand, the defect situation of each grid area of the wafer can be obtained, and on the other hand, the data processing volume is reduced.

[0113] Based on the above embodiments, before performing the overlay operation on the aligned multiple wafer images according to the preset overlay rule, the method further includes: If the wafer image contains line defects, intercept the line defect image from the image of the wafer according to the position of the line defects; Extract the skeleton of the line defect from the line defect image to obtain a skeleton image; Correspondingly, performing the overlay operation on the aligned multiple wafer images according to the preset overlay rule includes: Performing the overlay operation on the skeleton images according to the preset overlay rule.

[0114] In the specific implementation process, for line defects, such as scratches, hidden cracks, cutting lines and other defects. After defect detection and classification, methods such as the mask_rcnn deep learning model or threshold segmentation can be used to accurately extract the defect area along the defect contour. Remove the small discrete areas and retain the main area of the defect, then perform morphological closing operation on the image to eliminate the internal holes, and then calculate the maximum outer contour to obtain a connected area. Figure 5 These are three defect area maps provided by the embodiments of the present application. Perform skeleton extraction on the connected areas in the defect area maps. Specifically, the fire model or the maximum disk method can be used for skeleton extraction to obtain a skeleton image with a width of only one pixel. Figure 6 These are three skeleton maps provided by the embodiments of the present application, which are Figure 5 obtained by performing skeleton extraction on the three defect area maps (a), (b), and (c) in Figure 6 The three skeleton images (d), (e), and (f) in

[0115] "Graphite disk scratch" is a common defect in the semiconductor wafer production process. In the chemical vapor deposition equipment, the wafer is placed in the graphite disk of the reaction chamber. When the graphite disk is damaged, comet-shaped defects extending from the edge to the center will appear on the wafer. Since the graphite disk is reused, the "graphite disk damage" defects that appear in the same graphite disk slot have similar position and morphological characteristics. The graphite disk damage defect has a certain width, and directly overlaying multiple images may cover the entire wafer, making it difficult to analyze the consistency of the defect position and trend. Figure 7A schematic diagram of direct image overlay provided by an embodiment of the present application. As can be seen from Figure 7 , after image overlay, the defects almost cover the entire wafer image. Therefore, skeleton extraction is first performed to depict the main features of the defects with the center line along the length direction of the defects, and then image overlay is performed. Figure 8 A schematic diagram after image overlay using the skeleton image provided by an embodiment of the present application. After image overlay, the intersection positions, lengths, and directions of each defect skeleton and the wafer edge can also be calculated. After statistical analysis, a quantitative feature description of the breakage defects of this batch of graphite plates can be generated.

[0116] In an embodiment of the present application, after multiple defective wafer images are overlaid, the defects may cover the entire wafer image, making it difficult to analyze information such as the defect positions and orientations. Therefore, before overlaying, the skeletons of the defects in each wafer image can be extracted first to obtain a skeleton image containing the defect skeletons, and then the skeleton images can be overlaid to facilitate subsequent defect analysis.

[0117] Based on the above embodiments, according to the defect characteristics, combined with the status information of each component in the production process during operation, analysis is performed to obtain the factors causing the defects, including: According to the defect characteristics, combined with the status information of each component in the production process during operation, analysis is performed to obtain the process information and component information causing the defects.

[0118] In a specific implementation process, the overlay image can present image features that are not present in a single wafer image. Matching analysis is performed based on the image features on the overlay image and the element information in the production process. When the defect features on the overlay image have a certain degree of consistency with the features required in production, it indicates the possible causes of the defects.

[0119] Among them, defect features can include geometric features, statistical features, color features, etc. Among them, geometric features include the shape, size, area, perimeter, aspect ratio, position, orientation, periodicity, etc. of the defect. For example, circular or elliptical defects may be particle contamination, and irregularly shaped defects may be scratches or pattern missing, etc. The area and perimeter can be used to measure the scale of the defect, and the aspect ratio can help distinguish different types of linear defects. Statistical features reflect the distribution of defects in the superimposed image. It includes the occurrence frequency of defects (i.e., the number of defects per unit area), the aggregation degree of defects (such as whether the distribution of defects in the image is random, aggregated or evenly distributed, etc.). For example, if the defects show an aggregated distribution, it may imply that there are specific problems in certain local areas during the production process. According to the color coding rules of the superimposed image, the color or gray value of the defect area can provide information about its severity or the degree of deviation of physical parameters from the normal range. For example, in the thickness mapping superimposed image, the red area may represent defects with thickness exceeding the normal range, while the blue area may represent defects with insufficient thickness. Information on production factors includes the shape, size, processing position, movement path, processing time, batch number, equipment number, physical and chemical principles and geometric properties of production and processing of components of production equipment.

[0120] When extracting defect features, image segmentation methods can be used, such as: threshold segmentation, region growing segmentation, edge detection segmentation, etc., to segment the defect area from the superimposed image. For example, for a color-coded superimposed image, a threshold can be set according to a specific range of color channels to segment the defect color area. If the value of the red channel is high while the values of the green and blue channels are low, it can be determined that this area is a red defect area.

[0121] Some defects are caused by the periodic movement of equipment components. For such defects, the process information and abnormal component information causing the defects can be determined according to the periodic characteristics of the defect position and the matching of the movement rules of the components. To this end, equipment operation parameters related to the production process can be collected, such as: the number of probes in the production process, the actual gap between probes, etc. An association model between defect features and production process component status information is established. By analyzing a large number of superimposed images with defect features and the corresponding production process component status data, the correlation between defect features and factors such as equipment parameters, component wear, and process recipes can be found. For example, if it is found that when the exposure energy of the lithography machine exceeds a certain threshold, the frequency of a certain specific shape and size of defects in the superimposed image increases significantly, an association model between the exposure energy and the defect can be established.

[0122] Based on the established association model, fault diagnosis and traceability are carried out for specific defect situations. When defect features are detected in the new superimposed image, combined with the status information of production process components at that time, the specific process steps and related components causing the defects are determined through model calculation or look-up table, etc. For example, if a scratch defect is found on the surface of a wafer, by analyzing the shape, direction and distribution characteristics of the scratch, and combining the status information of the mechanical components of the equipment (such as the moving components of the wafer transfer system) during the production process, it can be judged that a scratch defect is caused by the wear or improper adjustment of a certain component of the conveyor belt, and the specific conveyor belt component can be located.

[0123] In the embodiment of the present application, the presence of defects and the defect positions on a single wafer image are accidental. By superimposing multiple wafer images, the distribution of defects becomes dense, and then defect features can be extracted, and the causes of defects are analyzed based on these defect features.

[0124] On the basis of the above embodiment, the defect features include the distribution characteristics of pin mark defects. According to the defect features, combined with the status information of each component during the working process in the production process, the analysis includes: Obtain the minimum spacing of the pin marks in the superimposed image according to the distribution characteristics of the pin mark defects; among them, the pin mark defects are caused by the abnormal working state of the probes during the production of the wafer. Determine the process information and probe information causing the pin mark defects according to the minimum spacing and the actual spacing of the probes in each production process.

[0125] In the specific implementation process, the positions of the pin mark stripes on a single wafer are accidental, and the intervals of the pin marks cannot be completely inferred, so it is impossible to determine which probe in which process causes them. Figure 9 The following are three schematic diagrams of pin mark defects provided by the embodiment of the present application, as Figure 9 shown. (x), (y), and (z) are three schematic diagrams of pin mark defects generated by the wafer in a certain process. The pin mark defects in each schematic diagram of the pin mark defects are relatively sparse, and it is impossible to determine the probe information corresponding to the process only for the defects of a single wafer. When the wafer images of the same batch of wafers produced in the same production process are superimposed, the distribution of the pin marks becomes dense, the spacing of the pin mark stripes can be counted, and it can be calculated that the wide spacings are all multiples of the narrowest spacing. Figure 10 The following is a schematic diagram of the superimposition of multiple wafer images provided by the embodiment of the present application, as Figure 10 shown. According to the spacing of the pin marks and the actual spacing set for the probes in each process, it can be inferred which probe in which process causes the pin marks to appear on this batch of products.

[0126] In the embodiments of the present application, since the actual distances between the probes corresponding to different production processes are different, after superimposing multiple wafer images under the same process, the minimum distance of the pin marks in the wafer images can be found. Based on the minimum distance, the production process information and probe information that cause the pin mark defect can be quickly located, which is convenient for subsequent maintenance.

[0127] On the basis of the above embodiments, according to a preset superimposing rule, perform a superimposing operation on the aligned multiple wafer images to obtain a superimposed image, including: For the case where multiple wafer images are images of the same wafer under different processes, superimpose the wafer image corresponding to the current process on the wafer image before the current process to obtain a process superimposed image corresponding to the current process; According to the defect characteristics, analyze in combination with the state information of each component in the production process during operation to obtain the factors causing the defect, including: Calculate the difference degree between the process superimposed images respectively corresponding to adjacent processes; Determine the process information where the defect appears and / or determine the evolution information of the defect along with the production process according to the difference degree.

[0128] In a specific implementation process, align the images of the same wafer under different processes, which is a prerequisite for the superimposing operation. Through the alignment operation, ensure that the positions and postures of the wafer images in different processes are consistent, so as to be able to accurately perform superimposing and comparison. The alignment process usually determines the geometric transformation relationship between the images, such as translation, rotation, scaling, etc., based on specific marks (such as alignment marks, corner points of the chip arrangement pattern, etc.) on the wafer images.

[0129] On the aligned wafer images, perform a superimposing operation using an appropriate superimposing algorithm. That is, the wafer images can be superimposed in the order of the production processes. For example: there are four production processes, namely process 1, process 2, process 3, and process 4. When superimposing the images, first superimpose the wafer image of process 1 and the wafer image of process 2 to obtain superimposed image 1; then superimpose superimposed image 1 on the wafer image of process 3 to obtain superimposed image 2; then superimpose superimposed image 2 on the wafer image of process 4 to obtain the final superimposed image. It should be noted that the superimposing algorithm can refer to the above embodiments and will not be elaborated here.

[0130] To quantify the variations between adjacent processes, the difference degree between the superimposed images corresponding to adjacent processes is calculated. The difference degree can be calculated by comparing the gray values, color values or specific feature parameters of the images. For example, metrics such as the mean squared error (MSE) and the structural similarity index (SSIM) can be used to measure the difference between two images. MSE reflects the average gray difference between images, while SSIM takes into account the structural similarity of the images and can better reflect the human perception of image differences.

[0131] Whether a defect occurs in the current process is judged by setting a difference degree threshold. When the difference degree between adjacent processes exceeds the set threshold, it can be considered that an obvious defect or change has occurred in the current process. For example, if the difference degree threshold is set to T, when the calculated difference degree D between the current process and the previous process is greater than T, it is determined that the current process may be the key process where the defect appears. The state information of each component during the working process in each process can be understood as whether the component is in a working state. Therefore, after determining the key process, it can be further determined whether the degree of damage of the components in this process is increasing, that is, the defect evolves as the components in the production process are damaged.

[0132] In addition, by calculating the difference degrees between multiple adjacent processes, the evolution of defects during the production process can be traced. A difference degree curve graph is plotted, with the horizontal axis representing the process sequence and the vertical axis representing the difference degree value, so as to visually display the evolution trend of defects with the process. For example, if the difference degree curve shows an obvious upward trend after a certain process, it indicates that the defect may start to occur or intensify after this process.

[0133] Based on the difference degree curve and the superimposed images, the evolution pattern of the defects is identified. For example, some defects may gradually appear and gradually worsen after a specific process, which may imply that certain factors in this process or subsequent processes are continuously affecting the development of the defects; while some defects may suddenly appear and have a large difference degree after a certain process, which may indicate that there are sudden quality problems in this process. By analyzing the evolution pattern of the defects, the formation mechanism of the defects can be better understood, providing a basis for optimizing the production process and preventing defects.

[0134] It should be noted that the evolution of the degree of damage of the components in the production process can also be determined according to the image conditions of different wafers in the same process. The specific method can refer to the above embodiments, that is, calculate the wafer superimposed image after superimposing each wafer image with the previous wafer image, and then calculate the difference degree between the wafer superimposed images corresponding to adjacent two wafer images. According to the difference degree, the time point when the defect appears in this process can be determined, and according to the components in the working state in this process, the range of the faulty components can be initially locked. In addition, as the difference degree increases, the evolution information of the component failure can be further determined.

[0135] In the embodiments of the present application, by superimposing the wafer image corresponding to the current process on the previous wafer image and calculating the difference degree between the process superimposed images corresponding to adjacent processes, the influence of the current process on the wafer can be clearly observed. If new defect features appear in the superimposed image, it can be accurately determined that these defects are generated in the current process.

[0136] Figure 11 FIG. is a schematic structural diagram of a defect analysis device based on wafer image overlay provided by an embodiment of the present application. The device may be a module, a program segment, or code on an electronic device. It should be understood that the device corresponds to the above Figure 1 method embodiment and can execute Figure 1 each step involved in the method embodiment. The specific functions of the device can be referred to the description above. To avoid repetition, the detailed description is appropriately omitted here. The device includes: an image acquisition module 1101, a feature extraction module 1102, an image alignment module 1103, an image overlay module 1104, a defect feature extraction module 1105, and a defect analysis module 1106, where: The image acquisition module 1101 is configured to acquire multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes, or images of different wafers in the same production process; The feature extraction module 1102 is configured to extract calibration features on each wafer image, and the calibration features are features used for positioning when aligning multiple wafer images; The image alignment module 1103 is configured to perform alignment processing on multiple wafer images based on the calibration features to obtain multiple aligned wafer images; The image overlay module 1104 is configured to perform an overlay operation on the multiple aligned wafer images according to a preset overlay rule to obtain an overlay image; The defect feature extraction module 1105 is configured to extract defect features on the overlay image; The defect analysis module 1106 is configured to perform wafer defect analysis based on the overlay image.

[0137] Based on the above embodiments, the image type of the wafer image is an AOI image; the wafer image includes the defect information, and the defect information includes a defect type and a defect position; the overlay image includes a first single-defect overlay image. The image overlay module 1104 is specifically configured to: Extract defect images containing a single defect type from the wafer images based on the defect type; For defect images of the same defect type, count the number of first defect images with defects at the same pixel position, and generate a first single-defect overlay image according to the number of first defect images.

[0138] Based on the above embodiments, the superimposed image further includes a first multi-defect superimposed image, and the image superimposing module 1104 is further configured to: Count the number of second defect images of the first target defect type at the same pixel position in the first single-defect superimposed image, and generate the first multi-defect superimposed image according to the number of second defect images; wherein, the first target defect type is all defect types or some defect types selected from all defect types.

[0139] Based on the above embodiments, the image superimposing module 1104 is specifically configured to: Count the number of second defect images of the first target defect type at the same pixel position in the first single-defect superimposed image, and generate the superimposed image according to the number of second defect images.

[0140] Based on the above embodiments, the image superimposing module 1104 is specifically configured to: Determine the color parameter corresponding to the pixel position according to the number of first defect images corresponding to each pixel position; Render and generate the first single-defect superimposed image based on the color parameter.

[0141] Based on the above embodiments, the image type of the wafer image is an AOI image; the wafer image includes the defect information, and the defect information includes the defect type and the defect position; the superimposed image includes a second single-defect superimposed image; the image superimposing module 1104 is specifically configured to: Extract the defect images containing a single defect type from the wafer image based on the defect type; Perform grid division on the defect images corresponding to each defect type to obtain a plurality of grid images; For each defect type, count the number of defective chips contained in each grid image in the corresponding defect image; According to the number of defective chips contained in each grid image obtained by statistics, calculate the superimposed value corresponding to the grid images at the same position in multiple defect images of the same defect type according to a preset superimposing algorithm, and generate a second single-defect superimposed image based on the superimposed value.

[0142] Based on the above embodiments, the image superimposing module 1104 is further configured to: Count the number of chips of the second target defect type on the same grid image in the second single-defect superimposed image, and generate the second multi-defect superimposed image according to the number of chips; wherein, the second target defect type is all defect types or some defect types selected from all defect types.

[0143] Based on the above embodiments, the image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter values at each pixel position of the wafer; the image superposition module 1104 is specifically configured to: Perform superposition calculation on the target measurement parameter values at the same pixel position in multiple wafer images according to a preset superposition algorithm to obtain a first superposition parameter value; the preset superposition algorithm includes summation, mean calculation, variance calculation, and standard deviation calculation; Generate the superposition image according to the first superposition parameter value.

[0144] Based on the above embodiments, the image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter values at each pixel position of the wafer; the image superposition module 1104 is specifically configured to: Divide each of the wafer images into grids to obtain a plurality of second grid images corresponding to each of the wafer images; Calculate the mean value of the target measurement parameter values within each of the second grid images to obtain a parameter mean value corresponding to each of the second grid images; Perform superposition calculation on the parameter mean values of the second grid images at the same position in multiple wafer images according to a preset superposition algorithm to obtain a second superposition parameter value; Generate the superposition image according to the second superposition parameter value.

[0145] Based on the above embodiments, the superposition rules include: The parameters in the wafer image participating in the superposition operation; The preset superposition algorithm corresponding to the superposition operation; The rendering rule of the superposition image.

[0146] Based on the above embodiments, the device further includes a skeleton extraction module, which is configured to: If the wafer image contains a linear defect, intercept a linear defect image from the image of the wafer according to the position of the linear defect; Extract the skeleton of the linear defect from the linear defect image to obtain a skeleton image; Correspondingly, the image superposition module 1104 is specifically configured to: Perform a superposition operation on the skeleton images according to a preset superposition rule.

[0147] Based on the above embodiments, the defect analysis module 1106 is specifically configured to: Analyze according to the defect characteristics in combination with the state information of each component during the working process in the production process to obtain the process information and component information that cause the defects.

[0148] Based on the above embodiments, the defect features include the distribution features of pin mark defects, and the defect analysis module 1106 is specifically configured to: Obtain the minimum spacing of the pin marks in the superimposed image according to the distribution features of the pin mark defects; wherein, the pin mark defects are caused by abnormal working states of the probes during the production process of the wafer; Determine the process information and probe information that cause the pin mark defects according to the minimum spacing and the actual spacing of the probes in each production process.

[0149] Based on the above embodiments, the image superimposing module 1104 is specifically configured to: For the case where multiple wafer images are images of the same wafer under different processes, superimpose the wafer image corresponding to the current process on the wafer image before the current process to obtain the process superimposed image corresponding to the current process; The defect analysis module 1106 is specifically configured to: Calculate the difference degree between the process superimposed images corresponding to adjacent processes respectively; Determine the process information where the defect appears and / or determine the evolution information of the defect with the production process according to the difference degree.

[0150] Figure 12 The following is a schematic physical structure diagram of the electronic device provided by the embodiments of the present application. As Figure 12 shown, the electronic device includes: a processor 1201, a memory 1202, and a bus 1203; wherein: The processor 1201 and the memory 1202 communicate with each other through the bus 1203; The processor 1201 is used to call the program instructions in the memory 1202 to execute the methods provided by the above method embodiments, for example, including: obtaining multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes or images of different wafers in the same production process; extracting the calibration features on each wafer image, where the calibration features are features used for positioning when aligning multiple wafer images; based on the calibration features, performing alignment processing on multiple wafer images to obtain multiple aligned wafer images; according to a preset superimposing rule, performing a superimposing operation on the multiple aligned wafer images to obtain a superimposed image; extracting the defect features on the superimposed image; according to the defect features, combining the state information of each component during the working process in the production process for analysis to obtain the factors causing the defects.

[0151] The processor 1201 may be an integrated circuit chip with signal processing capabilities. The aforementioned processor 1201 may be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. It can implement or execute various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0152] The memory 1202 may include, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.

[0153] This embodiment discloses a computer program product. The computer program product includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the methods provided in the above method embodiments, for example, including: obtaining multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes or images of different wafers in the same production process; extracting calibration features on each of the wafer images, where the calibration features are features used for positioning when aligning the multiple wafer images; aligning the multiple wafer images based on the calibration features to obtain aligned multiple wafer images; performing a superposition operation on the aligned multiple wafer images according to a preset superposition rule to obtain a superposed image; extracting defect features on the superposed image; analyzing according to the defect features in combination with the state information of each component during operation in the production process to obtain factors causing defects.

[0154] This embodiment provides a non-transitory computer-readable storage medium. The non-transitory computer-readable storage medium stores computer instructions, and the computer instructions cause the computer to execute the methods provided in the above method embodiments. For example, it includes: obtaining multiple wafer images; the multiple wafer images are images corresponding to the same wafer in different production processes or images of different wafers in the same production process; extracting calibration features on each of the wafer images, where the calibration features are features used for positioning when aligning the multiple wafer images; aligning the multiple wafer images based on the calibration features to obtain the aligned multiple wafer images; performing a superposition operation on the aligned multiple wafer images according to a preset superposition rule to obtain a superposed image; extracting defect features on the superposed image; and analyzing based on the defect features in combination with the state information of each component during operation in the production process to obtain the factors causing the defects.

[0155] In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some communication interfaces. The indirect coupling or communication connection of the devices or units can be in an electrical, mechanical or other form.

[0156] In addition, the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0157] Furthermore, in each embodiment of this application, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0158] In this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0159] The above are only embodiments of the present application and are not intended to limit the protection scope of the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.

Claims

1. A defect analysis method based on wafer image overlay, characterized in that, Including: Obtaining multiple wafer images; The multiple wafer images are images corresponding to the same wafer in different production processes or images of different wafers in the same production process; Extracting calibration features on each of the wafer images, where the calibration features are features used for positioning when aligning the multiple wafer images; Performing alignment processing on the multiple wafer images based on the calibration features to obtain the aligned multiple wafer images; Performing a superposition operation on the aligned multiple wafer images according to a preset superposition rule to obtain a superposed image; Extracting defect features on the superposed image; Analyzing according to the defect features in combination with the state information of each component during the working process in the production process to obtain the factors causing the defects.

2. The method according to claim 1, wherein The image type of the wafer image is an AOI image; the wafer image includes defect information, and the defect information includes defect type and defect location; the superposed image includes a first single-defect superposed image; the performing a superposition operation on the aligned multiple wafer images according to a preset superposition rule to obtain a superposed image includes: Extracting defect images containing a single defect type from the wafer images based on the defect type; Counting the number of first defect images with defects at the same pixel position for the defect images of the same defect type; Generating a first single-defect superposed image according to the number of first defect images.

3. The method according to claim 2, wherein The superposed image further includes a first multi-defect superposed image, and the method further includes: Counting the number of second defect images with a first target defect type at the same pixel position in the first single-defect superposed image, and generating the first multi-defect superposed image according to the number of second defect images; where the first target defect type is all defect types or some defect types selected from all defect types.

4. The method according to claim 1, wherein The image type of the wafer image is an AOI image; the wafer image includes defect information, and the defect information includes defect type and defect location; the superposed image includes a second single-defect superposed image; the performing a superposition operation on the aligned multiple wafer images according to a preset superposition rule to obtain a superposed image includes: Extracting defect images containing a single defect type from the wafer images based on the defect type; Performing grid division on the defect images corresponding to each defect type to obtain multiple grid images; For each defect type, counting the number of defective chips contained in each grid image in the corresponding defect image; According to the number of defective chips contained in each grid image obtained by statistics, calculating the superposition value corresponding to the grid images at the same position in the multiple defect images of the same defect type according to a preset superposition algorithm, and generating a second single-defect superposed image based on the superposition value.

5. The method according to claim 4, characterized in that, The superposed image further includes a second multi-defect superposed image, and the method further includes: Count the number of chips with the second target defect type on the same grid image in the second single-defect superimposed image, and generate the second multi-defect superimposed image according to the number of chips; wherein, the second target defect type is all defect types or some defect types selected from all defect types.

6. The method according to claim 1, characterized in that, The image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter values at each pixel position of the wafer; the operation of superimposing the aligned multiple wafer images according to a preset superimposing rule to obtain a superimposed image includes: Perform a superimposing calculation on the target measurement parameter values at the same pixel position in multiple wafer images according to a preset superimposing algorithm to obtain a first superimposed parameter value; the preset superimposing algorithm includes summation, mean, variance, and standard deviation; Generate the superimposed image according to the first superimposed parameter value.

7. The method according to claim 1, wherein The image type of the wafer image is a mapping image; the wafer image is generated based on the target measurement parameter values at each pixel position of the wafer; the operation of superimposing the aligned multiple wafer images according to a preset superimposing rule to obtain a superimposed image includes: Divide each wafer image into grids to obtain multiple second grid images corresponding to each wafer image; Calculate the mean value of the target measurement parameter values within each second grid image to obtain the parameter mean value corresponding to each second grid image; Perform a superimposing calculation on the parameter mean values of the second grid images at the same position in multiple wafer images according to a preset superimposing algorithm to obtain a second superimposed parameter value; Generate the superimposed image according to the second superimposed parameter value.

8. The method according to claim 1, characterized in that, Before performing the operation of superimposing the aligned multiple wafer images according to a preset superimposing rule, the method further includes: If the wafer image contains line defects, intercept a line defect image from the image of the wafer according to the position of the line defects; Extract the skeleton of the line defects from the line defect image to obtain a skeleton image; Correspondingly, the operation of superimposing the aligned multiple wafer images according to a preset superimposing rule includes: Perform a superimposing operation on the skeleton images according to a preset superimposing rule.

9. The method according to claim 1, characterized in that The analysis of obtaining the factors causing the defects by combining the defect characteristics with the state information of each component in the working process of the production process includes: Analyze according to the defect characteristics and combine the state information of each component in the working process of the production process to obtain the process information and component information causing the defects.

10. The method according to any one of claims 1-9, characterized in that, The operation of superimposing the aligned multiple wafer images according to a preset superimposing rule to obtain a superimposed image includes: For the case where multiple wafer images are images of the same wafer in different processes, superimpose the wafer image corresponding to the current process with the wafer image before the current process to obtain the process superimposed image corresponding to the current process; The analysis of obtaining the factors causing the defects by combining the defect characteristics with the state information of each component in the working process of the production process includes: Calculate the difference degree between the process superposition images corresponding to adjacent processes; Determine the process information where the defect appears and / or determine the evolution information of the defect along with the production process according to the difference degree.

11. An electronic device, characterized in that, Comprising: A processor, a memory and a bus, wherein: The processor and the memory complete communication with each other through the bus; The memory stores program instructions executable by the processor, and the processor can execute the method according to any one of claims 1-10 by invoking the program instructions.

12. A non-transitory computer-readable storage medium, characterized in that, The non-transitory computer-readable storage medium stores computer instructions, and when the computer instructions are run by the computer, the computer executes the method according to any one of claims 1-10.

13. A computer program product, characterized in that, Comprising computer program instructions, and when the computer program instructions are read and run by a processor, the method according to any one of claims 1-10 is executed.

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