A chip packaging defect detection method based on YOLOv11m for edge devices

Abstract

The present invention relates to the field of computer vision target detection and proposes a chip package defect detection method based on YOLOv11m applied to edge devices. The method comprises: obtaining a chip package defect dataset, performing data enhancement on the dataset and dividing the dataset into a training set, a test set and a validation set; innovating the network structure of the model, adopting a Starnet network as the backbone network and combining modules such as C2CGA and SimAM to enhance feature extraction and key feature capture, introducing GSConv technology and an improved module based on the GSConv technology to optimize the feature pyramid structure, and using the innovative LWNBDet detection head to fuse multi-scale features in the detection head to achieve efficient target prediction; importing the dataset into the detection model for training to obtain an improved model; while maintaining detection accuracy, the improved model significantly improves detection speed, reduces model size and computational complexity, and enhances the feasibility of deployment on edge devices.

Description

Technical Field

[0001] The present invention relates to the field of computer vision target detection, and in particular to a chip packaging defect detection method based on YOLOv11m applied to edge devices. Background Art

[0002] In today's rapidly evolving technological landscape, the semiconductor industry, as the core and cornerstone of the modern information technology industry, is booming. The rise of emerging technologies such as 5G communications, artificial intelligence, and the Internet of Things has led to explosive growth in chip demand. Not only is the number of chips continuing to climb, but the requirements for performance, size, and integration are also becoming increasingly stringent. As chip integration continues to increase, the chip packaging process becomes increasingly critical. During the packaging process, any slight deviation can cause packaging defects on the chip surface, which can seriously affect the chip's reliability and performance. In large-scale chip production, accurately detecting various surface packaging defects while ensuring efficient detection speeds has become a key challenge that the industry urgently needs to address.

[0003] Traditional chip inspection methods have numerous drawbacks. Manual visual inspection is highly subjective, making it difficult to detect minor defects and extremely inefficient. While automated optical inspection has improved inspection efficiency to a certain extent, it lacks the ability to recognize complex textures and multi-layered structures on chip surfaces, and is prone to misjudgment when interference factors such as reflections and shadows are present on the chip surface. While electron beam inspection can provide high-resolution images, the equipment is expensive to purchase, and the electron beam carries the potential risk of damaging the chip surface during inspection. Inspection speed is also relatively slow, with a long inspection time per square centimeter. This hinders its large-scale application in the current pursuit of efficient, non-destructive testing.

[0004] Despite its impressive performance in target detection, YOLOv11m still faces significant shortcomings when applied to chip packaging defect detection. Chip packaging defects are complex and tiny, making conventional YOLOv11m's small-target detection capabilities insufficient, leading to missed detections. Furthermore, chip production lines place extremely high demands on real-time detection. Conventional YOLOv11m's computational complexity under high-resolution images makes it difficult to achieve the required inference speed. Furthermore, the limited resources of edge computing devices commonly used in chip workshops make conventional YOLOv11m's large model parameters difficult to implement in a lightweight deployment. These issues make it difficult for conventional YOLOv11m to achieve a balance between detection accuracy, real-time performance, and deployment feasibility, necessitating urgent improvements.

[0005] Similar needs exist in other fields, and some effective improvement solutions have been developed. For example, the lightweight layered architecture of the Starnet backbone network can reduce the amount of computation and improve feature extraction capabilities in fields such as small target detection in medical images and real-time detection in autonomous driving. The SimAM attention mechanism and GSConv lightweight convolution technology also demonstrate their value in scenarios such as focusing on key features of remote sensing images and optimizing the computing cost of on-board edge devices. In the field of chip packaging defect detection, Starnet's layered architecture adapts to the characteristics of small targets and reduces the amount of computation. The SimAM attention mechanism adapts to the complex background and defects that are easily disturbed by interference in the image. The GSConv technology is suitable for low-computing-power edge devices. These improved technologies have shown good adaptability and application potential in this field.

[0006] Faced with these challenges, traditional detection methods and existing object detection models are gradually exposing their limitations and are unable to meet the growing industry needs. Furthermore, solutions that address similar needs in other fields have not yet been effectively applied to this field. Therefore, an innovative and efficient detection model is urgently needed to fill this gap. Summary of the Invention

[0007] Based on the original YOLOv11 model, this paper provides a chip package defect detection method based on YOLOv11m and applied to edge devices. While maintaining detection accuracy, it aims to improve the detection speed of chip package defects, reduce model size and computational complexity, and enhance the feasibility of deployment on edge devices.

[0008] The present invention is specifically implemented through the following technical solutions. According to the present invention, a chip package defect detection method based on YOLOv11m applied to edge devices is proposed, and the steps are as follows:

[0009] Step 1: Take an image of the packaged chip, mark the coordinates of the defect locations in the image, and export the coordinate file and image to form a data set;

[0010] Step 2: Data enhancement of the dataset, including cropping and splicing the images, flipping the images, and adjusting the brightness, contrast, and saturation of the images;

[0011] Step 3: Divide the dataset into training set, test set, and validation set in a ratio of 8:1:1;

[0012] Step 4: Build the YOLOv11-ALE target detection model. Its network structure includes the Backbone module, Neck module, and Head module, which are responsible for feature extraction, feature fusion, and target prediction respectively.

[0013] The Backbone module adopts the Starnet network structure, and then replaces the original C2PSA module with the C2CGA module to adjust the feature correlation between channels, and then adds the SimAM attention module to strengthen the key feature output;

[0014] The Neck module introduces the lightweight convolution technology GSConv to replace the original Conv module, combining standard convolution with depthwise convolution, outputting through a 1×1 convolutional hybrid channel, and then replacing the original C3k2 module with the MSR-VoVGSCSP module based on GSConv. Through cross-level connection and fusion strategies, feature processing and structural optimization are completed.

[0015] The Head module adopts the LWNBDet detection head, which uses a bidirectional feature propagation architecture to connect and fuse multi-scale features across scales, determine feature importance in a weighted manner, and achieve efficient target detection;

[0016] Step 5: Import the data set into the network for training to obtain the improved target detection model;

[0017] In step 6, the obtained model format is converted into an edge device compatible format, ported to the edge device, and chip packaging defects are detected.

[0018] Furthermore, the data enhancement of the dataset includes: cropping the portion of the image containing the defect, and then evenly arranging 4-8 cropped images and splicing them into one image; flipping the image horizontally or vertically; increasing the brightness, contrast, and saturation of the image by 25% and decreasing it by 25%, respectively; and combining the above methods on the same image to make the defect features more prominent, which helps the model better capture the subtle details of the defect edges.

[0019] Furthermore, the Starnet network structure adopts a four-stage layered architecture. First, the input image is downsampled through convolutional layers, changing the size and dimensionality of the input feature map. Batch normalization replaces the original normalization and is applied post-process to facilitate fusion during inference. GELU is replaced with ReLU6 to simplify computation. Star Blocks then perform further feature extraction. Next, convolutional layers perform another downsampling, further reducing the feature map size and increasing the number of channels. Star Blocks then extract more abstract features. The convolutional downsampling process is repeated, further reducing the feature map resolution and doubling the number of channels. Star Blocks further enrich the feature representation. Finally, convolutional downsampling occurs again, followed by feature extraction through Star Blocks, and the output is processed through global average pooling and fully connected layers. Depthwise separable convolutions are added at the end of each module, extracting local features through depthwise convolutions and integrating channel information through pointwise convolutions. Star blocks contain two branches, which are fused through linear transformations, element-wise multiplications, and residual connections to enhance feature representation. The network channel expansion factor is fixed at 4, with the width doubling at each stage. The number of blocks and embedding channels can be adjusted to suit different scenarios.

[0020] Furthermore, the C2PSA module in the baseline model network structure of the Backbone module is replaced with the C2CGA module. After C2CGA is embedded in the baseline model, the input feature map is divided into multiple groups by channel. The number of input channels is 1024, which are divided into 16 groups, each with 64 channels. The attention is calculated independently for each feature group. During cascade fusion, the previous output is spliced with the current group to enhance cross-scale interaction, optimize the network structure, and adapt to chip packaging defect detection.

[0021] Furthermore, the SimAM attention mechanism is introduced in the Backbone module. First, the feature map with the dimension of N×C×H×W output from the previous layer is received. Then, an energy function is constructed based on the "spatial inhibition" theory of neuroscience to solve the importance value of each neuron. , generating 3D attention weights covering channel and spatial dimensions; then, after processing these weights with the sigmoid function, they are multiplied element-by-element with the original feature map to highlight key features and suppress redundancy; finally, the processed feature map is output.

[0022] Furthermore, the lightweight convolution technology GSConv divides the input feature map into two groups, one group undergoes standard convolution and the other group undergoes depth-wise separable convolution, and then fuses the features through channel rearrangement, reducing the amount of computation while retaining the feature expression capability.

[0023] Furthermore, the MSR-VoVGSCSP module is built on the basis of GSConv, which divides the input feature map into two branches through cross-level connections, performs GSConv operation in each branch, and introduces multi-scale 3×3 and 5×5 convolution kernels in parallel to process branch features and capture information of different scales. The output of each branch is fused element-by-element with the shallow features transmitted by the residual connection, and then the branch features are spliced and fused to optimize the feature pyramid structure and enhance the feature representation capability.

[0024] Furthermore, the LWNBDet detection head constructs a multi-level feature interaction system, extracting the original resolution from different convolution stages of the backbone network. Figure 1 The system uses feature maps with sizes of 1 / 16, 1 / 32, 1 / 64, and 1 / 128. By building a bidirectional parallel transmission link, upsampled and downsampled features are element-by-element added and channel-wise concatenated. Nodes that transmit only as a single data stream are eliminated, and bypass connections are established between features at the same level to enhance information reuse. For each input feature branch, a trainable weight vector is deployed to weight the channel dimension, and the feature fusion coefficient is calculated based on the normalized fusion formula. The fused feature matrix is finally input into a bounding box-category prediction network composed of shared parameter convolutional layers to achieve defect location regression and category determination.

[0025] Furthermore, the format of the obtained model is converted into a format compatible with edge devices. After being transplanted to the edge device, the following steps are taken to realize package chip defect detection: establishing a feature library containing package defects, scratch defects, pin defects, and stain defects; setting a confidence threshold, and judging the validity of the result based on the confidence of the model recognition result; realizing defect size measurement through pixel-physical size calibration algorithm; setting an early warning mechanism to generate different levels of quality alerts based on production requirements, defect type, size and confidence.

[0026] The YOLOv11-ALE chip package defect detection model of the present invention optimizes the YOLOv11m model, introduces the Starnet backbone network, and uses a lightweight layered architecture to reduce the amount of computation and adapt to the extraction of small target defect features; adopts the CSCGA module grouping mechanism to reduce the computational complexity while enhancing cross-group feature interaction; adds the SimAM attention mechanism to focus on key feature points of defects; improves the original convolution operation, GSConv combines standard convolution with depth convolution to reduce computational cost and accelerate Neck layer reasoning, and the improved MSR-VoVGSCSP module based on GSConv improves cross-layer connection efficiency and adapts to defect features of different sizes; with the help of the bidirectional feature propagation architecture of the LWNBDet detection head, cross-scale connections are used to fuse multi-scale features and weightedly determine feature importance, reducing invalid operations. While maintaining detection accuracy, the detection speed of chip package defects is greatly improved, the model size and computational complexity are reduced, and the feasibility of deployment on edge devices is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a flowchart of a lightweight chip packaging defect detection model based on YOLOv11m and a construction method thereof of the present invention.

[0028] Figure 2 This is a schematic diagram of the network structure of the improved YOLOv11-ALE target detection model of the present invention.

[0029] Figure 3 This is a structural diagram of the SimAM attention mechanism module.

[0030] Figure 4 This is a structural diagram of the GSConv module.

[0031] Figure 5 It is a schematic diagram of the MSR-VoVGSCSP structure.

[0032] Figure 6 This is a structural diagram of the LWNBDet detection head.

[0033] Figure 7 This is a comparison chart of YOLOv11 and YOLOv11-ALE training indicators changing with training rounds, where Figure 7 a is a comparison chart of the accuracy of YOLOv11 and YOLOv11-ALE; Figure 7 b is the comparison chart of recall rates between YOLOv11 and YOLOv11-ALE; Figure 7 c is a comparison chart of the mean average precision of YOLOv11 and YOLOv11-ALE with an orthogonality ratio threshold of 0.5; Figure 7 d is a comparison chart of the mean average precision between YOLOv11 and YOLOv11-ALE with orthogonality ratio thresholds between 0.5 and 0.95.

[0034] Figure 8 This is a comparison chart of the loss curves of YOLOv11 and YOLOv11-ALE, where Figure 8 a is a comparison of the bounding box loss of the YOLOv11 and YOLOv11-ALE training sets; Figure 8 b is a comparison of the step-by-step focal loss of the YOLOv11 and YOLOv11-ALE training sets; Figure 8 c is a comparison chart of the classification loss of YOLOv11 and YOLOv11-ALE training sets; Figure 8 d is a comparison of the bounding box loss of the YOLOv11 and YOLOv11-ALE validation sets; Figure 8 e is a comparison chart of the step-by-step focal loss of the YOLOv11 and YOLOv11-ALE validation sets; Figure 8f is a comparison chart of the classification loss of the YOLOv11 and YOLOv11-ALE validation sets.

[0035] Figure 9 This is the detection effect diagram of the YOLOv11-ALE chip packaging defect detection network. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the present invention clearer, the specific embodiments of the present invention are further described below with reference to the accompanying drawings.

[0037] Figure 1 The flowchart of the method of the present invention is as follows: a lightweight chip package defect detection model based on YOLOv11m and a construction method thereof provided by the present invention specifically include the following steps:

[0038] Step 1: Take an image of the packaged chip, mark the coordinates of the defect locations in the image, and export the coordinate file and image to form a data set.

[0039] Step 2: Data enhancement of the dataset, including cropping and splicing the images, flipping the images, and adjusting the brightness, contrast, and saturation of the images.

[0040] In step 2, the data enhancement of the dataset includes: cropping the portion of the image containing the defect, and then evenly arranging 4-8 cropped images and splicing them into one image; flipping the image horizontally or vertically; increasing the brightness, contrast, and saturation of the image by 25% and decreasing it by 25%, respectively; and combining the above methods on the same image to make the defect features more prominent, which helps the model better capture the subtle details of the defect edge.

[0041] In step 3, write a Python script to divide the images in the public dataset into training, test, and validation sets in an 8:1:1 ratio. Next, write a program to convert the original dataset labels into a format suitable for the YOLO model and create a summary file (data.yaml) that stores the relative paths and categories of each dataset.

[0042] Step 4: Build the YOLOv11-ALE target detection model. Its network structure includes the Backbone module, Neck module, and Head module, which are responsible for feature extraction, feature fusion, and target prediction, respectively.

[0043] The Starnet network structure is added to the Backbone module, which adopts a four-stage layered architecture. First, the input image is downsampled through the convolution layer to change the size and dimension of the input feature map; batch normalization is used to replace the original normalization and post-process it to facilitate fusion operations during inference; GELU is replaced with ReLU6 to simplify calculations; and then Star Blocks is used to further extract features. Secondly, the convolution layer is downsampled again, the feature map size is further reduced, the number of channels is increased, and then StarBlocks extracts more abstract features. Then, the convolution downsampling process is repeated, the feature map resolution continues to decrease, and the number of channels continues to double, and Star Blocks makes the feature expression richer. Finally, convolution downsampling is performed again, and then features are extracted by Star Blocks, and the results are output through global average pooling and fully connected layers. Depthwise separable convolution is added at the end of each module to extract local features by depthwise convolution and integrate channel information by pointwise convolution. The star operation block contains two branches, which are linearly transformed, element-by-element multiplied and fused, and output with residual connections to enhance feature expression. The network channel expansion factor is fixed at 4, the width is doubled at each stage, and the number of blocks and embedded channels is adjusted to adapt to different scenarios.

[0044] Its mathematical expression is as follows:

[0045]

[0046]

[0047]

[0048] Here, i and j are used to index the channels, and α is the coefficient of each term:

[0049]

[0050] After rewriting the star operation, it is expanded into a Each term (with x) shows a nonlinear correlation, indicating that it is an independent and implicit dimension. Finally, by stacking multiple layers, the implicit dimension is infinitely increased in a recursive manner.

[0051] The batch normalization formula is:

[0052]

[0053] in, is the first The original eigenvalues of the channels.

[0054] Secondly, the C2PSA module in the baseline model network structure of the Backbone module is replaced with the C2CGA module. After C2CGA is embedded in the baseline model, the input feature map is divided into multiple groups by channel. The number of input channels is 1024, which are divided into 16 groups, each with 64 channels. The attention is calculated independently for each feature group. During cascade fusion, the previous output is spliced with the current group to enhance cross-scale interaction, optimize the network structure, and adapt to chip packaging defect detection.

[0055] The group attention calculation formula is as follows:

[0056]

[0057] in, is the learnable parameter matrix, Indicates the number of channels of the input feature map, Indicates the number of groups into which the input feature map is divided along the channel dimension.

[0058] The attention score calculation formula is as follows:

[0059]

[0060] in, is a scaling factor used to prevent gradient vanishing.

[0061] The cross-scale interaction formula is as follows:

[0062]

[0063] Among them, Projection is the dimension alignment operation, and Fuse is the fusion function.

[0064] Then, the SimAM attention mechanism is introduced in the Backbone module. First, the dimension of the output of the previous layer is received. Then, based on the "spatial inhibition" theory of neuroscience, an energy function is constructed to solve the importance value of each neuron. , generating 3D attention weights covering channel and spatial dimensions; then, after processing these weights with the sigmoid function, they are multiplied element-by-element with the original feature map to highlight key features and suppress redundancy; finally, the processed feature map is output.

[0065] The energy function is as follows:

[0066]

[0067] in, is the target neuron, are other neurons in the same channel, is the number of neurons in the channel, and are the weights and biases of the linear transformation, is the regularization coefficient.

[0068] The minimum energy at each position can be obtained by the following formula:

[0069]

[0070] in, Represents the mean of all neurons (including target neuron t) in the same channel of the feature map, Represents the variance of all neurons (including target neuron t) in the same channel of the feature map.

[0071] The sigmoid function is as follows:

[0072]

[0073] in, Integrates all neurons , Represents element-wise multiplication.

[0074] In the Neck module, the Conv module in the baseline model is replaced with the GSConv module, such as Figure 4 As shown in the figure, GSConv divides the input feature map into two groups, one group undergoes standard convolution and the other group undergoes depth-wise separable convolution, and then fuses the features by channel rearrangement, reducing the amount of computation while retaining the feature expression ability.

[0075] In the Neck module, the C3k2 module is replaced with the MSR-VoVGSCSP module, such as Figure 5 As shown in the figure, it is built on the basis of GSConv, which divides the input feature map into two branches through cross-level connections, performs GSConv operation in each branch, and introduces multi-scale 3×3 and 5×5 convolution kernels in parallel to process branch features and capture information of different scales. The output of each branch is fused with the shallow features transmitted by the residual connection element by element, and then the branch features are spliced and fused to optimize the feature pyramid structure and enhance the feature representation capability.

[0076] The multi-scale feature fusion formula is as follows:

[0077]

[0078]

[0079]

[0080] in, is the output feature map of the 3×3 convolution branch, is the output feature map of the 5×5 hole convolution branch, BN represents batch normalization, and ReLU represents the activation function. represents a 3×3 dilated convolution with a dilation rate of 2, It is the output feature map after multi-scale feature fusion.

[0081] The Head module uses LWNBDet detection head, such as Figure 6 As shown in the figure, it builds a multi-level feature interaction system, extracting the original resolution from different convolution stages of the backbone network. Figure 1 The system uses feature maps with sizes of 1 / 16, 1 / 32, 1 / 64, and 1 / 128. By building a bidirectional parallel transmission link, upsampled and downsampled features are element-by-element added and channel-wise concatenated. Nodes that transmit only as a single data stream are eliminated, and bypass connections are established between features at the same level to enhance information reuse. For each input feature branch, a trainable weight vector is deployed to weight the channel dimension, and the feature fusion coefficient is calculated based on the normalized fusion formula. The fused feature matrix is finally input into a bounding box-category prediction network composed of shared parameter convolutional layers to achieve defect location regression and category determination.

[0082] The formula for fast normalization fusion is:

[0083]

[0084] is the normalized weight coefficient of the kth input feature, ranging between [0,1], Indicates the contribution of the feature in the fusion process; is a learnable original weight parameter, which is dynamically adjusted through network training; m is the total number of feature branches involved in the fusion.

[0085] In step 5, the dataset is imported into the network for training to obtain the improved YOLOv11-ALE target detection model, and the training results are evaluated.

[0086] The operations in step 5 are as follows: the computational complexity, parameter count, model size, and image processing speed of the statistical model, as well as the Precision and mAP50 on the test set, are compared with the original YOLOv11 target detection method. The results are shown in Table 1 below.

[0087] Table 1

[0088]

[0089] As shown in Table 1, compared with the original YOLOv11 model, although the accuracy of the proposed model is slightly reduced, the GFLOPs are reduced by 74.2%, the number of parameters is reduced by 56.0%, and the model size is reduced by 55.6%. At the same time, the FPS is improved by 88.2%, meeting the requirements of detection accuracy and feasibility of deployment on edge devices.

[0090] In step 6, the obtained model format is converted into an edge device-compatible format, ported to the edge device, and then packaged chip defect detection is implemented through the following steps: establishing a feature library containing package defects, scratch defects, pin defects, and stain defects; setting a confidence threshold to judge the validity of the result based on the confidence of the model recognition result; realizing defect size measurement through the pixel-physical size calibration algorithm; setting an early warning mechanism to generate different levels of quality alerts based on production requirements, defect type, size, and confidence.

[0091] The model training environment of the present invention is as follows: the CPU uses Intel(R) Core(TM) i9-13900HX @ 2.2 GHz, the GPU uses NVIDIA GeForce RTX4080 Laptop, the running memory is 32GB, the operating system is Windows 11, the CUDA version is 12.6, the deep learning framework is PyTorch, based on the YOLO11m model, and the embedded development version is NVIDIA JetsonOrin NX 16GB.

Claims

1. A chip package defect detection method based on YOLOv11m applied to edge devices, characterized in that: The steps include: Step 1: Take an image of the packaged chip, mark the coordinates of the defect locations in the image, and export the coordinate file and image to form a data set; Step 2: Data enhancement of the dataset, including cropping and splicing the images, flipping the images, and adjusting the brightness, contrast, and saturation of the images; Step 3: Divide the dataset into training set, test set, and validation set in a ratio of 8:1:1; Step 4: Build the YOLOv11-ALE target detection model. Its network structure includes the Backbone module, Neck module, and Head module, which are responsible for feature extraction, feature fusion, and target prediction respectively. The Backbone module adopts the Starnet network structure, and then replaces the original C2PSA module with the C2CGA module to adjust the feature correlation between channels, and then adds the SimAM attention module to strengthen the key feature output; The Neck module introduces the lightweight convolution technology GSConv to replace the original Conv module, combining standard convolution with depthwise convolution, outputting through a 1×1 convolutional hybrid channel, and then replacing the original C3k2 module with the MSR-VoVGSCSP module based on GSConv. Through cross-level connection and fusion strategies, feature processing and structural optimization are completed. The Head module adopts the LWNBDet detection head, which uses a bidirectional feature propagation architecture to connect and fuse multi-scale features across scales and determine the feature importance in a weighted manner; Step 5: Import the data set into the network for training to obtain the improved target detection model; Step 6: Convert the obtained model format into an edge device compatible format, port it to the edge device, and detect chip packaging defects; The Starnet network structure adopts a four-stage layered architecture. First, the input image is processed by convolutional layers, batch normalization and ReLU6 activation function to extract initial features, and then enters Star Blocks for further feature extraction. Secondly, it is downsampled again by convolutional layers, the feature map size is further reduced and the number of channels is increased, and then Star Blocks extract more abstract features. Then, the convolutional downsampling process is repeated, the feature map resolution is continuously reduced and the number of channels is further doubled, and Star Blocks make the feature expression richer. Finally, convolutional downsampling is performed again, and then features are extracted by Star Blocks, and the output is output through global average pooling and fully connected layers. The C2PSA module in the baseline model network structure of the Backbone module is replaced with the C2CGA module. After C2CGA is embedded in the baseline model, the input feature map is divided into multiple groups by channel. The number of input channels is 1024, which are divided into 16 groups, each with 64 channels. The attention is calculated independently for each feature group. During cascade fusion, the previous output is spliced with the current group to enhance cross-scale interaction and optimize the network structure. The SimAM attention mechanism is introduced in the Backbone module. It first receives the feature map output by the previous layer. Then, it constructs an energy function based on the "spatial inhibition" theory of neuroscience to obtain the importance value of each neuron and generate 3D attention weights covering channel and spatial dimensions. Subsequently, after these weights are processed by the sigmoid function, they are multiplied element-by-element with the original feature map; finally, the processed feature map is output; The lightweight convolution technology GSConv divides the input feature map into two groups, one group undergoes standard convolution and the other group undergoes depth-wise separable convolution, and then fuses the features through channel rearrangement; The MSR-VoVGSCSP module is built on GSConv. It divides the input feature map into two branches through cross-level connections, performs GSConv operations on each branch, and introduces multi-scale 3×3 and 5×5 convolution kernels in parallel to process branch features and capture information at different scales. The shallow features transmitted by the residual connection of each branch are added and fused element by element, and then the branch features are fused by splicing. The LWNBDet detection head is based on a bidirectional feature propagation architecture and obtains differentiated scale feature sets from the backbone network layer by layer. It constructs a cross-hierarchical feature flow path, eliminates redundant unidirectional connection nodes, adds direct connection channels for features at the same level, and uses an adaptive weight allocation mechanism to parameterize each input feature. After optimization through a normalized fusion strategy, the integrated features are output to the target positioning and classification prediction module.

2. The chip package defect detection method based on YOLOv11m applied to edge devices according to claim 1 is characterized in that: The data enhancement of the dataset includes: cropping the defective portion of the image, and then evenly arranging and splicing 4-8 cropped images into one image; flipping the image horizontally or vertically; and increasing and decreasing the brightness, contrast, and saturation of the image by 25% and 25%, respectively.

3. The chip package defect detection method based on YOLOv11m applied to edge devices according to claim 1 is characterized in that: The format of the obtained model is converted into an edge device compatible format. After being transplanted to the edge device, the following steps are taken to realize package chip defect detection: establishing a feature library containing package defects, scratch defects, pin defects, and stain defects; setting a confidence threshold according to production needs, and judging the validity of the result based on the confidence of the model recognition result; realizing defect size measurement through the pixel-physical size calibration algorithm; setting an early warning mechanism to generate different levels of quality alarms based on production needs, defect type, size and confidence.

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