Gate driving circuit and display panel

Abstract

The application discloses a gate driving circuit and a display panel. The gate driving circuit comprises a plurality of cascaded gate driving units. Each gate driving unit comprises a first output unit, a second output unit and a control unit. The first output unit is used for outputting a pulse signal of the gate driving unit. The second output unit is used for outputting a pulse signal of a next-stage gate driving unit. The control unit is connected with the first output unit and the second output unit, and is used for controlling the work of the first output unit and / or the second output unit, so as to realize the switching of a first driving mode and a second driving mode.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display panels, and in particular to a gate driving circuit and a display panel. BACKGROUND

[0002] With the continuous development of TFT display technology, the market demand for higher refresh rate applications will be increasingly large, especially in the field of game display, some e-sports players will be very fond of, high refresh rate display will make the game more smooth, but at the same time, with the increase of refresh rate, the power consumption will be higher and higher. In order to solve the problem of high power consumption in the high refresh rate scenario, some display technologies currently existing in the industry are based on Normal (normal display mode) and push out frequency doubling display technology. Frequency doubling display technology includes DLG (Dual Line Gate, dual line gate technology) and HSR (Hardware Super Resolution, hardware super resolution). DLG technology is to change the original line-by-line scanning mode to scan two lines at a time, that is, Gate two lines are opened at the same time, and Source two lines output the same data (two lines of content are the same), so as to realize the doubling of pixel charging time and double the refresh rate. HSR technology is also a kind of frequency doubling technology, which mainly realizes difference display through timing adjustment, that is, in each frame of image, only the pixels of odd or even rows are rendered, and the other row is fused with the information of adjacent two rows for display.

[0003] Taking a UHD (Ultra High Definition, ultra high definition) 3840*2160 resolution 240Hz refresh rate product as an example, frequency doubling display technology reduces the display resolution to half, that is, two rows of pixels display the same data, and the refresh rate is increased to 480Hz, which is twice the original. However, the total data transmission rate remains unchanged. These display technologies update all pixels at the same time after a frame, and the simultaneous update may cause flicker phenomenon; however, although the frequency doubling display technology reduces the total amount of data by half, the transfer stages and frequency of GOA (gate driving circuit) remain unchanged. Taking UHD (ultra high definition) as an example, after adopting DLG technology, Gate (gate) is switched at least 2160 times in a frame, and 2160 times of data are output by the driving IC, so there is still room for power consumption to decrease. For example, in the AOD (always on display, always-on display) display of OLED (Organic Light Emitting Display, organic light emitting display), there are a large number of black state regions in the image, and GOA scans according to the pixel row, which can be regarded as a kind of redundant frequency, which greatly affects the service life of GOA.

[0004] Therefore, in order to solve the problems of high brush and high power consumption and the life reduction caused by high frequency use of GOA, it is urgent to provide a new design of gate drive circuit. SUMMARY

[0005] The technical problem solved by the present application is to provide a gate drive circuit and a display panel, which realize switching of conventional driving and frequency doubling driving and multiplexing of the gate drive circuit, and are suitable for high refresh rate panels.

[0006] To solve the above problems, the present application provides a gate drive circuit in a first aspect, wherein the gate drive circuit comprises: a plurality of cascaded gate drive units, each of the gate drive units comprising: a first output unit configured to output a pulse signal of the gate drive unit; a second output unit configured to output a pulse signal of a next stage gate drive unit; and a control unit connected with the first output unit and the second output unit, configured to control the working of the first output unit and / or the second output unit to realize switching between a first driving mode and a second driving mode; wherein in the first driving mode, the control unit controls the first output unit to work and the second output unit not to work, so that each of the gate drive units outputs the pulse signal in turn; and in the second driving mode, the control unit controls the first output unit and the second output unit to work to output the same adjacent two-stage pulse signals.

[0007] Each of the gate drive units further comprises a first cascade control unit, a control end of the first cascade control unit being connected with a previous stage gate drive unit or a high potential signal line, configured to control the output of the first output unit according to the previous stage gate drive unit or the high potential signal line, so that the odd-numbered stage gate drive units output the pulse signal of the current stage and the pulse signal of the next stage at the same time, and the even-numbered stage gate drive units have no output of the first output unit.

[0008] The control unit comprises: a first register connected with an output end of a first signal line or a gate drive unit of a previous stage, used for receiving a first start signal output by the first signal line or a pulse signal output by the gate drive unit of the previous stage, and outputting a first control signal according to the first start signal or the pulse signal of the previous stage; and a second register connected with an output end of a second signal line or gate drive units of two previous stages, used for receiving a second start signal output by the second signal line or a pulse signal output by the gate drive units of the two previous stages, and outputting a second control signal according to the second start signal or the pulse signal of the two previous stages; wherein an output end of the first register is connected with a control end of the first output unit, and an output end of the second register is connected with a control end of the second output unit, used for controlling the first output unit and / or the second output unit to work according to the first control signal and the second control signal.

[0009] The control unit further comprises: a first control unit connected with the output end of the first register and the control end of the first output unit, used for controlling the first output unit to output the pulse signal of the current stage according to the first control signal; and a second control unit connected with the output end of the second register and the control end of the second output unit, used for controlling the second output unit to output the pulse signal of a next stage according to the second control signal; and the control end of the first output unit is further connected with the second control unit, used for controlling the first output unit to output the pulse signal of the current stage according to the control signals output by the first control unit and the second control unit.

[0010] The first control unit comprises: a first sub-control unit connected with the first register, a high potential signal line and the first output unit, used for controlling the output of the first output unit according to the first control signal output by the first register; and a second sub-control unit connected with the first register, a low potential signal line and the first output unit, used for controlling the output of the first output unit according to the first control signal output by the first register; and the second control unit comprises: a third sub-control unit connected with the second register, the high potential signal line and the second output unit, used for controlling the output of the second output unit according to the second control signal output by the second register; and a fourth sub-control unit connected with the second register, the low potential signal line and the second output unit, used for controlling the output of the second output unit according to the second control signal output by the second register; wherein the first sub-control unit and the second sub-control unit comprise a group of transistors with opposite driving characteristics; and the third sub-control unit and the fourth sub-control unit comprise a group of transistors with opposite driving characteristics.

[0011] The control end of the second output unit is connected with the second register, and the input end is connected with the first output unit, for controlling the output of the next stage pulse signal according to the cascade signal transmitted by the second register, thereby realizing the switching of the first driving mode and the second driving mode.

[0012] The second cascade control unit has an input end connected with the first output unit and an output end connected with the input end of the next stage gate drive unit, for driving the next stage gate drive unit to work according to the pulse signal; the third cascade control unit has an input end connected with the first output unit and an output end connected with the input ends of the next two stage gate drive units, for driving the next two stage gate drive units to work according to the pulse signal; the control end of the second cascade control unit is connected with the output end of the first register; and the control end of the third cascade control unit is connected with the output end of the second register.

[0013] The first register comprises a first cascade unit having an input end connected with the first signal line or the output end of the previous stage gate drive unit and a control end connected with a first control signal line, for receiving the cascade signal transmitted by the previous stage gate drive unit; and a first storage unit connected with the output end of the first cascade unit, for storing the cascade signal transmitted by the previous stage gate drive unit; and the second register comprises a second cascade unit having an input end connected with the second signal line or the output ends of the previous two stage gate drive units and a control end connected with the first control signal line, for receiving the cascade signal transmitted by the previous two stage gate drive units; and a second storage unit connected with the output end of the second cascade unit, for storing the cascade signal transmitted by the previous two stage gate drive units.

[0014] The first register further comprises a first delay control unit having an input end connected with the output end of the first cascade unit and the first storage unit and a control end connected with a second control signal line, for delaying the control effect of the cascade signal transmitted by the previous stage gate drive unit on the first output unit; and a third storage unit connected with the output end of the first delay control unit, for storing the cascade signal transmitted by the previous stage gate drive unit; and the second register further comprises a second delay control unit having an input end connected with the output end of the second cascade unit and the second storage unit and a control end connected with the second control signal line, for delaying the control effect of the cascade signal transmitted by the previous two stage gate drive units on the second output unit and / or the first output unit; and a fourth storage unit connected with the output end of the second delay control unit, for storing the cascade signal transmitted by the previous two stage gate drive units.

[0015] To solve the above problems, the display panel provided in the second aspect of the present application comprises the gate drive circuit of any one of the first aspect.

[0016] The beneficial effects of the present application are: by cascading the control unit with the upper-stage gate drive unit or the upper-two-stage gate drive unit, and controlling the output of the first output unit and / or the second output unit according to the cascaded signal, the switching between the first driving mode and the second driving mode is realized, so as to solve the problems of high brush and high power consumption in the frequency doubling display mode, and the problem of life reduction caused by high frequency use of the gate drive circuit. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 The structural schematic diagram of an embodiment of the gate drive unit provided by the present application is shown in the figure.

[0019] Figure 2 The timing diagram of an embodiment of the first driving mode provided by the present application is shown in the figure.

[0020] Figure 3 The timing diagram of an embodiment of the second driving mode provided by the present application is shown in the figure.

[0021] Figure 4 The structural schematic diagram of an embodiment of the gate drive circuit provided by the present application is shown in the figure.

[0022] Figure 5 The structural schematic diagram of the gate drive circuit provided by the present application driven according to the first driving mode is shown in the figure.

[0023] Figure 6 The structural schematic diagram of the gate drive circuit provided by the present application driven according to the second driving mode is shown in the figure.

[0024] Figure 7 The structural schematic diagram of the first specific embodiment of the gate drive unit provided by the present application is shown in the figure.

[0025] Figure 8 The structural schematic diagram of the second specific embodiment of the gate drive unit provided by the present application is shown in the figure.

[0026] Figure 9 The structural schematic diagram of the third specific embodiment of the gate drive circuit provided by the present application is shown in the figure.

[0027] Figure 10 Structure diagram of a fourth embodiment of the gate drive circuit provided in the present application;

[0028] Figure 11 Structure diagram of a fifth embodiment of the gate drive unit provided in the present application;

[0029] Figure 12 Structure diagram of a sixth embodiment of the gate drive unit provided in the present application;

[0030] Figure 13 Structure diagram of a seventh embodiment of the gate drive unit provided in the present application;

[0031] Figure 14 Structure diagram of an eighth embodiment of the gate drive unit provided in the present application;

[0032] Figure 15 Structure diagram of a ninth embodiment of the gate drive circuit provided in the present application;

[0033] Figure 16 Circuit structure diagram of an embodiment of the gate drive unit provided in the present application;

[0034] Figure 17 First drive circuit diagram of the gate drive unit provided in the present application in a first drive mode;

[0035] Figure 18 Second drive circuit diagram of the gate drive unit provided in the present application in a first drive mode;

[0036] Figure 19 Third drive circuit diagram of the gate drive unit provided in the present application in a first drive mode;

[0037] Figure 20 Fourth drive circuit diagram of the gate drive unit provided in the present application in a first drive mode;

[0038] Figure 21 Fifth drive circuit diagram of the gate drive unit provided in the present application in a first drive mode;

[0039] Figure 22 First drive circuit diagram of the odd-stage gate drive unit provided in the present application in a second drive mode;

[0040] Figure 23 Second drive circuit diagram of the odd-stage gate drive unit provided in the present application in a second drive mode;

[0041] Figure 24 Third drive circuit diagram of the odd-stage gate drive unit provided in the present application in a second drive mode;

[0042] Figure 25 The fourth drive circuit diagram of the odd-stage gate drive unit in the second driving mode provided in the present application;

[0043] Figure 26 The fifth drive circuit diagram of the odd-stage gate drive unit in the second driving mode provided in the present application;

[0044] Figure 27 The drive circuit diagram of the even-stage gate drive unit in the second driving mode provided in the present application;

[0045] Figure 28 The structural schematic diagram of an embodiment of the display panel provided in the present application.

[0046] Symbol explanation:

[0047] GOA, gate drive unit; GOA(n), Nth-stage gate drive unit; scan, pulse signal; scan(n), Nth-stage pulse signal; 11, first output unit; 12, second output unit; 20, control unit; 21, first register; 22, second register; Q, output terminal of the first register; P, output terminal of the second register; 23, first control unit; 24, second control unit; 231, first sub-control unit; 232, second sub-control unit; 241, third sub-control unit; 242, fourth sub-control unit; 111, first sub-output unit; 112, second sub-output unit; 113, third sub-output unit; 114, fourth sub-output unit; 211, first cascaded unit; C1, first storage unit / first capacitor; 221, second cascaded unit; C2, second storage unit / second capacitor; XCK, first control signal line; 212, first delay control unit; C3, third storage unit / third capacitor; 222, second delay control unit; C4, fourth storage unit / fourth capacitor; CK, second control signal line; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; T14, fourteenth transistor; T15, fifteenth transistor; T16, sixteenth transistor; 1000, display panel; 1001, display area; 1002, non-display area. DETAILED DESCRIPTION

[0048] With reference to the accompanying drawings, the technical solutions in the embodiments of the present application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0049] The terms used in the embodiments of the present application are merely for the purpose of describing particular embodiments, and are not intended to limit the present application. The singular forms "a", "an" and "the" used in the embodiments of the present application and the appended claims are intended to include plural forms, unless the context clearly indicates otherwise. "Plural" generally includes at least two, but does not exclude the case of including at least one.

[0050] It should be understood that the term "and / or" used herein is merely an association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this application generally represents an "or" relationship between the front and rear associated objects. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0051] It should be understood that the terms "include", "contain" or any other variation used herein are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0052] It should be noted that if the present application has any direction indication (such as up, down, left, right, front, back, etc.), the direction indication is only used to explain the relative position relationship, movement condition, etc. between the components in a certain posture (as shown in the drawings), and if the specific posture changes, the direction indication will also change accordingly.

[0053] Reference to an "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art, embodiments described herein can be combined with other embodiments.

[0054] The application provides a gate drive circuit, which comprises a plurality of gate drive units connected in series, specifically referring to Figure 1 , Figure 1 The application provides a structure schematic diagram of an embodiment of the gate drive unit. As shown in Figure 1 each of the gate drive units GOA at least comprises a first output unit 11, a second output unit 12 and a control unit 20.

[0055] Taking the Nth gate drive unit GOA(n) as an example, wherein N and n are natural numbers.

[0056] The first output unit 11 is used for outputting the pulse signal scan(n) of the current gate drive unit GOA(n), and the second output unit 12 is used for outputting the pulse signal scan(n+1) of the next gate drive unit GOA(n+1).

[0057] The control unit 20 is connected with the first output unit 11 and the second output unit 12, and is used for controlling the working of the first output unit 11 and / or the second output unit 12, so as to realize the switching of the first driving mode and the second driving mode.

[0058] Specifically, the control unit 20 comprises two input ends connected with the previous gate drive unit GOA(n-1) or the previous two gate drive units GOA(n-2) respectively, specifically, the control unit 20 comprises a first cascade end and a second cascade end, the first cascade end is connected with the previous gate drive unit GOA(n-1) or the first signal line STV1, the second cascade end is connected with the previous two gate drive units GOA(n-2) or the second signal line STV2, and the output end is connected with the control ends of the first output unit 11 and the second output unit 12, and is used for controlling whether the first output unit 11 and the second output unit 12 work or not.

[0059] It should be noted that the first cascade end of the control unit 20 in the first-stage gate drive unit GOA(1) is connected with the first signal line STV1, the second cascade end is connected with the second signal line STV2, the first cascade end of the control unit 20 in the second-stage and the Nth-stage gate drive unit GOA(n) is connected with the gate drive unit GOA(n-1) of the previous stage, the second cascade end of the control unit 20 in the second-stage gate drive unit GOA(2) can be left floating or connected with a high potential signal line VGH, and the second cascade end of the control unit 20 in the Nth-stage gate drive unit GOA(n) is connected with the gate drive unit GOA(n-2) of the previous two stages. Therefore, the connection relationship of "and / or" in the cascade end of the gate drive unit selects the connection relationship of the former (such as connection with the first signal line and connection with the second signal line) in the special case (i.e. no cascade object, such as in the first-stage gate drive unit), and selects the connection relationship of the latter (such as the gate drive unit of the previous stage / the gate drive unit of the previous two stages) in the non-special case (with a cascade object). The above applies to the subsequent cascade units (such as the first cascade unit, the second cascade unit, the first cascade control unit, the second cascade control unit and the third cascade control unit), which will not be described one by one.

[0060] The first driving mode is also referred to as a normal mode. For details, please refer to Figure 2 , Figure 2 The timing diagram of an embodiment of the first driving mode provided in the present application is shown in FIG. 2. The first signal line STV1 is used to transmit a first start signal, so that the gate drive unit is driven in the first driving mode. G1 is the scan signal scan(1) output to the first row of pixel units in the panel, G2 is the scan signal scan(1) output to the second row of pixel units in the panel, and so on. In the first driving mode, each stage of the gate drive unit GOA outputs different timing of the scan signal, so as to control the pixel units in the panel to open row by row, thereby realizing row-by-row scanning and row-by-row display.

[0061] The second driving mode is also referred to as a double frequency driving mode (DLG mode). For details, please refer to Figure 3 , Figure 3 The timing diagram of an embodiment of the second driving mode provided in the present application is shown in FIG. 3. The second signal line STV2 is used to transmit a second start signal, so that the gate drive unit is driven in the second driving mode. As shown in FIG. 3, Figure 3As shown, in the second driving mode, the gate driving unit controls the output of the same scanning signal for two adjacent rows, that is, controls the pixel units of each two adjacent rows to be turned on at the same time, and charges the same data into the pixel units of each two adjacent rows, so that the pixel units of each two adjacent rows display the same brightness. The second driving mode can reduce the display resolution to half and increase the refresh rate to twice the original. For example, in the first driving mode, the refresh rate of the display panel is 240Hz, and the refresh rate of the display panel in the second driving mode will increase to 480Hz, which is twice the original rate, but the total data transmission rate remains unchanged.

[0062] For further details, please refer to Figure 4 , Figure 4 This is a schematic diagram of the structure of an embodiment of the gate drive circuit provided by this application. Figure 4 As shown, the N-th stage gate driver unit GOA(n) is connected to the N-1-th stage (previous stage) gate driver unit GOA(n-1) or the first signal line STV1, and to the N-2-th stage (two stages above) gate driver unit GOA(n-2) or the second signal line STV2, and is used to output the N-th stage (current stage) pulse signal scan(n) and / or the N+1-th stage (next stage) pulse signal scan(n+1). The N+1-th stage gate driver unit GOA(n+1) is connected to the N-th stage gate driver unit GOA(n), and is connected to the second signal line STV2 or the N-1-th stage gate driver unit GOA(n-1), and is used to output the N+1-th stage pulse signal scan(n+1) and / or the N+2-th stage pulse signal scan(n+2). The N+2-th level gate driver unit GOA(n+2) is connected to the N+1-th level gate driver unit GOA(n+1) and to the N-th level gate driver unit GOA(n), and is used to output the N+2-th level pulse signal scan(n+2) and / or the N+3-th level pulse signal scan(n+3). The N+3-th level gate driver unit GOA(n+3) is connected to the N+2-th level gate driver unit GOA(n+2) and to the N+1-th level gate driver unit GOA(n+1), and is used to output the N+3-th level pulse signal scan(n+3) and / or the N+4-th level pulse signal scan(n+4). And so on, until all gate driver units GOA are cascaded with each other.

[0063] Among them, the N+1th level (next level) pulse signal scan(n+1) output by the N-level gate driving unit GOA(n) and the N+1th level (current level) pulse signal scan(n+1) output by the N+1-level gate driving unit GOA(n+1) are the same pulse signal, that is, the output end of the second output unit of the N-level gate driving unit GOA(n) is connected to the output end of the first output unit of the N+1-level gate driving unit GOA(n+1).

[0064] It should be noted that the pulse signal scan is also called a scanning signal, which is used for output to the display panel to control the data writing in the display panel.

[0065] Specifically, when N is 1, the two input ends of the first-stage gate drive unit GOA(1) are connected with the first signal line STV1 and the second signal line STV2 respectively, when N is 2, the two input ends of the second-stage gate drive unit GOA(2) are connected with the output end of the first-stage gate drive unit GOA(1) and a high potential signal line VGH (or suspended) respectively, when N is 3, the two input ends of the third-stage gate drive unit GOA(3) are connected with the output end of the second-stage gate drive unit GOA(2) and the output end of the first-stage gate drive unit GOA(1) respectively, when N is 4, the input ends of the fourth-stage gate drive unit GOA(4) are connected with the output end of the third-stage gate drive unit GOA(3) and the output end of the second-stage gate drive unit GOA(2) respectively, and so on.

[0066] Specifically, please refer to Figure 5 , Figure 5 The structure schematic diagram of the gate drive circuit provided in the present application is driven according to the first driving mode. In the first driving mode, the control unit 20 controls the first output unit 11 to work and the second output unit 12 to not work, so as to make each of the gate drive units GOA output the pulse signal scan(n) corresponding to the gate drive unit GOA(n) in turn.

[0067] As shown in Figure 5 , the first-stage gate drive unit GOA(1) is driven to output the first-stage (row) pulse signal scan(1), the second-stage gate drive unit GOA(2) is driven to output the second-stage (row) pulse signal scan(2), the third-stage gate drive unit GOA(3) is driven to output the third-stage (row) pulse signal scan(3), the fourth-stage gate drive unit GOA(4) is driven to output the fourth-stage (row) pulse signal scan(4), and so on, that is, each of the gate drive units GOA(n) outputs the pulse signals with different time sequences in turn. That is, the time sequences of the adjacent two-stage (row) pulse signals scan are different, and the duty cycles are the same. Specifically, please refer to the timing diagram in Figure 2 .

[0068] It should be noted that the Nth stage pulse signal scan(n) refers to the scanning signal output by the gate drive circuit to the Nth row of pixels in the display area of the panel. The first stage (row) pulse signal scan(1) is the scanning signal output to the first row of pixels, used to control the data writing of the first row of pixels; the second stage (row) pulse signal scan(2) is the scanning signal output to the second row of pixels; the third stage (row) pulse signal scan(3) is the scanning signal output to the third row of pixels; the fourth stage (row) pulse signal scan(4) is the scanning signal output to the fourth row of pixels; and so on, until the entire panel is scanned.

[0069] For details, please refer to Figure 6 , Figure 6 The structure diagram of the gate drive circuit provided by the present application driven in the second driving mode. In the second driving mode, the control unit 20 controls the first output unit 11 and / or the second output unit 12 to work to output the same adjacent two-stage pulse signals scan, which specifically includes outputting the current stage pulse signal scan(n) and the next stage pulse signal scan(n+1). Wherein, the same refers to the timing and duty cycle of the current stage pulse signal scan(n) and the next stage pulse signal scan(n+1) being the same, for details, please refer to the timing diagram in Figure 3 .

[0070] As shown in Figure 6 , the first stage gate drive unit GOA(1) outputs the same first stage pulse signal scan(1) and second stage pulse signal scan(2), the second stage gate drive unit GOA(2) does not output, the third stage gate drive unit GOA(3) outputs the same third stage pulse signal scan(3), the fourth stage gate drive unit GOA(4) does not output, and so on, so as to output the same adjacent two-stage pulse signals scan. In other words, the second output end of the first stage gate drive unit GOA(1) is connected with the first output end of the second stage gate drive unit GOA(2), and the second stage pulse signal scan(2) is output through the first stage gate drive unit GOA(1).

[0071] It should be noted that N is counted from 1, the Nth stage gate drive unit GOA(n) is also called the odd stage gate drive unit, the N+1th stage gate drive unit GOA(n+1) is also called the even stage gate drive unit, and so on.

[0072] For details, please refer to Figure 7 , Figure 7 The structure diagram of the first specific embodiment of the gate drive unit provided by the present application. As shown in Figure 7As shown, each gate drive unit GOA further comprises a first cascade control unit 101. Specifically, the control end of the first cascade control unit 101 is connected with the upper stage gate drive unit GOA(n-1) or the high potential signal line VGH, the input end is connected with the output end of the first output unit 11, for controlling the output of the first output unit 11 of the current stage gate drive unit GOA(n) according to the upper stage gate drive unit GOA(n-1) or the high potential signal line VGH, that is, controlling whether the first output unit 11 outputs the pulse signal scan(n) of the current stage.

[0073] It should be noted that the first cascade control unit 101 in the first stage gate drive unit GOA(1) is connected with the high potential signal line VGH, and the first cascade control unit 101 in the second stage and subsequent Nth stage gate drive unit GOA(n) is connected with the upper stage gate drive unit GOA(n-1).

[0074] Specifically, in the first driving mode, the first cascade control unit 101 in each stage gate drive unit GOA is kept on. The gate drive unit GOA controls the output of the pulse signal of the current stage in turn, which can be referred to in Figure 5 .

[0075] In the second driving mode, the first cascade control unit 101 in the odd stage gate drive unit GOA is kept on, and the first cascade control unit 101 in the even stage gate drive unit GOA is in the off state when the odd stage gate drive unit GOA outputs the low potential, so that the even stage gate drive unit GOA has no output. It can be referred to in Figure 6 .

[0076] Specifically, the first stage gate drive unit GOA(1) controls the first output unit 11 and the second output unit 12 to work at the same time, and the first cascade control unit 101 in the first stage gate drive unit GOA(1) is connected with the high potential signal line VGH and kept on under the action of the high potential signal line VGH, therefore, the first stage gate drive unit GOA(1) simultaneously outputs the same first stage pulse signal scan(1) and the second stage pulse signal scan(2).

[0077] The second stage gate drive unit GOA(2) controls the first output unit 11 to work and keep outputting high potential according to the cascade signal received by the control unit 20, and the second output unit 12 does not work (no output), at this time, the first cascade control unit 101 in the second stage gate drive unit GOA(2) is controlled to be closed by the first stage gate drive unit GOA(1) when outputting the low potential, so as to control the first output unit 11 of the second stage gate drive unit GOA(2) to have no output, therefore, the first output unit 11 and the second output unit 12 of the second stage gate drive unit GOA(2) have no output.

[0078] The third-stage gate driving unit GOA(3) controls the first output unit 11 and the second output unit 12 to work and output low potential according to the cascade signal received by the control unit 20, at this time, the second-stage gate driving unit GOA(2) controls the first cascade control unit 101 in the third-stage gate driving unit GOA(3) to keep on, thus the third-stage gate driving unit GOA(3) controls the first output unit 11 and the second output unit 12 to have output, and outputs the same third-stage pulse signal scan(3) and fourth-stage pulse signal scan(4).

[0079] The first cascade control unit 101 of the fourth-stage gate driving unit GOA(4) is off, thus the first output unit 11 and the second output unit 12 of the fourth-stage gate driving unit GOA(4) have no output; and the like.

[0080] It should be noted that the first-stage gate driving unit GOA(1), the third-stage gate driving unit GOA(3) and the like are also called odd-stage gate driving units GOA, and the second-stage gate driving unit GOA(2), the fourth-stage gate driving unit GOA(4) and the like are also called even-stage gate driving units GOA. In the embodiment, when the odd-stage gate driving unit GOA outputs the current-stage pulse signal and the next-stage pulse signal, the even-stage gate driving unit GOA does not work; when the odd-stage gate driving unit GOA outputs high potential, the high potential of the next-stage pulse signal is controlled to be output by the even-stage gate driving unit GOA. In other words, the next-stage pulse signal is controlled by the odd-stage gate driving unit and the even-stage gate driving unit at the same time, specifically, the low potential of the next-stage pulse signal is controlled to be output by the odd-stage gate driving unit, and the high potential of the next-stage pulse signal is controlled to be output by the even-stage gate driving unit, so that the next-stage pulse signal keeps the same time sequence and duty cycle as the current-stage pulse signal.

[0081] That is, when the odd-stage gate driving unit GOA outputs the current-stage pulse signal and the next-stage pulse signal at the same time, the first output unit of the even-stage gate driving unit GOA is controlled to have no output, so as to avoid the conflict between the low potential output by the odd-stage gate driving unit GOA and the high potential output by the even-stage gate driving unit GOA when the odd-stage gate driving unit GOA outputs low potential, and to avoid affecting the output of the next-stage pulse signal. It should be noted that the output of the pulse signal refers to the output of low potential, that is, the potential for controlling the on of the in-plane transistor, when the pulse signal keeps high potential, the in-plane transistor is in the off state; that is, the pulse signal in the embodiment is a low potential pulse with normally high potential. In other embodiments, the high potential can also be the on potential of the in-plane transistor, and the low potential is the off potential of the in-plane transistor, that is, the in-plane transistor is an N-type transistor with high potential on, at this time, the pulse signal is a high potential pulse with normally low potential, which is not limited here.

[0082] It should be noted that, in other embodiments, the first cascade control units in all even-numbered gate driving units may also be connected by a switching signal line, which is not limited here.

[0083] See further Figure 8 , Figure 8 This is a schematic diagram of the structure of the second specific embodiment of the gate drive unit provided in this application. Figure 8 As shown, the control unit 20 includes a first register 21 and a second register 22. Specifically, the first register 21 is connected to the first signal line STV1 or the output end of the previous gate driving unit GOA(n-1), and is used to receive the first start signal output by the first signal line STV1 or the pulse signal scan(n-1) output by the previous gate driving unit GOA(n-1), and control the output end Q(n) of the first register 21 to output the first control signal according to the first start signal or the previous pulse signal scan(n-1).

[0084] The second register 22 is connected to the second signal line STV2 or the output end of the upper two-stage gate driving unit GOA(n-2), and is used to receive the second start signal output by the second signal line STV2 or the pulse signal scan(n-2) output by the upper two-stage gate driving unit GOA(n-2), and control the output end P(n) of the second register 22 to output the second control signal according to the second start signal or the upper two-stage pulse signal scan(n-2).

[0085] The first control signal and the second control signal both include low-potential pulses and high-potential pulses of pulse signals. The low-potential pulses are low-potential (signal / voltage), and the high-potential pulses are high-potential (signal / voltage).

[0086] In this embodiment, in the first drive mode, the first signal line STV1 outputs a low-potential pulse with a normally high potential, while the second signal line STV2 either continues to transmit a high-potential pulse or does not output. In the second drive mode, the second signal line STV2 outputs a low-potential pulse with a normally high potential, while the first signal line STV1 continues to transmit a high-potential pulse or does not output. In this embodiment, the drive mode of the gate drive circuit is switched via the first signal line STV1 and the second signal line STV2. Specifically, the switching between the first drive mode and the second drive mode of the gate drive circuit is achieved by controlling the output signals of the first signal line STV1 and the second signal line STV2.

[0087] Specifically, the output end Q(n) of the first register 21 is also connected with the control end of the first output unit 11, and the output end P(n) of the second register 22 is connected with the control end of the second output unit 12, for controlling the first output unit 11 and / or the second output unit 12 to work according to the first control signal and the second control signal, and further controlling the output of the first output unit 11 and / or the second output unit 12. It should be noted that Q(n) refers to the output end Q(n) of the first register 21 in the Nth gate drive unit GOA(n), and P(n) refers to the output end P(n) of the second register 22 in the Nth gate drive unit GOA(n). N / n represents the Nth gate drive unit.

[0088] Further, the control end of the first output unit 11 is also connected with the output end P(n) of the second register 22, and the first register 21 and the second register 22 control the output of the first output unit 11 simultaneously; the input end of the second output unit 12 is also connected with the output end of the first output unit 11, so that the second output unit 12 outputs the same pulse signal as the first output unit 11 simultaneously in the second driving mode.

[0089] Further please refer to Figure 9 , Figure 9 The structural schematic diagram of the third embodiment of the gate drive circuit provided in the present application is shown in FIG. 3. As shown in FIG. 3, the control unit 20 further comprises a first control unit 23 and a second control unit 24. Figure 9

[0090] Specifically, the control end of the first control unit 23 is connected with the output end Q(n) of the first register 21, for outputting high potential or low potential according to the first control signal output by the first register 21, and the output end of the first control unit 23 is connected with the control end of the first output unit 11, for controlling the first output unit 11 whether to output the pulse signal scan(n) of the present stage according to the first control signal output by the first register 21. The control end of the second control unit 24 is connected with the output end P(n) of the second register 22, for outputting high potential or low potential according to the second control signal output by the second register 22, and the output end of the second control unit 24 is connected with the control end of the second output unit 12, for controlling the second output unit 12 whether to output the pulse signal scan(n+1) of the next stage according to the second control signal output by the second register 22.

[0091] ​The first control unit 23 and the second control unit 24 are used to output a high potential or a low potential to control the output of the first output unit 11 and the second output unit 12 .

[0092] Furthermore, the output end of the second control unit 24 is also connected to the control end of the first output unit 11, and the output of the first output unit 11 is simultaneously controlled by the first control unit 23 and the second control unit 24. Furthermore, the output end of the first output unit 11 is also connected to the input end of the second output unit 12, and the second control unit 24 controls the second output unit 12 to output the same pulse signal as the first output unit 11.

[0093] See further Figure 10 , Figure 10 This is a schematic diagram of the structure of the fourth specific embodiment of the gate drive circuit provided by this application. Figure 10 As shown, the first control unit 23 includes a first sub-control unit 231 and a second sub-control unit 232 , and the second control unit 24 includes a third sub-control unit 241 and a fourth sub-control unit 242 .

[0094] The first sub-control unit 231 is connected to the first register 21 and a high-potential signal line VGH. Specifically, the control end of the first sub-control unit 231 is connected to the first register 21, the input end is connected to the high-potential signal line VGH, and the output end is connected to the control end of the first output unit 11. It is used to control the output of the high-potential control signal according to the first control signal output by the first register 21, thereby controlling the output of the first output unit 11.

[0095] The second sub-control unit 232 is connected to the first register 21 and a low-potential signal line VGL. Specifically, the control end of the first sub-control unit 231 is connected to the output end Q(n) of the first register 21, the input end is connected to the low-potential signal line VGL, and the output end is connected to the control end of the first output unit 11, and is used to control the output of the low-potential control signal according to the first control signal output by the first register 21, thereby controlling the output of the first output unit 11.

[0096] The third sub-control unit 241 is connected to the second register 22, the high-potential signal line VGH and the second output unit 12. Specifically, the control end of the third sub-control unit 241 is connected to the output end P(n) of the second register 22, the input end is connected to the high-potential signal line VGH, and the output end is connected to the control end of the second output unit 12. It is used to control the output of the high-potential control signal according to the second control signal output by the second register 22, and then control whether the second output unit 12 is working, that is, to control its output.

[0097] The fourth sub-control unit 242 is connected to the second register 22, the low-potential signal line VGL and the second output unit 12. Specifically, the control end of the fourth sub-control unit 242 is connected to the output end P(n) of the second register 22, the input end is connected to the low-potential signal line VGL, and the output end is connected to the control end of the second output unit 12. It is used to control the output of the low-potential control signal according to the second control signal output by the second register 22, and then control whether the second output unit 12 is working, that is, to control its output.

[0098] Furthermore, the output ends of the third sub-control unit 241 and the fourth sub-control unit 242 are also connected to the control end of the first output unit 11, for controlling the first output unit 11 to be in a working state in both the first driving mode and the second driving mode, and controlling the first output unit 11 to output a pulse signal including a high potential and a low potential.

[0099] It should be noted that the high potential signal line VGH and the low potential signal line VGL can be interchanged, which is not limited here. The high potential signal line VGH is used to transmit a high potential voltage (high potential signal), and the low potential signal line VGL is used to transmit a low potential voltage (high potential signal).

[0100] The first sub-control unit 231 and the second sub-control unit 232 include a group of transistors with opposite driving characteristics. That is, when the first sub-control unit 231 is operating / conducting, the second sub-control unit 232 is inoperative; when the second sub-control unit 232 is operating, the first sub-control unit 231 is inoperative. The third sub-control unit 241 and the fourth sub-control unit 242 also include a group of transistors with opposite driving characteristics.

[0101] See further Figure 11 , Figure 11 This is a schematic structural diagram of the fifth specific embodiment of the gate drive unit provided in this application. Figure 11 As shown, in a specific embodiment, the first output unit 11 includes a first sub-output unit 111, a second sub-output unit 112, a third sub-output unit 113, and a fourth sub-output unit 114. Each sub-output unit includes a switching transistor, which is not limited here.

[0102] Among them, the first sub-output unit 111 is connected to the first control unit 23 and the high-potential signal line VGH. Specifically, the input end of the first sub-output unit 111 is connected to the high-potential signal line VGH, the control end is connected to the output end of the first control unit 23, and the output end is connected to the output end of the first output unit 11 through the second sub-output unit 112, and is used to control the output of the first output unit 11 according to the control signal (high potential or low potential) output by the first control unit 23.

[0103] The second sub-output unit 112 is connected with the first sub-output unit 111 and the second control unit 24. Specifically, the input end of the second sub-output unit 112 is connected with the first sub-output unit 111, the control end is connected with the output end of the second control unit 24, and the output end is connected with the output end of the first output unit 11, for controlling the output of the first output unit 11 according to the control signal output by the second control unit 24. Wherein, the first sub-output unit 111 and the second sub-output unit 112 are arranged side by side, for controlling whether the first output unit 11 outputs the high potential pulse.

[0104] The third sub-output unit 113 is connected with the first control unit 23 and the low potential signal line VGL. Specifically, the input end of the third sub-output unit 113 is connected with the low potential signal line VGL, the control end is connected with the output end of the first control unit 23, and the output end is connected with the output end of the first output unit 11, for controlling the output of the first output unit 11 according to the control signal output by the first control unit 23.

[0105] The fourth sub-output unit 114 is connected with the second control unit 24 and the low potential signal line VGL. Specifically, the input end of the fourth sub-output unit 114 is connected with the low potential signal line VGL, the control end is connected with the output end of the second control unit 24, and the output end is connected with the output end of the first output unit 11, for controlling the output of the first output unit 11 according to the control signal output by the second control unit 24.

[0106] Wherein, the first sub-output unit 111 and the third sub-output unit 113 are used for controlling the first output unit 11 to output the pulse signal including the high potential and the low potential in the first driving mode; and the second sub-output unit 112 and the fourth sub-output unit 114 are used for controlling the first output unit 11 to output the pulse signal including the high potential and the low potential in the second driving mode.

[0107] In the embodiment, the first sub-output unit 111 and the third sub-output unit 113 include a group of transistors with opposite driving characteristics, so that when the first control unit 23 controls the first sub-output unit 111 to be turned on / working, the third sub-output unit 113 is controlled to be turned off / not working; and when the third sub-output unit 113 is working, the first sub-output unit 111 is not working. Similarly, the second sub-output unit 112 and the fourth sub-output unit 114 also include a group of transistors with opposite driving characteristics.

[0108] In other embodiments, the first output unit 11 can also adopt other connection structures, which are not limited here.

[0109] Further, the control end of the second output unit 12 is also connected with the output end of the second register 22, and the input end is connected with the output end of the first output unit 11, for controlling whether to output the next stage pulse signal scan(n+1) according to the second control signal transmitted by the second register 22, so as to realize the switching of the first driving mode and the second driving mode. Specifically, the second output unit 12 is controlled to work in the second driving mode, and not to work in the first driving mode.

[0110] Specifically in the second driving mode, the second output unit 12 in the odd stage gate drive unit GOA is controlled to work, and the second output unit 12 in the even stage gate drive unit GOA is not controlled to work. In a specific embodiment, when the odd stage gate drive unit GOA drives the second output unit 12 to work, the even stage gate drive unit GOA controls the first output unit 11 to have no output through the first cascade control unit 101; when the odd stage gate drive unit GOA drives the second output unit 12 to have no output, the even stage gate drive unit GOA controls the first output unit 11 to have output through the first cascade control unit 101. Wherein, the conduction / work of the first cascade control unit 101 is related to the second control signal of the odd stage gate drive unit GOA.

[0111] In the embodiment, the first output unit 11 keeps outputting the current stage pulse signal scan(n) in the first driving mode or the second driving mode.

[0112] Further please refer to Figure 12 , Figure 12 The structure schematic diagram of the sixth specific embodiment of the gate drive unit provided in the present application is shown in the figure. Figure 12 As shown in the figure, each gate drive unit GOA further comprises a second cascade control unit 102 and a third cascade control unit 103.

[0113] Taking the Nth gate drive unit GOA(n) as an example for description.

[0114] Specifically, the input end of the second cascade control unit 102 is connected with the first output unit 11, and the output end is connected with the input end of the next stage gate drive unit GOA(n+1), for driving the next stage gate drive unit GOA(n+1) to work according to the current stage pulse signal scan(n).

[0115] The input end of the third cascade control unit 103 is connected with the first output unit 11, and the output end is connected with the input end of the next two stage gate drive unit GOA(n+2), for driving the next two stage gate drive unit GOA(n+2) to work according to the current stage pulse signal scan(n).

[0116] Furthermore, the control end of the second cascade control unit 102 is connected to the output end of the first register 21, and is used to control the cascade connection of the current-stage gate driving unit GOA(n) and the next-stage gate driving unit GOA(n+1) in the first driving mode. The control end of the third cascade control unit 103 is connected to the output end of the second register 22, and is used to control the cascade connection of the current-stage gate driving unit GOA(n) and the next two-stage gate driving units GOA(n+2) in the second driving mode.

[0117] Specifically, the output end of the second cascade control unit 102 is connected to the first register 21 in the next-stage gate driving unit GOA(n+1), that is, connected to the first cascade end of the next-stage gate driving unit GOA(n+1). The output end of the third cascade control unit 103 is connected to the second register 22 of the next two-stage gate driving unit GOA(n+2), that is, connected to the second cascade end of the next two-stage gate driving unit GOA(n+2).

[0118] In a preferred embodiment, the input terminals of the second cascade control unit 102 and the third cascade control unit 103 are connected to the output terminal of the first cascade control unit 101, that is, the second cascade control unit 102 and the third cascade control unit 103 are arranged after the first cascade control unit 101, and the second cascade control unit 102 and the third cascade control unit 103 are connected to the output terminal of the first output unit 11 through the first cascade control unit 101. In another preferred embodiment, the first cascade control unit 101 may be arranged after the input terminals of the second cascade control unit 102 and the third cascade control unit 103, that is, the input terminals of the second cascade control unit 102 and the third cascade control unit 103 are connected to the output terminal of the first output unit 11 and the input terminal of the first cascade control unit 101, respectively.

[0119] Please refer to the following for details Figure 13 , Figure 13 This is a schematic structural diagram of the seventh specific embodiment of the gate drive unit provided in this application. Figure 13 As shown, the second cascade control unit 102 includes a first switch unit 1021 and a first pull-up unit 1022 . The third cascade control unit 103 includes a second switch unit 1031 and a second pull-up unit 1032 .

[0120] Specifically, the first switch unit 1021 includes a switch transistor, the control end of the first switch unit 1021 is connected with the output end Q of the first register 21, and the input end is connected with the first output unit 11, for controlling the first output unit 11 of the current stage gate drive unit GOA(n) and the next stage gate drive unit GOA(n+1) to be cascaded according to the first control signal Q output by the first register 21. The first pull-up unit 1022 includes a high potential signal line VGH and a first resistor R1, the first pull-up unit 1022 is connected with the output end of the first switch unit 1021, for keeping the cascaded signal input to the next stage gate drive unit GOA(n+1) as a high potential signal when the first switch unit 1021 is not working.

[0121] The control end of the second switch unit 1031 is connected with the output end P of the second register 22, and the input end is connected with the first output unit 11, for controlling the first output unit 11 of the current stage gate drive unit GOA(n) and the next two stage gate drive unit GOA(n+2) to be cascaded according to the second control signal output by the second register 22.

[0122] The control end of the second pull-up unit 1032 includes a high potential signal line VGH and a second resistor R2, the second pull-up unit 1032 is connected with the output end of the second switch unit 1031, for keeping the cascaded signal input to the next two stage gate drive unit GOA(n+2) as a high potential signal when the second switch unit 1031 is not working.

[0123] Please further refer to Figure 14 , Figure 14 The structure schematic diagram of the eighth embodiment of the gate drive unit provided in the present application is shown in the figure. Figure 14 As shown in the figure, the first register 21 includes a first cascade unit 211 and a first storage unit C1, and the second register 22 includes a second cascade unit 221 and a second storage unit C2.

[0124] The input end of the first cascade unit 211 is connected with the first signal line STV1 or the output end of the previous stage gate drive unit GOA(n-1), and the control end is connected with the first control signal line XCK, for receiving the cascaded signal transmitted by the previous stage gate drive unit GOA(n-1). Specifically, whether the first cascade unit 211 receives the cascaded signal transmitted by the previous stage gate drive unit GOA(n-1) is controlled by the first control signal line XCK.

[0125] The first storage unit C1 is connected with the output end of the first cascade unit 211, for storing the cascaded signal transmitted by the previous stage gate drive unit GOA(n-1). Specifically, the first plate of the first storage unit C1 is connected with the output end of the first cascade unit 211, and the second plate is connected with a low potential signal line VGL or a ground wire.

[0126] In the embodiment, the output end Q of the first register 21 is the output end of the first cascade unit 211 and the first plate of the first storage unit C1.

[0127] The input end of the second cascade unit 221 is connected with the second signal line STV2 or the output end of the upper two-stage gate driving unit GOA(n-2), and the control end is connected with the first control signal line XCK, for receiving the cascade signal transmitted by the upper two-stage gate driving unit GOA(n-2).

[0128] The second storage unit C2 is connected with the output end of the second cascade unit 221, for storing the cascade signal transmitted by the upper two-stage gate driving unit GOA(n-2). Specifically, the first plate of the second storage unit C2 is connected with the output end of the second cascade unit 221, and the second plate is connected with a low potential signal line VGL.

[0129] In the embodiment, the output end P of the second register 22 is the output end of the second cascade unit 221 and the first plate of the second storage unit C2.

[0130] It should be noted that the cascade signal is a pulse signal scan, specifically including the high potential and the low potential of the pulse signal scan.

[0131] Further referring to Figure 15 , Figure 15 The structure schematic diagram of the ninth embodiment of the gate driving circuit provided in the application is shown in the figure. Figure 15 As shown in the figure, the first register 21 further includes a first delay control unit 212 and a third storage unit C3, and the second register 22 further includes a second delay control unit 222 and a fourth storage unit C4.

[0132] The input end of the first delay control unit 212 is connected with the output end of the first cascade unit 211 and the first storage unit C1, and the control end is connected with the second control signal line CK, for delaying the control / driving effect of the cascade signal transmitted by the upper-stage gate driving unit GOA(n-1) on the first output unit 11 or the first control unit 23.

[0133] The third storage unit C3 is connected with the output end of the first delay control unit 212, for storing the cascade signal transmitted by the upper-stage gate driving unit GOA(n-1).

[0134] The input end of the second delay control unit 222 is connected with the output end of the second cascade unit 221 and the second storage unit C2, the control end is connected with the second control signal line CK, and is used for delaying the control / driving effect of the cascade signal transmitted by the upper two-stage gate driving unit GOA(n-2) on the second output unit 12 and / or the first output unit 11, or delaying the control effect on the second control unit 24.

[0135] The fourth storage unit C4 is connected with the output end of the second delay control unit 222, and is used for storing the cascade signal transmitted by the upper two-stage gate driving unit GOA(n-2).

[0136] In the embodiment, the second plate of the third storage unit C3 and the fourth storage unit C4 is also connected with a fixed signal line, and specifically is connected with a low potential signal line VGL.

[0137] In the embodiment, the output end Q of the first register 21 is the output end of the first delay control unit 212 and the first plate of the third storage unit C3. The output end P of the second register 22 is the output end of the second delay control unit 222 and the first plate of the fourth storage unit C4.

[0138] For details, please refer to Figure 16 , Figure 16 The circuit structure schematic diagram of a specific embodiment of the gate driving unit provided in the application is shown in the following figure. Figure 16 As shown in the figure.

[0139] The first register 21 includes a first transistor T1, a first capacitor C1, a second transistor T2 and a third capacitor C3.

[0140] The second register 22 includes a third transistor T3, a second capacitor C2, a fourth transistor T4 and a fourth capacitor C4.

[0141] The first control unit 23 includes a fifth transistor T5 and a sixth transistor T6.

[0142] The second control unit 24 includes a seventh transistor T7 and an eighth transistor T8.

[0143] The first output unit 11 includes a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12.

[0144] The second output unit 12 includes a thirteenth transistor T13.

[0145] The first cascade control unit 101 includes a fourteenth transistor T14.

[0146] The second cascade control unit 102 includes a fifteenth transistor T15.

[0147] The third cascade control unit 103 includes a sixteenth transistor T16.

[0148] Further refer to Figures 17-21 , Figures 17-21 The driving process diagram of the gate drive unit provided by the present application in the first driving mode. Specifically, Figure 17 The first driving circuit diagram of the gate drive unit provided by the present application in the first driving mode. Figure 18 The second driving circuit diagram of the gate drive unit provided by the present application in the first driving mode. Figure 19 The third driving circuit diagram of the gate drive unit provided by the present application in the first driving mode. Figure 20 The fourth driving circuit diagram of the gate drive unit provided by the present application in the first driving mode. Figure 21 The fifth driving circuit diagram of the gate drive unit provided by the present application in the first driving mode.

[0149] The first driving mode includes a sampling stage, an output stage 1, an output stage 2, and a holding stage 1 and a holding stage 2.

[0150] In the sampling stage, the first transistor T1 and the third transistor T3 are turned on, the first register 21 writes the cascade signal, and the first capacitor C1 stores the low potential pulse output by the previous stage gate drive unit GOA(n-1). The third capacitor C3 in the first register 21 maintains the high potential voltage of the previous stage, that is, the first control signal output by the output end Q(n) of the first register 21 is maintained as high potential. The fourth capacitor C4 in the second register 22 maintains the high potential voltage of the previous stage, that is, the second control signal output by the output end P(n) of the second register 22 is also maintained as high potential. The fifth transistor T5 in the first control unit 23 is turned on, the first control unit 23 outputs high potential, and further controls the ninth transistor T9 in the first output unit 11 to be turned on. The seventh transistor T7 in the second control unit 24 is turned on, the second control unit 24 outputs high potential, and further controls the tenth transistor T10 in the first output unit 11 to be turned on. The output end P(n-1) of the second register 22 in the previous stage gate drive unit GOA(n-1) maintains output high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to be turned on. Therefore, the stage pulse signal scan(n) output by the current stage gate drive unit GOA(n) is high potential pulse. The output end Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned off, thereby making the first cascade end output to the next stage gate drive unit GOA(n+1) as high potential signal. The output end P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned off, thereby making the second cascade end output to the next two stage gate drive unit GOA(n+2) as high potential signal. The output end P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off, and therefore, the next stage pulse signal scan(n+1) is not output by the current stage gate drive unit GOA(n). For details, please refer to Figure 17 .

[0151] In the output stage 1, the first transistor T1 and the third transistor T3 are turned off, the second transistor T2 and the fourth transistor T4 are turned on, the first capacitor C1 transmits the low potential voltage stored in the last time sequence to the third capacitor C3 through the second transistor T2 for storage, and the fourth capacitor C4 stores the high potential. Therefore, the first control signal output by the output end Q(n) of the first register 21 is low potential. The second control signal output by the output end P(n) of the second register 22 remains high potential. The sixth transistor T6 in the first control unit 23 is turned on, the first control unit 23 outputs the low potential signal, and the eleventh transistor T11 in the first output unit 11 is turned on. The output end of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, the second control unit 24 outputs the high potential, and the tenth transistor T10 in the first output unit 11 is turned on. The output end P(n-1) of the second register 22 in the last stage gate drive unit GOA(n-1) keeps outputting the high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to be kept turned on. Therefore, through the eleventh transistor T11 and the fourteenth transistor T14, the stage pulse signal scan(n) output by the current stage gate drive unit GOA(n) is the low potential pulse. The output end Q(n) of the first register 21 controls the fifteenth transistor T15 in the second cascade control unit 102 to be turned on, so that the first output unit 11 of the current stage gate drive unit GOA(n) is cascaded with the next stage gate drive unit GOA(n+1), thereby making the first cascade end output to the next stage gate drive unit GOA(n+1) be the low potential signal. The output end P(n) of the second register 22 controls the sixteenth transistor T16 in the third cascade control unit 103 to be turned off, thereby making the second cascade end output to the next two stage gate drive unit GOA(n+2) be the high potential signal. The output end P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off, so that the current stage gate drive unit GOA(n) does not output the next stage pulse signal scan(n+1). For details, please refer to the above description of the output stage 1. Figure 18 .

[0152] In the output stage 2, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, and the first capacitor C1 and the second capacitor C2 store high potentials. The third capacitor C3 keeps the low potential stored in the last stage, and the fourth capacitor C4 keeps the high potential. Therefore, the first control signal outputted by the output terminal Q(n) of the first register 21 keeps the low potential. The second control signal outputted by the output terminal P(n) of the second register 22 keeps the high potential. The sixth transistor T6 in the first control unit 23 is turned on, the first control unit 23 outputs the low potential signal, and the eleventh transistor T11 in the first output unit 11 is turned on. The output terminal of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, the second control unit 24 outputs the high potential, and the tenth transistor T10 in the first output unit 11 is turned on. The output terminal P(n-1) of the second register 22 in the last stage gate drive unit GOA(n-1) keeps outputting the high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to keep being turned on. Therefore, the pulse signal scan(n) outputted by the current stage gate drive unit GOA(n) is the low potential pulse through the eleventh transistor T11 and the fourteenth transistor T14. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 in the second cascade control unit 102 to be turned on, so that the first output unit 11 of the current stage gate drive unit GOA(n) is cascaded with the next stage gate drive unit GOA(n+1), thereby making the first cascade terminal outputting to the next stage gate drive unit GOA(n+1) be the low potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 in the third cascade control unit 103 to be turned off, thereby making the second cascade terminal outputting to the next two stage gate drive unit GOA(n+2) be the high potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off, so that the current stage gate drive unit GOA(n) does not output the next stage pulse signal scan(n+1). For details, please refer to the following figure. Figure 19 .

[0153] In the holding stage 1, the first transistor T1 and the third transistor T3 are turned off, and the second transistor T2 and the fourth transistor T4 are turned on. The high potential stored on the first capacitor C1 is transmitted to the third capacitor C3 through the second transistor T2 and stored. The fourth capacitor C4 keeps storing the high potential. Therefore, the first control signal outputted by the output terminal Q(n) of the first register 21 is a high potential. The first control signal outputted by the output terminal Q(n) of the first register 21 is a high potential. The fifth transistor T5 in the first control unit 23 is turned on, the first control unit 23 outputs a high potential signal, and then controls the ninth transistor T9 in the first output unit 11 to be turned on. The output terminal P(n) of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, the second control unit 24 outputs a high potential, and then controls the tenth transistor T10 in the first output unit 11 to be turned on. The output terminal P(n-1) of the second register 22 in the previous stage gate drive unit GOA(n-1) keeps outputting a high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to be turned on. Therefore, the stage pulse signal scan(n) outputted by the current stage gate drive unit GOA(n) is a high potential pulse through the ninth transistor T9 and the tenth transistor T10. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 in the second cascade control unit 102 to be turned off, thereby making the first cascade end outputted to the next stage gate drive unit GOA(n+1) a high potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 in the third cascade control unit 103 to be turned off, thereby making the second cascade end outputted to the next two stage gate drive unit GOA(n+2) a high potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off, therefore, the current stage gate drive unit GOA(n) does not output the next stage pulse signal scan(n+1). For details, please refer to the following figure. Figure 20 .

[0154] In the holding stage 2, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, the first capacitor C1 and the second capacitor C2 store high potential. The third capacitor C3 and the fourth capacitor C4 keep storing high potential. Therefore, the first control signal outputted by the output terminal Q(n) of the first register 21 is high potential. The second control signal outputted by the output terminal P(n) of the second register 22 is high potential. The fifth transistor T5 in the first control unit 23 is turned on, the first control unit 23 outputs high potential signal, and then controls the ninth transistor T9 in the first output unit 11 to be turned on. The output terminal of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, the second control unit 24 outputs high potential, and then controls the tenth transistor T10 in the first output unit 11 to be turned on. The output terminal P(n-1) of the second register 22 in the previous stage gate drive unit GOA(n-1) keeps outputting high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to keep being turned on. Therefore, through the ninth transistor T9 and the tenth transistor T10, the stage pulse signal scan(n) outputted by the current stage gate drive unit GOA(n) is high potential pulse. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned off, thereby making the first cascade terminal outputting to the next stage gate drive unit GOA(n+1) be high potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned off, thereby making the second cascade terminal outputting to the next two stage gate drive unit GOA(n+2) be high potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off, therefore, the current stage gate drive unit GOA(n) does not output the next stage pulse signal scan(n+1). For details, please refer to the following table 1. Figure 21 .

[0155] In the holding stage 1 and the holding stage 2, the third capacitor C3 is covered by the high potential of the first capacitor C1, the first register 21 will keep outputting high potential, therefore, the current stage GOA(n) keeps outputting the current stage pulse signal scan(n) as high potential. It is to be noted that, in the first driving mode in the embodiment, the input terminal (i.e. the second cascade terminal) of the second register 22 is connected with the high potential signal line VGH, in other embodiments, the input terminal (i.e. the second cascade terminal) of the second register 22 can be set as floating, which is not limited here.

[0156] Each stage gate drive unit GOA (including odd stage gate drive unit and even stage gate drive unit) is in accordance with the above Figures 17 to 21Driven in sequence. It should be noted that the gate of the fourteenth transistor T14 in the first-stage gate driving unit GOA (1) is connected to a high-potential signal line VGH. In other embodiments, a zero-stage gate driving unit GOA (0) may also be provided, and the input end of the first-stage gate driving unit GOA (1) is cascaded with GOA (0), wherein the output end of the zero-stage gate driving unit GOA (0) is left floating, that is, no output is provided.

[0157] For the second drive mode, please refer to Figures 22-26 , Figures 22-26 This is a driving process diagram of the odd-level gate driving unit provided by this application in the second driving mode. Specifically, Figure 22 This is a first driving circuit diagram of the odd-numbered gate driving unit provided by this application in the second driving mode. Figure 23 This is a second driving circuit diagram of the odd-numbered gate driving unit provided by this application in the second driving mode. Figure 24 This is a third driving circuit diagram of the odd-numbered gate driving unit provided in this application in the second driving mode. Figure 25 This is a fourth driving circuit diagram of the odd-numbered gate driving unit provided in this application in the second driving mode. Figure 26 This is a fifth driving circuit diagram of the odd-numbered gate driving unit provided in this application in the second driving mode.

[0158] The second driving mode is divided into odd-numbered gate driving units GOA and even-numbered gate driving units GOA.

[0159] The description is made by taking the current-stage (Nth-stage) gate driving unit GOA(n) as an odd-numbered-stage gate driving unit.

[0160] The odd-numbered gate drive unit GOA includes a sampling phase, an output phase 1, an output phase 2, a holding phase 1, and a holding phase 2.

[0161] In the sampling stage, the first transistor T1 and the third transistor T3 are turned on, the second register 22 writes the cascade signal, and the first capacitor C1 stores the low potential pulse output by the previous stage (odd stage) gate drive unit GOA(n-2). The third capacitor C3 in the first register 21 maintains the high potential voltage of the previous timing, that is, the first control signal output by the output end Q(n) of the first register 21 is maintained as high potential. The fourth capacitor C4 in the second register 22 maintains the high potential voltage of the previous timing, that is, the second control signal output by the output end P(n) of the second register 22 is also maintained as high potential. The fifth transistor T5 in the first control unit 23 is turned on, the first control unit 23 outputs high potential, and then controls the ninth transistor T9 in the first output unit 11 to be turned on. The seventh transistor T7 in the second control unit 24 is turned on, the second control unit 24 outputs high potential, and then controls the tenth transistor T10 in the first output unit 11 to be turned on. In the current stage (odd stage) gate drive unit GOA(n), the output end P(n-1) of the second register 22 in the previous stage (even stage) gate drive unit GOA(n-1) maintains output high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to be kept on. Therefore, the pulse signal scan(n) output by the current stage gate drive unit GOA(n) is a high potential pulse. The output end Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned off, so that the first cascade end output to the next stage gate drive unit GOA(n+1) is a high potential signal. The output end P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned off, so that the second cascade end output to the next two stages gate drive unit GOA(n+2) is a high potential signal. The output end P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off, so that the next stage pulse signal scan(n+1) is not output by the current stage gate drive unit GOA(n). For details, please refer to Figure 22 .

[0162] It should be noted that when the current stage (odd stage) gate drive unit GOA(n) does not output the next stage pulse signal scan(n+1), the next stage (even stage) gate drive unit GOA(n+1) outputs the next stage pulse signal scan(n+1) as high potential. As shown in Figure 22 , the second control signal output by the output end P(n) of the second register 22 in the current stage (odd stage) gate drive unit GOA(n) is high potential, which can control the fourteenth transistor T14 in the next stage (even stage) gate drive unit GOA(n+1) to be turned on, so that the pulse signal scan(n+1) output by the next stage (even stage) gate drive unit GOA(n+1) in this timing stage is high potential.

[0163] In the output stage 1, the first transistor T1 and the third transistor T3 are turned off, the second transistor T2 and the fourth transistor T4 are turned on, the second capacitor C2 transmits the low potential voltage stored in the last stage to the fourth capacitor C4 through the fourth transistor T4 for storage, the fourth capacitor C4 stores the high potential, and the third capacitor C3 keeps storing the high potential. Therefore, the first control signal output by the output end Q(n) of the first register 21 is the high potential. The second control signal output by the output end P(n) of the second register 22 is the low potential. The fifth transistor T5 in the first control unit 23 is turned on, the first control unit 23 outputs the high potential signal, and the ninth transistor T9 in the first output unit 11 is turned on. The output end P(n) of the second register 22 controls the eighth transistor T8 in the second control unit 24 to be turned on, the second control unit 24 outputs the low potential, and the twelfth transistor T12 in the first output unit 11 is turned on. The output end P(n-1) of the second register 22 in the last stage (even stage) gate drive unit GOA(n-1) keeps outputting the high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 in the current stage (odd stage) gate drive unit GOA(n) to be kept turned on. Therefore, the pulse signal scan(n) output by the current stage gate drive unit GOA(n) can be the low potential pulse through the twelfth transistor T12 and the fourteenth transistor T14. The output end Q(n) of the first register 21 also controls the fifteenth transistor T15 in the second cascade control unit 102 to be turned off, thereby making the first cascade end output to the next stage (even stage) gate drive unit GOA(n+1) be the high potential signal. The output end P(n) of the second register 22 controls the sixteenth transistor T16 in the third cascade control unit 103 to be turned on, so that the first output unit 11 of the current stage gate drive unit GOA(n) is cascaded with the next two stages of gate drive units GOA(n+2), thereby making the second cascade end output to the next two stages of gate drive units GOA(n+2) be the low potential signal. The output end P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned on, therefore, the current stage (odd stage) gate drive unit GOA(n) also outputs the next stage pulse signal scan(n+1), and the output next stage pulse signal scan(n+1) is the low potential pulse. Please refer to the following figure for details. Figure 23 .

[0164] At this stage, the output end P(n) of the second register 22 in the gate drive unit GOA(n) at this stage (odd stage) also controls the fourteenth transistor T14 in the first cascade control unit 101 in the gate drive unit GOA(n+1) at the next stage (even stage) to be off, so that the gate drive unit GOA(n+1) at the next stage (even stage) does not output the pulse signal scan(n+1) at the next stage, and the gate drive unit GOA(n+1) at the next stage (even stage) also does not output the pulse signal scan(n+2) at the next two stages.

[0165] In the output stage 2, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, and the first capacitor C1 and the second capacitor C2 store high potentials. The fourth capacitor C4 keeps the low potential stored in the previous timing, and the third capacitor C3 keeps the high potential. Therefore, the first control signal output by the output end Q(n) of the first register 21 keeps the high potential. The second control signal output by the output end P(n) of the second register 22 keeps the low potential. The fifth transistor T5 in the first control unit 23 is turned on, the first control unit 23 outputs the high potential signal, and then controls the ninth transistor T9 in the first output unit 11 to be turned on. The output end of the second register 22 controls the eighth transistor T8 in the second control unit 24 to be turned on, the second control unit 24 outputs the low potential, and then controls the twelfth transistor T12 in the first output unit 11 to be turned on. The output end P(n-1) of the second register 22 in the gate drive unit GOA(n-1) at the previous stage (even stage) keeps outputting the high potential, so as to control the fourteenth transistor T14 in the first cascade control unit 101 in the gate drive unit GOA(n) at this stage (odd stage) to keep being turned on. Therefore, the twelfth transistor T12 and the fourteenth transistor T14 can make the pulse signal scan(n) output by the gate drive unit GOA(n) at this stage be the low potential pulse. The output end Q(n) of the first register 21 also controls the fifteenth transistor T15 in the second cascade control unit 102 to be turned off, so that the first cascade end output to the gate drive unit GOA(n+1) at the next stage (even stage) is the high potential signal. The output end P(n) of the second register 22 controls the sixteenth transistor T16 in the third cascade control unit 103 to be turned on, so that the first output unit 11 in the gate drive unit GOA(n) at this stage is cascaded with the gate drive unit GOA(n+2) at the next two stages, and the second cascade end output to the gate drive unit GOA(n+2) at the next two stages is the low potential signal. The output end P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned on, so that the pulse signal scan(n+1) output by the gate drive unit GOA(n) at this stage (odd stage) is the low potential pulse. For details, please refer to Figure 24 .

[0166] In the holding stage 1, the first transistor T1 and the third transistor T3 are turned off, and the second transistor T2 and the fourth transistor T4 are turned on. The high potential stored on the second capacitor C2 is transmitted to the fourth capacitor C4 through the fourth transistor T4 and stored. The third capacitor C3 keeps storing the high potential. Therefore, the first control signal outputted by the output terminal Q(n) of the first register 21 is high potential. The second control signal outputted by the output terminal P(n) of the second register 22 is high potential. The fifth transistor T5 in the first control unit 23 is turned on, the first control unit 23 outputs high potential signal, and the ninth transistor T9 in the first output unit 11 is turned on. The output terminal of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, the second control unit 24 outputs high potential, and the tenth transistor T10 in the first output unit 11 is turned on. The output terminal P(n-1) of the second register 22 in the previous stage (even stage) gate driving unit GOA(n-1) keeps outputting high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to be turned on. Therefore, the stage pulse signal scan(n) outputted by the current stage gate driving unit GOA(n) is high potential pulse through the ninth transistor T9 and the tenth transistor T10. The output terminal Q(n) of the first register 21 controls the fifteenth transistor T15 in the second cascade control unit 102 to be turned off, thereby making the first cascade terminal outputted to the next stage gate driving unit GOA(n+1) be high potential signal. The output terminal P(n) of the second register 22 controls the sixteenth transistor T16 in the third cascade control unit 103 to be turned off, thereby making the second cascade terminal outputted to the next two stage gate driving unit GOA(n+2) be high potential signal. The output terminal P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off, therefore, the current stage gate driving unit GOA(n) does not output the next stage pulse signal scan(n+1). For details, please refer to the following figure. Figure 25 .

[0167] In the holding stage 2, the first transistor T1 and the third transistor T3 are turned on, the second transistor T2 and the fourth transistor T4 are turned off, the first capacitor C1 and the second capacitor C2 store high potentials. The third capacitor C3 and the fourth capacitor C4 keep storing high potentials. Therefore, the first control signal output by the output end Q(n) of the first register 21 is high potential. The second control signal output by the output end P(n) of the second register 22 is high potential. The fifth transistor T5 in the first control unit 23 is turned on, the first control unit 23 outputs a high potential signal, thereby controlling the ninth transistor T9 in the first output unit 11 to be turned on. The output end of the second register 22 controls the seventh transistor T7 in the second control unit 24 to be turned on, the second control unit 24 outputs a high potential, thereby controlling the tenth transistor T10 in the first output unit 11 to be turned on. The output end P(n-1) of the second register 22 in the previous stage (even stage) gate drive unit GOA(n-1) keeps outputting a high potential, thereby controlling the fourteenth transistor T14 in the first cascade control unit 101 to be kept turned on. Therefore, through the ninth transistor T9 and the tenth transistor T10, the stage pulse signal scan(n) output by the current stage gate drive unit GOA(n) is a high potential pulse. The output end Q(n) of the first register 21 controls the fifteenth transistor T15 of the second cascade control unit 102 to be turned off, thereby making the first cascade end output to the next stage gate drive unit GOA(n+1) be a high potential signal. The output end P(n) of the second register 22 controls the sixteenth transistor T16 of the third cascade control unit 103 to be turned off, thereby making the second cascade end output to the next two stage gate drive unit GOA(n+2) be a high potential signal. The output end P(n) of the second register 22 also controls the thirteenth transistor T13 in the second output unit 12 to be turned off, therefore, the current stage gate drive unit GOA(n) does not output the next stage pulse signal scan(n+1). For details, please refer to Figure 26 .

[0168] In the holding stage, the fourth capacitor C4 is covered by the high potential on the second capacitor C2, the first register 21 will continue to keep outputting a high potential, therefore, no matter whether the cascade unit (T1 / T3) is turned on or not, the current stage gate drive unit GOA(n) keeps outputting the current stage pulse signal scan(n) as a high potential.

[0169] Further, the present application also provides a driving circuit diagram of the even stage gate drive unit in the second driving mode. For details, please refer to Figure 27 , Figure 27 The driving circuit diagram of the even stage gate drive unit in the second driving mode provided by the present application, or in other words, Figure 27Figure 2 shows a driving circuit diagram of the (N+1)th gate driving unit in the second driving mode. The (N+1)th gate driving unit GOA(n+1) is taken as an even-numbered gate driving unit for description. As shown in Figure 2, the first cascade end of the (N+1)th gate driving unit GOA(n+1) is connected with the Nth gate driving unit. Please refer to the output end GOA(n+1) shown in Figure 1, the Nth gate driving unit outputs all high potential signals. Figure 27 As shown in Figure 2, the second cascade end of the (N+1)th gate driving unit GOA(n+1) is connected with the (N-1)th gate driving unit. Please refer to the output end GOA(n+1) shown in Figure 1, the (N-1)th gate driving unit outputs all high potential signals. Therefore, both input ends of the (N+1)th gate driving unit GOA(n+1) input high potential signals, so that the (N+1)th gate driving unit GOA(n+1) can be driven according to the gate driving circuit shown in Figure 1. The output end P(n) of the second register 22 in the (N+1)th gate driving unit GOA(n+1) can control the fourteenth transistor T14 in the first cascade control unit 101 to be off when outputting low potential, so as to control the (N+1)th gate driving unit GOA(n+1) not to output the pulse signal scan(n+1) of the current stage. Therefore, the (N+1)th gate driving unit GOA(n+1) does not output the pulse signal scan(n+1) of the current stage and the pulse signal scan(n+2) of the next stage. Figures 22-26 Figure 27 Figures 25-26

[0170] It should be noted that, in the second driving mode, when the odd-numbered gate driving unit is driven according to the output stage 1 and the output stage 2, the even-numbered gate driving unit is driven according to the output stage 1 and the output stage 2 shown in Figure 2, so there is no output. When the odd-numbered gate driving unit is driven according to the output stage 3 and the output stage 4 shown in Figure 1, the even-numbered gate driving unit is driven according to the output stage 3 and the output stage 4 shown in Figure 2. Thus, the adjacent two gate driving units output the same pulse signal. Figure 27 Figure 22 Figure 25 Figure 26 Figures 25-26

[0171] The application further provides a display panel, please refer to Figure 28 Figure 28 Figure 3 shows a structure schematic diagram of an embodiment of the display panel provided by the application. As shown in Figure 3, the display panel comprises a plurality of gate driving units GOA(n) and a plurality of sub-pixels SP(n). The gate driving units GOA(n) are connected with the sub-pixels SP(n) in sequence. The gate driving units GOA(n) are driven according to the driving mode shown in Figure 1. Figure 28 ​​​​​​​​​As shown, the display panel 1000 includes a display area 1001 and a non-display area 1002, and the non-display area 1002 of one side or opposite sides of the display panel 1000 is provided with the gate drive circuit in any of the above embodiments, which includes a plurality of cascaded gate drive units. The gate drive circuit sequentially transmits a scanning signal scan(n) to each row of pixel units of the display area 1001, that is, a pulse signal scan(n). The pulse signal scan(n) is a low potential pulse with a normally high potential.

[0172] In the above embodiments, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10 and the fourteenth transistor T14 in the above gate drive circuit are N-type transistors, and the other transistors are P-type transistors. In other embodiments, the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, the tenth transistor T10 and the fourteenth transistor T14 can be P-type transistors, and the other transistors can be N-type transistors, which are not limited herein.

[0173] The control unit in the above gate drive circuit is cascaded with the previous stage gate drive unit or the two previous stage gate drive units, and the output of the first output unit and / or the second output unit is controlled according to the cascaded signal, so as to realize the switching of the first driving mode and the second driving mode, thereby solving the problems of high brush and high power consumption in the frequency doubling display mode and the problem of life decline caused by high frequency use of the gate drive circuit.

[0174] The above is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: include: A plurality of cascaded gate drive units, each of which comprises: A first output unit, used to output a pulse signal of the gate drive unit of this stage; A second output unit, used to output a pulse signal to the gate drive unit of the next stage; a control unit connected to the first output unit and the second output unit, and configured to control the operation of the first output unit and / or the second output unit to implement switching between the first driving mode and the second driving mode; Wherein, in the first driving mode, the control unit controls the first output unit of each stage of the gate driving unit to work, and the second output unit to not work, so that each stage of the gate driving unit sequentially outputs the pulse signal; In the second driving mode, the control unit controls the first output unit and the second output unit of the odd-numbered gate driving unit to work, and the first output unit and the second output unit of the even-numbered gate driving unit not to work, so as to output the same pulse signals of the two adjacent levels.

2. The gate drive circuit according to claim 1, wherein: Each level of the gate driving unit also includes a first cascade control unit, the control end of the first cascade control unit is connected to the gate driving unit of the previous level or the high-potential signal line, and is used to control the output of the first output unit of this level according to the gate driving unit of the previous level or the high-potential signal line, so that the gate driving units of the odd levels simultaneously output the pulse signal of this level and the pulse signal of the next level, and at the same time, the first output units of the gate driving units of the even levels have no output.

3. The gate drive circuit according to claim 1, wherein: The control unit comprises: a first register connected to the first signal line or the output end of the gate driving unit of the previous stage, configured to receive a first start signal output by the first signal line or a pulse signal output by the gate driving unit of the previous stage, and control the output of a first control signal according to the first start signal or the pulse signal of the previous stage; a second register connected to the second signal line or the output end of the gate driving unit two stages above, for receiving the second start signal output by the second signal line or the pulse signal output by the gate driving unit two stages above, and controlling the output of the second control signal according to the second start signal or the pulse signal two stages above; Among them, the output end of the first register is connected to the control end of the first output unit, the output end of the second register is connected to the control ends of the first output unit and the second output unit, the first register and the second register are used to output the first control signal and the second control signal to control the operation of the first output unit, and the second register is used to output the second control signal to control the operation of the second output unit.

4. The gate driving circuit according to claim 3, wherein: The control unit further comprises: a first control unit, connected to the output end of the first register and the control end of the first output unit, and configured to control the first output unit to output the pulse signal of this stage according to the first control signal; a second control unit, connected to the output end of the second register and the control end of the second output unit, for controlling the second output unit to output the next level of the pulse signal according to the second control signal; The control end of the first output unit is also connected to the second control unit, and is used to control the first output unit to output the pulse signal of this level according to the control signals output by the first control unit and the second control unit.

5. The gate driving circuit according to claim 4, wherein: The first control unit includes: a first sub-control unit, connected to the first register, a high-potential signal line, and the first output unit, and configured to control the output of the first output unit according to a first control signal output by the first register; a second sub-control unit, connected to the first register, a low-potential signal line, and the first output unit, and configured to control the output of the first output unit according to a first control signal output by the first register; The second control unit includes: a third sub-control unit, connected to the second register, the high-potential signal line, and the second output unit, and configured to control the output of the second output unit according to a second control signal output by the second register; a fourth sub-control unit, connected to the second register, the low-potential signal line, and the second output unit, and configured to control the output of the second output unit according to a second control signal output by the second register; The first sub-control unit and the second sub-control unit include a group of transistors with opposite driving characteristics; the third sub-control unit and the fourth sub-control unit include a group of transistors with opposite driving characteristics.

6. The gate driving circuit according to claim 3, wherein: The control end of the second output unit is connected to the second register, and the input end is connected to the first output unit, and is used to control the output of the next level of the pulse signal according to the second control signal transmitted by the second register, thereby realizing the switching between the first driving mode and the second driving mode.

7. The gate driving circuit according to claim 3, wherein: Each of the gate driving units further includes: a second cascade control unit, whose input end is connected to the first output unit, and whose output end is connected to the input end of the gate driving unit of the next stage, and is used to drive the gate driving unit of the next stage to work according to the pulse signal output by the first output unit; a third cascade control unit, whose input end is connected to the first output unit, and whose output end is connected to the input ends of the gate driving units of the next two stages, and is used to drive the gate driving units of the next two stages to work according to the pulse signal output by the first output unit; The control end of the second cascade control unit is connected to the output end of the first register; The control end of the third cascade control unit is connected to the output end of the second register.

8. The gate driving circuit according to claim 3, wherein: The first register includes: A first cascade unit, having an input end connected to the first signal line or the output end of the gate driving unit of the previous stage, and a control end connected to the first control signal line, for receiving a cascade signal transmitted by the gate driving unit of the previous stage; a first storage unit, wherein the first plate is connected to the output end of the first cascade unit and is used to store the cascade signal transmitted by the gate driving unit of the previous stage, and the second plate is connected to the low-potential signal line; The second register includes: A second cascade unit, having an input end connected to the second signal line or the output ends of the two previous gate driving units, and a control end connected to the first control signal line, for receiving the cascade signal transmitted by the two previous gate driving units; The second storage unit has a first plate connected to the output end of the second cascade unit and is used to store the cascade signals transmitted by the two previous gate driving units, and a second plate connected to the low potential signal line.

9. The gate driving circuit according to claim 8, wherein: The first register further includes: a first delay control unit, having an input end connected to the output end of the first cascade unit and the first storage unit, and a control end connected to the second control signal line, for delaying the control effect of the cascade signal transmitted by the gate driving unit of the previous stage on the first output unit; a third storage unit, wherein the first plate is connected to the output end of the first delay control unit, and is used to store the cascade signal transmitted by the gate driving unit of the previous stage, and the second plate is connected to the low-potential signal line; The second register further includes: a second delay control unit, having an input end connected to the output end of the second cascade unit and the second storage unit, and a control end connected to the second control signal line, for delaying the control effect of the cascade signal transmitted by the two previous gate driving units on the second output unit and / or the first output unit; The fourth storage unit has a first plate connected to the output end of the second delay control unit and is used to store the cascade signals transmitted by the two previous gate driving units, and a second plate connected to the low-potential signal line.

10. A display panel, characterized in that: The display panel includes the gate driving circuit according to any one of claims 1 to 9.

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