Memory, manufacturing method thereof and electronic equipment

Abstract

The invention provides a memory, a manufacturing method thereof and electronic equipment, relates to the technical field of semiconductors, and is used for solving the technical problem that the performance of the memory is poor. The memory comprises a plurality of bit line function groups, a plurality of memory cells and a step structure, wherein each bit line function group comprises a first bit line structure, a plurality of second bit line structures and a plurality of selection transistors. The first bit line structure comprises a first isolation layer and a first bit line circumferentially surrounding the first isolation layer. The first side of the first bit line in the third direction is provided with a plurality of second bit line structures, the second side of the first bit line in the third direction is provided with a step structure, and a plurality of conductive steps of the step structure are respectively coupled with the corresponding first bit line. The first isolation layer is used for isolation to avoid disconnection of a part of the first bit line close to the second bit line structure and ensure the consistency of the part of the first bit line, so that the connection performance with the second bit line structure is ensured, and the performance of the memory is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and particularly to a memory, a manufacturing method thereof, and an electronic device. Background Art

[0002] With the continuous development of semiconductor technologies and storage technologies, electronic devices are continuously moving towards miniaturization and integration. Dynamic Random Access Memory (DRAM) is widely used in various electronic devices due to its high storage density and fast read / write speed.

[0003] A dynamic random access memory includes word lines (WL), bit lines (BL), and multiple memory cells. Each memory cell generally includes an access transistor and a capacitor. The gate of the access transistor is electrically connected to the word line, one of the source and the drain is electrically connected to the bit line, and the other of the source and the drain is electrically connected to the capacitor. The voltage on the word line can control the opening and closing of the access transistor, so that data information in the capacitor can be read through the bit line, or data information can be written into the capacitor.

[0004] To improve the storage density, the bit line generally includes a common bit line and a local bit line, and the local bit line is correspondingly coupled to the memory cell. The common bit line is coupled to the local bit line through a selection transistor and is externally connected through a stepped structure. However, during the manufacturing process of the above-mentioned bit line, the common bit line is prone to breakage, and the performance of the memory is poor. Summary of the Invention

[0005] In view of the above problems, embodiments of the present disclosure provide a memory, a manufacturing method thereof, and an electronic device for improving the performance of the memory.

[0006] According to some embodiments, the present disclosure provides a memory, which includes: a plurality of bit line function groups arranged at intervals along a first direction, a plurality of memory cells, and a stepped structure; each of the bit line function groups includes: a first bit line structure, the first bit line structure includes a first isolation layer extending along a second direction and a first bit line circumferentially surrounding the first isolation layer; a plurality of second bit line structures, the plurality of second bit line structures are located on a first side of the first bit line in a third direction and are arranged at intervals along the second direction, the second direction, the third direction and the first direction are perpendicular to each other in pairs; a plurality of selection transistors, the plurality of selection transistors are located between the first bit line structure and the plurality of second bit line structures, and each of the second bit line structures is coupled to the first bit line through one of the selection transistors; the plurality of memory cells are respectively coupled to the corresponding second bit line structures; the stepped structure is located on a second side of the first bit line in the third direction and includes a plurality of conductive steps, and the plurality of conductive steps are respectively coupled to the first bit lines in the plurality of bit line function groups.

[0007] In some possible implementation manners, the first bit line in at least one of the bit line function groups includes a first bit line portion and a second bit line portion, the first bit line portion is in a non-closed ring shape, an opening of the non-closed ring shape is located on a second side of the first bit line structure in the third direction, the second bit line portion is located at the opening of the non-closed ring shape, and the second bit line portion has the same material composition as the conductive step.

[0008] In some possible implementation manners, the first bit line in some of the bit line function groups includes a first bit line portion and a second bit line portion, and the first bit line in the remaining bit line function groups only includes the first bit line portion; the second bit line structure includes a second isolation layer extending along the third direction and a second bit line circumferentially surrounding the second isolation layer, the second isolation layer has the same material composition as the first isolation layer, and the first bit line portion has the same material composition as the second bit line.

[0009] In some possible implementation manners, the first isolation layers opposite to each other along the first direction are connected to form an integral structure, and the first bit lines opposite to each other along the first direction are spaced apart from each other; the second isolation layers opposite to each other along the first direction are connected to form an integral structure, and the second bit lines opposite to each other along the first direction are spaced apart from each other.

[0010] In some possible implementation manners, the multiple memory cells are arranged at intervals along the first direction, at intervals along the second direction, and at intervals along the third direction. At least one side of each of the two opposite sides of each second bit line structure along the second direction is correspondingly provided with a memory cell; each memory cell includes an access transistor and a capacitor connected in series. The access transistor is correspondingly connected to the second bit line structure, and the capacitor is disposed on a side of the access transistor away from the corresponding second bit line structure.

[0011] In some possible implementation manners, the memory further includes a plurality of filling patterns located on a first side of the first bit line along the third direction. Along the second direction, the plurality of filling patterns are opposite to the plurality of selection transistors, and at least one of the filling patterns is disposed between two adjacent selection transistors.

[0012] In some possible implementation manners, the selection transistor and the access transistor include a gate, a gate dielectric layer surrounding the gate, and an active layer surrounding the gate dielectric layer; the gates opposite to each other along the first direction are connected to form a word line, the gate dielectric layers opposite to each other along the first direction are connected to form an integral structure, the active layers opposite to each other along the first direction are spaced apart from each other, and are connected to the corresponding second bit line structure; and / or, the capacitor includes a first electrode, a capacitive dielectric layer surrounding the first electrode, and a second electrode surrounding the capacitive dielectric layer; the first electrodes opposite to each other along the first direction are connected to form an integral structure, the capacitive dielectric layers opposite to each other along the first direction are connected to form an integral structure, the second electrodes opposite to each other along the first direction are spaced apart from each other, and are connected to the corresponding active layer.

[0013] In some possible implementation manners, each of the conductive steps has a groove, and the groove divides the corresponding conductive step into a first segment and a second segment spaced apart along the second direction. The grooves communicate with each other, and each groove has a first end and a second end opposite to each other along the second direction; among any three adjacent grooves along the first direction, the first end of the groove in the middle is opposite to the first end of one of the remaining two grooves, and the second end is opposite to the second end of the other of the remaining two grooves, so that the first segments arranged in a staggered pattern form a first step, the second segments arranged in a staggered pattern form a second step, and the step surfaces of the first step and the second step are staggered along the first direction, and the first step and the second step form the stepped structure.

[0014] In some possible implementations, each of the conductive steps has a first end and a second end that are opposite to each other in the second direction; among any three adjacent conductive steps in the first direction, the first end of the middle conductive step is opposite to the first end of one of the remaining two conductive steps, and the second end is opposite to the second end of the other of the remaining two conductive steps, so that the first ends of the staggered conductive steps form a first step, the second ends of the staggered conductive steps form a second step, and the step surfaces of the first step and the second step are staggered in the first direction, and the first step and the second step form the stepped structure.

[0015] The memory provided by the embodiments of the present disclosure has at least the following advantages:

[0016] The memory provided by the embodiments of the present disclosure includes a plurality of bit line function groups, a plurality of memory cells, and a stepped structure, and the plurality of bit line function groups are arranged at intervals in the first direction. Each bit line function group includes a first bit line structure, a plurality of second bit line structures, and a plurality of selection transistors. Among them, the first bit line structure includes a first isolation layer and a first bit line, the first isolation layer extends in the second direction, and the first bit line circumferentially surrounds the first isolation layer. A plurality of second bit line structures are provided on the first side of the first bit line in the third direction, and the plurality of second bit line structures are arranged at intervals in the second direction. Each second bit line structure is coupled to the first bit line structure through a selection transistor. A stepped structure is provided on the second side of the first bit line in the third direction, and the plurality of conductive steps of the stepped structure are respectively coupled to the corresponding first bit line. By arranging the stepped structure and the second bit line structure on both sides of the first bit line structure, and the first bit line structure adopts a structure in which the first bit line surrounds the first isolation layer, when manufacturing the stepped structure, the first isolation layer can block, avoiding the open circuit of some of the first bit lines on the side of the first isolation layer close to the second bit line structure, ensuring the consistency of this part of the first bit line, thereby ensuring the connection performance with the second bit line structure and improving the performance of the memory.

[0017] According to some embodiments, the present disclosure also provides an electronic device, including the memory as described above, and a processor coupled to the memory. Since the electronic device has the above memory, it has at least the advantage of better storage performance. For details, refer to the above text and will not be elaborated here.

[0018] According to some embodiments, the present disclosure also provides a method for manufacturing a memory, including: forming a stacked structure on a substrate, the stacked structure including a first dielectric layer and a second dielectric layer alternately arranged in sequence along a first direction; removing a part of the stacked structure to form a first trench and a plurality of second trenches, the first trench extending along a second direction, the plurality of second trenches being located on a first side of the first trench in a third direction and arranged at intervals along the second direction, the second direction and the third direction intersecting with the first direction pairwise; removing a part of the first dielectric layer exposed in the first trench and the second trenches to form a plurality of first receiving grooves communicating with the first trench and a plurality of second receiving grooves communicating with the second trench; forming a first bit line structure in the first trench and the first receiving grooves, forming a second bit line structure in the second trench and the second receiving grooves, and forming a stepped structure; the first bit line structure includes a first isolation layer and a first bit line circumferentially surrounding the first isolation layer, the first bit line being correspondingly located in the first receiving groove, and the stepped structure being located on a second side of the first bit line in the third direction.

[0019] In some possible implementation manners, forming a first bit line structure in the first trench and the first receiving grooves, forming a second bit line structure in the second trench and the second receiving grooves, and forming the stepped structure includes: depositing an initial conductive layer, the initial conductive layer filling the first receiving groove and the second receiving groove and covering the side walls and the bottom wall of the first trench, and the side walls and the bottom wall of the second trench; retaining the initial conductive layer located in the first receiving groove and the second receiving groove, removing the remaining initial conductive layer, and the initial conductive layer located in the first receiving groove forms the first bit line; depositing an initial isolation layer, the initial isolation layer filling the remaining first trench and the remaining second trench, the initial isolation layer located in the first trench forms the first isolation layer, and the initial conductive layer located in the second filling groove and the initial isolation layer located in the second trench form the second bit line structure; forming the stepped structure, the stepped structure including a plurality of conductive steps, and the plurality of conductive steps are respectively coupled to the corresponding first bit lines.

[0020] In some possible implementations, the manufacturing method also includes: etching the first dielectric layer and the second dielectric layer to form a first hole, a second hole, a third hole and a fourth hole; the first hole is located between the first bit line and the second bit line structure, the second hole is located on two opposite sides of the second bit line structure along the second direction, the third hole is located on the side of the second hole away from the second bit line structure, the fourth hole is located on the first side of the first bit line along the third direction, along the second direction, the fourth hole is opposite to the first hole, and at least one fourth hole is arranged between two adjacent first holes; forming a selection transistor, an access transistor, a capacitor and a filling pattern, the selection transistor is located in the first hole and coupled to the second bit line structure, the access transistor is located in the second hole and coupled to both the second bit line structure and the first bit line, the capacitor is located in the third hole and coupled to the access transistor, and the filling pattern is located in the fourth hole.

[0021] In some possible implementations, the access transistor and the selection transistor are formed synchronously.

[0022] In some possible implementations, forming the stepped structure includes: etching the first dielectric layer and the second dielectric layer on a side of the second bit line away from the first bit line to form a groove, wherein the groove exposes each first bit line, and two side walls opposite to each other along the second direction are both stepped, and a step surface of one of the side walls includes surfaces of the second dielectric layers of odd numbers other than one second dielectric layer adjacent to the substrate facing away from the substrate, and a step surface of the other side wall includes surfaces of the second dielectric layers of even numbers facing away from the substrate; etching and removing a portion of the first dielectric layer exposed in the groove to form a third accommodating groove, wherein each first bit line is correspondingly exposed in the third accommodating groove; forming a conductive step, wherein the conductive step is filled in the third accommodating groove and contacts with each first bit line correspondingly, and each conductive step forms a stepped structure; and forming a third isolation layer in the groove, wherein the third isolation layer fills the groove.

[0023] The memory manufacturing method provided by the embodiment of the present disclosure has at least the following advantages:

[0024] In the method for manufacturing a memory provided by an embodiment of the present disclosure, a stacked structure is formed on a substrate, and a part of the stacked structure is removed to form a first trench and a plurality of second trenches. The plurality of second trenches are located on a first side of the first trench in a third direction and are arranged at intervals along a second direction. A part of a first dielectric layer exposed in the first trench and the second trenches is removed to form a plurality of first receiving grooves communicating with the first trench and a plurality of second receiving grooves communicating with the second trenches. A first bit line structure is formed in the first trench and the first receiving grooves, a second bit line structure is formed in the second trench and the second receiving grooves, and a stepped structure is formed. The first bit line structure includes a first isolation layer and a first bit line circumferentially surrounding the first isolation layer. The first bit line is correspondingly located in the first receiving groove. The stepped structure is located on a second side of the first bit line in the third direction and includes a plurality of conductive steps, and the plurality of conductive steps are respectively coupled to the corresponding first bit lines. By arranging the stepped structure and the second bit line structure on both sides of the first bit line structure, and the first bit line structure adopts a structure in which the first bit line surrounds the first isolation layer, when the stepped structure is manufactured, the first isolation layer can act as a barrier to prevent a part of the first bit line on the side close to the second bit line structure from being open-circuited, ensuring the consistency of this part of the first bit line, thereby ensuring the connection performance with the second bit line structure and improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic structural diagram of a memory in an embodiment of the present disclosure;

[0026] Figure 2 is an architecture diagram of a first bit line structure, a second bit line structure and a selection transistor in an embodiment of the present disclosure;

[0027] Figure 3 is a schematic simplified diagram of an architecture of a memory in an embodiment of the present disclosure;

[0028] Figure 4 is a schematic diagram of a stepped structure in an embodiment of the present disclosure;

[0029] Figure 5 is another schematic diagram of a stepped structure in an embodiment of the present disclosure;

[0030] Figure 6 is yet another schematic diagram of a stepped structure in an embodiment of the present disclosure;

[0031] Figure 7 is a flowchart of a method for manufacturing a memory in an embodiment of the present disclosure;

[0032] Figure 8 is a three-dimensional schematic diagram of a substrate and a stacked structure in an embodiment of the present disclosure;

[0033] Figure 9Schematic plan view of a substrate and a stacked structure in an embodiment of the present disclosure;

[0034] Figure 10 Schematic three-dimensional view after forming a first mask layer in an embodiment of the present disclosure;

[0035] Figure 11 For Figure 10 Cross-sectional view at A in;

[0036] Figure 12 Schematic three-dimensional view after forming a first trench and a second trench in an embodiment of the present disclosure;

[0037] Figure 13 Process diagram of forming a second receiving groove in an embodiment of the present disclosure;

[0038] Figure 14 Schematic diagram of forming a first receiving groove in an embodiment of the present disclosure;

[0039] Figure 15 Process diagram of forming a second bit line and a second isolation layer in an embodiment of the present disclosure;

[0040] Figure 16 Process diagram of forming a first bit line and a first isolation layer in an embodiment of the present disclosure;

[0041] Figure 17 Schematic three-dimensional view after forming a second mask layer in an embodiment of the present disclosure;

[0042] Figure 18 Schematic three-dimensional view of the schematic diagram after etching a first dielectric layer in an embodiment of the present disclosure;

[0043] Figure 19 Schematic three-dimensional view after forming a photoresist layer in an embodiment of the present disclosure;

[0044] Figure 20 Schematic three-dimensional view after etching two layers of the first dielectric layer downward in an embodiment of the present disclosure;

[0045] Figure 21 Schematic three-dimensional view of the flared photoresist layer in an embodiment of the present disclosure;

[0046] Figure 22 Schematic three-dimensional view after continuously etching two layers of the first dielectric layer downward in an embodiment of the present disclosure;

[0047] Figure 23 Process diagram of forming a third receiving groove in an embodiment of the present disclosure;

[0048] Figure 24 Process diagram of forming a conductive step and a third isolation layer in an embodiment of the present disclosure;

[0049] Figure 25 Process diagram of forming the third hole in an embodiment of the present disclosure;

[0050] Figure 26 Process diagram of forming the initial electrode layer and the third dielectric layer in an embodiment of the present disclosure;

[0051] Figure 27 Process diagram of forming the second electrode layer in an embodiment of the present disclosure;

[0052] Figure 28 Process diagram of forming the capacitive dielectric layer in an embodiment of the present disclosure;

[0053] Figure 29 Schematic diagram after forming the first electrode in an embodiment of the present disclosure;

[0054] Figure 30 Process diagram of forming the first hole in an embodiment of the present disclosure;

[0055] Figure 31 Process diagram of forming the exposed initial active layer in an embodiment of the present disclosure;

[0056] Figure 32 Process diagram of forming the active layer in an embodiment of the present disclosure.

[0057] Explanation of reference numerals:

[0058] 10 - Bit - line function group; 11 - First bit - line structure; 12 - First bit - line;

[0059] 13 - First isolation layer; 14 - Second bit - line structure; 15 - Second bit - line;

[0060] 16 - Second isolation layer; 17 - Select transistor; 18 - Filling pattern;

[0061] 20 - Memory cell; 21 - Access transistor; 22 - Capacitor;

[0062] 23 - Capacitive plug; 30 - Step structure; 31 - Conductive step;

[0063] 32 - First segment; 33 - Second segment; 34 - Bit - line plug;

[0064] 35 - Third isolation layer; 40 - Substrate; 50 - Stacked structure;

[0065] 51 - First dielectric layer; 52 - Second dielectric layer; 53 - First trench;

[0066] 54 - Second groove; 55 - First receiving groove; 56 - Second receiving groove;

[0067] 61 - Gate; 62 - Gate dielectric layer; 63 - Active layer;

[0068] 71 - First mask layer; 72 - Second mask layer; 73 - Photoresist layer;

[0069] 81 - Third hole; 82 - Initial electrode layer; 83 - Third dielectric layer;

[0070] 84 - Second electrode; 85 - Capacitor dielectric layer; 86 - First electrode;

[0071] 87 - First hole; 88 - Initial active layer; 91 - Groove;

[0072] 92 - Third receiving groove; 93 - Fourth receiving groove; 94 - Fifth receiving groove. Detailed implementation manners

[0073] In order to make the above - mentioned objects, features, and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present disclosure.

[0074] Refer to Figures 1 to 6 , the embodiments of the present disclosure provide a memory, and the memory can be a dynamic random - access memory. The memory includes a plurality of bit - line functional groups 10, a plurality of memory cells 20, and a stepped structure 30. Among them, the bit - line functional groups 10 are connected to the corresponding memory cells 20 to read or write data into the corresponding memory cells 20, the plurality of memory cells 20 are used to store data, and the stepped structure 30 is used to externally connect the plurality of bit - line functional groups 10.

[0075] The plurality of bit - line functional groups 10 are arranged at intervals along a first direction, and the first direction is as Figure 1The Z direction shown in the figure. Each bit line functional group 10 includes a first bit line structure 11, a plurality of second bit line structures 14, and a plurality of selection transistors 17. Among them, the plurality of second bit line structures 14 are located on one side of the first bit line structure 11, and the first bit line structure 11 is coupled to the plurality of second bit line structures 14 to be used as a common bit line to aggregate the plurality of second bit line structures 14. Each second bit line structure 14 is coupled to a corresponding memory cell 20, and the selection transistor 17 is used to gate one of the second bit line structures 14. It can be understood that the first bit line structures 11 in the plurality of bit line functional groups 10 are opposite to each other in the first direction, and the second bit line structures 14 in the plurality of bit line functional groups 10 are opposite to each other in the first direction.

[0076] In some possible exemplary embodiments, the first bit line structure 11 includes a first isolation layer 13 and a first bit line 12. The first isolation layer 13 extends in a second direction, and the second direction intersects the first direction. The second direction is as Figure 1 shown in the X direction in the figure. The first bit line 12 circumferentially surrounds the first isolation layer 13. For example, the first bit line 12 circumferentially surrounds the first isolation layer 13 entirely, that is, the first bit line 12 is a closed ring, and it surrounds the first isolation layer 13 for a full circle. A plurality of second bit line structures 14 are provided on the first side of the first bit line 12 in a third direction. Among them, the third direction intersects both the second direction and the first direction, that is, the third direction, the second direction, and the first direction intersect pairwise, for example, perpendicular. The third direction is as Figure 1 shown in the Y direction in the figure, and the first side of the first bit line 12 in the third direction is the Figure 2 upper side shown in the figure.

[0077] With such a setting, both sides of the first isolation layer 13 opposite to each other in the third direction have partial first bit lines 12. When other structures are fabricated on one side of the two sides of the first bit line 12 opposite to each other in the third direction, for example, when a stepped structure 30 is fabricated on the second side of the first bit line 12 in the third direction, the first isolation layer 13 can act as a barrier to prevent the first bit line 12 on the other side from being open-circuited, ensuring the consistency of the first bit line 12 on the other side and its connection performance with other structures.

[0078] In the third direction, the thickness of the first isolation layer 13 can be greater than the thickness of the first bit line 12. Exemplarily, the first isolation layer 13 includes a first sub-isolation layer extending in the second direction and a second sub-isolation layer surrounding the first sub-isolation layer. The material of the first sub-isolation layer is different from the material of the second sub-isolation layer. The material of the thicker first sub-isolation layer can be an oxide, such as silicon oxide, aluminum oxide, etc., and the material of the thinner second sub-isolation layer can be a nitride, such as silicon nitride, silicon oxynitride, silicon carbonitride, etc.

[0079] In some possible implementations, the first bit line 12 in at least one bit line functional group 10 includes a first bit line portion and a second bit line portion, and the first bit line portion is in a non-closed loop shape. Exemplarily, the first bit line 12 in each bit line functional group 10 includes a first bit line portion and a second bit line portion. Alternatively, the first bit lines 12 in some bit line functional groups 10 include a first bit line portion and a second bit line portion in a non-closed loop shape (for example, this part of the bit line functional group is usually far away from the substrate 40), and the first bit lines 12 in the remaining bit line functional groups 10 are in a closed loop shape (for example, this part of the bit line functional group is usually close to the substrate 40), that is, the first bit line portions in the remaining bit line functional groups 10 include first bit line portions in a closed loop shape.

[0080] In the example where the first bit line 12 includes a first bit line portion and a second bit line portion, the first bit line portion is in a non-closed ring shape, and the opening of the non-closed ring shape is located at the second side of the first bit line structure 11 in the third direction. In some examples, the opening of the first bit line portion is formed during the manufacturing process of the step structure 30. The second bit line portion is located at the opening of the non-closed ring shape, and illustratively, the second bit line portion fills the opening, and the first bit line portion and the second bit line portion are connected end to end to form a closed ring shape surrounding the first isolation layer 13.

[0081] It can be understood that an opening is formed between the two ends of the first bit line portion, the first bit line portion is continuous on the side of the first isolation layer 13 facing the second bit line structure 14, and both ends of the first bit line portion are located on the side of the first isolation layer 13 away from the second bit line structure 14. The first bit line portion is coupled to each second bit line structure 14 to ensure that each second bit line structure 14 is connected to a portion of the first bit line 12 having the same material composition, thereby ensuring consistency in connection performance between each second bit line structure 14 and the first bit line 12.

[0082] Continue reading Figure 1 , a plurality of second bit line structures 14 are located on a first side of the first bit line 12 in the third direction. Exemplarily, along the second direction, both ends of the first bit line 12 correspond to the two outermost second bit line structures 14 protruding outward, so that the plurality of second bit lines 15 pass through and couple with the first bit line 12. The plurality of second bit line structures 14 extend along the third direction and are arranged at intervals along the second direction.

[0083] In some possible examples, the second bit line structure 14 includes a second isolation layer 16 extending along a third direction, and a second bit line 15 circumferentially surrounding the second isolation layer 16. For example, the second bit line 15 circumferentially surrounds the second isolation layer 16, that is, the second bit line 15 is a closed ring. Along the third direction, the thickness of the second isolation layer 16 may be greater than the thickness of the second bit line 15. The second isolation layer 16 has the same material composition as the first isolation layer 13, that is, the second isolation layer 16 has the same structure as the first isolation layer 13, and the corresponding film layers have the same material.

[0084] It is understandable that the first isolation layer 13 has at least two film layers, the second isolation layer 16 also has the same number of film layers, the arrangement direction of each film layer of the first isolation layer 13 is the same as the arrangement mode of each film layer of the second isolation layer 16, and the materials of the film layers at the corresponding positions of the first isolation layer 13 and the second isolation layer 16 are the same. Exemplarily, the first isolation layer 13 includes a first sub-isolation layer and a second sub-isolation layer, and the second sub-isolation layer surrounds the first sub-isolation layer. Correspondingly, the second isolation layer 16 includes a third sub-isolation layer and a fourth sub-isolation layer, and the fourth sub-isolation layer surrounds the third sub-isolation layer. The materials of the first sub-isolation layer and the third sub-isolation layer are the same, and the materials of the second sub-isolation layer and the fourth sub-isolation layer are the same.

[0085] The first bit line 12 in the partial bit line functional group 10 includes a first bit line portion and a second bit line portion, and the first bit line portion and the second bit line portion have different material compositions. The first bit line 12 in the remaining bit line functional groups 10 only includes the first bit line portion, the first bit line portion in the remaining bit line functional groups 10 is the overall first bit line 12, and the second bit line 15 and the first bit line portion have the same material composition. The second bit line 15 and the first bit line portion have the same structure, and the materials of the corresponding film layers are the same.

[0086] In some possible examples, the first isolation layers 13 opposite to each other along the first direction are connected to form an integral structure, and the first bit lines 12 opposite to each other along the first direction are spaced apart from each other to facilitate the fabrication of the first isolation layer 13. It is understandable that the first isolation layer 13 is columnar, its axis direction is the first direction, taking the plane perpendicular to the axis direction as the cross-section, the cross-sectional shape of the first isolation layer 13 is rectangular. Along the axis direction, a plurality of first bit lines 12 are sleeved on the outer peripheral surface of the first isolation layer 13 at intervals.

[0087] In some possible examples, the second isolation layers 16 opposite to each other along the first direction are connected to form an integral structure, and the second bit lines 15 opposite to each other along the first direction are spaced apart from each other to facilitate the fabrication of the second isolation layer 16. It is understandable that the second isolation layer 16 is columnar, its axis direction is the first direction, taking the plane perpendicular to the axis direction as the cross-section, the cross-sectional shape of the second isolation layer 16 is rectangular. Along the axis direction, a plurality of second bit lines 15 are sleeved on the outer peripheral surface of the second isolation layer 16 at intervals.

[0088] Refer to Figures 1 to 3, a plurality of selection transistors 17 are located between the first bit line structure 11 and the plurality of second bit line structures 14. Each second bit line structure 14 is coupled to the first bit line structure 11 through a selection transistor 17. Specifically, the plurality of selection transistors 17 are arranged at intervals along the second direction. A selection transistor 17 is correspondingly arranged on one side of each second bit line structure 14 and the first bit line structure 11 that face each other. Among them, the second bit line 15 in the second bit line structure 14 is coupled to the corresponding selection transistor 17, and the first bit line 12 in the first bit line structure 11 is coupled to the corresponding selection transistor 17.

[0089] The plurality of memory cells 20 are arranged at intervals along the first direction, along the second direction, and along the third direction. At least one side of each of the two opposite sides of each second bit line structure 14 along the second direction is correspondingly provided with a memory cell 20, and the memory cell 20 is coupled to the corresponding second bit line structure 14. Exemplarily, memory cells 20 are respectively arranged on each of the two opposite sides of each second bit line structure 14 along the second direction to improve the storage density of the memory. The memory cells 20 on the adjacent sides of two adjacent second bit line structures 14 are spaced apart.

[0090] As Figure 1 shown, each memory cell 20 includes a coupled access transistor 21 and a capacitor 22. The access transistor 21 is correspondingly coupled to the second bit line structure 14, for example, coupled to the second bit line 15. The capacitor 22 is arranged on the side of the access transistor 21 away from the corresponding second bit line structure 14.

[0091] In some possible implementation manners, both the selection transistor 17 and the access transistor 21 include a gate 61, a gate dielectric layer 62 surrounding the gate 61, and an active layer 63 surrounding the gate dielectric layer 62, that is, the access transistor 21 is a Channel All Around (CAA) transistor. Among them, the gates 61 opposite to each other along the first direction are connected to form a word line, that is, the word line extends along the first direction. The gate dielectric layers 62 opposite to each other along the first direction are connected to form an integral structure. The active layers 63 opposite to each other along the first direction are spaced apart from each other and are coupled to the corresponding second bit line structure 14. The material of the active layer 63 can be Indium Gallium Zinc Oxide (IGZO) to improve the performance such as the electron mobility of the active layer 63.

[0092] In some possible implementations, the capacitor 22 includes a first electrode, a capacitive dielectric layer surrounding the first electrode, and a second electrode surrounding the capacitive dielectric layer. The first electrodes opposite to each other along the first direction are connected to form an integral structure, the capacitive dielectric layers opposite to each other along the first direction are connected to form an integral structure, the second electrodes opposite to each other along the first direction are spaced apart from each other, and are coupled to the corresponding active layer 63. Among them, multiple first electrodes are connected together to form a first electrode column, and the first electrode column is further provided with a filling hole extending along the first direction, and the filling hole is filled with a capacitive plug 23.

[0093] Continue to refer to Figure 1 , the memory further includes a plurality of filling patterns 18, and the plurality of filling patterns 18 are located on the first side of the first bit line 12 along the third direction, that is, the plurality of filling patterns 18 and the plurality of selection transistors 17 are located on the same side of the first bit line 12. Along the second direction, the plurality of filling patterns 18 are opposite to the plurality of selection transistors 17. For example, the plurality of filling patterns 18 and the plurality of selection transistors 17 form a row along the second direction. At least one filling pattern 18 is disposed between two adjacent selection transistors 17, which can improve the overall arrangement uniformity of the selection transistors 17, access transistors 21, and filling patterns 18, and reduce the etching loading effect during manufacturing.

[0094] Continue to refer to Figure 3 , the stepped structure 30 is located on the second side of the first bit line 12 in the third direction, that is, the stepped structure 30 and the plurality of second bit line structures 14 are respectively located on both sides of the first bit line 12. The stepped structure 30 includes a plurality of conductive steps 31, and the plurality of conductive steps 31 are respectively coupled to the first bit line 12 in the plurality of bit line functional groups 10, that is, at least one (for example, one) conductive step 31 is connected to one first bit line 12 to externally connect the first bit line 12.

[0095] Among them, in the example where the first bit line 12 in at least one bit line functional group 10 includes a first bit line portion and a second bit line portion, the second bit line portion has the same material composition as the conductive step 31. The second bit line portion can be formed synchronously with the conductive step 31, that is, when the conductive step 31 is formed, the material used to form the conductive step 31 also fills at least part of the opening of the first bit line portion, and this part of the material forms the second bit line portion.

[0096] In some possible implementations, refer to Figure 4 and Figure 5 , each conductive step 31 has a groove, and the groove separates the corresponding conductive step 31 into a first segment 32 and a second segment 33 spaced apart along the second direction. The grooves communicate with each other, and each groove has a first end and a second end opposite to each other along the second direction, where the first end of each groove can be Figure 4 the left end shown, and the second end of each groove can beFigure 4 The right end shown.

[0097] Among any three adjacent grooves along the first direction, the first end of the middle groove is opposite to the first end of one of the remaining two grooves, and the second end is opposite to the second end of the other of the remaining two grooves, that is, a stepped structure 30 is formed in the middle of the conductive step 31. Specifically, as Figure 4 shown, two adjacent first segments 32 among the plurality of first segments 32 are aligned at the ends facing the second segment 33, or two adjacent second segments 33 among the plurality of second segments 33 are aligned at the ends facing the first segment 32, so that the staggered first segments 32 form a first step, the staggered second segments 33 form a second step, and the step surfaces of the first step and the second step are staggered along the first direction, and the first step and the second step form the stepped structure 30.

[0098] Exemplarily, there are five conductive steps 31. For the sake of description, these five conductive steps 31 are sequentially defined as the first conductive step, the second conductive step, the third conductive step, the fourth conductive step, and the fifth conductive step. Among them, the first conductive step is located at the uppermost, and the fifth conductive step is located at the lowermost.

[0099] As Figure 4 shown, the end of the first segment 32 of the fourth conductive step facing the second segment 33 of the fourth conductive step ( Figure 4 the right end shown), is aligned with the end of the first segment 32 of the third conductive step facing the second segment 33 of the third conductive step ( Figure 4 the right end shown). The end of the first segment 32 of the second conductive step facing the second segment 33 of the second conductive step ( Figure 4 the right end shown), is aligned with the end of the first segment 32 of the first conductive step facing the second segment 33 of the first conductive step. The first segments 32 of the fifth conductive step, the first segments 32 of the third conductive step, and the first segments 32 of the first conductive step form a first step, and the first step is used to externally connect the first bit lines 12 corresponding to the fifth conductive step, the first bit lines 12 corresponding to the third conductive step, and the first bit lines 12 corresponding to the first conductive step (for example, through Figure 4 the bit line plug 34 in).

[0100] The end of the second segment 33 of the fifth conductive step facing the first segment 32 of the fifth conductive step ( Figure 4 the left end shown), is aligned with the end of the second segment 33 of the fourth conductive step facing the first segment 32 of the fourth conductive step ( Figure 4 the left end shown). The end of the second segment 33 of the third conductive step facing the first segment 32 of the third conductive step ( Figure 4(the left end shown), aligned with one end of the second segment 33 of the second conductive step facing the first segment 32 of the second conductive step Figure 4 The second segment 33 of the fourth conductive step and the second segment 33 of the second conductive step form a second step for externally connecting the first bit line 12 opposite to the fourth conductive step and the first bit line 12 opposite to the second conductive step (e.g., through the bit line plug 34 in FIG. 4).

[0101] Based on the above implementation, in some examples, refer to Figure 5 The non-aligned end of the uppermost groove can also extend to the end of the corresponding conductive step 31.

[0102] In some other possible implementations, refer to Figure 6 Each conductive step 31 has a first end and a second end opposite to each other in the second direction. Among any three adjacent conductive steps 31 in the first direction, the first end of the middle conductive step 31 is opposite to the first end of one of the remaining two conductive steps 31, and the second end is opposite to the second end of the other of the remaining two conductive steps 31, so as to form a stepped structure 30, that is, both ends of the conductive step 31 form a stepped structure 30 to reduce the difference in signal transmission resistance.

[0103] Exemplarily, there are five conductive steps 31, and for the convenience of description, these five conductive steps 31 are sequentially defined as the first conductive step, the second conductive step, the third conductive step, the fourth conductive step, and the fifth conductive step. Among them, the first conductive step is located at the uppermost, and the fifth conductive step is located at the lowermost.

[0104] The first end of the fifth conductive step is aligned with the first end of the fourth conductive step, and the second end of the fifth conductive step protrudes from the second end of the fourth conductive step. The second end of the fourth conductive step is aligned with the second end of the third conductive step, and the first end of the fourth conductive step protrudes from the first end of the second conductive step. The first end of the third conductive step is aligned with the first end of the second conductive step, and the second end of the third conductive step protrudes from the second end of the second conductive step. The second end of the second conductive step is aligned with the second end of the first conductive step, and the first end of the second conductive step protrudes from the first end of the first conductive step.

[0105] The first end of the fourth conductive step and the first end of the second conductive step form a first step, and the first step is used to externally connect the first bit line 12 corresponding to the fourth conductive step and the first bit line 12 corresponding to the second conductive step. The second end of the fifth conductive step, the second end of the third conductive step, and the second end of the first conductive step form a second step, and the second step is used to externally connect the first bit line 12 corresponding to the fifth conductive step, the first bit line 12 corresponding to the third conductive step, and the first bit line 12 corresponding to the first conductive step.

[0106] In some other possible implementation manners, each conductive step 31 has a first end and a second end opposite to each other in the second direction. Along the first direction, among two adjacent conductive steps 31, the first end of the lower conductive step 31 protrudes from the first end of the upper conductive step 31, and the second end of the lower conductive step 31 protrudes from the second end of the upper conductive step 31. The first ends of the conductive steps 31 in odd rows form a first step, and the second ends of the conductive steps 31 in even rows form a second step to form a stepped structure 30.

[0107] In summary, the memory in the embodiments of the present application includes a plurality of bit line function groups 10, a plurality of memory cells 20, and a stepped structure 30. The plurality of bit line function groups 10 are arranged at intervals in the first direction. Each bit line function group 10 includes a first bit line structure 11, a plurality of second bit line structures 14, and a plurality of selection transistors 17. Among them, the first bit line structure 11 includes a first isolation layer 13 and a first bit line 12. The first isolation layer 13 extends in the second direction, and the first bit line 12 circumferentially surrounds the first isolation layer 13. A plurality of second bit line structures 14 are arranged on the first side of the first bit line 12 in the third direction, and the plurality of second bit line structures 14 are arranged at intervals in the second direction. Each second bit line structure 14 is coupled to the first bit line structure 11 through a selection transistor 17. A stepped structure 30 is arranged on the second side of the first bit line 12 in the third direction, and the plurality of conductive steps 31 of the stepped structure 30 are respectively coupled to the corresponding first bit lines 12. By arranging the stepped structure 30 and the second bit line structure 14 on both sides of the first bit line structure 11, and the first bit line structure 11 adopts a structure in which the first bit line 12 surrounds the first isolation layer 13, when manufacturing the stepped structure 30, the first isolation layer 13 can block, avoiding the disconnection of a part of the first bit line 12 on the side of the first isolation layer 13 close to the second bit line structure 14, ensuring the consistency of this part of the first bit line 12, thereby ensuring the connection performance with the second bit line structure 14 and improving the performance of the memory.

[0108] An embodiment of the present application further provides an electronic device, which includes a memory and a processor coupled to the memory. The memory may refer to the above, and the processor may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0109] The electronic device in the embodiment of the present application includes the above-mentioned memory, and thus has at least the advantages that the partial first bit lines 12 close to the side of the second bit line structure 14 are not easily broken and the storage performance is good. For the specific effects, refer to the above, and details are not described herein again.

[0110] Refer to Figure 7 , an embodiment of the present application provides a method for manufacturing a memory, and the manufacturing method specifically includes the following steps:

[0111] Step S100: Form a stacked structure on a substrate, and the stacked structure includes a first dielectric layer and a second dielectric layer alternately arranged in a first direction in sequence.

[0112] Refer to Figure 8 and Figure 9 , the substrate 40 may be a silicon substrate, a germanium substrate, a silicon carbide substrate, a silicon germanium substrate, a Germanium on Insulator (GOI) substrate, or a Silicon on Insulator (SOI) substrate, etc. The stacked structure 50 is formed on the substrate 40, and it includes a first dielectric layer 51 and a second dielectric layer 52 alternately arranged in a first direction in sequence. The first direction is Figure 8 the Z direction shown, and in some examples, the second dielectric layer 52 is disposed on the substrate 40, the material of the second dielectric layer 52 may be an oxide, such as silicon oxide, and the material of the first dielectric layer 51 may be a nitride, such as silicon nitride or silicon oxynitride.

[0113] Step S200: Remove a part of the stacked structure to form a first trench and a plurality of second trenches. The first trench extends in a second direction, and the plurality of second trenches are located on a first side of the first trench in a third direction and are arranged at intervals along the second direction. The second direction and the third direction intersect with the first direction pairwise.

[0114] Refer to Figures 10 to 12, remove part of the stacked structure 50 to form a first groove 53 and a plurality of second grooves 54 within the stacked structure 50. The first groove 53 and the plurality of second grooves 54 expose the substrate 40. For example, the first groove 53 and the plurality of second grooves 54 penetrate the stacked structure 50, and the bottom of the groove is located within the substrate 40. The first groove 53 extends in a second direction, which intersects the first direction, for example, is perpendicular. A plurality of second grooves 54 are formed on the first side of the first groove 53 in a third direction.

[0115] The plurality of second grooves 54 all extend in the third direction and are arranged at intervals in the second direction. The third direction intersects both the second direction and the first direction, that is, the third direction, the second direction, and the first direction intersect pairwise, for example, are pairwise perpendicular. The second direction is as Figure 12 shown in the X direction, and the third direction is as Figure 12 shown in the Y direction.

[0116] The plurality of second grooves 54 and the first groove 53 can be formed simultaneously by an etching process. As shown in Figure 11 and Figure 12 , a first mask layer 71 is formed on the stacked structure 50. The first mask layer 71 has a preset pattern. Using the first mask layer 71 as a mask, the exposed stacked structure 50 is etched away to form the second groove 54 and the first groove 53. Then, the remaining first mask layer 71 is removed.

[0117] Step S300: Remove part of the first dielectric layer exposed in the first groove and the second groove to form a plurality of first receiving grooves communicating with the first groove and a plurality of second receiving grooves communicating with the second groove.

[0118] Referring to Figure 13 and Figure 14 , remove part of the first dielectric layer 51 exposed in the first groove 53 to form a plurality of first receiving grooves 55. The plurality of first receiving grooves 55 circumferentially surround the first groove 53 entirely and communicate with the first groove 53. The plurality of first receiving grooves 55 are spaced apart from each other in the first direction. And remove part of the second dielectric layer 52 exposed in the second groove 54 to form a plurality of second receiving grooves 56. The plurality of second receiving grooves 56 circumferentially surround the second groove 54 entirely and communicate with the second groove 54. The plurality of second receiving grooves 56 are spaced apart from each other in the first direction. The second receiving grooves 56 and the first receiving grooves 55 can be formed synchronously.

[0119] Step S400: Form a first bit line structure in the first groove and the first receiving groove, form a second bit line structure in the second groove and the second receiving groove, and form a stepped structure 30; the first bit line structure includes a first isolation layer and a first bit line circumferentially surrounding the first isolation layer. The first bit line is correspondingly located in the first receiving groove. The stepped structure 30 is located on the second side of the first bit line in the third direction. The stepped structure 30 is located on the second side of the first bit line in the third direction.

[0120] Refer to Figure 15 and Figure 16 as well as Figure 1 In the first trench 53 and the first receiving groove 55, a first bit line structure 11 is formed. The first bit line structure 11 includes a first isolation layer 13 and a first bit line 12. The first isolation layer 13 extends in the second direction. The first bit line 12 circumferentially surrounds the first isolation layer 13. For example, the first bit line 12 circumferentially surrounds the first isolation layer 13 entirely. The first isolation layer 13 is an integral body in the first direction. The first bit lines 12 are correspondingly located in the first receiving grooves 55, and the first bit lines 12 are spaced apart from each other in the first direction.

[0121] In some possible examples, the first bit line 12 fills the first receiving groove 55, that is, the first bit line 12 is in a closed loop shape, and its inner surface is aligned with the side wall of the first trench 53. The first isolation layer 13 is correspondingly filled in the first trench 53. In some other possible examples, the first bit line 12 fills the part of the first receiving groove 55 away from the first trench 53, that is, the first bit line 12 is filled at the bottom of the first receiving groove 55. The first isolation layer 13 is filled in the first trench 53 and in a part of the first receiving groove 55 adjacent to the first trench 53. The first bit line 12 and a part of the first isolation layer 13 fill the first trench 53. In still some other possible examples, the first bit line 12 fills the first receiving groove 55 and protrudes from the first receiving groove 55, that is, the first bit line 12 extends into the first trench 53, and the first isolation layer 13 fills the remaining first trench 53.

[0122] The stepped structure 30 is located on the second side of the first bit line 12 in the third direction, that is, the stepped structure 30 and a plurality of second bit line structures 14 are respectively located on both sides of the first bit line 12. The stepped structure 30 includes a plurality of conductive steps 31. The plurality of conductive steps 31 are arranged at intervals in the first direction and are respectively coupled to the corresponding first bit lines 12 to externally connect the first bit lines 12. Each conductive step 31 is arranged on the same layer as the second dielectric layer 52.

[0123] In summary, in the method for manufacturing a memory in the embodiments of the present application, a stacked structure 50 is formed on a substrate 40, and a part of the stacked structure 50 is removed to form a first trench 53 and a plurality of second trenches 54. The plurality of second trenches 54 are located on a first side of the first trench 53 in a third direction and are arranged at intervals along a second direction. A part of the first dielectric layer 51 exposed in the first trench 53 and the second trenches 54 is removed to form a plurality of first receiving grooves 55 communicating with the first trench 53 and a plurality of second receiving grooves 56 communicating with the second trenches 54. A first bit line structure 11 is formed in the first trench 53 and the first receiving grooves 55, a second bit line structure 14 is formed in the second trenches 54 and the second receiving grooves 56, and a stepped structure 30 is formed. The first bit line structure 11 includes a first isolation layer 13 and a first bit line 12 circumferentially surrounding the first isolation layer 13. The first bit line 12 is correspondingly located in the first receiving grooves 55. The stepped structure 30 is located on a second side of the first bit line 12 in the third direction and includes a plurality of conductive steps 31, and the plurality of conductive steps 31 are respectively coupled to the corresponding first bit lines 12. By arranging the stepped structure 30 and the second bit line structure 14 on both sides of the first bit line structure 11, and the first bit line structure 11 adopts a structure in which the first bit line 12 surrounds the first isolation layer 13, when the stepped structure 30 is manufactured, the first isolation layer 13 can act as a barrier to prevent a part of the first bit line 12 on the side of the first isolation layer 13 close to the second bit line structure 14 from being open-circuited, ensuring the consistency of this part of the first bit line 12, thereby ensuring the connection performance with the second bit line structure 14 and improving the performance of the memory.

[0124] In some possible examples, forming the first bit line structure 11 in the first trench 53 and the first receiving grooves 55, forming the second bit line structure 14 in the second trenches 54 and the second receiving grooves 56, and forming the stepped structure 30 (step S400) includes:

[0125] Step S101: Deposit an initial conductive layer, and the initial conductive layer fills the first receiving grooves 55 and the second receiving grooves 56 and covers the side walls and the bottom wall of the first trench 53 and the side walls and the bottom wall of the second trench 54.

[0126] Deposit the initial conductive layer in the first receiving grooves 55, the second receiving grooves 56, the first trench 53, and the second trench 54. The initial conductive layer fills the first receiving grooves 55 and the second receiving grooves 56, covers the side walls and the bottom wall of the first trench 53, and covers the side walls and the bottom wall of the second trench 54, and does not fill the first trench 53 and the second trench 54.

[0127] Exemplarily, the initial conductive layer includes an initial first conductive layer and an initial second conductive layer. The initial first conductive layer covers the sidewalls and bottom wall of the first receiving groove 55, the sidewalls and bottom wall of the second receiving groove 56, the sidewalls and bottom wall of the first trench 53, and the sidewalls and bottom wall of the second trench 54. The initial second conductive layer covers the initial first conductive layer and fills the remaining first receiving groove 55 and second receiving groove 56. The material of the initial first conductive layer may be titanium nitride, and the material of the initial second conductive layer may be tungsten.

[0128] Step S102: Retain the initial conductive layer within the first receiving groove 55 and the second receiving groove 56, and remove the remaining initial conductive layer. The initial conductive layer within the first receiving groove 55 forms the first bit line 12.

[0129] Etch the initial conductive layer, retain the initial conductive layer within the first receiving groove 55 and the second receiving groove 56, and remove the remaining initial conductive layer to form the first bit line 12. There are multiple first bit lines 12, and they are located within the corresponding first receiving grooves 55. The multiple first bit lines 12 are isolated from each other along the first direction.

[0130] Step S103: Deposit the initial isolation layer. The initial isolation layer fills the remaining first trench 53 and the remaining second trench 54. The initial isolation layer within the first trench 53 forms the first isolation layer 13, and the initial conductive layer within the second filling groove and the initial isolation layer within the second trench 54 form the second bit line structure 14.

[0131] Deposit the initial isolation layer within the remaining first trench 53 and second trench 54 to fill the first trench 53 and the second trench 54. The initial isolation layer within the first trench 53 forms the first isolation layer 13, and the first isolation layer 13 is continuous along the first direction. The initial conductive layer within the second filling groove forms the second bit line 15. There are multiple second bit lines 15, and they are located within the corresponding second receiving grooves 56. The multiple second bit lines 15 are isolated from each other along the first direction. The initial isolation layer within the second trench 54 forms the second isolation layer 16, and the second isolation layer 16 is continuous along the first direction. The second isolation layer 16 and the second bit line 15 form the second bit line structure 14. That is, the second bit line structure 14 and the first bit line structure 11 can be formed synchronously, reducing the number of etching and deposition times and simplifying the manufacturing process.

[0132] Step S104: Form a stepped structure 30. The stepped structure 30 includes multiple conductive steps 31, and the multiple conductive steps 31 are respectively coupled to the corresponding first bit lines 12.

[0133] The stepped structure 30 and the plurality of second bit line structures 14 are respectively located on both sides of the first bit line 12 . The stepped structure 30 includes a plurality of conductive steps 31 . The plurality of conductive steps 31 are arranged at intervals along the first direction and are respectively coupled to the corresponding first bit lines 12 to externalize each first bit line 12 .

[0134] For some possible implementations, see Figures 17 to 24 , forming the stepped structure 30 (step S104) specifically includes:

[0135] Step S1041: Etching the first dielectric layer 51 and the second dielectric layer 52 on the side of the second bit line 15 away from the first bit line 12 to form a groove 91, wherein the groove 91 exposes each first bit line 12, and the two side walls opposite to each other along the second direction are both stepped, and the step surface of one side wall includes the surfaces of the odd-numbered second dielectric layers 52 except for the second dielectric layer 52 adjacent to the substrate 40 that are away from the substrate 40, and the step surface of the other side wall includes the surfaces of the even-numbered second dielectric layers 52 that are away from the substrate 40.

[0136] The groove 91 exposes a portion of each first bit line 12, and the two side walls of the groove 91 opposite to each other along the second direction are both stepped. The left side wall and the right side wall of the groove 91 are both stepped. The step surface of one of the two side walls of the groove 91 includes the surfaces of the second dielectric layers 52 of odd numbers other than the second dielectric layer 52 adjacent to the substrate 40 that are away from the substrate 40, and the step surface of the other of the two side walls of the groove 91 includes the surfaces of the second dielectric layers 52 of even numbers that are away from the substrate 40.

[0137] Illustratively, along the direction away from the substrate 40, the surfaces of the third second dielectric layer 52, ..., and the 2n+1th second dielectric layer 52 facing away from the substrate 40 form a step surface of one side wall of the groove 91, and the surfaces of the second second dielectric layer 52, ..., and the 2nth second dielectric layer 52 facing away from the substrate 40 form a step surface of the other side wall of the groove 91, where n is a positive integer greater than 1.

[0138] Among them, Figures 17 to 22 As shown, the groove 91 can be formed by the following process:

[0139] See also Figure 17 , a second mask layer 72 is formed on the stacked structure 50, wherein the second mask layer 72 includes a second side of the first bit line. Figure 18 , a portion of a second dielectric layer 52 and a first dielectric layer 51 on the second side of the first bit line 12 farthest from the substrate 40 is removed by etching, exposing the second dielectric layer 52 under the first dielectric layer 51 and a first bit line 12 farthest from the substrate 40, forming two step surfaces. Figure 19, a photoresist layer 73 is formed. The photoresist layer 73 has an opening that exposes parts of these two step surfaces. Refer to Figure 20 , using the photoresist layer 73 as a mask, etch downward to remove parts of the two second dielectric layers 52 and the corresponding two first dielectric layers 51, so that the original two step surfaces are transferred downward and two new step surfaces are formed. Refer to Figure 21 , expand the opening of the photoresist layer 73, and using the photoresist layer 73 with the expanded opening as a mask, continue to etch downward to remove parts of the two second dielectric layers 52 and the corresponding two first dielectric layers 51, transfer the original four step surfaces downward, and form two new step surfaces. Repeat the previous step until etching reaches one of the second dielectric layers 52 closest to the substrate 40, or until etching reaches the substrate 40, as Figure 22 shown.

[0140] Step S1042: Etch away the exposed part of the first dielectric layer 51 in the groove 91 to form a third receiving groove 92, and each first bit line 12 is correspondingly exposed in the third receiving groove 92.

[0141] Refer to Figure 23 , etch part of the side wall of the groove 91 to remove part of the first dielectric layer 51, and form a plurality of third receiving grooves 92 arranged at intervals along the first direction. Each first bit line 12 is correspondingly exposed in the third receiving groove 92. In some examples, during the formation of the groove 91, the exposed first bit line 12 may be etched until it is completely removed, even exposing the first isolation layer 13. The groove 91 and the third receiving groove 92 are located on one side of the first isolation layer 13. The first isolation layer 13 can act as a barrier layer to prevent the first bit lines 12 on the other side of the first isolation layer 13 from breaking, so as to ensure that each second bit line structure 14 is connected to the same structure, ensuring the reliability and consistency of the connection.

[0142] Step S1043: Form a conductive step 31. The conductive step 31 is filled in the third receiving groove 92 and is in corresponding contact with each first bit line 12. Each conductive step 31 forms a stepped structure 30.

[0143] Refer to Figure 23 and Figure 24 , deposit the conductive step 31 in the third receiving groove 92. Each conductive step 31 is arranged at intervals along the first direction and is in corresponding contact with each first bit line 12. The conductive step 31 can be formed by deposition and back-etching, and it can fill the third receiving groove 92. Each conductive step 31 forms a stepped structure 30 to realize the external connection of each first bit line 12.

[0144] Step S1044: Form a third isolation layer 35 in the groove 91. The third isolation layer 35 fills the groove.

[0145] Refer to Figure 24 andFigure 5 The third isolation layer 35 may include a nitride layer conformally covering the stepped structure 30 and an oxide layer filling the remaining grooves 91. A bit line plug 34 is formed in the third isolation layer 35, and the bit line plug 34 is in contact with each conductive step 31 correspondingly to achieve the external connection of the corresponding first bit line 12.

[0146] In some possible examples, refer to Figures 25 to 32 This manufacturing method further includes the following steps:

[0147] Step a: Etch the first dielectric layer 51 and the second dielectric layer 52 to form a first hole, a second hole, a third hole, and a fourth hole. The first hole is located between the first bit line 12 and the second bit line structure 14. The second holes are located on opposite sides of the second bit line structure 14 along the second direction. The third hole is located on the side away from the second bit line structure 14 of the second holes. The fourth hole is located on the first side of the first bit line 12 along the third direction. Along the second direction, the fourth hole is opposite to the first hole, and at least one fourth hole is provided between adjacent two first holes.

[0148] The first hole, the second holes, the third hole, and the fourth hole may penetrate through the first dielectric layer 51 and the second dielectric layer 52. Among them, the first hole is located on the first side of the first bit line 12 in the second direction, on the same side as the second bit line structure 14, and on the side of the second bit line structure 14 adjacent to the first bit line 12. A plurality of second holes are provided on opposite sides of the second bit line structure 14 along the second direction, and the plurality of second holes are spaced along the third direction. The third hole is located on the side away from the second bit line structure 14 of the second bit line structure 14. The fourth hole is on the same side as the first hole and is in a row with the first hole along the second direction. For example, the first hole and the fourth hole are evenly spaced as a whole.

[0149] With such an arrangement, the first hole, the second holes, the third hole, and the fourth hole are relatively evenly distributed, and the loading effect is reduced when etching to form the first hole, the second holes, the third hole, and the fourth hole. It can be understood that this step may be before step S200, and its sequence is not limited.

[0150] Step b: Form a selection transistor 17, an access transistor 21, a capacitor 22, and a filling pattern 18. The selection transistor 17 is located in the first hole and is coupled to the second bit line structure 14. The access transistor 21 is located in the second holes and is coupled to both the second bit line structure 14 and the first bit line 12. The capacitor 22 is located in the third hole and is coupled to the access transistor 21. The filling pattern 18 is located in the fourth hole.

[0151] Among them, the access transistor 21 and the selection transistor 17 are formed synchronously to simplify the manufacturing process. The material of the filling pattern 18 can be aluminum oxide. The access transistor and the selection transistor 17 can both include a gate 61, a gate dielectric layer 62 surrounding the gate 61, and an active layer 63 surrounding the gate dielectric layer 62. Among them, the gates 61 opposite to each other in the first direction are connected to form a word line, that is, the word line extends in the first direction. The gate dielectric layers 62 opposite to each other in the first direction are connected to form an integral structure. The active layers 63 opposite to each other in the first direction are spaced apart from each other and are coupled to the corresponding second bit line structure 14. The material of the active layer 63 can be indium gallium zinc oxide to improve the migration performance of the active layer 63.

[0152] The capacitor 22 includes a first electrode, a capacitive dielectric layer surrounding the first electrode, and a second electrode surrounding the capacitive dielectric layer. The first electrodes opposite to each other in the first direction are connected to form an integral structure. The capacitive dielectric layers opposite to each other in the first direction are connected to form an integral structure. The second electrodes opposite to each other in the first direction are spaced apart from each other and are coupled to the corresponding active layer 63. Among them, a plurality of first electrodes are connected together to form a first electrode column. The first electrode column is also provided with a filling hole extending in the first direction, and the filling hole is filled with a capacitive plug 23.

[0153] It can be understood that the manufacturing sequence of the access transistor, the selection transistor 17, the capacitor 22, and the filling pattern 18 is not limited, and the manufacturing sequence with other structures is not limited either. For example, the manufacturing process of the access transistor and the selection transistor 17 can be carried out alternately with the manufacturing process of the first bit line structure 11 and the second bit line structure 14.

[0154] In some possible implementation manners, the first hole, the second hole, the third hole, and the fourth hole are formed synchronously. After the first hole, the second hole, the third hole, and the fourth hole are formed, a filling material is formed in the first hole, the second hole, the third hole, and the fourth hole. The filling material located in the fourth hole forms the filling pattern 18.

[0155] In some possible implementation manners, refer to Figures 25 to 29 , the capacitor 22 can be manufactured through the following process:

[0156] Refer to Figure 25 , remove the filling material in the third hole 81 to expose the third hole 81. Then, laterally etch the first dielectric layer 51 exposed in the third hole 81 to form a fourth receiving groove 93 to expand the third hole 81. Refer to Figure 26 , form an initial electrode layer 82 on the side wall of the fourth receiving groove 93, as well as on the side wall and the bottom wall of the third hole 81, and form a third dielectric layer 83 covering the initial electrode layer 82. The initial electrode layer 82 does not fill the fourth receiving groove 93, and the third dielectric layer 83 fills the fourth receiving groove 93. Refer to Figure 26, remove the third dielectric layer 83 outside the fourth receiving groove 93 to expose a part of the initial electrode layer 82. Remove the exposed initial electrode layer 82 to form a plurality of second electrodes 84 arranged at intervals, and then remove the remaining third dielectric layer 83. Refer to Figure 28 , form a capacitive dielectric layer 85 in the third hole 81 and the fourth receiving groove 93. The capacitive dielectric layer 85 covers the second electrode 84, and then form a first electrode 86 in the remaining third hole 81 and the fourth receiving groove 93.

[0157] In some possible implementation manners, refer to Figures 30 to 32 , the selection transistor 17 can be specifically fabricated through the following process:

[0158] Refer to Figure 30 , remove the filling pattern in the third hole 81 to expose the first hole 87. Then, laterally etch the first dielectric layer 51 exposed in the first hole 87 to form a fifth receiving groove 94. The fifth receiving groove 94 exposes the sidewalls of the first bit line 12 and the second bit line 15. Refer to Figure 31 , form an initial active layer 88 on the sidewalls of the fifth receiving groove 94, and the sidewalls and bottom wall of the first hole 87. The initial active layer 88 fills the fifth receiving groove 94. Then, refer to Figure 32 , etch and remove the initial active layer 88 on the sidewall of the second dielectric layer 52, and retain the initial active layer 88 in the fifth receiving groove 94 to form a plurality of active layers 63. Then, form a gate dielectric layer 62 conformally covering the active layer 63 in the first hole 87, and form a gate electrode 61 (i.e., word line) in the remaining first hole 87.

[0159] The fabrication of the access transistor 21 can refer to the selection transistor 17. During the fabrication process of the access transistor 21, the sidewalls of the corresponding second bit line 15 and the second electrode 84 of the capacitor will be exposed. Other fabrication processes are similar to those of the selection transistor 17 and will not be elaborated here.

[0160] In this specification, the embodiments or implementation manners are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. The descriptions with reference to terms such as "one implementation manner", "some implementation manners", "schematic implementation manner", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in connection with the implementation manner or example are included in at least one implementation manner or example of the present disclosure. In this specification, the schematic expressions of the above terms do not necessarily refer to the same implementation manner or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more implementation manners or examples.

[0161] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A memory, characterized in that, Including: A plurality of bit-line function groups, a plurality of memory cells, and a stepped structure arranged at intervals in a first direction; Each of the bit-line function groups includes: A first bit-line structure, the first bit-line structure including a first isolation layer extending in a second direction and a first bit-line circumferentially surrounding the first isolation layer; A plurality of second bit-line structures, the plurality of second bit-line structures being located on a first side of the first bit-line in a third direction and arranged at intervals in the second direction, the second direction and the third direction intersecting the first direction pairwise; A plurality of select transistors, the plurality of select transistors being located between the first bit-line structure and the plurality of second bit-line structures, and each of the second bit-lines being coupled to the first bit-line through one of the select transistors; The plurality of memory cells are respectively coupled to the corresponding second bit-lines, the stepped structure being located on a second side of the first bit-line in the third direction and including a plurality of conductive steps, the plurality of conductive steps being respectively coupled to the first bit-lines in the plurality of bit-line function groups.

2. The memory according to claim 1, characterized in that, The first bit-line in at least one of the bit-line function groups includes a first bit-line portion and a second bit-line portion, the first bit-line portion being in a non-closed ring shape, an opening of the non-closed ring shape being located on a second side of the first bit-line structure in the third direction, and the second bit-line portion being located at the opening of the non-closed ring shape, the second bit-line portion having the same material composition as the conductive step.

3. The memory according to claim 2, wherein The first bit-line in some of the bit-line function groups includes the first bit-line portion and the second bit-line portion, and the first bit-line in the remaining bit-line function groups is in a closed ring shape; The second bit-line structure includes a second isolation layer extending in the third direction and a second bit-line circumferentially surrounding the second isolation layer, the second isolation layer having the same material composition as the first isolation layer, and the first bit-line portion having the same material composition as the second bit-line.

4. The memory according to claim 3, characterized in that, The first isolation layers opposite to each other in the first direction are connected to form an integral structure, and the first bit-lines opposite to each other in the first direction are spaced apart from each other; The second isolation layers opposite to each other in the first direction are connected to form an integral structure, and the second bit-lines opposite to each other in the first direction are spaced apart from each other.

5. The memory according to any one of claims 1-4, characterized in that, The plurality of memory cells are arranged at intervals in the first direction, arranged at intervals in the second direction, and arranged at intervals in the third direction, and at least one side of each of the two opposite sides of each second bit-line structure in the second direction is correspondingly provided with a memory cell; Each of the memory cells includes an access transistor and a capacitor coupled thereto, the access transistor being correspondingly coupled to the second bit-line structure, and the capacitor being disposed on a side of the access transistor away from the corresponding second bit-line structure.

6. The memory according to claim 5, characterized in that, The memory further includes a plurality of filling patterns located on a first side of the first bit-line in the third direction, and in the second direction, the plurality of filling patterns are opposite to the plurality of select transistors, and at least one of the filling patterns is disposed between two adjacent select transistors.

7. The memory according to claim 5, wherein The selection transistor and the access transistor include a gate, a gate dielectric layer surrounding the gate, and an active layer surrounding the gate dielectric layer; The gates connected opposite to each other in the first direction form a word line, the gate dielectric layers connected opposite to each other in the first direction form an integral structure, the active layers connected opposite to each other in the first direction are spaced apart from each other, and are coupled to the corresponding second bit line structure; And / or, the capacitor includes a first electrode, a capacitive dielectric layer surrounding the first electrode, and a second electrode surrounding the capacitive dielectric layer; The first electrodes connected opposite to each other in the first direction form an integral structure, the capacitive dielectric layers connected opposite to each other in the first direction form an integral structure, the second electrodes connected opposite to each other in the first direction are spaced apart from each other, and are coupled to the corresponding active layer.

8. The memory according to any one of claims 1-4, characterized in that, Each of the conductive steps has a groove, the groove divides the corresponding conductive step into a first segment and a second segment spaced apart in the second direction, the grooves communicate with each other, and each groove has a first end and a second end opposite to each other in the second direction; Among any three adjacent grooves in the first direction, the first end of the groove in the middle is opposite to the first end of one of the remaining two grooves, and the second end is opposite to the second end of the other of the remaining two grooves, so that the first segments in every other row form a first step, the second segments in every other row form a second step, and the step surfaces of the first step and the second step are staggered in the first direction, and the first step and the second step form the stepped structure.

9. The memory according to any one of claims 1-4, characterized in that Each of the conductive steps has a first end and a second end opposite to each other in the second direction; Among any three adjacent conductive steps in the first direction, the first end of the conductive step in the middle is opposite to the first end of one of the remaining two conductive steps, and the second end is opposite to the second end of the other of the remaining two conductive steps, so that the first ends of the conductive steps in every other row form a first step, the second ends of the conductive steps in every other row form a second step, and the step surfaces of the first step and the second step are staggered in the first direction, and the first step and the second step form the stepped structure.

10. An electronic device, characterized in that, Comprising a memory according to any one of claims 1-9, and a processor coupled to the memory.

11. A method for manufacturing a memory, characterized in that, Comprising: Forming a stacked structure on a substrate, the stacked structure including a first dielectric layer and a second dielectric layer alternately arranged in a first direction in sequence; Removing a part of the stacked structure to form a first trench and a plurality of second trenches, the first trench extending in a second direction, the plurality of second trenches being located on a first side of the first trench in a third direction and spaced apart from each other in the second direction, the second direction and the third direction intersecting with the first direction in pairs; Removing a part of the first dielectric layer exposed in the first trench and the second trenches to form a plurality of first receiving grooves communicating with the first trench and a plurality of second receiving grooves communicating with the second trenches; A first bit line structure is formed in the first trench and the first receiving groove, a second bit line structure is formed in the second trench and the second receiving groove, and a stepped structure is formed; the first bit line structure includes a first isolation layer and a first bit line circumferentially surrounding the first isolation layer, the first bit line is correspondingly located in the first receiving groove, and the stepped structure is located on a second side of the first bit line in the third direction.

12. The manufacturing method according to claim 11, characterized in that, Forming a first bit line structure in the first trench and the first receiving groove, forming a second bit line structure in the second trench and the second receiving groove, and forming the stepped structure, including: Depositing an initial conductive layer, the initial conductive layer filling the first receiving groove and the second receiving groove, and covering the sidewalls and the bottom wall of the first trench, and the sidewalls and the bottom wall of the second trench; Retaining the initial conductive layer located in the first receiving groove and the second receiving groove, removing the remaining initial conductive layer, and the initial conductive layer located in the first receiving groove forms the first bit line; Depositing an initial isolation layer, the initial isolation layer filling the remaining first trench and the remaining second trench, the initial isolation layer located in the first trench forms the first isolation layer, and the initial conductive layer located in the second filling groove and the initial isolation layer located in the second trench form the second bit line structure; Forming the stepped structure, the stepped structure including a plurality of conductive steps, and the plurality of conductive steps are respectively coupled to the corresponding first bit line.

13. The manufacturing method according to claim 11 or 12, characterized in that, The manufacturing method further includes: Etching the first dielectric layer and the second dielectric layer to form a first hole, a second hole, a third hole, and a fourth hole; the first hole is located between the first bit line and the second bit line structure, the second hole is located on opposite sides of the second bit line structure along the second direction, the third hole is located on a side of the second hole away from the second bit line structure, the fourth hole is located on a first side of the first bit line in the third direction, along the second direction, the fourth hole is opposite to the first hole, and at least one fourth hole is provided between two adjacent first holes; Forming a select transistor, an access transistor, a capacitor, and a filling pattern, the select transistor is located in the first hole and is coupled to the second bit line structure, the access transistor is located in the second hole and is coupled to both the second bit line structure and the first bit line, the capacitor is located in the third hole and is coupled to the access transistor, and the filling pattern is located in the fourth hole.

14. The manufacturing method according to claim 13, characterized in that, The access transistor and the select transistor are formed synchronously.

15. The manufacturing method according to claim 11 or 12, characterized in that, Forming the stepped structure, including: Etching the first dielectric layer and the second dielectric layer on the side of the second bit line away from the first bit line to form a groove, wherein the groove exposes each first bit line, and two side walls opposite to each other along the second direction are both stepped, wherein a step surface of one side wall includes surfaces of the second dielectric layers of odd numbers other than the second dielectric layer adjacent to the substrate facing away from the substrate, and a step surface of the other side wall includes surfaces of the second dielectric layers of even numbers facing away from the substrate; Etching and removing a portion of the first dielectric layer exposed in the groove to form a third receiving groove, wherein each of the first bit lines is correspondingly exposed in the third receiving groove; forming a conductive step, wherein the conductive step is filled in the third receiving groove and contacts with each of the first bit lines correspondingly, and each of the conductive steps forms a step structure; A third isolation layer is formed in the groove, and the third isolation layer fills the groove.

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