Operation method and device of memory, equipment and storage medium
By using different incremental step pulse programming steps according to the threshold voltage distribution interval during the memory programming process, the problem of too long programming time caused by a fixed step is solved, and more efficient memory programming is achieved.
Patent Information
- Application Number
- CN202311811938.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-25
- Publication Date
- 2025-06-27
Smart Images
Figure CN120220769A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of storage technologies, and particularly to an operation method, device, equipment and storage medium of a memory. Background Art
[0002] In recent years, the field of semiconductor memories has received increasing attention. Semiconductor memories can be volatile or non-volatile. Non-volatile semiconductor storage devices can store data even when not powered, and thus are widely used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.
[0003] When studying the operation method of a memory, during memory programming, a two-stage programming method can be adopted. In the coarse programming stage, a rough threshold voltage distribution is formed. In the fine programming stage, the rough threshold voltage distribution is finely programmed. In the coarse programming stage, the ISPP (Increment Step Pulse Program) method is used for memory programming. According to a fixed ISPP step size, during the programming cycle, the pulse voltage is gradually increased to form a rough threshold voltage distribution.
[0004] In the above method, in the coarse programming stage, a fixed ISPP step size is adopted, lacking flexibility, which will lead to the problem of too long programming time. For example, when the interval between the threshold voltage distributions corresponding to two programming states is too large and the fixed ISPP step size is small, it will cause too many programming cycles and verification cycles, resulting in too long programming time. Summary of the Invention
[0005] The embodiments of the present application provide a programming operation method, device, equipment and storage medium of a storage unit. The technical solutions provided by the embodiments of the present application are as follows:
[0006] According to one aspect of the embodiments of the present application, an operation method of a memory is provided, and the method includes:
[0007] In a first programming stage, a first memory cell is programmed to a first programming state corresponding to a first threshold voltage distribution among N programming states, a second memory cell is programmed to a second programming state corresponding to a second threshold voltage distribution among the N programming states, and a third memory cell is programmed to a third programming state corresponding to a third threshold voltage distribution among the N programming states, where N is an integer greater than or equal to 3 and less than M, and M is an integer greater than or equal to 4; wherein, the first threshold voltage distribution, the second threshold voltage distribution, and the third threshold voltage distribution are sequentially and adjacently distributed, and a first interval between the first threshold voltage distribution and the second threshold voltage distribution is different from a second interval between the second threshold voltage distribution and the third threshold voltage distribution; in the first programming stage, after programming the first memory cell and before programming the second memory cell, a first incremental step pulse programming step size is used, and after programming the second memory cell in the first programming stage and before programming the third memory cell, a second incremental step pulse programming step size is used, and the first incremental step pulse programming step size is different from the second incremental step pulse programming step size;
[0008] In a second programming stage, the first memory cell, the second memory cell, and the third memory cell are respectively programmed to corresponding programming states among M programming states.
[0009] According to one aspect of the embodiments of the present application, a storage device is provided, the storage device includes:
[0010] A memory array including a plurality of memory cells; and
[0011] A peripheral circuit coupled to the memory array and configured to:
[0012] In a first programming stage, a first memory cell is programmed to a first programming state corresponding to a first threshold voltage distribution among N programming states, a second memory cell is programmed to a second programming state corresponding to a second threshold voltage distribution among the N programming states, and a third memory cell is programmed to a third programming state corresponding to a third threshold voltage distribution among the N programming states, where N is an integer greater than or equal to 3 and less than M, and M is an integer greater than or equal to 4; wherein, the first threshold voltage distribution, the second threshold voltage distribution, and the third threshold voltage distribution are adjacent to each other in sequence, and a first interval between the first threshold voltage distribution and the second threshold voltage distribution is different from a second interval between the second threshold voltage distribution and the third threshold voltage distribution; when programming the second memory cell after programming the first memory cell in the first programming stage, a first incremental step pulse programming step size is adopted, and when programming the third memory cell after programming the second memory cell in the first programming stage, a second incremental step pulse programming step size is adopted, and the first incremental step pulse programming step size is different from the second incremental step pulse programming step size;
[0013] In a second programming stage, the first memory cell, the second memory cell, and the third memory cell are respectively programmed to corresponding programming states among M programming states.
[0014] According to one aspect of the embodiments of the present application, a storage system is provided. The storage system includes a controller and the storage device described in the above technical solution. The controller is coupled to the storage device and is configured to control the storage device to execute the operation method of the above memory. According to one aspect of the embodiments of the present application, an electronic device is provided. The electronic device includes a host and a storage system coupled to the host. The storage system includes a controller and at least one storage device coupled to the controller. The controller controls the storage device to execute the operation method of the above memory.
[0015] According to one aspect of the embodiments of the present application, a computer-readable storage medium is provided. A computer program is stored in the computer-readable storage medium and is used to be executed by a storage device to implement the operation method of the above memory.
[0016] The technical solutions provided by the embodiments of the present application at least include the following beneficial effects:
[0017] For intervals of different threshold voltage distributions, different ISPP step sizes are adopted, avoiding the problem of a large number of programming cycles and verification cycles caused by using a fixed ISPP step size, and achieving the technical effect of shortening the programming time of the memory. Description of the Drawings
[0018] Figure 1 is a block diagram of a system with a storage device provided by an embodiment of the present application;
[0019] Figure 2 is a schematic diagram of a memory card provided by an embodiment of the present application;
[0020] Figure 3 is a schematic diagram of an SSD provided by an embodiment of the present application;
[0021] Figure 4 is a schematic diagram of an exemplary storage device including a peripheral circuit provided by an embodiment of the present application;
[0022] Figure 5 is a schematic diagram of a peripheral circuit provided by an embodiment of the present application;
[0023] Figure 6 is a flowchart of an operation method of a memory provided by an embodiment of the present application;
[0024] Figure 7 is a schematic diagram of a threshold voltage distribution of two - time programming of a QLC memory provided by an embodiment of the present application;
[0025] Figure 8 is a schematic diagram of a threshold voltage distribution of two - time programming of a QLC memory provided by another embodiment of the present application;
[0026] Figure 9 is a schematic diagram of a threshold voltage distribution of 6 - 16 programming of a QLC memory provided by an embodiment of the present application;
[0027] Figure 10 is a flowchart of a threshold voltage distribution of 6 - 16 programming of a QLC memory provided by an embodiment of the present application;
[0028] Figure 11 is a schematic diagram of a pulse voltage timing diagram provided by an embodiment of the present application;
[0029] Figure 12 is a block diagram of a structure of an electronic device provided by an embodiment of the present application. Detailed Embodiments
[0030] To make the objectives, technical solutions, and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.
[0031] Please refer to Figure 1, which shows a block diagram of a system with a storage device provided by an embodiment of the present application. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As Figure 1 shown, the system 100 can include a host 108 and a storage device 102, and the storage device 102 has one or more storage devices 104 and a controller 106. The host 108 can be a processor of the electronic device, for example, a central processing unit (CPU) or a system on chip (SoC), for example, an application processor (AP). The host 108 can be configured to send data to the storage device 104 or receive data from the storage device 104.
[0032] The storage device 104 can be any storage device disclosed in this application. As will be disclosed in detail below, the storage device 104 (e.g., a NAND flash storage device (e.g., a three-dimensional (3D) NAND flash storage device)). According to some embodiments, the controller 106 is coupled to the storage device 104 and the host 108 and is configured to control the storage device 104. The controller 106 can manage the data stored in the storage device 104 and communicate with the host 108. In some embodiments, the controller 106 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 106 is designed to operate in a high-duty-cycle environment, such as a Solid State Drive (SSD) or an embedded Multi-Media Card (eMMC), where the SSD or eMMC serves as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., and enterprise storage arrays. The controller 106 can be configured to control the operations of the storage device 104, such as read, erase, and program operations. The controller 106 can also be configured to manage various functions regarding the data stored in or to be stored in the storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 106 is also configured to process the Error Correction Code (ECC) regarding the data read from or written to the storage device 104. The controller 106 can also perform any other suitable functions, such as formatting the storage device 104. The controller 106 can communicate with external devices (e.g., the host 108) according to a specific communication protocol.For example, the controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC (Multi-Media Card) protocol, Peripheral Component Interconnect (PCI) protocol, Peripheral Component Interconnect Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.
[0033] The controller 106 and one or more storage devices 104 can be integrated into various types of storage devices. For example, they can be included in the same package (such as Universal Flash Storage (UFS) package or eMMC package). That is, the storage device 102 can be implemented and packaged into different types of terminal electronic products. In Figure 2 In one example as shown in Figure 1 , the controller 106 and a single storage device 104 can be integrated into the memory card 202. The memory card 202 can include PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, Memory Stick, Multi-Media Card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (such as
[0034] In another example as shown in Figure 3 , the controller 106 and multiple storage devices 104 can be integrated into the SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (such as Figure 1 the host 108 in
[0035] Figure 4 Schematic of a storage device 400 including a peripheral circuit provided by an embodiment of the present application is shown. The storage device 400 may be an example of the storage device 104 in Figure 1 . The storage device 400 may include a storage array 401 and a peripheral circuit 402 coupled to the storage array 401. The storage array 401 may be an array of NAND flash (Not AND Flash, NAND Flash) cells, where the storage cells 406 are provided in the form of an array of NAND storage strings 408 each vertically extending above a substrate (not shown). In some embodiments, each NAND storage string 408 includes a plurality of storage cells 406 coupled in series and vertically stacked. Each storage cell 406 may hold a continuous analog value, such as a voltage or a charge, depending on the number of electrons trapped within the region of the storage cell 406. Each storage cell 406 may be a floating-gate type storage cell including a floating-gate transistor, or a charge-trapping type storage cell including a charge-trapping transistor.
[0036] In some embodiments, each storage cell 406 is a single-level cell (SLC) having two possible storage states (levels) and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first threshold voltage range, while a second storage state "1" may correspond to a second threshold voltage range. In some embodiments, each storage cell 406 is an xLC capable of storing more than a single bit of data in more than or equal to four storage states (levels), such as a multi-level cell (MLC), a trinary-level cell (TLC), a quad-level cell (QLC), etc.). Each storage cell may be configured to store x bits of data in one of 2 x storage states, where x is an integer greater than 1. The 2 x storage states include an erased state and 2 x -1 programmed states. In one example, each QLC storage cell may be configured to store 4 bits of data in one of 16 storage states (P0 - P 15 ), where P0 is the erased state and P1 - P 15 are 15 programmed states respectively.
[0037] As Figure 4As shown, each NAND memory string 408 may also include a Source Selection Gate (SSG) transistor 410 at its source extreme and a Drain Selection Gate (DSG) transistor 412 at its drain extreme. The SSG transistor 410 and the DSG transistor 412 may be configured to activate a selected NAND memory string 408 (a column of the array) during read and program operations. As Figure 4 As shown, the NAND memory strings 408 may be organized into a plurality of memory blocks 404. In some embodiments, the sources of the NAND memory strings 408 in the same memory block 404 are coupled through the same Source Line (SL) 414 (e.g., a common SL). In other words, according to some embodiments, all the NAND memory strings 408 in the same memory block 404 have an Array Common Source (ACS). According to some embodiments, the drain of each NAND memory string 408 is coupled to a corresponding bit line 416, and data can be read from or written to the corresponding bit line via an output bus (not shown). In some embodiments, each NAND memory string 408 is configured to be selected or deselected by applying a select voltage or a deselect voltage to the gate of the corresponding DSG transistor 412 via one or more DSG lines 413 and / or by applying a select voltage or a deselect voltage to the gate of the corresponding SSG transistor 410 via one or more SSG lines 415.
[0038] As Figure 4 As shown, each memory block may have, for example, a common source line 414 coupled to the ACS. In some embodiments, each memory block 404 is a basic data unit for an erase operation, i.e., all the memory cells 406 on the same memory block 404 are erased simultaneously. To erase the memory cells 406 in a selected memory block 404, the source line 414 coupled to the selected memory block 404 and the unselected memory blocks 404 in the same plane as the selected memory block 404 may be biased with an erase voltage (Vers) (e.g., a high positive bias (e.g., 20V or greater)). The memory cells of adjacent NAND memory strings may be coupled through a Word Line (WL), and which row of memory cells is affected by read and program operations can be selected through the word line.
[0039] As Figure 4 As shown, the memory array 401 may include an array of memory cells 406 in multiple rows and multiple columns in each memory block 404. The multiple rows of memory cells 406 may be coupled to different word lines 418 respectively, and the multiple columns of memory cells 406 may be coupled to different bit lines 416 respectively. The peripheral circuit 402 may be coupled to the memory array 401 through the bit lines 416 and the word lines 418.
[0040] Please refer to Figure 4 , the peripheral circuit 402 can be coupled to the memory array 401 through bit lines 416, word lines 418, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 can include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory array 401 by applying voltage signals and / or current signals to each target memory cell 406 and sensing voltage signals and / or current signals from each target memory cell 406 via bit lines 316, word lines 318, source lines 414, SSG lines 415, and DSG lines 413. The peripheral circuit 402 can include various types of peripheral circuits formed using Metal-Oxide-Semiconductor (MOS) technology.
[0041] For example, Figure 5 FIG. shows a schematic diagram of a peripheral circuit provided by an embodiment of the present application. The peripheral circuit 502 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in Figure 5 may also be included.
[0042] The page buffer / sense amplifier 504 can be configured to read data from the memory array 401 and program (write) data to the memory array 401 according to control signals from the control logic unit 512. In one example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that data has been correctly programmed into the memory cells 406 coupled to the selected word line 418. In another example, the page buffer / sense amplifier 504 can also sense a low-power signal representing the data bits stored in the memory cells 406 from the bit lines 416 and amplify a small voltage swing to an identifiable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic unit 512 and select one or more NAND memory strings 408 by applying bit line voltages generated from the voltage generator 510.
[0043] The row decoder / word line driver 508 may be configured to be controlled by the control logic unit 512, and to select / deselect the memory blocks 404 of the memory array 401 and to select / deselect the word lines 418 of the memory blocks 404. The row decoder / word line driver 508 may also be configured to drive the word lines 418 with word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the SSG lines 415 and the DSG lines 413. As described in detail below, the row decoder / word line driver 508 is configured to perform an erase operation on the memory cells 406 coupled to the selected word line(s) 418. The voltage generator 510 may be configured to be controlled by the control logic unit 512, and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory array 401.
[0044] The control logic unit 512 may be coupled to each of the peripheral circuits described above, and is configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic unit 512, and includes status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic unit 512, and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 512, and to buffer status information received from the control logic unit 512 and relay it to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and acts as a data I / O (Input / Output) interface and data buffer to buffer data and relay it to or from the memory array 401.
[0045] As Figure 4 shown, the memory cells in the memory string 408 share a set of word lines (WL) with the memory cells in other memory strings. Assuming that each memory string includes m memory cells, the 3D memory may include m WLs: WL1 to WL m, m is an integer greater than 1. Each WL is connected to each memory cell located in the same layer (i.e., having the same height relative to the bearing surface of the substrate). Alternatively, it can be understood that the control gates of each memory cell located in the same layer, and the gate connection lines between the control gates form a WL. The memory cells in each memory string are also connected to the memory cells in other memory strings through the word line (WL). In a 3D memory, each memory cell connected to the same word line is called a page, and all memory strings sharing a set of word lines are called a block.
[0046] The storage device can store more than one bit of information into each memory cell having multiple storage states to increase the storage capacity and reduce the cost per bit.
[0047] In some embodiments, data can be written into memories such as MLC, TLC, QLC, etc. When writing data into a memory cell, a programming voltage can be applied to the control gate of the floating-gate field-effect transistor to cause electrons in the channel of the floating-gate field-effect transistor to tunnel to the floating gate. By controlling the magnitude of this programming voltage, the number of electrons tunneling to the floating gate can be controlled, and thus the magnitude of the threshold voltage of this floating-gate field-effect transistor can be controlled. Generally, the higher the amount of charge stored in the floating gate, the higher the threshold voltage of the floating-gate field-effect transistor. It can be understood that when the threshold voltages of the floating-gate field-effect transistors are different, the voltages required to be applied to the control gates of the floating-gate field-effect transistors to turn them on are different. Therefore, the magnitude of the threshold voltage of the floating-gate field-effect transistor can reflect the content of the data it stores.
[0048] Please refer to Figure 6 , which shows a flowchart of an operation method of a memory provided in an embodiment of the present application. The execution subject of each step of this method can be Figure 1 the storage device 102 in Figure 1 Furthermore, the execution subject of each step of this method can be
[0049] Step 610, in the first programming stage, program the first memory cell into the first programming state corresponding to the first threshold voltage distribution among N programming states, program the second memory cell into the second programming state corresponding to the second threshold voltage distribution among N programming states, and program the third memory cell into the third programming state corresponding to the third threshold voltage distribution among N programming states, where N is an integer greater than or equal to 3 and less than M, and M is an integer greater than or equal to 4; wherein, the first threshold voltage distribution, the second threshold voltage distribution, and the third threshold voltage distribution are sequentially and adjacently distributed, and a first interval between the first threshold voltage distribution and the second threshold voltage distribution is different from a second interval between the second threshold voltage distribution and the third threshold voltage distribution; in the first programming stage, after programming the first memory cell and before programming the second memory cell, use a first incremental step pulse programming step size, and after programming the second memory cell in the first programming stage and before programming the third memory cell, use a second incremental step pulse programming step size, and the first incremental step pulse programming step size is different from the second incremental step pulse programming step size.
[0050] A memory cell refers to the basic storage component that constitutes a memory and is the basic unit for storing data information. According to the number of data bits stored in a memory cell, memory cells can be classified into different types such as SLC memory cells, MLC memory cells, TLC memory cells, and QLC memory cells. For each type of memory cell, when it is programmed into different programming states, it will have different storage states, and each storage state stores x bits of data, where x is an integer greater than 1. When a memory cell stores x bits of data, it corresponds to M different storage states, where M = 2 x , and each memory cell is configured to store x bits of data in one of 2 x storage states.
[0051] Exemplarily, each SLC memory cell can store 1 bit of data, which is 0 to 1. Each MLC memory cell can store 2 bits of data, which is 00 to 11. Each TLC memory cell can store 3 bits of data, which is 000 to 111. Each QLC memory cell can store 4 bits of data, which is 0000 to 1111.
[0052] The first programming stage refers to the rough programming stage, in which the memory is initially programmed. The process of programming the memory refers to the process of writing data into the memory. When performing a programming operation on the memory, a two-stage programming method can be used, namely rough programming and fine programming, also called the first programming stage and the second programming stage. In this application, a QLC memory is taken as an example to introduce two-stage programming. In the rough programming stage, the QLC memory is programmed into N programming states, where N is an integer greater than 3 and less than or equal to 16. Each programming state corresponds to a threshold voltage distribution. Exemplarily, as Figure 6 shown, the threshold voltage distribution corresponding to the programming state P0 is as shown by the mark 61. In the fine programming stage, based on the N programming states programmed in the rough programming stage, the QLC memory is programmed into 16 programming states. This method is called N-16 programming.
[0053] Exemplarily, please refer to Figure 7 , which shows a schematic diagram of the threshold voltage distribution of two programming operations of a QLC memory provided by an embodiment of this application. In the first programming stage, the QLC memory can be programmed into 3 programming states, namely Figure 7 P0, P1, and P2 in the first programming stage of
[0054] , where P0 refers to the first programming state, P1 refers to the second programming state, and P2 refers to the third programming state. The first programming state P0 corresponds to the first threshold voltage distribution 71, the second programming state P1 corresponds to the second threshold voltage distribution 72, and the third programming state P2 corresponds to the third threshold voltage distribution 73.
[0054] In the second programming stage, the above 3 programming states are further programmed into 16 fine programming states, that is Figure 7 the programming states P0 - P 15 corresponding to the fine programming in
[0055] . This programming method can be called 3-16 programming.
[0055] When studying the rough programming method of the memory, optionally, the ISPP method can be adopted. During the memory programming process, when applying a pulse voltage to the memory cell, the voltage is not applied in place at one time, but is incrementally increased step by step until the voltage reaches the programming requirement. This incremental step pulse programming step size is also called the ISPP step size, which refers to the voltage difference between adjacent pulse voltages. Assuming that the pulse voltage applied in the t-th programming cycle is V t , and the pulse voltage applied in the (t + 1)-th time is V t+1 , the ISPP step size is ΔV = V t+1 - V t .
[0056] Please refer to Figure 7 and Figure 8, in the first programming stage, the target state of the first memory cell is the first programmed state, the target state of the second memory cell is the second programmed state, and the target state of the third memory cell is the third programmed state, where the target state refers to the final programmed state that the memory cell is expected to reach in the first programming stage. The programming process of the memory includes a programming stage and a verification stage. In the programming stage, the pulse voltage needs to be gradually increased to ensure that the memory cell reaches the target state; in the verification stage, the current voltage of the memory cell needs to be read out and compared with the target pulse voltage to ensure successful programming.
[0057] In the programming stage, a pulse voltage is applied to the first memory cell, the second memory cell, and the third memory cell whose target states are the first programmed state P0, the second programmed state P1, and the third programmed state P2, respectively. In the verification stage, it is verified whether the first memory cell, the second memory cell, and the third memory cell reach their target pulse voltages respectively after applying the current pulse voltage. For the memory cells that have reached the target pulse voltage, no subsequent programming is performed. For the memory cells that have not reached the target pulse voltage, subsequent programming is still required.
[0058] Specifically, in the first programming cycle, an initial voltage V1 is applied to the first memory cell, the second memory cell, and the third memory cell whose target states are the first programmed state P0, the second programmed state P1, and the third programmed state P2, respectively.
[0059] In the verification stage, it is verified whether the first memory cell whose target state is the first programmed state P0 reaches the target pulse voltage after applying the initial voltage V1. For the first memory cell that has reached the target pulse voltage, no subsequent programming is performed. For the first memory cell that has not reached the target pulse voltage, subsequent programming is still required.
[0060] In the second programming cycle, an incremental step pulse programming step ΔV0 is added on the basis of the initial voltage V1. A pulse voltage V2 is applied to the first memory cell that has not reached the target pulse voltage, the second memory cell whose target state is the second programmed state P1, and the third memory cell whose target state is the third programmed state P2, where V2 = V1 + ΔV0. Then it is verified whether the above-mentioned first memory cell reaches the target pulse voltage after applying the pulse voltage V2. For the first memory cell that has not reached the target pulse voltage, the pulse voltage needs to be continuously applied until the first memory cell whose target state is the first programmed state P0 passes the verification.
[0061] In some embodiments, the first memory cell can be verified in the nth programming cycle (n is a positive integer). This means that it is not necessarily required to verify the first memory cell starting from the first programming cycle. By this strategy, the number of verification times can be reduced and the programming time can be shortened.
[0062] In some embodiments, during the above verification phase, in the t-th programming cycle (where t is a positive integer), it is also possible to verify whether a second storage cell with a target state of the second programming state P1 reaches a target pulse voltage after applying an initial voltage V t where V t refers to the pulse voltage applied in the t-th programming cycle. For the second storage cells that have reached the target pulse voltage, no subsequent programming is performed. For the second storage cells that have not reached the target pulse voltage, subsequent programming is still required.
[0063] In some embodiments, during the above verification phase, in the m-th programming cycle (where m is a positive integer), it is also possible to verify whether a third storage cell with a target state of the third programming state P2 reaches a target pulse voltage after applying a pulse voltage V m where V m refers to the pulse voltage applied in the m-th programming cycle. For the third storage cells that have reached the target pulse voltage, no subsequent programming is performed. For the third storage cells that have not reached the target pulse voltage, subsequent programming is still required.
[0064] Optionally, the programming cycle round at which the first storage cell starts verification is earlier than that of the second storage cell, and the programming cycle round at which the second storage cell starts verification is earlier than that of the third storage cell, i.e., n < t < m.
[0065] Assume that after the T1-th programming cycle, the first storage cells all pass the verification. Apply a pulse voltage to the storage cells with a target state of the second programming state P1 and the third storage cells with a target state of the third programming state P2 where ΔV1 refers to the first incremental step pulse programming step corresponding to the first interval in Figure 7 or Figure 8 and ΔV1 has a different magnitude from ΔV0. During the verification phase, verify whether a second storage cell with a target state of P1 reaches a target pulse voltage after applying this pulse voltage For the second storage cells that have reached the target pulse voltage, no subsequent programming is performed. For the second storage cells that have not reached the target pulse voltage, subsequent programming is still required.
[0066] In the (T1 + 2)-th programming cycle, apply a pulse voltage to the second storage cells that have not reached the target pulse voltage and the third storage cells with a target state of the third programming state P2 where Then verify the above-mentioned second storage cells after applying the pulse voltage After that, it is checked whether the target pulse voltage is reached for all. For the second memory cells that have not reached the target pulse voltage, the pulse voltage needs to be continuously applied until all the second memory cells with the target state being the second programming state P1 pass the verification.
[0067] In some embodiments, in the above verification stage, in the i-th programming cycle (i is a positive integer greater than or equal to T1 + 1), it is also possible to verify whether the third memory cells with the target state being the third programming state P2 reach the target pulse voltage after applying the pulse voltage V i where V i refers to the i-th programming cycle. For the third memory cells that have reached the target pulse voltage, no subsequent programming is performed. For the third memory cells that have not reached the target pulse voltage, subsequent programming is still required.
[0068] Assume that after the T2-th programming cycle, all the second memory cells pass the verification. Apply the pulse voltage to the memory cells with the target state being the third programming state P2 wherein, ΔV2 refers to the second incremental step pulse programming step corresponding to Figure 7 or Figure 8 the second interval in. In the verification stage, verify whether the third memory cells with the target state being the third programming state P2 reach the target pulse voltage after applying this pulse voltage For the third memory cells that have reached the target pulse voltage, no subsequent programming is performed. For the third memory cells that have not reached the target pulse voltage, subsequent programming is still required.
[0069] In the (T2 + 2)-th programming cycle, apply the pulse voltage to the third memory cells that have not reached the target pulse voltage where Then verify whether the above third memory cells all reach the target pulse voltage after applying the pulse voltage For the third memory cells that have not reached the target pulse voltage, the pulse voltage needs to be continuously applied until all the third memory cells with the target state being the third programming state P2 pass the verification.
[0070] In some embodiments, the first interval is less than the second interval, and the first incremental step pulse programming step is less than the second incremental step pulse programming step. Exemplarily, such as Figure 7As shown, when the first interval between the first threshold voltage distribution and the second threshold voltage distribution is smaller than that between the second threshold voltage distribution and the third threshold voltage distribution, that is, the first incremental step pulse programming step size ΔV1 is smaller than the second incremental step pulse programming step size ΔV2. This is because after the programming of the first programming state is completed, that is, when the first threshold voltage distribution 71 is reached, due to the smaller first interval between the first threshold voltage distribution and the second threshold voltage distribution, in order to avoid over-programming, a smaller ISPP step size is considered. A smaller ISPP step size means that the step amount of the pulse voltage increased each time is smaller, enabling the storage cell to reach the target programming state more precisely, so that the finally formed second threshold voltage distribution is not over-diffused, that is, over-programming is avoided to make the distribution of the second threshold voltage too wide, improving the programming accuracy.
[0071] After reaching the second threshold voltage distribution 72, since the second interval between the second threshold voltage distribution and the third threshold voltage distribution is larger, a larger ISPP step size is considered, which can shorten the programming time of the third programming state and improve the programming efficiency.
[0072] In some embodiments, the first interval is greater than the second interval, and the first incremental step pulse programming step size is greater than the second incremental step pulse programming step size. Exemplarily, as Figure 8 shown, when the first interval between the first threshold voltage distribution 81 and the second threshold voltage distribution 82 is greater than that between the second threshold voltage distribution and the third threshold voltage distribution 83, the first incremental step pulse programming step size ΔV1 is greater than the second incremental step pulse programming step size ΔV2.
[0073] In some embodiments, it is assumed that the first interval is equal to the second interval, and the first incremental step pulse programming step size is equal to the second incremental step pulse programming step size.
[0074] For the above method, different ISPP step sizes are adopted according to different threshold voltage distribution intervals. On the one hand, when the threshold voltage distribution interval is small, a smaller ISPP step size is adopted, which can achieve a more accurate programming process. On the other hand, when the threshold voltage distribution interval is large, a larger ISPP step size is adopted, which can achieve a more efficient programming process.
[0075] In some embodiments, when the first incremental step pulse programming step size is smaller than the second incremental step pulse programming step size, in response to the second programming state being verified as passed, the first incremental step pulse programming step size is switched to the second incremental step pulse programming step size.
[0076] Please refer to Figure 7, assuming that the first programming state passes the verification, a pulse voltage is applied to the storage unit with the target state being the second programming state P1 and the third storage unit with the target state being the third programming state P2. At this time, the ISPP step size is the first incremental step pulse programming step size ΔV1. When the second programming state passes the verification, the ISPP step size becomes the second incremental step pulse programming step size ΔV2. When programming the third storage unit, the ISPP step size is ΔV2 until all the third storage units pass the verification.
[0077] In the above method, since the first interval is smaller than the second interval, when the second storage unit passes the verification, a larger ISPP step size is used, which can improve the programming efficiency and shorten the programming time.
[0078] In some embodiments, when the first incremental step pulse programming step size is greater than the second incremental step pulse programming step size, in response to the start of the third programming state verification, the first incremental step pulse programming step size is switched to the second incremental step pulse programming step size.
[0079] Please refer to Figure 8 , assuming that the first programming state passes the verification, a pulse voltage is applied to the second storage unit with the target state being the second programming state P1 and the third storage unit with the target state being the third programming state P2. At this time, the ISPP step size is the first incremental step pulse programming step size ΔV1. When the third storage unit starts the verification, the ISPP step size becomes the second incremental step pulse programming step size ΔV2. At this time, when applying the pulse voltage to the second storage unit with the target state being the second programming state P1 and the third storage unit with the target state being the third programming state P2, the ISPP step size is ΔV2 until all the second storage units and third storage units pass the verification. Here, it is default that when the third programming state starts the verification, the second programming state has not passed the verification.
[0080] In some embodiments, when the first incremental step pulse programming step size is equal to the second incremental step pulse programming step size, the incremental step pulse programming step size is not switched.
[0081] In the above method, since the first interval is greater than the second interval, in order to improve the programming accuracy, when the third storage unit starts the verification, a smaller ISPP step size is started to be used to improve the programming accuracy.
[0082] Please refer to Figure 9 , which shows a schematic diagram of the threshold voltage distribution of QLC memory 6-16 programming provided by an embodiment of the present application. In the first programming stage, the QLC memory can be programmed into 6 programming states, which are respectively Figure 9P0, P1, P2, P3, P4, and P5 in the first programming stage. Among them, P0 corresponds to the first threshold voltage distribution, P1 corresponds to the second threshold voltage distribution, P2 corresponds to the third threshold voltage distribution, P3 corresponds to the fourth threshold voltage distribution, P4 corresponds to the fifth threshold voltage distribution, and P5 corresponds to the sixth threshold voltage distribution. Program the first memory cell into the first programming state corresponding to the first threshold voltage distribution among the N programming states, program the second memory cell into the second programming state corresponding to the second threshold voltage distribution among the N programming states, program the third memory cell into the third programming state corresponding to the third threshold voltage distribution among the N programming states, program the fourth memory cell into the fourth programming state corresponding to the third threshold voltage distribution among the N programming states, program the fifth memory cell into the fifth programming state corresponding to the third threshold voltage distribution among the N programming states, and program the sixth memory cell into the sixth programming state corresponding to the third threshold voltage distribution among the N programming states. N is an integer greater than or equal to 3 and less than M, and M is an integer greater than or equal to 4. Among them, the first threshold voltage distribution, the second threshold voltage distribution, the third threshold voltage distribution, the fourth threshold voltage distribution, the fifth threshold voltage distribution, and the sixth threshold voltage distribution are adjacent to each other in sequence, and the first interval between the first threshold voltage distribution and the second threshold voltage distribution is less than the second interval between the second threshold voltage distribution and the third threshold voltage distribution. The above-mentioned second interval is equal to the third interval between the third threshold voltage distribution and the fourth threshold voltage distribution. The above-mentioned third interval is greater than the fourth interval between the third threshold voltage distribution and the fourth threshold voltage distribution. The above-mentioned fourth interval is greater than the fifth interval between the fifth threshold voltage distribution and the sixth threshold voltage distribution. And ISPP step size 1 < ISPP step size 5 < ISPP step size 4 < ISPP step size 2 = ISPP step size 3.
[0083] Please refer to Figure 10 , which shows the flowchart of the threshold voltage distribution of QLC memory 6-16 programming provided by an embodiment of the present application. First, apply an initial pulse voltage V1 to the first memory cell, the second memory cell, the third memory cell, the fourth memory cell, the fifth memory cell, and the sixth memory cell whose target states are the first programming state P0, the second programming state P1, the third programming state P2, the fourth programming state P3, the fifth programming state P4, and the sixth programming state P5 respectively. At this time, the ISPP step size is ISPP step size 1. Because ISPP step size 1 is less than ISPP step size 2, in response to the successful verification of the second programming state P1, switch ISPP step size 1 to ISPP step size 2. As Figure 11 shown, assume that in the Nth programming cycle, the second programming state P1 is successfully verified. Then apply pulse voltages to the second memory cell, the third memory cell, the fourth memory cell, the fifth memory cell, and the sixth memory cell whose target states are the third programming state P2, the fourth programming state P3, the fifth programming state P4, and the sixth programming state P5 respectively with the ISPP step size being ISPP step size 2.
[0084] Here, the third storage unit, the fourth storage unit, the fifth storage unit, and the sixth storage unit with target states being the third programming state P2, the fourth programming state P3, the fifth programming state P4, and the sixth programming state P5 respectively refer to the storage units that have not passed verification. For the storage units that have passed verification, no subsequent programming is performed. Similar descriptions below are consistent with the idea expressed here.
[0085] And here, for the third programming state, when the ISPP step size is ISPP step size 2, the third programming state may pass verification or may not pass verification. Whether the third programming state passes verification here is not the focus of our attention. In this article, it is defaulted that the third programming state passes verification.
[0086] Since the ISPP step size 2 is equal to the ISPP step size 3, the incremental stepping pulse programming step size is not switched, and the ISPP step size 3 remains the ISPP step size 2. Pulse voltages are applied to the fourth storage unit, the fifth storage unit, and the sixth storage unit with target states being the fourth programming state P3, the fifth programming state P4, and the sixth programming state P5 respectively with the ISPP step size being ISPP step size 2.
[0087] Here, for the fourth programming state, when the ISPP step size is ISPP step size 2, the fourth programming state may pass verification or may not pass verification. Whether the fourth programming state passes verification here is not the focus of our attention. In this article, it is defaulted that the fourth programming state passes verification.
[0088] Since the ISPP step size 2 is greater than the ISPP step size 4, in response to the start of verification of the fifth programming state P4, the ISPP step size 2 is switched to the ISPP step size 4, as Figure 11 shown. Assuming the (M + 1)-th programming cycle, when the verification of the fifth programming state P4 starts, pulse voltages are applied to the fifth storage unit and the sixth storage unit with target states being the fifth programming state P4 and the sixth programming state P5 respectively with the ISPP step size being the ISPP step size 4.
[0089] Here, for the fifth programming state, when the verification of the sixth programming state P5 starts, the fifth programming state may pass verification or may not pass verification. Whether the fifth programming state passes verification here is not the focus of our attention. In this article, it is defaulted that the fifth programming state passes verification.
[0090] Since the ISPP step size 4 is greater than the ISPP step size 5, in response to the start of verification of the sixth programming state P5, the ISPP step size 4 is switched to the ISPP step size 5, and pulse voltage is applied to the sixth storage unit with the target state being the sixth programming state P5 with the ISPP step size being the ISPP step size 5. The programming ends until the sixth programming state passes verification.
[0091] In some embodiments, when the N programming states are arranged in ascending order from the lowest state to the highest state, the interval between the threshold voltage distributions corresponding to two adjacent programming states among the N programming states gradually decreases.
[0092] To make the programming more accurate, since the interval between the threshold voltage distributions corresponding to two adjacent programming states among the N programming states gradually decreases, the ISPP step size also gradually decreases, and the smaller ISPP step size makes the memory programming more accurate.
[0093] Step 620, in the second programming stage, program the first memory cell, the second memory cell, and the third memory cell into corresponding programming states among the M programming states.
[0094] As Figure 7 shown, program the first memory cell into the P0 - P3 programming states of the second programming stage, program the second memory cell into the P4 - P9 programming states of the second programming stage, and program the third memory cell into the P 10 -P 15 programming states.
[0095] In some embodiments, when programming the first memory cell into the P0 - P3 programming states of the second programming stage, programming the second memory cell into the P4 - P9 programming states of the second programming stage, and programming the third memory cell into the P 10 -P 15 programming states, a fixed ISPP step size can be adopted. To ensure that the finally obtained programming states are accurate enough, a smaller ISPP step size can be considered.
[0096] The technical solution provided by the embodiments of the present application adopts different ISPP step sizes for different intervals of threshold voltage distributions, avoiding the problem of a large number of programming loops and verification loops caused by using a fixed ISPP step size, and achieving the technical effect of shortening the memory programming time.
[0097] The embodiments of the present application further provide a storage device. As Figure 4 shown, the storage device 400 includes:
[0098] A storage array 401, the storage array including a plurality of memory cells; and
[0099] A peripheral circuit 402, the peripheral circuit being coupled to the storage array and configured to:
[0100] In a first programming stage, a first memory cell is programmed to a first programming state corresponding to a first threshold voltage distribution among N programming states, a second memory cell is programmed to a second programming state corresponding to a second threshold voltage distribution among the N programming states, and a third memory cell is programmed to a third programming state corresponding to a third threshold voltage distribution among the N programming states, where N is an integer greater than or equal to 3 and less than M, and M is an integer greater than or equal to 4; wherein, the first threshold voltage distribution, the second threshold voltage distribution, and the third threshold voltage distribution are sequentially and adjacently distributed, and a first interval between the first threshold voltage distribution and the second threshold voltage distribution is different from a second interval between the second threshold voltage distribution and the third threshold voltage distribution; during programming of the first memory cell in the first programming stage, a first incremental step pulse programming step size is used when programming the second memory cell, and a second incremental step pulse programming step size is used when programming the third memory cell after programming the second memory cell in the first programming stage, and the first incremental step pulse programming step size is different from the second incremental step pulse programming step size;
[0101] In a second programming stage, the first memory cell, the second memory cell, and the third memory cell are respectively programmed to corresponding programming states among M programming states.
[0102] In some embodiments, the first interval is greater than the second interval, and the first incremental step pulse programming step size is greater than the second incremental step pulse programming step size; or, the first interval is less than the second interval, and the first incremental step pulse programming step size is less than the second incremental step pulse programming step size.
[0103] In some embodiments, the peripheral circuit 402 is further configured to: in a case where the first incremental step pulse programming step size is greater than the second incremental step pulse programming step size, switch the first incremental step pulse programming step size to the second incremental step pulse programming step size in response to the start of verification of the third programming state; or, in a case where the first incremental step pulse programming step size is less than the second incremental step pulse programming step size, switch the first incremental step pulse programming step size to the second incremental step pulse programming step size in response to the passing of verification of the second programming state.
[0104] In some embodiments, when the N programming states are arranged in ascending order from a low state to a high state, the interval between threshold voltage distributions corresponding to two adjacent programming states among the N programming states gradually decreases.
[0105] In some embodiments, M = 2 x , and each memory cell is configured to be in 2 xOne of the storage states stores x-bit data, where x is an integer greater than 1.
[0106] For details not described in detail in this embodiment, reference may be made to the method embodiment above, and the present application will not elaborate herein.
[0107] Please refer to Figure 12 , which exemplarily shows the structural block diagram of the electronic device 1200 provided by an embodiment of the present application.
[0108] Generally, the electronic device 1200 includes: a storage device 102 and a host 108.
[0109] The storage device 102 may include a controller 106 and one or more storage devices 104. The storage device 102 is coupled to the host 108. The controller 106 controls the storage device 104 to execute to implement the operation method of the above-mentioned memory.
[0110] For the specific structures of the storage device 102 and the host 108 and the specific introduction of their interaction manners, reference may be made to the above embodiments, and details will not be elaborated herein.
[0111] In some embodiments, a computer-readable storage medium is further provided. A computer program is stored in the storage medium, and the computer program is loaded and executed by the storage device to implement the operation method of the above-mentioned memory.
[0112] Optionally, the computer-readable storage medium may include: ROM, RAM, SSD (Solid State Drives, solid-state drive) or optical disc, etc. Among them, RAM may include ReRAM (Resistance Random Access Memory, resistive random access memory) and DRAM (Dynamic Random Access Memory, dynamic random access memory).
[0113] It should be understood that "a plurality of" mentioned herein refers to two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after. In addition, the step numbers described herein only exemplarily show a possible execution sequence between steps. In some other embodiments, the above steps may not be executed in the order of the numbers. For example, two steps with different numbers are executed simultaneously, or two steps with different numbers are executed in the reverse order of the illustration. The embodiments of the present application do not limit this.
[0114] The above are only exemplary embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the protection scope of the present application.
Claims
1. A method for operating a memory, characterized in that, The method includes: In a first programming stage, programming a first memory cell to a first programming state corresponding to a first threshold voltage distribution among N programming states, programming a second memory cell to a second programming state corresponding to a second threshold voltage distribution among the N programming states, and programming a third memory cell to a third programming state corresponding to a third threshold voltage distribution among the N programming states, where N is an integer greater than or equal to 3 and less than M, and M is an integer greater than or equal to 4; wherein, the first threshold voltage distribution, the second threshold voltage distribution, and the third threshold voltage distribution are sequentially and adjacently distributed, and a first interval between the first threshold voltage distribution and the second threshold voltage distribution is different from a second interval between the second threshold voltage distribution and the third threshold voltage distribution; when programming the second memory cell after programming the first memory cell in the first programming stage, a first incremental step pulse programming step size is adopted, and when programming the third memory cell after programming the second memory cell in the first programming stage, a second incremental step pulse programming step size is adopted, and the first incremental step pulse programming step size is different from the second incremental step pulse programming step size; In a second programming stage, programming the first memory cell, the second memory cell, and the third memory cell to respective programming states among M programming states.
2. The method according to claim 1, wherein the first interval is greater than the second interval, and the first incremental step pulse programming step size is greater than the second incremental step pulse programming step size; or the first interval is less than the second interval, and the first incremental step pulse programming step size is less than the second incremental step pulse programming step size.
3. The method according to claim 1, wherein The method further includes: When the first incremental step pulse programming step size is greater than the second incremental step pulse programming step size, in response to the start of verification of the third programming state, switching the first incremental step pulse programming step size to the second incremental step pulse programming step size; or When the first incremental step pulse programming step size is less than the second incremental step pulse programming step size, in response to the passing of verification of the second programming state, switching the first incremental step pulse programming step size to the second incremental step pulse programming step size.
4. The method according to claim 1, wherein When the N programming states are arranged in ascending order from a low state to a high state, the interval between the threshold voltage distributions corresponding to two adjacent programming states among the N programming states gradually decreases.
5. The method according to claim 1, characterized in that, M = 2 x , each memory cell is configured to store x-bit data in one of 2 x memory states, where x is an integer greater than 1.
6. A storage device, characterized in that, The storage device includes: a storage array including a plurality of memory cells; and a peripheral circuit coupled to the storage array and configured to: In a first programming stage, a first memory cell is programmed to a first programming state corresponding to a first threshold voltage distribution among N programming states, a second memory cell is programmed to a second programming state corresponding to a second threshold voltage distribution among the N programming states, and a third memory cell is programmed to a third programming state corresponding to a third threshold voltage distribution among the N programming states, where N is an integer greater than or equal to 3 and less than M, and M is an integer greater than or equal to 4; wherein, the first threshold voltage distribution, the second threshold voltage distribution, and the third threshold voltage distribution are sequentially and adjacently distributed, and a first interval between the first threshold voltage distribution and the second threshold voltage distribution is different from a second interval between the second threshold voltage distribution and the third threshold voltage distribution; in the first programming stage, after programming the first memory cell and when programming the second memory cell, a first incremental step pulse programming step size is adopted, and after programming the second memory cell in the first programming stage and when programming the third memory cell, a second incremental step pulse programming step size is adopted, and the first incremental step pulse programming step size is different from the second incremental step pulse programming step size; In a second programming stage, the first memory cell, the second memory cell, and the third memory cell are respectively programmed to corresponding programming states among M programming states.
7. The storage device according to claim 6, wherein: the first interval is greater than the second interval, and the first incremental step pulse programming step size is greater than the second incremental step pulse programming step size; or the first interval is less than the second interval, and the first incremental step pulse programming step size is less than the second incremental step pulse programming step size.
8. The storage device according to claim 6, wherein The peripheral circuit is further configured to: in a case where the first incremental step pulse programming step size is greater than the second incremental step pulse programming step size, in response to the start of verification of the third programming state, switch the first incremental step pulse programming step size to the second incremental step pulse programming step size; or in a case where the first incremental step pulse programming step size is less than the second incremental step pulse programming step size, in response to the passing of verification of the second programming state, switch the first incremental step pulse programming step size to the second incremental step pulse programming step size.
9. The storage device according to claim 6, characterized in that, In a case where the N programming states are arranged in ascending order from a low state to a high state, an interval between threshold voltage distributions corresponding to two adjacent programming states among the N programming states gradually decreases.
10. The storage device according to claim 6, characterized in that, M = 2 x , each storage cell is configured to store x-bit data in one of 2 x storage states, where x is an integer greater than 1.
11. A storage system, characterized in that, The storage system includes: a storage device, the storage device including the storage device according to any one of claims 6 to 10; and a controller, the controller being coupled to the storage device and configured to control the storage device.
12. An electronic device, characterized in that, The electronic device includes a host and a storage system coupled to the host, the storage system including a controller and at least one storage device coupled to the controller, and the controller controls the storage device to execute the method according to any one of claims 1 to 5.
13. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, and the computer program is used to be executed by the storage device to implement the method according to any one of claims 1 to 5.