Memory management method and storage device

Abstract

The invention provides a memory management method and a storage device. The method includes: determining an operation mode of a first entity unit in the storage device, in which each storage unit in the first entity unit is configured to store n bits; according to the operation mode, a critical voltage distribution corresponding to a first entity unit is determined to contain a plurality of states, the total number of the plurality of states is larger than a preset number, and the preset number is the n power of 2; and based on the operation mode, executing a programmed operation on the first entity unit to disperse critical voltages of a plurality of memory cells in the first entity unit to a plurality of voltage intervals, the plurality of voltage intervals respectively corresponding to the plurality of states. Therefore, the operation stability and / or the operation efficiency of the storage device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and particularly to a memory management method and a storage device. Background Art

[0002] Non-volatile memories have been widely used in various electronic devices. Among them, NAND flash memories have advantages such as fast reading and earthquake resistance. When a NAND flash memory is being programmed (also known as programming), a high voltage is applied to the floating gate, causing electrons to enter the floating gate through the tunneling oxide layer by quantum tunneling effect, thereby changing the critical voltage (also known as the threshold voltage) of the memory cell to store data. In addition, the erase operation is to remove the electrons in the floating gate and reduce the threshold voltage to return the cell to the erased state.

[0003] Traditionally, the voltage range of a word line is divided into a certain number of threshold voltage windows, and each window corresponds to a logical state. However, as the number of read and write operations increases, factors such as programming interference and temperature changes can cause threshold voltage drift, which in turn affects the accuracy and reliability of data. Especially for high-density storage media such as second-order memory cell (Multi Level Cell, MLC) NAND flash memory modules, third-order memory cell (Triple Level Cell, TLC) NAND flash memory modules, and fourth-order memory cell (Quad Level Cell, QLC) NAND flash memory modules, after the threshold voltage drifts, the operation stability (such as the stability of reading data) and / or operation efficiency (such as the speed of reading data) of the storage device may decrease significantly. Summary of the Invention

[0004] The present invention provides a memory management method and a storage device, which can improve the operation stability and / or operation efficiency of the storage device.

[0005] An embodiment of the present invention provides a memory management method for a storage device, where the storage device includes a memory module, the memory module includes a plurality of physical units, and the memory management method includes: determining an operation mode of a first physical unit among the plurality of physical units, where in the operation mode, each memory cell in the first physical unit is used to store n bits; according to the operation mode, determining the critical voltage distribution corresponding to the first physical unit as including a plurality of states, where the total number of the plurality of states is greater than a predetermined number, and the predetermined number is 2 to the power of n; and based on the operation mode, performing a programming operation on the first physical unit to disperse the critical voltages of a plurality of memory cells in the first physical unit to a plurality of voltage intervals, where the plurality of voltage intervals respectively correspond to the plurality of states.

[0006] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of physical units, and the memory controller is configured to: determine an operation mode of a first physical unit among the plurality of physical units, wherein in the operation mode, each memory cell in the first physical unit is used to store n bits; according to the operation mode, determine a threshold voltage distribution corresponding to the first physical unit as including a plurality of states, wherein a total number of the plurality of states is greater than a predetermined number, and the predetermined number is 2 to the power of n; and based on the operation mode, perform a programming operation on the first physical unit to disperse threshold voltages of a plurality of memory cells in the first physical unit to a plurality of voltage intervals, wherein the plurality of voltage intervals respectively correspond to the plurality of states.

[0007] Based on the above, after determining the operation mode of the first physical unit, according to the operation mode, the threshold voltage distribution corresponding to the first physical unit can be determined as including a plurality of states. In particular, in the operation mode, each memory cell in the first physical unit can be used to store n bits, the total number of the plurality of states is greater than a predetermined number, and the predetermined number is 2 to the power of n. Based on the operation mode, the first physical unit can be subjected to a programming operation to disperse threshold voltages of a plurality of memory cells in the first physical unit to the plurality of voltage intervals corresponding to the plurality of states. Thereby, the operation stability and / or operation efficiency of the storage device can be improved. Description of the Drawings

[0008] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention;

[0009] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention;

[0010] Figure 3 is a schematic diagram of a managed memory module shown according to an embodiment of the present invention;

[0011] Figure 4 is a schematic diagram of a threshold voltage distribution corresponding to a first physical unit shown according to an embodiment of the present invention;

[0012] Figure 5 is a schematic diagram of a threshold voltage distribution corresponding to a first physical unit shown according to an embodiment of the present invention;

[0013] Figure 6 is a flowchart of a memory management method shown according to an embodiment of the present invention. Detailed implementation manners

[0014] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0015] Figure 1 is a schematic diagram of a data storage system shown according to an embodiment of the present invention. Please refer to Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 can include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0016] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 (such as exchanging signals, instructions, and / or data) via the connection interface 121.

[0017] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more arrays of memory cells. The memory cells in the memory cell array store data in the form of voltages (also referred to as threshold voltages). For example, the memory module 122 may include single-level cell (SLC) NAND flash memory modules, multi-level cell (MLC) NAND flash memory modules, triple-level cell (TLC) NAND flash memory modules, quad-level cell (QLC) NAND flash memory modules, and / or other memory modules with the same or similar characteristics.

[0018] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the overall or partial operations of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices, or a combination of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0019] The memory controller 123 can send an instruction sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in specific memory cells. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from specific memory cells. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in specific memory cells. In addition, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited in the present invention. The memory module 122 can receive the instruction sequence from the memory controller 123 and access the memory cells inside the memory module 122 according to this instruction sequence.

[0020] Figure 2 is a schematic diagram of a memory controller shown according to an embodiment of the present invention. Please refer to Figure 1 and Figure 2 , the memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0021] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 can be used to control or manage the overall or partial operation of the memory controller 123. For example, the memory control circuit 23 can communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 can include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is the same as the description of the memory controller 123.

[0022] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and is used to cache data. For example, the buffer memory 24 can be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0023] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on data to ensure the correctness of the data. For example, the decoding circuit 25 can support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may further include various other types of circuit modules (such as a power management circuit, etc.), which are not limited in the present invention.

[0024] Figure 3 is a schematic diagram of managing a memory module shown according to an embodiment of the present invention. Please refer to Figures 1 to 3 , the memory module 122 includes a plurality of physical units 301(1) to 301(B). Each physical unit includes a plurality of memory cells and is used to store data in a non-volatile manner. For example, one physical unit may include one or more physical programming units.

[0025] In one embodiment, an entity programming unit may include multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, both the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit may be adjusted according to practical requirements, and the present invention is not limited thereto. In one embodiment, an entity programming unit may be regarded as an entity page. For example, the storage capacity of an entity programming unit may be 16 kilobytes, and the present invention is not limited to this.

[0026] In one embodiment, an entity programming unit is the minimum unit for synchronously writing data in the memory module 122. For example, when performing a programming operation (also referred to as a write operation or a programming operation) on an entity programming unit to write data into this entity programming unit, multiple memory cells in this entity programming unit may be synchronously programmed (i.e., programmed) to store the corresponding data. For example, when programming an entity programming unit, a write voltage may be applied to this entity programming unit to change the threshold voltage of at least some of the memory cells in this entity programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in this memory cell.

[0027] In one embodiment, an entity erasure unit may include multiple entity programming units. The multiple entity programming units in an entity erasure unit may be synchronously erased. For example, when performing an erase operation on an entity erasure unit, an erase voltage may be applied to the multiple entity programming units in this entity erasure unit to change the threshold voltage of at least some of the memory cells in these entity programming units. By performing an erase operation on an entity erasure unit, the data stored in this entity erasure unit can be cleared. In one embodiment, an entity erasure unit may be regarded as an entity block.

[0028] In one embodiment, the memory control circuit 23 may logically associate the entity units 301(1) to 301(A) and 301(A + 1) to 301(B) with the data area 31 and the idle area 32 respectively. The entity units 301(1) to 301(A) in the data area 31 all store data (also referred to as user data) from the host system 11. For example, any one of the entity units in the data area 31 may store valid data and / or invalid data. In addition, the entity units 301(A + 1) - 301(B) in the idle area 32 do not store data (such as valid data).

[0029] In one embodiment, if a certain physical unit does not store valid data, this physical unit can be associated with the idle area 32. In addition, the physical units in the idle area 32 can be erased to clear the data in this physical unit. In one embodiment, the physical units in the idle area 32 are also referred to as idle physical units. In one embodiment, the idle area 32 is also referred to as a free pool.

[0030] In one embodiment, when data is to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data in the selected physical units. After the data is stored in this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be alternately used between the data area 31 and the idle area 32.

[0031] In one embodiment, the memory control circuit 23 can configure a plurality of logical units 302(1) to 302(C) to map the physical units (i.e., physical units 301(1) to 301(A)) in the data area 31. For example, one logical unit can correspond to one logical block address (LBA) or other logical management units. One logical unit can be mapped to one or more physical units.

[0032] In one embodiment, if a certain physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. On the contrary, if a certain physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0033] In one embodiment, the memory control circuit 23 can record the mapping relationship between the logical units and the physical units in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 can instruct the memory module 122 to perform operations such as data reading, writing, or erasing according to the information in this management table (i.e., the logical-to-physical mapping table).

[0034] In one embodiment, the memory control circuit 23 can determine the operation mode of a specific physical unit (also referred to as the first physical unit) in the memory module 122. In this operation mode, each storage unit in the first physical unit can be used to store n bits. For example, the operation mode of the first physical unit can be a single-level cell (SLC) mode, a multi-level cell (MLC) mode, a triple-level cell (TLC) mode, a quad-level cell (QLC) mode, or other modes.

[0035] In one embodiment, if the operation mode of the first physical unit is the SLC mode, then in the SLC mode, each memory cell in the first physical unit can be used to store 1 bit (i.e., n = 1). In one embodiment, if the operation mode of the first physical unit is the MLC mode, then in the MLC mode, each memory cell in the first physical unit can be used to store 2 bits (i.e., n = 2). In one embodiment, if the operation mode of the first physical unit is the TLC mode, then in the TLC mode, each memory cell in the first physical unit can be used to store 3 bits (i.e., n = 3). In one embodiment, if the operation mode of the first physical unit is the QLC mode, then in the QLC mode, each memory cell in the first physical unit can be used to store 4 bits (i.e., n = 4).

[0036] Figure 4 is a schematic diagram corresponding to the threshold voltage distribution of the first physical unit shown in the embodiments of the present invention. Please refer to Figure 4 , the horizontal axis represents the threshold voltage of the memory cell, and the vertical axis represents the number of memory cells.

[0037] Taking the TLC mode as an example, generally, after performing a programming operation on the first physical unit based on the TLC mode, the threshold voltage distribution corresponding to the first physical unit may include multiple states 401 to 408. The states 401 to 408 can be used to describe the distribution of the threshold voltages of multiple memory cells in the first physical unit.

[0038] Furthermore, the states 401 to 408 can correspond to multiple bit sequences. For example, the states 401 to 408 can sequentially correspond to the bit sequences "111", "110", "101", "011", "010", "001", "000", and "100". According to which state among the states 401 to 408 each memory cell in the first physical unit belongs to, the data stored in this memory cell can be determined. For example, if a certain memory cell in the first physical unit belongs to state 406 (for example, the threshold voltage of this memory cell is within the voltage range corresponding to state 406), then this memory cell can be identified as storing the bit sequence "001", and so on. In addition, the bit sequences respectively corresponding to the states 401 to 408 can also be adjusted according to actual needs, and the present invention does not limit this.

[0039] It should be noted that taking Figure 4For example, after performing a programming operation on the first physical unit based on the TLC mode, the critical voltage distribution corresponding to the first physical unit includes "8" states (i.e., states 401 to 408). However, in an embodiment, after performing a programming operation on the first physical unit based on other modes (such as the SLC mode, MLC mode, or QLC mode), the critical voltage distribution corresponding to the first physical unit may also include more or fewer states, depending on the operation mode currently adopted. For example, generally, after performing a programming operation on the first physical unit based on the SLC mode, MLC mode, or QLC mode, the critical voltage distribution corresponding to the first physical unit may include 2, 4, or 16 states, respectively.

[0040] In an embodiment, as the usage degree of the memory module 122 (including the first physical unit) increases, the critical voltages of at least some of the memory cells in the memory module 122 (including the first physical unit) will shift. In this case, the data read from the first physical unit is likely to be in error (i.e., the read data contains error bits). Generally, if the data read from the first physical unit contains a small number of errors, the errors can be quickly corrected by decoding the read data. However, if the data read from the first physical unit contains a large number of errors, the time for correcting the errors will increase significantly, and may even result in a data read failure. Therefore, after the aforementioned voltage shift occurs, the operation stability and / or operation efficiency of the storage device 12 tend to decrease.

[0041] Take Figure 4 as an example. States 411 to 418 can be used to represent the critical voltage distribution of multiple memory cells in the first physical unit after a voltage shift occurs. Compared with states 401 to 408, after a voltage shift occurs in at least some of the memory cells in the first physical unit, the data read from the first physical unit will contain more errors (i.e., bit errors). For example, assume that before the voltage shift occurs, a read voltage RV is applied to the first physical unit, and a certain memory cell in the first physical unit can be correctly identified as belonging to state 405 or 406. However, after the voltage shift occurs, if the read voltage RV is applied to the first physical unit, some memory cells belonging to state 415 may be misidentified as belonging to state 416, and / or some memory cells belonging to state 416 may be misidentified as belonging to state 415.

[0042] In particular, as the usage of the memory module 122 (including the first physical unit) continues to increase, the voltage offset of at least some memory cells in the memory module 122 (including the first physical unit) will become more and more serious. In this case, the total number of errors (i.e., error bits) included in the data read from the first physical unit will also continue to increase, thereby causing the operation stability and / or operation performance of the storage device 12 to be significantly reduced.

[0043] In addition, as the data storage density of the memory module 122 (including the first physical unit) increases, for example, the value of n increases, it is necessary to divide more states (or voltage intervals corresponding to each state) within the same or similar voltage range. Thereafter, as long as a small voltage offset occurs, it is easy to cause a large number of errors in the read data. Therefore, in practice, how to effectively improve the above-mentioned problems and improve the operation stability and / or operation performance of the storage device is one of the topics that those skilled in the art are committed to studying.

[0044] In one embodiment, after determining the operation mode of the first physical unit, the memory control circuit 23 may determine the critical voltage distribution corresponding to the first physical unit to include multiple states according to the operation mode. In particular, the total number of the multiple states must be greater than a predetermined number, and the predetermined number is 2 to the power of n. For example, in SLC mode, n is 1, so the predetermined number may be determined to be 2. Alternatively, in MLC mode, n is 2, so the predetermined number may be determined to be 4. Alternatively, in TLC mode, n is 3, so the predetermined number may be determined to be 8. Alternatively, in QLC mode, n is 4, so the predetermined number may be determined to be 16. By analogy, the predetermined number may be dynamically set or adjusted according to the current operation mode of the first physical unit.

[0045] In one embodiment, after determining the multiple states, based on the operation mode of the first physical unit, the memory control circuit 23 may instruct the memory module 122 to perform a programming operation on the first physical unit to disperse the threshold voltages of the multiple memory cells in the first physical unit into multiple voltage intervals. In particular, the multiple voltage intervals may correspond to the multiple states, respectively. For example, based on the operation mode of the first physical unit, the memory control circuit 23 may send at least one write instruction (also referred to as a programming instruction) to the memory module 122 to instruct the memory module 122 to perform the programming operation on the first physical unit.

[0046] In one embodiment, after performing the programming operation on the first physical unit, in the threshold voltage distribution corresponding to the first physical unit, at least two of the multiple states may correspond to the same bit sequence. Taking the TLC mode as an example, at least two of the multiple states may synchronously correspond to one of the bit sequences "111", "110", "101", "011", "010", "001", "000", and "100".

[0047] In one embodiment, the at least two states corresponding to the same bit sequence may include a first state and a second state. The first state corresponds to a specific voltage range (also referred to as the first voltage range) among the multiple voltage ranges. The second state corresponds to another voltage range (also referred to as the second voltage range) among the multiple voltage ranges. In particular, the first voltage range and the second voltage range do not overlap with each other. In other words, there may be a voltage interval (or voltage gap) between the first voltage range and the second voltage range.

[0048] In one embodiment, by performing the programming operation on the first physical unit, the memory control circuit 23 may adjust the threshold voltage (also referred to as the first threshold voltage) of at least one memory cell (also referred to as the first memory cell) in the first physical unit to the aforementioned first voltage range, so that the first memory cell stores a specific bit sequence (also referred to as the target bit sequence). Taking the TLC mode as an example, the target bit sequence may be one of the bit sequences "111", "110", "101", "011", "010", "001", "000", and "100".

[0049] On the other hand, by performing the programming operation on the first physical unit, the memory control circuit 23 may subsequently or synchronously adjust the threshold voltage (also referred to as the second threshold voltage) of at least one memory cell (also referred to as the second memory cell) in the first physical unit to the aforementioned second voltage range, so that the second memory cell also stores the aforementioned target bit sequence. For example, in the TLC mode, assuming the target bit sequence is "001", after performing the programming operation on the first physical unit, even though the threshold voltages of the first memory cell and the second memory cell are in different voltage ranges (i.e., the first voltage range and the second voltage range), the first memory cell and the second memory cell can be used to store the same target bit sequence (such as "001").

[0050] Figure 5 is a schematic diagram of the threshold voltage distribution corresponding to the first physical unit shown in the embodiment of the present invention. Please refer to Figure 5, in one embodiment, after performing a programming operation on a plurality of memory cells in a first physical unit based on a specific operation mode (e.g., TLC mode), the threshold voltage distribution of the plurality of memory cells in the first physical unit may include states 511 to 525. States 511 to 525 respectively correspond to voltage ranges R1 to R15. In particular, during this programming operation, the threshold voltages of the plurality of memory cells in the first physical unit may be dispersed to voltage ranges R1 to R15.

[0051] In one embodiment, any two adjacent voltage ranges among voltage ranges R1 to R15 may not overlap with each other. In one embodiment, the voltage coverage range of any one of voltage ranges R1 to R15 may be narrower than Figure 4 the voltage coverage range of any one of states 401 to 408 or 411 to 418 in

[0052] In one embodiment, the total number of states 511 to 525 (or voltage ranges R1 to R15) (e.g., 15) must be greater than a predetermined number. Taking the operation mode as TLC mode as an example, this predetermined number may be 8 (2 to the power of 3 = 8). However, the total number of states 511 to 525 (or voltage ranges R1 to R15) may also be adjusted according to practical requirements (e.g., increased or decreased), and the present invention does not limit it.

[0053] In one embodiment, state 511 corresponds to the bit sequence "111"; states 512 and 513 correspond to the bit sequence "110"; states 514 and 515 correspond to the bit sequence "101"; states 516 and 517 correspond to the bit sequence "011"; states 518 and 519 correspond to the bit sequence "010"; states 520 and 521 correspond to the bit sequence "001"; states 522 and 523 correspond to the bit sequence "000"; states 524 and 525 correspond to the bit sequence "100".

[0054] That is to say, if the critical voltage of a certain storage unit is within the voltage range R1, the memory control circuit 23 can determine that this storage unit is currently used to store the bit sequence "111"; if the critical voltage of a certain storage unit is within the voltage range R2 or R3, the memory control circuit 23 can determine that this storage unit is currently used to store the bit sequence "110"; if the critical voltage of a certain storage unit is within the voltage range R4 or R5, the memory control circuit 23 can determine that this storage unit is currently used to store the bit sequence "101"; if the critical voltage of a certain storage unit is within the voltage range R6 or R7, the memory control circuit 23 can determine that this storage unit is currently used to store the bit sequence "011"; if the critical voltage of a certain storage unit is within the voltage range R8 or R9, the memory control circuit 23 can determine that this storage unit is currently used to store the bit sequence "010"; if the critical voltage of a certain storage unit is within the voltage range R10 or R11, the memory control circuit 23 can determine that this storage unit is currently used to store the bit sequence "001"; if the critical voltage of a certain storage unit is within the voltage range R12 or R13, the memory control circuit 23 can determine that this storage unit is currently used to store the bit sequence "000"; if the critical voltage of a certain storage unit is within the voltage range R14 or R15, the memory control circuit 23 can determine that this storage unit is currently used to store the bit sequence "100".

[0055] In one embodiment, compared with Figure 4 the embodiment, it can also be considered that the memory control circuit 23 divides the state 412 into states 512 and 513; divides the state 413 into states 514 and 515; divides the state 414 into states 516 and 517; divides the state 415 into states 518 and 519; divides the state 416 into states 520 and 521; divides the state 417 into states 522 and 523; and divides the state 418 into states 524 and 525.

[0056] In one embodiment, even if the total number of states 511 to 525 (or voltage ranges R1 to R15) is greater than Figure 4 the total number of states 401 to 408 (or 411 to 418) in Figure 4 i.e., the predetermined number (e.g., 8), however, the overall voltage coverage range of states 511 to 525 can be the same or similar to the overall voltage coverage range of states 401 to 408 (or 411 to 418). For example, assuming that in Figure 5 the embodiment, the overall voltage coverage range of states 401 to 408 (or 411 to 418) is between 0 and 3.3 V (volts), then in

[0057] In one embodiment, during the execution of the programming operation on the first physical unit, the memory control circuit 23 may determine a specific storage unit (also referred to as the target storage unit) from among a plurality of storage units of the first physical unit. Further, according to the data to be stored in the target storage unit (also referred to as the target bit sequence), the memory control circuit 23 may determine a specific state (also referred to as the target state) from among the plurality of states. For example, the target state may correspond to a specific voltage range (also referred to as the target voltage range) among the plurality of voltage ranges.

[0058] In one embodiment, during the execution of the programming operation on the first physical unit, according to the target state, the memory control circuit 23 may adjust the programming parameters corresponding to the target storage unit. Then, the memory control circuit 23 may change the threshold voltage of the target storage unit (also referred to as the target threshold voltage) according to this programming parameter, so that the target threshold voltage moves (e.g., adjusts) to the target voltage range.

[0059] For Figure 5 example, in one embodiment, assume that the target bit sequence for the target storage unit is "101". During the execution of the programming operation on the first physical unit, the memory control circuit 23 may determine state 514 or 515 corresponding to the target bit sequence (i.e., "101") as the target state. After determining the target state, the memory control circuit 23 may adjust the programming parameters corresponding to the target storage unit. Then, the memory control circuit 23 may instruct the memory module 122 to use the adjusted programming parameters to change the threshold voltage of the target storage unit (i.e., the target threshold voltage), so that the target threshold voltage moves (e.g., adjusts) to voltage range R4 or R5 (i.e., the target voltage range). For example, if the target state is state 514, the target threshold voltage may be moved (e.g., adjusted) to voltage range R4. Or, if the target state is state 515, the target threshold voltage may be moved (e.g., adjusted) to voltage range R5.

[0060] Alternatively, in an embodiment, assume that the target bit sequence for a target storage cell is "000". During the execution of the programming operation on the first physical cell, the memory control circuit 23 may determine the state 522 or 523 corresponding to the target bit sequence (i.e., "000") as the target state. After determining the target state, the memory control circuit 23 may adjust the programming parameters corresponding to the target storage cell. Then, the memory control circuit 23 may instruct the memory module 122 to use the adjusted programming parameters to change the threshold voltage of the target storage cell (i.e., the target threshold voltage), causing the target threshold voltage to shift (e.g., adjust) to the voltage range R12 or R13 (i.e., the target voltage range). For example, if the target state is state 522, the target threshold voltage may be shifted (e.g., adjusted) to the voltage range R12. Alternatively, if the target state is state 523, the target threshold voltage may be shifted (e.g., adjusted) to the voltage range R13.

[0061] In an embodiment, the programming parameters include at least one of a programming time sequence and a programming voltage pulse amplitude. The programming time sequence is used to control the duration of applying a voltage pulse to the target storage cell at least once during the execution of the programming operation on the first physical cell. In addition, the programming voltage pulse amplitude is used to control the voltage value (e.g., voltage peak value) of the voltage pulse applied to the target storage cell during the execution of the programming operation on the first physical cell.

[0062] In an embodiment, assume that the target bit sequence for the target memory cell is "010", and the target voltage range corresponding to the target bit sequence (i.e., "010") is voltage range R8 or R9. Here, assume that the target voltage range is voltage range R8, and the voltage coverage range of voltage range R8 is 0.99V to 1.155V. During the execution of the programming operation on the first physical cell, the memory control circuit 23 can first apply 10 voltage pulses with a voltage value of 18V and a pulse width of 10 μs (microseconds) to the target memory cell in sequence based on a programming parameter (also called the first programming parameter), so that the threshold voltage of the target memory cell is increased to around 0.8V. Then, the memory control circuit 23 can apply 5 voltage pulses with a voltage value of 16V and a pulse width of 5 μs to the target memory cell in sequence based on another programming parameter (also called the second programming parameter), so that the threshold voltage of the target memory cell is further increased to around 1.05V. Finally, the memory control circuit 23 can apply 3 voltage pulses with a voltage value of 15V and a pulse width of 1 μs to the target memory cell in sequence based on yet another programming parameter (also called the third programming parameter), so that the threshold voltage of the target memory cell is precisely located around 1.1V (i.e., moving the target threshold voltage within 0.99V to 1.155V). In addition, the programming method for the remaining voltage ranges can be inferred by analogy and will not be elaborated one by one here.

[0063] In an embodiment, when data is to be read from the first physical cell, the memory control circuit 23 can perform a read operation on the first physical cell based on the operation mode of the first physical cell to determine the voltage range (e.g., the target voltage range) where the threshold voltage (e.g., the target threshold voltage) of at least one memory cell (e.g., the target memory cell) in the first physical cell is located. For example, the memory control circuit 23 can apply at least one read voltage to the first physical cell and obtain the read result of the memory module 122 corresponding to the at least one read voltage. Then, the memory control circuit 23 can determine the target voltage range where the target threshold voltage of the target memory cell is located according to this read result.

[0064] In an embodiment, after determining the target voltage range where the target threshold voltage of the target memory cell is located, according to the target voltage range, the memory control circuit 23 can determine that the bit sequence (e.g., the target bit sequence) stored in the target memory cell is one of multiple bit sequences (also called candidate bit sequences). In particular, the total number of the multiple candidate bit sequences is the same as the predetermined number. Figure 5For example, the multiple candidate bit sequences may include bit sequences "111", "110", "101", "011", "010", "001", "000", and "100". For example, when data is to be read from the first physical unit, if the memory control circuit 23 determines that the threshold voltage of a certain memory cell is within the voltage range R6 (or R7), the memory control circuit 23 may determine that the bit sequence currently stored in this memory cell is "011", and so on.

[0065] In one embodiment, the memory control circuit 23 may evaluate the wear state of the first physical unit (or the memory module 122). For example, the wear state of the first physical unit (or the memory module 122) may reflect the degree of wear of the first physical unit. Then, the memory control circuit 23 may adjust (such as increasing or decreasing) the total number of the multiple states (such as Figure 5 the states 511 to 525 in

[0066] In one embodiment, the total number of the multiple states (such as Figure 5 the states 511 to 525 in Figure 5 may be positively correlated with the degree of wear of the first physical unit. That is, if the degree of wear of the first physical unit is higher, the total number of the multiple states (such as

[0067] the states 511 to 525 in

[0068] In one embodiment, the memory control circuit 23 may obtain an evaluation value according to the read count, write count, erase count, or bit error rate (BER) of the first physical unit (or the memory module 122). This evaluation value can be used to reflect the wear state of the first physical unit (or the memory module 122). This read count can reflect the number of read operations performed on the first physical unit. This write count can reflect the number of programming operations performed on the first physical unit. This erase count can reflect the number of erase operations performed on the first physical unit. This bit error rate can reflect the error rate of the data read from the first physical unit. In one embodiment, this read count, write count, erase count, and / or bit error rate may be positively correlated with the degree of wear of the first physical unit. That is, if this read count, write count, erase count, and / or bit error rate is larger, it means that the degree of wear of the first physical unit is higher.

[0069] In one embodiment, the memory control circuit 23 may perform a logic operation according to the read count, write count, erase count or bit error rate to obtain the evaluation value. In one embodiment, the evaluation value may be positively correlated to the degree of wear of the first physical unit. That is, the larger the evaluation value is, the higher the degree of wear of the first physical unit is. In addition, the memory control circuit 23 may also evaluate the wear state of the first physical unit (or memory module 122) in other ways, which is not limited by the present invention.

[0070] In one embodiment, in response to the wear level of the first physical unit increasing (for example, the evaluation value is higher than the critical value), the memory control circuit 23 may Figure 5 The total number of additionally divided states 511-525 in the memory is controlled to be a specific number (also referred to as a first number). In one embodiment, in response to the wear level of the first physical unit decreasing (for example, the evaluation value is not higher than the critical value), the memory control circuit 23 may Figure 5 The total number of the additionally divided states 511-525 is controlled to be another number (also referred to as a second number). The first number may be greater than the second number.

[0071] In one embodiment, during the execution of the programming operation on the first physical unit, the memory control circuit 23 may determine whether the programming (i.e., programming) for all the memory cells in the first physical unit has been completed. If the programming for all the memory cells in the first physical unit has not been completed, the memory cells in the first physical unit that have not been programmed can be determined as the aforementioned target memory cells and the target memory cells are programmed to adjust the critical voltage of the target memory cells. The relevant operation details have been described in detail above and will not be repeated here. However, if the programming for all the memory cells in the first physical unit has been completed, the memory control circuit 23 may perform write verification or other operations on the first physical unit, which is not limited by the present invention.

[0072] Figure 6 is a flow chart of a memory management method according to an embodiment of the present invention. Figure 6 In step S601, an operation mode of a first physical unit in a memory module is determined, wherein in the operation mode, each memory cell in the first physical unit is used to store n bits. In step S602, according to the operation mode, a critical voltage distribution corresponding to the first physical unit is determined to include a plurality of states, wherein the total number of the plurality of states is greater than a predetermined number, and the predetermined number is 2 to the power of n. In step S603, based on the operation mode, a programming operation is performed on the first physical unit to disperse the critical voltages of the plurality of memory cells in the first physical unit into a plurality of voltage intervals, wherein the plurality of voltage intervals correspond to the plurality of states, respectively.

[0073] However, Figure 6 Each step in has been described in detail above, so it will not be elaborated here. It should be noted that, Figure 6 Each step in can be implemented as multiple pieces of code or circuits, and the present invention does not limit this. In addition, Figure 6 The method of can be used in conjunction with the above exemplary embodiments or used alone, and the present invention does not limit this.

[0074] In summary, the memory management method and storage device proposed by the embodiments of the present invention may have the following beneficial effects, and the present invention is not limited thereto:

[0075] 1. By dividing the voltage range of the word line into more and narrower threshold voltage windows, with each window corresponding to a specific programming state, the accuracy and reliability of data programming can be improved, the error rate can be reduced, and the accuracy and efficiency of data reading can be increased;

[0076] 2. By changing the time series or the amplitude of the voltage pulse, the target threshold voltage of each memory cell can be adjusted independently, so that the threshold voltage distribution of each cell can be controlled more precisely, and the problem of non-all-"1" erase state caused by the overall shift of the voltage curve can be effectively solved;

[0077] 3. For TLC NAND Flash, dividing the original 8 relatively wide threshold windows into 16 or more or fewer narrower windows can enhance the distinguishability between different logic states and increase the storage density;

[0078] 4. For QLC NAND Flash, dividing the original 16 relatively wide threshold windows into 32 or more or fewer narrower windows can provide greater flexibility to adapt to different programming requirements, ensure that each cell can reach the ideal target threshold voltage, and meet the requirements of high-density storage;

[0079] 5. By controlling the threshold voltage distribution more precisely, the influence of the coupling effect between adjacent memory cells can be reduced, the uncertainty of the threshold voltage can be decreased, and the performance and reliability of the memory cells can be improved.

[0080] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that: For use in a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of entity units, and the memory management method comprises: Determining an operation mode of a first physical unit among the plurality of physical units, wherein in the operation mode, each storage unit in the first physical unit is used to store n bits; According to the operation mode, determining the critical voltage distribution corresponding to the first physical unit to include a plurality of states, wherein a total number of the plurality of states is greater than a predetermined number, and the predetermined number is 2 to the power of n; and Based on the operation mode, a programming operation is performed on the first physical cell to disperse the threshold voltages of a plurality of memory cells in the first physical cell into a plurality of voltage intervals, wherein the plurality of voltage intervals correspond to the plurality of states respectively. 2 . The memory management method according to claim 1 , wherein at least two states of the plurality of states correspond to the same bit sequence.

3. The memory management method according to claim 2, wherein the at least two states include a first state and a second state, the first state corresponds to a first voltage interval among the multiple voltage intervals, the second state corresponds to a second voltage interval among the multiple voltage intervals, and the first voltage interval and the second voltage interval do not overlap with each other.

4. The memory management method according to claim 3, wherein the plurality of memory cells include a first memory cell and a second memory cell, and based on the operation mode, the step of performing the programming operation on the first physical cell to disperse the threshold voltages of the plurality of memory cells in the first physical cell into the plurality of voltage intervals comprises: Through the programming operation, the first critical voltage of the first storage unit is adjusted to the first voltage range, so that the first storage unit stores a target bit sequence; as well as Through the programming operation, the second critical voltage of the second storage unit is adjusted to the second voltage range, so that the second storage unit also stores the target bit sequence.

5. The memory management method according to claim 1, wherein based on the operation mode, the step of performing the programmed operation on the first physical unit comprises: determining a target storage unit from among the plurality of storage units; determining a target state from the plurality of states, wherein the target state corresponds to a target voltage interval from the plurality of voltage intervals; adjusting a programming parameter corresponding to the target storage unit according to the target state; as well as The target threshold voltage of the target memory cell is changed according to the programming parameter so that the target threshold voltage moves to the target voltage range.

6. The memory management method according to claim 5, wherein the programmed parameters include at least one of a programmed time sequence and a programmed voltage pulse amplitude, the programmed time sequence is used to control the duration of a voltage pulse applied to the target memory cell at least once, and the programmed voltage pulse amplitude is used to control the voltage value of the voltage pulse.

7. The memory management method according to claim 1, further comprising: Based on the operation mode, performing a read operation on the first physical unit to determine a target voltage interval where a target critical voltage of a target memory cell is located; as well as According to the target voltage interval, determining that the target bit sequence stored in the target storage unit is one of a plurality of candidate bit sequences, The total number of the plurality of candidate bit sequences is equal to the predetermined number.

8. The memory management method according to claim 1, further comprising: evaluating a loss state of the first entity unit; as well as The total number of the plurality of states is adjusted based on the wear state. 9 . The memory management method according to claim 8 , wherein the total number of the plurality of states is positively correlated to a degree of wear of the first physical unit, and the degree of wear is negatively correlated to a reliability of data stored in the first physical unit.

10. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: Determining an operation mode of a first physical unit among the plurality of physical units, wherein in the operation mode, each storage unit in the first physical unit is used to store n bits; According to the operation mode, determining the critical voltage distribution corresponding to the first entity unit to include a plurality of states, wherein the total number of the plurality of states is greater than a predetermined number, and the predetermined number is 2 to the power of n; as well as Based on the operation mode, a programming operation is performed on the first physical cell to disperse the threshold voltages of a plurality of memory cells in the first physical cell into a plurality of voltage intervals, wherein the plurality of voltage intervals correspond to the plurality of states respectively. The memory device of claim 10 , wherein at least two of the plurality of states correspond to the same bit sequence.

12. The storage device according to claim 11, wherein the at least two states include a first state and a second state, the first state corresponds to a first voltage interval among the multiple voltage intervals, the second state corresponds to a second voltage interval among the multiple voltage intervals, and the first voltage interval and the second voltage interval do not overlap with each other.

13. The storage device according to claim 12, wherein the plurality of storage units include a first storage unit and a second storage unit, and the memory controller performs the programming operation on the first physical unit based on the operation mode, comprising: By means of the programming operation, the first critical voltage of the first storage unit is adjusted to the first voltage range, so that the first storage unit stores a target bit sequence; as well as Through the programming operation, the second critical voltage of the second storage unit is adjusted to the second voltage range, so that the second storage unit also stores the target bit sequence.

14. The storage device according to claim 10, wherein the memory controller performs the programming operation on the first physical unit based on the operation mode, comprising: determining a target storage unit from among the plurality of storage units; determining a target state from the plurality of states, wherein the target state corresponds to a target voltage interval from the plurality of voltage intervals; adjusting a programming parameter corresponding to the target storage unit according to the target state; as well as The target threshold voltage of the target memory cell is changed according to the programming parameter so that the target threshold voltage moves to the target voltage range.

15. The storage device according to claim 14, wherein the programming parameters include at least one of a programming time sequence and a programming voltage pulse amplitude, wherein the programming time sequence is used to control the duration of at least one voltage pulse applied to the target storage unit, and the programming voltage pulse amplitude is used to control the voltage value of the voltage pulse.

16. The storage device according to claim 10, wherein the memory controller is further configured to: Based on the operation mode, performing a read operation on the first physical cell to determine a target voltage interval where a critical voltage of a target memory cell among the plurality of memory cells lies; and According to the target voltage range, determining that the bit sequence stored in the target storage unit is one of a plurality of candidate bit sequences, The total number of the plurality of candidate bit sequences is equal to the predetermined number.

17. The storage device according to claim 10, wherein the memory controller is further configured to: evaluating a wear state of the first physical element; and The total number of the plurality of states is adjusted based on the wear state. 18 . The storage device of claim 17 , wherein the total number of the plurality of states is positively correlated to a degree of wear of the first physical unit, and the degree of wear is negatively correlated to a reliability of data stored in the first physical unit.

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