A memory and a mode switching method

Abstract

The present invention provides a memory and a mode switching method. The memory includes: a flash chip; a main controller connected to the flash chip; a ball grid array package pad connected to the main controller; a flash interface pad connected to the flash chip; wherein, the main controller is configured to determine the state of the ball grid array package pad: when the ball grid array package pad is in a normal state, the main controller controls the line for communicating with the flash chip to be in a conducting state, and the flash chip interacts with an electronic device sequentially through the main controller and the ball grid array package pad; when the ball grid array package pad is in an abnormal state, the main controller controls the line for communicating with the flash chip to be in a disconnected state, and the flash chip interacts with other storage devices through the flash interface pad. Through the memory and the mode switching method provided by the present invention, a memory with an abnormal interface can be reused.

Description

Technical Field

[0001] The present invention relates to the field of storage, and particularly to a memory and a mode switching method. Background Art

[0002] An embedded multimedia card (eMMC) is an embedded memory integrating a main controller and a flash memory chip (NAND Flash), which communicates with an electronic device through a standardized bus interface and is widely used in terminals such as mobile phones, tablet computers, and smart TVs. Since a large number of memories are produced in a batch, it is inevitable that some memories have faults such as communication anomalies. When the memory has a communication anomaly due to a bus interface fault, the prior art usually adopts the following two processing methods: scrapping the whole memory, and disassembling and recycling the memory.

[0003] When scrapping the whole memory, since the damage states of the main controller and the flash memory chip cannot be distinguished, it may lead to waste of the internal intact flash memory chip resources and a significant increase in cost. When disassembling and recycling the memory, although the flash memory chip can be separated through an opening process for secondary use, this process is complex, costly, and prone to physical damage, and its practical application value is limited. Therefore, there is room for improvement. Summary of the Invention

[0004] The purpose of the present invention is to provide a memory and a mode switching method, which can reuse a memory with an abnormal interface.

[0005] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0006] The present invention provides a memory, including:

[0007] A flash memory chip;

[0008] A main controller, connected to the flash memory chip;

[0009] A ball grid array package pad, connected to the main controller;

[0010] A flash memory interface pad, connected to the flash memory chip;

[0011] Wherein, the main controller is used to judge the state of the ball grid array package pad:

[0012] When the ball grid array package pad is in a normal state, the main controller controls the line for communicating with the flash memory chip to be in a conducting state, and the flash memory chip interacts with the electronic device through the main controller and the ball grid array package pad in sequence;

[0013] When the ball grid array package pads are in an abnormal state, the main controller controls the line for communicating with the flash memory chip to be in a disconnected state, and the flash memory chip interacts with other storage devices through the flash interface pads.

[0014] In an embodiment of the present invention, the flash interface pads include a plurality of signal solder balls, and each signal solder ball of the flash interface pads is correspondingly connected to a signal pin of the flash memory chip.

[0015] In an embodiment of the present invention, the flash interface pads further include verification solder balls, and the verification solder balls of the flash interface pads are connected to the verification pins of the main controller;

[0016] When the ball grid array package pads are in a normal state, the level states of the verification pins of the main controller and the verification solder balls of the flash interface pads are configured to be in a low level state, and the main controller controls its signal pins and the signal pins of the flash memory chip to be in a conducting state;

[0017] When the ball grid array package pads are in an abnormal state, the level states of the verification pins of the main controller and the verification solder balls of the flash interface pads are configured to be in a high level state, and the main controller controls its signal pins and the signal pins of the flash memory chip to be in a disconnected state.

[0018] In an embodiment of the present invention, when the ball grid array package pads are in an abnormal state, the verification solder balls of the flash interface pads are connected to the interface power supply pins of other storage devices, and the interface power supply pins are used to adjust the level states of the verification pins of the main controller and the verification solder balls of the flash interface pads.

[0019] In an embodiment of the present invention, when the ball grid array package pads are in an abnormal state, each signal solder ball of the flash interface pads is correspondingly connected to the signal pins of the main controllers of other storage devices.

[0020] In an embodiment of the present invention, the signal solder balls and the verification solder balls of the flash interface pads are distributed on the periphery of the ball grid array package pads.

[0021] In an embodiment of the present invention, the main controller detects the working state of the ball grid array package pads according to the following steps:

[0022] Connect the memory to the electronic device;

[0023] Detect the connection states of each signal solder ball and each power supply solder ball in the ball grid array package pads:

[0024] When at least one signal solder ball in the ball grid array package pad is in an open state, and / or when at least one power supply solder ball in the ball grid array package pad is in an open state, it is determined that the ball grid array package pad is in an abnormal state;

[0025] Otherwise, it is determined that the ball grid array package pad is in a normal state.

[0026] In an embodiment of the present invention, when the ball grid array package pad is in a normal state, the memory communicates with the electronic device through the embedded multimedia card protocol.

[0027] In an embodiment of the present invention, when the ball grid array package pad is in an abnormal state, the memory communicates with the other storage device through the open NAND flash interface protocol or the switching mode protocol.

[0028] The present invention also discloses a method for switching the mode of a memory. The memory includes a flash chip, a main controller, a ball grid array package pad, and a flash interface pad. The mode switching method includes:

[0029] Judge the state of the ball grid array package pad through the main controller:

[0030] When the ball grid array package pad is in a normal state, the main controller controls the line for communicating with the flash chip to be in a conducting state, and the flash chip interacts with the electronic device through the main controller and the ball grid array package pad in sequence;

[0031] When the ball grid array package pad is in an abnormal state, the main controller controls the line for communicating with the flash chip to be in an open state, and the flash chip interacts with the other storage device through the flash interface pad.

[0032] As described above, the present invention provides a memory and a mode switching method, which can realize the secondary utilization of the flash chip at a low cost in the case of damage or signal abnormality of the memory interface. When the interface is damaged, the memory can be directly used as the flash of other storage devices, and can be reused without additional cost, improving resource utilization and reducing maintenance costs.

[0033] Of course, it is not necessary for any product implementing the present invention to achieve all the above advantages at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0035] Figure 1 Schematic diagram of a memory in an embodiment of the present invention;

[0036] Figure 2 Circuit diagram of a ball grid array package pad in an embodiment of the present invention;

[0037] Figure 3 Circuit diagram of a main controller in an embodiment of the present invention;

[0038] Figure 4 [[ID=1⑥]]Circuit diagram of a flash memory chip in an embodiment of the present invention;

[0039] Figure 5 Circuit diagram of a flash memory interface pad in an embodiment of the present invention.

[0040] In the figure: 100, flash memory chip; 200, main controller; 300, ball grid array package pad; 400, flash memory interface pad. Specific embodiments

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0042] Please refer to Figure 1 , the present invention discloses a memory, which can be an Embedded MultiMedia Card (eMMC) or a Universal Flash Storage (UFS). The memory can communicate with an electronic device through the CMD line and the DATA0~7 lines, and execute operations such as reading, writing, and erasing by receiving instructions from the electronic device. The electronic device can send instructions through the CMD line and transmit data through the DATA0~7 lines. The communication protocol between the memory and the electronic device can follow the JEDEC protocol. The memory can include a flash memory chip 100, a main controller 200, a ball grid array package pad 300, a flash memory interface pad 400, and a substrate.

[0043] In some embodiments, the flash memory chip 100 (NAND Flash) can be the core storage unit for persistent data storage. The flash memory chip 100 can store data through charge trapping or floating gate transistors, and the read / write lifespan of the flash memory chip 100 is limited by the number of erase / write cycles.

[0044] In some embodiments, the main controller 200 can be a microcontroller unit (MCU). The main controller 200 can be used to execute specific control tasks, such as reading data, processing instructions from electronic devices, etc. The CPU core of the main controller 200 can be designed based on the RISC-V architecture to execute various control and computing tasks.

[0045] In some embodiments, the ball grid array package pad 300 (BGA pad) can serve as the physical and electrical interface between the main controller 200 and the electronic device to achieve signal transmission and power supply.

[0046] In some embodiments, the flash memory interface pad 400 can serve as the physical and electrical interface between the flash memory chip 100 and other storage devices to achieve signal transmission and power supply.

[0047] In some embodiments, the substrate can be a multi-layer PCB substrate that carries the flash memory chip 100, the main controller 200, the ball grid array package pad 300, and the flash memory interface pad 400. The substrate can be used to provide electrical interconnection and mechanical support.

[0048] In some embodiments, in mass-produced memories, the ball grid array package pad 300, as the key physical interface between the main controller 200 and the electronic device, may cause some pads to fail due to manufacturing process fluctuations or material defects. For example, physical damage may occur to the ball grid array package pad 300, such as the breakage of sub-pads or the detachment of solder balls, resulting in an interruption of the electrical connection. Another example is that the signal integrity of the ball grid array package pad 300 is abnormal, such as an open circuit, short circuit, or impedance mismatch in the I / O signals (CMD / CLK / DAT lines) of the eMMC bus, causing communication errors or data corruption.

[0049] In some embodiments, the main controller 200 can be used to determine the status of the ball grid array package pad 300: when the ball grid array package pad 300 is in a normal state, the main controller 200 controls the line for communicating with the flash memory chip 100 to be in a conducting state, and the flash memory chip 100 interacts with the electronic device through the main controller 200 and the ball grid array package pad 300 in sequence; when the ball grid array package pad 300 is in an abnormal state, the main controller 200 controls the line for communicating with the flash memory chip 100 to be in a disconnected state, and the flash memory chip 100 interacts with other storage devices through the flash memory interface pad 400.

[0050] In some embodiments, when the ball grid array package pad 300 is in a normal state, the electronic device can send control instructions through the ball grid array package pad 300. The main controller 200 parses the control instructions and controls the flash memory chip 100 to perform operations. After the flash memory chip 100 performs the operations, it can return the original data to the main controller 200, and after error correction and format conversion, it is sent back to the electronic device through the ball grid array package pad 300. When the ball grid array package pad 300 is in a normal state, communication can be carried out between the memory and the electronic device through the embedded multimedia card protocol.

[0051] In some embodiments, when the ball grid array package pad 300 is in an abnormal state, the electronic device cannot send control instructions through the ball grid array package pad 300. Since the flash memory chip 100 may be intact, the memory can continue to work using the intact flash memory chip 100, avoiding scrapping of the entire memory. At this time, this memory can be used as the flash memory of other storage devices. By being installed on the substrate of other storage devices, the main controller of other storage devices can interact with the flash memory chip 100 of this memory through the flash memory interface pad 400. When the ball grid array package pad 300 is in an abnormal state, communication can be carried out between the memory and other storage devices through the open NAND flash memory interface protocol or the switching mode protocol.

[0052] In some embodiments, the flash memory interface pad 400 can include multiple signal solder balls and power supply solder balls. Each signal solder ball of the flash memory interface pad 400 can be correspondingly connected to the signal pin of the flash memory chip 100. Each power supply solder ball of the flash memory interface pad 400 can be correspondingly connected to the power pin of the flash memory chip 100. The signal solder balls of the flash memory interface pad 400 can be used to transmit data signals, control signals, clock signals, etc. The power supply solder balls of the flash memory interface pad 400 can be used to provide core power supply (such as VCC) and ground (GND) connections.

[0053] In some embodiments, the signal solder balls of the flash memory interface pad 400 are connected to the signal pins of the flash memory chip 100 through the traces on the substrate to achieve the transmission of data and control signals. The power supply solder balls of the flash memory interface pad 400 are connected to the power pins of the flash memory chip 100 through the power layer on the substrate to provide necessary power supply and ground. The flash memory interface pad 400 can be packaged in the form of a ball grid array (BGA), and the solder balls are evenly distributed at the bottom of the substrate, facilitating soldering and signal transmission.

[0054] In some embodiments, each signal solder ball can transmit specific signals (such as data lines, address lines, control lines, etc.). Each signal solder ball is connected to a signal pin of the flash memory chip 100 in a one-to-one correspondence. For example, if the flash memory chip 100 has 8 data pins (such as F0D0~F0D7), then the flash memory interface pad 400 needs to have 8 signal solder balls respectively connected thereto. Another example is that if the flash memory chip 100 has control signal pins (such as CE, WE, etc.), then the flash memory interface pad 400 also needs to have corresponding signal solder balls connected thereto. Through the signal solder balls, the flash memory chip 100 can transmit data and control signals with other storage devices.

[0055] In some embodiments, each power supply solder ball can provide a core power supply or a ground connection. Each power supply solder ball is connected to a power pin of the flash memory chip 100 in a one-to-one correspondence. For example, if the flash memory chip 100 requires a 3.3V power supply and ground pins, then the flash memory interface pad 400 needs to have at least two power supply solder balls respectively connected to VCC and GND. Through the power supply solder balls, the flash memory chip 100 can obtain a stable power supply to ensure its normal operation.

[0056] In some embodiments, the flash memory interface pad 400 further includes a verification solder ball, and the verification solder ball of the flash memory interface pad 400 is connected to a verification pin of the main controller 200. The verification solder ball is a special solder ball in the flash memory interface pad 400 for connecting to the verification pin of the main controller 200. Through the level state (high level or low level) of the verification solder ball, the main controller 200 can judge the working state of the current ball grid array package pad 300 and adjust the connection mode between the main controller 200 and the flash memory chip 100.

[0057] In some embodiments, when the ball grid array package pad 300 is in a normal state, the level state of the verification pin of the main controller 200 and the verification solder ball of the flash memory interface pad 400 is configured to be in a low level state, and the main controller 200 controls its signal pins and the signal pins of the flash memory chip 100 to be in a conducting state.

[0058] In some embodiments, when the ball grid array package pad 300 is working properly, the main controller 200 communicates with the electronic device through the ball grid array package pad 300 while maintaining a direct connection with the flash memory chip 100. At this time, the signal pins of the main controller 200 and the signal pins of the flash memory chip 100 are in a conducting state, that is, data and control signals can be transmitted normally. The power supply pins of the main controller 200 and the power supply pins of the flash memory chip 100 are also in a conducting state to ensure that the flash memory chip 100 obtains a power supply.

[0059] In some embodiments, when the ball grid array package pad 300 is in an abnormal state, the level states of the verification pins of the main controller 200 and the verification solder balls of the flash interface pad 400 are configured to be in a high level state, and the main controller 200 controls its signal pins and the signal pins of the flash chip 100 to be in a disconnected state.

[0060] In some embodiments, when an abnormality occurs in the ball grid array package pad 300 (such as pad breakage or signal integrity failure), the main controller 200 detects the abnormality through the verification solder balls and disconnects the direct connection with the flash chip 100, that is, data and control signals cannot be transmitted. At this time, the power supply pins of the main controller 200 and the power supply pins of the flash chip 100 are also in a disconnected state, cutting off the power supply.

[0061] In some embodiments, when the ball grid array package pad 300 is in an abnormal state, the verification solder balls of the flash interface pad 400 are connected to the interface power supply pins (VCCQ) of other storage devices, and the interface power supply pins are used to adjust the level states of the verification pins of the main controller 200 and the verification solder balls of the flash interface pad 400. When the ball grid array package pad 300 is in an abnormal state, each signal solder ball of the flash interface pad 400 is correspondingly connected to the signal pins of the main controller of other storage devices.

[0062] In some embodiments, the interface power supply pins can be used to provide an interface power supply (such as 1.8V or 3.3V) to adjust the level state of the verification solder balls. When the ball grid array package pad 300 is abnormal, the verification solder balls of the flash interface pad 400 are connected to the VCCQ pins of other storage devices. The high-level signal of the VCCQ pins is transmitted to the verification pins of the main controller 200 through the verification solder balls, configuring it to a high level state. Subsequently, each signal solder ball of the flash interface pad 400 is correspondingly connected to the signal pins of the main controller of other storage devices one by one to use this memory as the flash memory of other storage devices. For example, the 8 signal solder balls (F0D0~F0D7) of the flash interface pad 400 are respectively connected to the 8 data pins of the main controller of other storage devices. Through the signal solder balls, the flash chip 100 can transmit data and control signals with the main controller of other storage devices.

[0063] In some embodiments, the signal solder balls and verification solder balls of the flash memory interface pad 400 may be distributed around the periphery of the ball grid array package pad 300. The solder balls of the ball grid array package pad 300 may be arranged in a matrix form, divided into a core area and a peripheral area. The core area can be used to place signal solder balls or power / ground solder balls. The peripheral area is generally used to place auxiliary signal solder balls, test solder balls or special function solder balls. The signal solder balls and verification solder balls of the flash memory interface pad 400 may be located in the peripheral area of the ball grid array package pad 300, rather than the core area. This distribution method can facilitate wiring, testing or connection to other devices. By placing the signal solder balls and verification solder balls in the peripheral area, the wiring complexity of the core area can be reduced and signal interference can be avoided. The solder balls in the peripheral area are usually connected to the traces at the edge of the substrate, which is convenient for signal transmission.

[0064] In some embodiments, the main controller 200 detects the working state of the ball grid array package pad 300 according to the following steps: connect the memory to the electronic device; detect the connection state of each signal solder ball and each power supply solder ball in the ball grid array package pad 300: when there is at least one signal solder ball in the ball grid array package pad 300 in a disconnected state, and / or, when there is at least one power supply solder ball in the ball grid array package pad 300 in a disconnected state, determine that the ball grid array package pad 300 is in an abnormal state; otherwise, determine that the ball grid array package pad 300 is in a normal state.

[0065] In some embodiments, Figure 2 shows the circuit diagram of the ball grid array package pad 300, Figure 3 shows the circuit diagram of the main controller 200. As Figure 2 and Figure 3As shown, the main controller 200 may be of model KS6581, and the ball grid array package pad 300 may be of model BGA153. Each Vcc power supply solder ball of the ball grid array package pad 300 may be electrically connected to the core power supply (VCC) of the electronic device. Each VccQ signal solder ball of the ball grid array package pad 300 may be electrically connected to the core power supply (VCCQ) of the electronic device. The RESET signal solder ball of the ball grid array package pad 300 may be electrically connected to pin 31 (EMMC_RSTn) of the main controller 200. The VDDI signal solder ball of the ball grid array package pad 300 may be electrically connected to all VCCK signal pins of the main controller 200. The CMD signal solder ball of the ball grid array package pad 300 may be electrically connected to pin 33 (EMMC_CMD) of the main controller 200. The CLK signal solder ball of the ball grid array package pad 300 may be electrically connected to pin 35 (EMMC_CLK) of the main controller 200. The DS signal solder ball of the ball grid array package pad 300 can be electrically connected to pin 29 (EMMC_RCLK) of the main controller 200. The DAT0~7 signal solder balls of the ball grid array package pad 300 can be electrically connected to pins 14 (EMMC_DAT[0]), 19 (EMMC_DAT[1]), 23 (EMMC_DAT[2]), 12 (EMMC_DAT[3]), 16 (EMMC_DAT[4]), 20 (EMMC_DAT[5]), 25 (EMMC_DAT[6]), and 27 (EMMC_DAT[7]) of the main controller 200, respectively.

[0066] In some embodiments, Figure 4 shows a circuit diagram of a flash memory chip 100, Figure 5 FIG. 4 shows a circuit diagram of the flash memory interface pad 400. Figure 3 、 Figure 4 and Figure 5As shown, all VSS pins of the flash memory chip 100 are grounded. Each VCC pin of the flash memory chip 100 can be electrically connected to the corresponding Vcc power supply solder ball of the ball grid array package pad 300. At the same time, each VCC pin of the flash memory chip 100 can be electrically connected to the T25 or T26 power supply solder ball of the flash memory interface pad 400. Each VCCQ pin of the flash memory chip 100 can be electrically connected to the corresponding VCCIO2 power supply pin of the main controller 200. At the same time, each VCCQ pin of the flash memory chip 100 can be electrically connected to the T21 or T22 power supply solder ball of the flash memory interface pad 400. The IO0~IO7 signal pins of the flash memory chip 100 can be electrically connected to the 52nd pin (F0_D[0]), 54th pin (F0_D[1]), 56th pin (F0_D[2]), 57th pin (F0_D[3]), 62nd pin (F0_D[4]), 63rd pin (F0_D[5]), 65th pin (F0_D[6]), and 66th pin (F0_D[7]) of the main controller 200 respectively. At the same time, the IO0~IO7 signal pins of the flash memory chip 100 can be electrically connected to the T24 signal solder ball, T9 signal solder ball, T18 signal solder ball, T5 signal solder ball, T13 signal solder ball, T15 signal solder ball, T19 signal solder ball, and T16 signal solder ball of the flash memory interface pad 400 respectively. The / RE signal pin of the flash memory chip 100 can be electrically connected to the 43rd signal pin (F0_REn) of the main controller 200 and the T20 signal solder ball of the flash memory interface pad 400 at the same time. The RE signal pin of the flash memory chip 100 can be electrically connected to the 42nd signal pin (F0_RE) of the main controller 200 and the T7 signal solder ball of the flash memory interface pad 400 at the same time. The WP signal pin of the flash memory chip 100 can be electrically connected to the 49th signal pin (F0_WPn) of the main controller 200 and the T11 signal solder ball of the flash memory interface pad 400 at the same time. The WE signal pin of the flash memory chip 100 can be electrically connected to the 48th signal pin (F0_WEn) of the main controller 200 and the T4 signal solder ball of the flash memory interface pad 400 at the same time. The RB0 signal pin of the flash memory chip 100 can be electrically connected to the 40th signal pin (RB0) of the main controller 200 and the T17 signal solder ball of the flash memory interface pad 400 at the same time. The RB1 signal pin of the flash memory chip 100 can be electrically connected to the 39th signal pin (RB1) of the main controller 200 and the T12 signal solder ball of the flash memory interface pad 400 at the same time. The CE0 signal pin of the flash memory chip 100 can be electrically connected to the 72nd signal pin (CE[0]) of the main controller 200 and the T8 signal solder ball of the flash memory interface pad 400 at the same time. The CE1 signal pin of the flash memory chip 100 can be electrically connected to the 71st signal pin (CE[1]) of the main controller 200 and the T3 signal solder ball of the flash memory interface pad 400 at the same time.The VREF signal pin of the flash memory chip 100 can be electrically connected to the 68th signal pin (VREFO) of the main controller 200 and the T23 signal solder ball of the flash memory interface pad 400 at the same time. The CLE signal pin of the flash memory chip 100 can be electrically connected to the 45th signal pin (F0_CLE) of the main controller 200 and the T1 signal solder ball of the flash memory interface pad 400 at the same time. The ALE signal pin of the flash memory chip 100 can be electrically connected to the 46th signal pin (F0_ALE) of the main controller 200 and the T14 signal solder ball of the flash memory interface pad 400 at the same time.

[0067] Please refer to Figure 3 and Figure 5 , in some embodiments, the T25 and T26 power supply solder balls of the flash memory interface pad 400 can be electrically connected to the core power supply of other storage devices. The T21 and T22 power supply solder balls of the flash memory interface pad 400 can be electrically connected to the interface power supply of other storage devices. The verification solder ball of the flash memory interface pad 400 can be the T27 verification solder ball, and the T27 verification solder ball can be electrically connected to the 81st signal pin (TEST_EXT) of the main controller 200, and the 81st signal pin of the main controller 200 can be a verification pin. The T2 power supply solder ball of the flash memory interface pad 400 can be grounded.

[0068] It can be seen that in the above solution, in the case of damage or signal abnormality of the interface of the memory, the flash memory chip can be reused at a low cost. When the interface is damaged, the memory can be directly used as the flash memory of other storage devices, and it can be reused without additional cost, improving resource utilization and reducing maintenance costs.

[0069] The present invention also provides a method for switching the mode of a memory. The mode switching method can be applied to the above memory, and the mode switching method can be as follows:

[0070] Judge the state of the ball grid array package pad through the main controller:

[0071] When the ball grid array package pad is in a normal state, the main controller controls the line for communicating with the flash memory chip to be in a conducting state, and the flash memory chip interacts with the electronic device through the main controller and the ball grid array package pad in sequence;

[0072] When the ball grid array package pad is in an abnormal state, the main controller controls the line for communicating with the flash memory chip to be in a disconnected state, and the flash memory chip interacts with other storage devices through the flash memory interface pad.

[0073] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification in order to better explain the principle and practical application of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A memory, characterized in that, Comprising: A flash memory chip; A main controller, connected to the flash memory chip; Ball grid array package pads, connected to the main controller; Flash memory interface pads, connected to the flash memory chip; Wherein, the main controller is used to judge the state of the ball grid array package pads: When the ball grid array package pads are in a normal state, the main controller controls the line for communicating with the flash memory chip to be in a conducting state, and the flash memory chip interacts with the electronic device through the main controller and the ball grid array package pads in sequence; When the ball grid array package pads are in an abnormal state, the main controller controls the line for communicating with the flash memory chip to be in a disconnected state, and the flash memory chip interacts with other storage devices through the flash memory interface pads.

2. The memory according to claim 1, wherein The flash memory interface pads include a plurality of signal solder balls, and each signal solder ball of the flash memory interface pads is correspondingly connected to a signal pin of the flash memory chip.

3. The memory according to claim 2, characterized in that, The flash memory interface pads further include check solder balls, and the check solder balls of the flash memory interface pads are connected to check pins of the main controller; When the ball grid array package pads are in a normal state, the level states of the check pins of the main controller and the check solder balls of the flash memory interface pads are configured to be in a low level state, and the main controller controls its signal pins to be in a conducting state with the signal pins of the flash memory chip; When the ball grid array package pads are in an abnormal state, the level states of the check pins of the main controller and the check solder balls of the flash memory interface pads are configured to be in a high level state, and the main controller controls its signal pins to be in a disconnected state with the signal pins of the flash memory chip.

4. The memory according to claim 3, wherein, When the ball grid array package pads are in an abnormal state, the check solder balls of the flash memory interface pads are connected to interface power supply pins of other storage devices, and the interface power supply pins are used to adjust the level states of the check pins of the main controller and the check solder balls of the flash memory interface pads.

5. The memory according to claim 3, wherein When the ball grid array package pads are in an abnormal state, each signal solder ball of the flash memory interface pads is correspondingly connected to a signal pin of the main controller of other storage devices.

6. The memory according to claim 3, wherein The signal solder balls and check solder balls of the flash memory interface pads are distributed on the periphery of the ball grid array package pads.

7. The memory according to claim 1, characterized in that, The main controller detects the working state of the ball grid array package pads according to the following steps: Connect the memory to the electronic device; Detect the connection states of each signal solder ball and each power supply solder ball in the ball grid array package pads: When at least one signal solder ball in the ball grid array package pads is in a disconnected state, and / or when at least one power supply solder ball in the ball grid array package pads is in a disconnected state, it is determined that the ball grid array package pads are in an abnormal state; Otherwise, it is determined that the ball grid array package pads are in a normal state.

8. The memory according to claim 1, wherein When the ball grid array package pads are in a normal state, the memory communicates with the electronic device through the embedded multimedia card protocol.

9. The memory according to claim 1, wherein When the ball grid array package pads are in an abnormal state, the memory communicates with the other storage devices through the open NAND flash memory interface protocol or the switching mode protocol.

10. A method for mode switching of a memory, characterized in that The memory includes a flash chip, a main controller, ball grid array package pads, and flash interface pads. The mode switching method includes: Judging the state of the ball grid array package pads by the main controller: When the ball grid array package pads are in a normal state, the main controller controls the line for communicating with the flash chip to be in a conducting state, and the flash chip interacts with the electronic device through the main controller and the ball grid array package pads in sequence; When the ball grid array package pads are in an abnormal state, the main controller controls the line for communicating with the flash chip to be in a disconnected state, and the flash chip interacts with other storage devices through the flash interface pads.

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