Error correction code engine of semiconductor memory device and semiconductor memory device

Abstract

An ECC engine of a semiconductor memory device includes an ECC encoder and an ECC decoder. The ECC encoder generates parity data based on the master data based on the primitive polynomial, and stores a codeword including the master data and the parity data in a target page. An ECC decoder reads a codeword from a target page based on an address to generate syndromes, and generates the codeword by applying different syndromes to a single bit error in the read codeword, adjacent bit errors, and non-adjacent bit errors occurring in two non-adjacent memory cells in the target page, respectively. At least one error bit in the read codeword is corrected based on the syndrome. The ECC decoder generates different syndromes based on a parity check matrix generated from a primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to the Galois field.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0190904, filed on December 26, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Example embodiments of the present disclosure generally relate to storage devices, and more particularly, to an error correction code (ECC) engine for a semiconductor storage device and a semiconductor storage device including the ECC engine. Background art

[0004] Semiconductor storage devices can be classified into non - volatile storage devices (e.g., flash memory devices) and volatile storage devices (e.g., dynamic random access memory (DRAM) devices). DRAM devices are generally used for system memory due to their high - speed operation and cost - efficiency. Due to the continuous reduction of the manufacturing design rules of DRAM devices, bit errors in the memory cells of DRAM devices may increase, and the yield of DRAM devices may decrease. Summary of the invention

[0005] Some example embodiments of the present disclosure provide an error correction code (ECC) engine for a semiconductor storage device, which can enhance performance and reliability.

[0006] Some example embodiments of the present disclosure provide a semiconductor storage device capable of enhancing performance and reliability.

[0007] According to some example embodiments, the ECC engine of a semiconductor storage device includes an ECC encoder and an ECC decoder. The ECC encoder generates parity data based on main data by using ECC based on a primitive polynomial, and stores a codeword including the main data and the parity data in a target page of a memory cell array. The ECC decoder reads the codeword from the target page based on an address to generate a syndrome, and corrects at least one error bit in the read codeword based on the syndrome by applying different syndromes to a single - bit error in the read codeword, an adjacent - bit error occurring in two adjacent memory cells in the target page, and a non - adjacent - bit error occurring in two non - adjacent memory cells in the target page. The ECC decoder generates different syndromes based on a parity check matrix, which is based on a default parity check matrix generated according to the primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to the Galois field (also known as a finite field).

[0008] According to some example embodiments, a semiconductor memory device includes a memory cell array, an ECC engine, and a control logic circuit. The memory cell array includes a plurality of volatile memory cells that are connected to a plurality of word lines and a plurality of bit lines. The ECC engine generates parity data based on main data by using ECC according to a primitive polynomial, stores a codeword including the main data and the parity data in a target page of the memory cell array, reads the codeword from the target page based on an address to generate a syndrome, and corrects at least one error bit in the read codeword based on the syndrome by applying different syndromes to a single-bit error in the read codeword, an adjacent bit error occurring in two adjacent memory cells in the target page, and a non-adjacent bit error occurring in two non-adjacent memory cells in the target page. The control logic circuit controls the ECC engine based on a command and an address. The ECC engine generates different syndromes based on a parity check matrix that is based on a default parity check matrix generated according to the primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to a Galois field.

[0009] According to some example embodiments, a semiconductor memory device includes a memory cell array, an ECC engine, and a control logic circuit. The memory cell array includes a plurality of volatile memory cells that are connected to a plurality of word lines and a plurality of bit lines. The ECC engine generates parity data based on main data by using ECC according to a primitive polynomial, stores a codeword including the main data and the parity data in a target page of the memory cell array, reads the codeword from the target page based on an address to generate a syndrome, and corrects at least one error bit in the read codeword based on the syndrome by applying different syndromes to a single-bit error in the read codeword, an adjacent bit error occurring in two adjacent memory cells in the target page, and a non-adjacent bit error occurring in two non-adjacent memory cells in the target page. The control logic circuit controls the ECC engine based on a command and an address. The ECC engine includes an ECC decoder that generates different syndromes based on a parity check matrix that is based on a default parity check matrix generated according to the primitive polynomial. The primitive polynomial has an alpha matrix as a solution belonging to a Galois field. The ECC decoder generates a first sub-check matrix and a second sub-check matrix by using the parity check matrix based on the least significant bit (LSB) of the row address of the address, corrects an adjacent bit error by applying the first sub-check matrix to the read codeword in response to the LSB of the row address being low, and corrects an adjacent bit error or a non-adjacent bit error by applying the second sub-check matrix to the read codeword in response to the LSB of the row address being high.

[0010] Accordingly, an ECC engine on a die and a semiconductor memory device including the ECC engine on the die can correct a single-bit error, an adjacent two-bit error, or a non-adjacent two-bit error by applying different syndromes to the single-bit error and the two-bit error using a single parity check matrix, thereby improving the error correction efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other features of the present disclosure will become more apparent by describing exemplary embodiments of the present disclosure in detail with reference to the accompanying drawings, in which like reference numerals (when used) in the multiple views denote corresponding elements.

[0012] Figure 1 is a schematic block diagram showing a storage system according to some exemplary embodiments.

[0013] Figure 2 shows, according to some exemplary embodiments, Figure 1 main data corresponding to multiple burst lengths in a storage system of.

[0014] Figure 3 is a schematic block diagram showing an example of a Figure 1 storage controller shown in according to some exemplary embodiments.

[0015] Figure 4 is a schematic block diagram showing an example of an Figure 3 ECC decoder shown in according to some exemplary embodiments.

[0016] Figure 5 is a schematic block diagram showing an example of a Figure 1 semiconductor memory device shown in according to some exemplary embodiments.

[0017] Figure 6 shows, according to some exemplary embodiments, Figure 5 an example of a first bank array in a semiconductor memory device of.

[0018] Figure 7 shows, according to some exemplary embodiments, Figure 5 an example of a first bank array in a semiconductor memory device of.

[0019] Figure 8 shows, according to some exemplary embodiments, Figure 7 at least a portion of the first bank array shown in.

[0020] Figure 9 shows at least a portion of a Figure 5 semiconductor memory device configured in a write operation of.

[0021] Figure 10 shows at least a portion of a semiconductor memory device configured in a read operationFigure 5 at least a portion of a semiconductor memory device.

[0022] Figure 11 is a schematic block diagram showing an example of an on-die ECC engine in a semiconductor memory device according to some example embodiments. Figure 5 of the semiconductor memory device.

[0023] Figures 12A to 12E Examples of error bits in data patterns stored in subarray blocks according to the least significant bit (LSB) of a row address are shown, respectively.

[0024] Figure 13 is a table showing an example of generating a parity check matrix using a primitive polynomial according to an example embodiment.

[0025] Figure 14 shows an example of ECC generated based on Figure 13 the table according to an example embodiment.

[0026] Figure 15 is a block diagram of an ECC decoder in an on-die ECC engine according to some example embodiments. Figure 11 of the on-die ECC engine.

[0027] Figure 16 An example of a default parity check matrix according to an example embodiment is shown.

[0028] Figure 17 An example of a single-bit error included in main data is shown.

[0029] Figure 18 An example of adjacent two-bit errors included in main data is shown.

[0030] Figure 19 is a schematic block diagram showing an example of a parity check matrix used in an on-die ECC engine according to some example embodiments. Figure 11 of the on-die ECC engine.

[0031] Figure 20 is a schematic block diagram showing an example of a parity check matrix according to some example embodiments. Figure 19 shown.

[0032] Figures 21A to 21E shows Figure 20 the corresponding example of the parity check matrix.

[0033] Figure 22A and Figure 22B show the corresponding examples of a first sub-check matrix generated by using the parity check matrix.

[0034] Figure 23A and Figure 23BShows corresponding examples of a second sub-check matrix generated by using a parity check matrix.

[0035] Figure 24 And Figure 25 Shows an example of generating an odd column vector.

[0036] Figure 26A Is a schematic block diagram showing an example of a syndrome generation circuit in an ECC decoder according to some example embodiments. Figure 15 Of.

[0037] Figure 26B Is an example of a default parity check matrix generated based on a primitive polynomial according to an example embodiment.

[0038] Figure 26C Is a table showing candidate primitive polynomials for generating a default parity check matrix according to an example embodiment.

[0039] Figure 26D Is a block diagram showing an example of a syndrome generation circuit in an ECC decoder according to some example embodiments. Figure 15 Of.

[0040] Figure 27A Is a schematic block diagram showing an example of a selection circuit in an ECC decoder according to some example embodiments. Figure 15 Of.

[0041] Figure 27B Is a schematic block diagram showing an example of a first corrector in an ECC decoder according to some example embodiments. Figure 15 Of.

[0042] Figure 28 Is a flowchart showing a method of operating a semiconductor memory device according to some example embodiments.

[0043] Figure 29 Is a block diagram showing a semiconductor memory device according to some example embodiments.

[0044] Figure 30 Is a configuration diagram showing a semiconductor package including a stacked memory device according to an example embodiment.

[0045] Figure 31 Is a schematic block diagram showing a storage system having a four-column memory module according to an example embodiment. Detailed Description

[0046] Example embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals throughout the drawings may represent like elements.

[0047] Figure 1 is a schematic block diagram showing a storage system according to an exemplary embodiment of the present disclosure.

[0048] Referring to Figure 1 , the storage system 30 may include a storage controller 100 (e.g., an external storage controller) and a semiconductor storage device 200.

[0049] The storage controller 100 may control the overall operation of the storage system 30. The storage controller 100 may control the overall data exchange between an external host (not explicitly shown) and the semiconductor storage device 200. For example, the storage controller 100 may write data to the semiconductor storage device 200 or read data from the semiconductor storage device 200 in response to a request from the host. In addition, the storage controller 100 may issue an operation command to the semiconductor storage device 200 to control the semiconductor storage device 200.

[0050] In an exemplary embodiment, the semiconductor storage device 200 is a storage device including a plurality of dynamic (volatile) storage cells, for example, a dynamic random access memory (DRAM), a double data rate 5 (DDR5) synchronous DRAM (SDRAM), or a DDR6 SDRAM, but the embodiment is not limited thereto.

[0051] The storage controller 100 may send a clock signal CK, a command CMD, and an address (signal) ADDR to the semiconductor storage device 200. Here, for convenience of description, the singular terms clock signal CK, command CMD, and address ADDR may be used interchangeably with the plural terms clock signals CK, commands CMD, and addresses ADDR. When the storage controller 100 writes main data MD to the semiconductor storage device 200, the storage controller 100 may send a data strobe signal DQS to the semiconductor storage device 200. When the storage controller 100 reads main data MD from the semiconductor storage device 200, the semiconductor storage device 200 may send a data strobe signal DQS to the storage controller 100. The address ADDR may accompany the command CMD, and the address ADDR may be referred to as an access address.

[0052] The storage controller 100 may include a central processing unit (CPU) 110 that controls the overall operation of the storage controller 100 and a system ECC engine 130.

[0053] The semiconductor memory device 200 includes a memory cell array 310 that stores main data MD, an error correction circuit (on-die ECC engine) 400, and a control logic circuit 210. The error correction circuit 400 may be referred to as a first error correction circuit. The memory cell array 310 includes a plurality of sub-array blocks arranged along a first direction and a second direction intersecting the first direction. It should be understood that although ordinal terms such as "first" and "second" may be used in this specification to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another and are not intended to convey any specific order of the elements, unless specifically stated. For example, without departing from the scope of the inventive concept, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0054] The system ECC engine 130 may generate parity data based on the main data MD to be sent to the semiconductor memory device 200, may store the parity data therein, may generate check bits based on the main data MD received from the semiconductor memory device 200, and may correct error bits in the main data MD by comparing the parity data and the check bits.

[0055] The semiconductor memory device 200 includes a memory cell array 310 that stores main data MD, an on-die ECC engine 400, and a control logic circuit 210. For ease of explanation, the on-die ECC engine 400 may be referred to as the ECC engine. The memory cell array 310 may include a plurality of sub-array blocks arranged along a first direction and a second direction intersecting the first direction.

[0056] The on-die ECC engine 400 may generate parity data by performing ECC encoding on the main data MD using ECC based on a primitive polynomial, and may correct / detect error bits in the read data by performing ECC decoding on the data read from the target page of the memory cell array 310. The on-die ECC engine 400 may include an ECC decoder. The ECC decoder may read a codeword from the target page based on an address provided by the memory controller 100 to generate a syndrome, and may correct at least one error bit in the read codeword based on the syndrome by applying different syndromes to a single-bit error in the read codeword, an adjacent-bit error occurring in two adjacent memory cells in the target page, and a non-adjacent-bit error occurring in two non-adjacent memory cells in the target page. The ECC decoder may generate different syndromes based on a parity check matrix, which is based on a default parity check matrix generated according to a primitive polynomial. The primitive polynomial may have an alpha matrix as a solution belonging to the Galois field (also known as the infinite field).

[0057] The main data MD may include a plurality of sub-data units, and each of the plurality of sub-data units may include a plurality of data bits. The ECC may include a plurality of column vectors, which are divided into a plurality of code groups corresponding to the sub-data units and parity data. The plurality of column vectors may correspond to the result of the power of the alpha matrix, and the alpha matrix may have an exponentially increasing value starting from zero.

[0058] The semiconductor memory device 200 may perform a burst operation. Here, the burst operation refers to an operation of writing or reading a large amount of data by sequentially increasing or decreasing an initial address provided from the memory controller 100. The basic unit of the burst operation may be referred to as a burst length BL. In an exemplary embodiment, the burst length BL may refer to the number of times of continuously reading or writing data by sequentially increasing or decreasing the initial address.

[0059] Figure 2 illustrates the main data corresponding to a plurality of burst lengths in a storage system according to some exemplary embodiments Figure 1 of.

[0060] Referring to Figure 2 , the main data MD corresponding to the plurality of burst lengths may be input to / output from the semiconductor memory device 200. The main data MD includes a plurality of data segments MD_SG1 to MD_SGt (where t is a natural number equal to or greater than 8), and each data segment corresponds to each of the plurality of burst lengths. In Figure 2 , it is assumed that the burst length is 8. However, the exemplary embodiments are not limited thereto. The main data MD corresponding to the plurality of burst lengths may be stored in the memory cell array 310 of the semiconductor memory device 200 ( Figure 1 ). In some embodiments, the main data MD may be arranged in a plurality of columns, for example, eight columns (DQ1 to DQ8). Each data segment includes corresponding rows across the plurality of columns.

[0061] Figure 3 is a schematic block diagram showing at least a part of an example of the storage controller 100 according to some exemplary embodiments Figure 1 shown in.

[0062] Referring to Figure 3 , the storage controller 100 may include a CPU 110, a data buffer 120, a system ECC engine 130, a command (CMD) buffer 180, and an address buffer 190. The system ECC engine 130 may include a parity generator 140, a buffer 145, a memory 150 storing a second ECC (ECC2) 155, and an ECC decoder 160.

[0063] The CPU 110 can receive a request REQ and data DTA from a host (not shown explicitly), and can provide the data DTA to the data buffer 120 and the parity generator 140.

[0064] The data buffer 120 can buffer the data DTA and provide first main data MD1 to the semiconductor memory device 200 ( Figure 1 ).

[0065] The parity generator 140 can be connected to the memory 150, can perform ECC encoding on the data DTA using the second ECC 155 to generate parity data PRTc, and can store the parity data PRTc in the buffer 145. As used herein, the term "connected" (or "connected to", or similar terms such as "contact" or "in contact with") is intended to refer to a physical connection and / or an electrical connection between two or more elements, and can include other intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0066] During a read operation of the semiconductor memory device 200, the ECC decoder 160 can receive second main data MD2 from the semiconductor memory device 200, can perform ECC decoding on the second main data MD2 by using the second ECC 155 and the system parity data PRTc provided to the ECC decoder 160, and can provide the corrected main data C_MD2 to the CPU 110. The CPU 110 provides the corrected main data C_MD2 to the host.

[0067] The command buffer 180 can store a command CMD corresponding to the request REQ, and can send the command CMD to the semiconductor memory device 200 under the control of the CPU 110. The address buffer 190 can store an address ADDR, and can send the address ADDR to the semiconductor memory device 200 under the control of the CPU 110.

[0068] Figure 4 is a schematic block diagram showing an example of the Figure 3 shown ECC decoder 160 according to some example embodiments.

[0069] Referring to Figure 4 , the ECC decoder 160 can include a check bit generator 161, a syndrome generator 163, and a data corrector 165.

[0070] The check bit generator 161 can receive the second main data MD2, and can generate check bits CHBc corresponding to the second main data MD2 by using the second ECC 155 ( Figure 3 ).

[0071] The syndrome generator 163 can compare the system parity check data PRTc and the check bit CHBc to generate syndrome data SDRc, which indicates whether the second main data MD2 includes at least one error bit and indicates the position of the at least one error bit.

[0072] The data corrector 165 can receive the second main data MD2 and can correct the error bits in the second main data MD2 based on the syndrome data SDRc to output the corrected main data C_MD2.

[0073] Figure 5 is a schematic block diagram showing at least a part of an example of Figure 1 the semiconductor memory device 200 shown according to an example embodiment.

[0074] Referring to Figure 5 , the semiconductor memory device 200 may include a control logic circuit 210, an address register 220, a bank control logic 230, a refresh counter 245, a row address (RA) multiplexer 240, a column address (CA) latch 250, a row decoder 260, a column decoder 270, a memory cell array (bank array) 310, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, an on-die ECC engine 400, a clock buffer 225, a strobe signal generator 235, and a data I / O buffer 320.

[0075] The memory cell array 310 may include a first bank array 310a to a sixteenth bank array 310p. The row decoder 260 may include a first row decoder 260a to a sixteenth row decoder 260p respectively coupled to the first bank array 310a to the sixteenth bank array 310p, the column decoder 270 may include a first column decoder 270a to a sixteenth column decoder 270p respectively coupled to the first bank array 310a to the sixteenth bank array 310p, and the sense amplifier unit 285 may include a first sense amplifier 285a to a sixteenth sense amplifier 285p respectively coupled to the first bank array 310a to the sixteenth bank array 310p. Although Figure 5 sixteen bank arrays 310a to 310p are shown in the example semiconductor memory device 200 of

[0076] The first bank array 310a to the sixteenth bank array 310p, the first row decoder 260a to the sixteenth row decoder 260p, the first column decoder 270a to the sixteenth decoder 270p, and the first sense amplifier 285a to the sixteenth sense amplifier 258p may form the first bank to the sixteenth bank. Each of the first bank array 310a to the sixteenth bank array 310p may include a plurality of memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

[0077] The address register 220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 100( Figure 1 ). The address register 220 may provide the received bank address BANK_ADDR to the bank control logic 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0078] The bank control logic 230 may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, the row decoder corresponding to the bank address BANK_ADDR among the first row decoder 260a to the sixteenth row decoder 260s is activated, and the column decoder corresponding to the bank address BANK_ADDR among the first column decoder 270a to the sixteenth column decoder 270p is activated in response to the bank control signals.

[0079] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220, and may receive the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address SRA. The row address SRA output from the row address multiplexer 240 is applied to the first row decoder 260a to the sixteenth row decoder 260p.

[0080] The refresh counter 245 may sequentially increment or decrement the refresh row address REF_ADDR under the control of the control logic circuit 210.

[0081] The row decoder activated by the bank control logic 230 among the first row decoder 260a to the sixteenth row decoder 260s may decode the row address SRA output from the row address multiplexer 240, and may activate the word line corresponding to the row address SRA. For example, the activated bank row decoder applies a word line drive voltage to the word line corresponding to the row address.

[0082] The column address latch 250 can receive a column address COL_ADDR from the address register 220 and can temporarily store the received column address COL_ADDR. In some embodiments, in burst mode, the column address latch 250 can generate a column address COL_ADDR' that increments from the received column address COL_ADDR. The column address latch 250 can apply the temporarily stored or generated column address COL_ADDR' to the first column decoder 270a to the sixteenth column decoder 270p.

[0083] The activated column decoders among the first column decoder 270a to the sixteenth column decoder 270p can activate sense amplifiers corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gating circuit 290.

[0084] The I / O gating circuit 290 can include a circuit for gating input / output data and can also include input data masking logic, a read data latch for storing data output from the first memory bank array 310a to the sixteenth memory bank array 310p, and a write driver for writing data to the first memory bank array 310a to the sixteenth memory bank array 310p.

[0085] The codeword CW read from the selected memory bank array among the first memory bank array 310a to the sixteenth memory bank array 310p (e.g., Figure 10 the read codeword RCW in Figure 10 is sensed by the corresponding sense amplifier 285 coupled to the selected memory bank array from which data is to be read and is stored in the read data latch of the I / O gating circuit 290. After the codeword CW is subjected to ECC decoding by the on-die ECC engine 400, the codeword CW stored in the read data latch can be provided to the data I / O buffer 320 as main data MD (e.g.,

[0086] The main data MD to be written into the selected memory bank among the first memory bank array 310a to the sixteenth memory bank array 310p can be provided to the data I / O buffer 320 by using the data strobe signal DQS from the memory controller 100. The data I / O buffer 320 can provide the main data MD to the on-die ECC engine 400. The on-die ECC engine 400 can perform ECC encoding on the main data MD to generate parity bits (or parity data), and the on-die ECC engine 400 can provide the codeword CW including the main data MD and the parity bits to the I / O gating circuit 290. The I / O gating circuit 290 can write the codeword CW into a sub-page in the selected memory bank through a write driver.

[0087] The data I / O buffer 320 can provide the main data MD from the memory controller 100 to the on-die ECC engine 400 during a write operation of the semiconductor memory device 200, and can send the main data MD and the data strobe signal DQS to the memory controller 100 during a read operation of the semiconductor memory device 200.

[0088] The on-die ECC engine 400 can perform ECC encoding on the main data MD based on the second control signal CTL2 from the control logic circuit 210 and can perform ECC decoding on the codeword CW. The on-die ECC engine 400 can read the codeword from the target page based on the address provided from the memory controller 100 ( Figure 1 ) to generate a syndrome, and can correct at least one error bit in the read codeword based on the syndrome by applying different syndromes to a single-bit error in the read codeword, an adjacent-bit error occurring in two adjacent memory cells in the target page, and a non-adjacent-bit error occurring in two non-adjacent memory cells in the target page.

[0089] The clock buffer 225 can receive the clock signal CK, can generate an internal clock signal ICK by buffering the clock signal CK, and can provide the internal clock signal ICK to circuit components that process the command CMD and the address ADDR.

[0090] The strobe signal generator 235 can receive the clock signal CK, can generate the data strobe signal DQS based on the clock signal CK, and can provide the data strobe signal DQS to the data I / O buffer 320.

[0091] The control logic circuit 210 can control the operation of the semiconductor memory device 200. For example, the control logic circuit 210 can generate control signals for the semiconductor memory device 200 to perform a write operation, a read operation, and a refresh operation. The control logic circuit 210 can include ( Figure 1A command decoder 211 that decodes the received command CMD and a mode register 212 that sets the operation mode of the semiconductor memory device 200.

[0092] For example, the command decoder 211 can generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc. The control logic circuit 210 can provide a first control signal CTL1 to the I / O gating circuit 290 and a second control signal CTL2 to the on-die ECC engine.

[0093] Figure 6 An example of a first bank array 310a in a semiconductor memory device 200 according to one or more embodiments is shown. Figure 5

[0094] Referring to Figure 6 , the first bank array 310a may include a plurality of word lines WL0 to WLm-1 (m is a natural number greater than 2), a plurality of bit lines BTL0 to BTLn-1 (n is a natural number greater than 2), and a plurality of memory cells MC disposed at intersections between the word lines WL0 to WLm-1 and the bit lines BTL0 to BTLn-1. Each memory cell MC includes a cell transistor coupled to each of the word lines WL0 to WLm-1 and each of the bit lines BTL0 to BTLn-1, and a cell capacitor coupled to the cell transistor. Each memory cell MC may have a DRAM cell structure. Each of the word lines WL0 to WLm-1 extends in a first direction D1, and each of the bit lines BTL1 to BTLn-1 extends in a second direction D2 intersecting the first direction D1.

[0095] The word lines WL0 to WLm-1 coupled to the plurality of memory cells MC may be referred to as rows of the first bank array 310a, and the bit lines BTL0 to BTLn-1 coupled to the plurality of memory cells MC may be referred to as columns of the first bank array 310a.

[0096] Figure 7 An example of a first bank array in a semiconductor memory device according to some example embodiments is shown. Figure 5

[0097] Referring to Figure 7, in the first memory bank array 310a, I sub-array blocks SCB can be arranged along the first direction D1, and J sub-array blocks SCB can be arranged along a second direction D2 that is substantially perpendicular to the first direction D1. I and J respectively represent the number of sub-array blocks SCB in the first direction and the second direction, and are natural numbers greater than 2. A plurality of bit lines, a plurality of word lines, and a plurality of memory cells connected to the bit lines and the word lines are provided in each sub-array block SCB.

[0098] I + 1 sub-word line driver regions SWB can be arranged along the first direction D1 between the sub-array blocks SCB. Sub-word line drivers can be provided in the sub-word line driver regions SWB. J + 1 bit line sense amplifier regions BLSAB can be arranged, for example, along the second direction D2 between the sub-array blocks SCB. Bit line sense amplifiers for sensing data stored in the memory cells can be provided in the bit line sense amplifier regions BLSAB.

[0099] A plurality of coupling regions CONJ can be arranged adjacent to the sub-word line driver regions SWB and the bit line sense amplifier regions BLSAB. A voltage generator can be provided in each coupling region CONJ. The following can be referred to Figure 8 to describe the portion 390 in the first memory bank array 310a.

[0100] Figure 8 Illustrated is the portion 390 of the first memory bank array 310a in Figure 7 according to some example embodiments.

[0101] Referring to Figure 7 and Figure 8 , in the portion 390 of the first memory bank array 310a, sub-array blocks SCB, bit line sense amplifier regions BLSAB, sub-word line driver regions SWB, and coupling regions CONJ are provided.

[0102] The sub-array block SCB includes a plurality of word lines WL0 to WL3 extending in the row direction (the first direction D1) and a plurality of bit line pairs BTL0 to BTL1 and BTLB0 to BTLB1 extending in the column direction (the second direction D2). The sub-array block SCB can include a plurality of memory cells MC provided at the intersections between the word lines WL0 to WL3 and the bit line pairs BTL0 to BTL1 and BTLB0 to BTLB1.

[0103] Referring to Figure 8, the sub-word line driver region SWB includes a plurality of sub-word line drivers (SWD) 551, 552, 553, and 554 that drive word lines WL0 to WL3, respectively. The sub-word line drivers 551 and 552 can be disposed in the sub-word line driver region SWB on the left side (in this example) with respect to the sub-array block SCB. Additionally, the sub-word line drivers 553 and 554 can be disposed in the sub-word line driver region SWB on the right side (in this example) with respect to the sub-array block SCB.

[0104] The bit line sense amplifier regions BLSABa and BLSABb can include bit line sense amplifiers BLSA560 and 570 coupled to bit line pairs BTL0 to BTL1 and BTLB0 to BTLB1, respectively, and local sense amplifier (LSA) circuits 580 and 590. As part of a differential sensing scheme, the bit line sense amplifier 560 can sense and amplify the voltage difference between the bit line pair BTL0 and BTLB0 to provide an amplified voltage difference to the local I / O line pair LIO1 and LIOB1. The bit line sense amplifier 570 can sense and amplify the voltage difference between the bit line pair BTL1 and BTLB1 to provide an amplified voltage difference to the local I / O line pair LIO2 and LIOB2.

[0105] The local sense amplifier circuit 580 controls the connection between the local I / O line pair LIO1 and LIOB1 and the global I / O line pair GIO1 and GIOB1, and the local sense amplifier circuit 590 controls the connection between the local I / O line pair LIO2 and LIOB2 and the global I / O line pair GIO2 and GIOB2.

[0106] As Figure 8 shown, the bit line sense amplifiers 560 and 570 can be alternately disposed in the upper and lower portions of the sub-array block SCB. The bonding region CONJ can be disposed adjacent to the bit line sense amplifier regions BLSABa and BLSABb, the sub-word line driver region SWB, and the sub-array block SCB. A plurality of voltage generators (VG) 510, 520, 530, and 540 can be disposed in the bonding region CONJ.

[0107] Figure 9 Illustrated is a portion of a semiconductor memory device 200 during a write operation according to one or more embodiments Figure 5 of.

[0108] During Figure 9 , the control logic circuit 210, the first bank array 310a, the I / O gating circuit 290, and the on-die ECC engine 400 are shown.

[0109] Referring to Figure 9, the first bank array 310a may include a normal cell array NCA and a redundant cell array RCA.

[0110] The normal cell array NCA may include a plurality of first memory blocks MB0 to MB15 (i.e., 311 to 313), and the redundant cell array RCA includes at least a second memory block 314. The first memory blocks 311 to 313 are the memory blocks that determine the storage capacity of the semiconductor memory device 200. The second memory block 314 is used for ECC and / or redundant repair. Since the second memory block 314 for ECC and / or redundant repair is used for ECC, data line repair, and block repair to repair the "failed" cells generated in the first memory blocks 311 to 313, the second memory block 314 is also referred to as an EDB block. In each of the first memory blocks 311 to 313, a plurality of first memory cells are arranged in rows and columns. The first memory cell connected to the intersection of the word line WL and the bit line BTL may be a dynamic memory cell. In the second memory block 314, a plurality of second memory cells are arranged in rows and columns. The second memory cell connected to the intersection of the word line WL and the bit line RBTL may be a dynamic memory cell. Each of the first memory blocks 311 to 313 and the second memory block 314 may correspond to Figure 7 a sub-array block SCB in

[0111] The I / O gating circuit 290 may include a plurality of switch circuits (e.g., multiplexers (MUX)) 291a to 291d respectively connected to the first memory blocks 311 to 313 and the second memory block 314.

[0112] The on-die ECC engine 400 may be connected to the switch circuits 291a to 291d through a first data line GIO and a second data line EDBIO. The control logic circuit 210 may receive a command CMD and an address ADDR, and may decode the command CMD to generate a first control signal CTL1 to the I / O gating circuit 290 and a second control signal CTL2 to the on-die ECC engine 400.

[0113] When the command CMD is a write command, the control logic circuit 210 may provide the second control signal CTL2 to the on-die ECC engine 400, and the on-die ECC engine 400 may perform ECC encoding on the main data MD to generate parity data associated with the main data MD, and may provide a codeword CW including the main data MD and the parity data to the I / O gating circuit 290. The control logic circuit 210 may provide the first control signal CTL1 to the I / O gating circuit 290 such that the codeword CW will be stored in a sub-page of a target page in the first bank array 310a.

[0114] Figure 10illustrates at least a portion of a semiconductor memory device 200 during a read operation in accordance with one or more embodiments Figure 5 of the semiconductor memory device 200.

[0115] For ease of explanation, Figure 10 will omit the description related to Figure 9 repetitions.

[0116] Referring to Figure 10 , when the command CMD is a read command specifying a read operation, the control logic circuit 210 may provide a first control signal CTL1 to the I / O gating circuit 290 such that the (read) codeword RCW in the sub - page of the target page stored in the first memory bank array 310a is provided to the on - die ECC engine 400.

[0117] The on - die ECC engine 400 may perform ECC decoding on the read codeword RCW to correct single - bit errors, adjacent two - bit errors, or non - adjacent two - bit errors in the read codeword RCW by applying different syndromes to the read codeword RCW, and output the corrected main data C_MD. Different syndromes may be generated based on a parity - check matrix.

[0118] Figure 11 is a schematic block diagram showing an example of the on - die ECC engine 400 in a semiconductor memory device 200 in accordance with some example embodiments Figure 5 of the semiconductor memory device 200.

[0119] Referring to Figure 11 , the on - die ECC engine 400 may include an (ECC) memory 410, an ECC encoder 420, and an ECC decoder 430.

[0120] The ECC memory 410 may store an ECC - based parity - generation matrix PGM and a parity - check matrix PCM. The parity - generation matrix PGM and the parity - check matrix PCM may be generated based on a primitive polynomial, and the parity - check matrix PCM may include a plurality of column vectors corresponding to data bits in the main data and parity data. The primitive polynomial may have an alpha matrix as a solution belonging to a Galois field, the plurality of column vectors may correspond to the results of powers of the alpha matrix, and the alpha matrix may have exponentially increasing values starting from zero.

[0121] The ECC encoder 420 may be connected to the ECC memory 410 and may perform ECC encoding on the main data MD using the parity - generation matrix PGM stored in the ECC memory 410 to generate parity data PRT during a write operation of the semiconductor memory device 200. The ECC encoder 420 may provide the parity data PRT to the I / O gating circuit 290( Figure 5) provides a code word CW including main data MD and parity data PRT.

[0122] The ECC decoder 430 can be connected to the ECC memory 410, can receive a codeword CW including main data MD and parity data PRT, can use a parity check matrix PCM to perform ECC decoding on the main data MD based on the parity data PRT to correct and / or detect error bits in the main data MD, and can output corrected main data C_MD.

[0123] Although the reference Figure 11 It is described that the ECC memory 410 is coupled to the ECC encoder 420 and the ECC decoder 430 , but in example embodiments, the ECC memory 410 may be implemented using XOR gates within the ECC encoder 420 and the ECC decoder 430 .

[0124] Figures 12A to 12E Examples of error bits in a data pattern stored in a sub-array block according to the least significant bit (LSB) of a row address according to one or more embodiments are respectively illustrated.

[0125] Figure 12A and Figure 12C shows a single bit error in the data pattern, Figure 12B and Figure 12D shows two adjacent bits of errors occurring in two adjacent storage cells, and Figure 12E It is shown that non-adjacent two-bit errors occur in two non-adjacent memory cells.

[0126] exist Figures 12A to 12E In , X represents an erroneous bit (ie, an error) in the data pattern.

[0127] Reference Figure 12A , when the LSB of the row address is low (when the row address specifies a target page coupled to an even word line), the memory cell specified by the cell index CINX 1 includes a single bit error. Figure 12B , when the LSB of the row address is at a low level, each of the memory cells specified by the cell indexes CINX 4 and 5 includes an error bit. That is, adjacent two-bit errors occur in the adjacent two memory cells specified by the cell indexes CINX 4 and 5. Figure 12B In the case of two adjacent storage cells specified by cell indexes CINX 1 and 2, 2 and 3, and 6 and 7, adjacent two-bit errors do not occur or occur with a low probability.

[0128] Reference Figure 12C, when the LSB of the row address is high (when the row address designates a target page coupled to an odd-numbered word line), the memory cells designated by cell index CINX 3 include a single bit error. Refer to Figure 12D , when the LSB of the row address is high, each of the memory cells designated by cell indices CINX 3 and 4 includes an error bit. That is, adjacent two-bit errors occur in two adjacent memory cells designated by cell indices CINX 3 and 4. In Figure 12D , in two adjacent memory cells designated by cell indices CINX 0 and 1, 2 and 3, 4 and 5, and 6 and 7, adjacent two-bit errors do not occur or occur with a low probability.

[0129] Refer to Figure 12E , when the LSB of the row address is high, each of the memory cells designated by cell indices CINX 7 and 0 includes an error bit. That is, non-adjacent two-bit errors occur in two non-adjacent memory cells designated by cell indices CINX 7 and 0.

[0130] Two-bit errors do not occur or occur with a low probability (as shown in Figure 12B and Figure 12D ), because the structure of the memory cells in the target page can be different based on the LSB of the row address, as described in reference to Figure 6 and Figure 8 .

[0131] Figure 13 is a table showing an example of generating a parity check matrix using a primitive polynomial according to an exemplary embodiment.

[0132] Refer to Figure 13 , in table TB, the index Vj indicating the exponent of the alpha matrix α, the alpha matrix α with the index Vj as the exponent Vj , and the alpha matrix α Vj can have a pattern of Galois field GF(2 5 ) based on the primitive polynomial represented by the following equation 1.

[0133] [Equation 1]

[0134] g(x) = x 5 + x 3 + 1

[0135] When assuming that the alpha matrix α is a solution of equation 1, the equation -α 5 = α 3+1. Thus, when the index Vj indicating the exponent of the alpha matrix α gradually increases from "0" to "31", the patterns of the Galois field GF(2 5 ) do not overlap. The pattern of the Galois field GF(2 5 ) in the case where the index Vj has "31" is the same as the pattern of the Galois field GF(2 5 ) in the case where the index Vj has "0".

[0136] When using the equation -α 5 = α 3 + 1, as the index Vj indicating the exponent of the alpha matrix α gradually increases from "0" to "31", 31 non - overlapping patterns of the Galois field GF(2 5 ) can be generated, and a default parity check matrix can be generated based on the 31 non - overlapping patterns of the Galois field GF(2 5 ).

[0137] Figure 14 Shows an example of the ECC generated based on the Figure 13 table TB according to an example embodiment.

[0138] Referring to Figure 14 , when the index Vj indicating the exponent of the alpha matrix α Vj gradually increases from "0" to "30", the ECC can be represented by non - overlapping combinations of the alpha matrices α 0 , α 1 , α 2 , α 3 and α 4 , and a default parity check matrix can be generated based on the combinations of the alpha matrices α 0 , α 1 , α 2 , α 3 and α 4 . The alpha matrix α Vj can correspond to the column vectors of the default parity check matrix.

[0139] Figure 15 is a schematic block diagram showing the ECC decoder 430 in the die - level ECC engine 400 according to some example embodiments of Figure 11 .

[0140] Referring to Figure 15 , the ECC decoder 430 can include a syndrome generation circuit 440, a first corrector 470, a second corrector 475, a third corrector 480, and a selection circuit 490.

[0141] The syndrome generation circuit 440 can generate a first syndrome SDR1, a second syndrome SDR2, and a third syndrome SDR3 based on the parity check matrix PCM and the read codeword CW, and can generate a selection signal SS based on the LSB LSB_RA of the row address and one of the second syndrome SDR2 and the third syndrome SDR3.

[0142] The first corrector 470 can correct a single-bit error in the main data MD based on the first syndrome SDR1 to provide a first output data DOUT1. In response to the LSB LSB_RA of the row address being low, the second corrector 475 can correct adjacent two-bit errors in the main data MD based on the second syndrome SDR2 to provide a second output data DOUT2. In response to the LSB LSB_RA of the row address being high, the third corrector 480 can correct adjacent two-bit errors or non-adjacent two-bit errors in the main data MD based on the third syndrome SDR3 to provide a third output data DOUT3.

[0143] The selection circuit 490 can receive the main data MD, the first output data DOUT1, the second output data DOUT2, and the third output data DOUT3, and can select one of the main data MD, the first output data DOUT1, the second output data DOUT2, and the third output data DOUT3 based on the selection signal SS and the LSB LSB_RA of the row address to output the corrected main data C_MD or the main data MD.

[0144] When the vector representation of the codeword CW stored in the memory cell array 310 corresponds to CV, Equation 2 is derived.

[0145] [Equation 2]

[0146] CV = WDV × G,

[0147] where WDV is the vector representation of the main data set MD, and G is the vector representation of the parity generation matrix PGM.

[0148] When the vector representation of the codeword CW read from the memory cell array 310 corresponds to R, R may include errors, and R can be represented by Equation 3.

[0149] [Equation 3]

[0150] R = WDV × G + E,

[0151] where E corresponds to the vector representation of the error.

[0152] The ECC decoder 430 can perform calculations on the read codeword CW using the parity check matrix PCM. When the vector representation of the parity check matrix PCM corresponds to H, the calculation result corresponds to Equation 4.

[0153] [Equation 4]

[0154] H × R T = H × (WDV × G) T + H × E T = H × G T × WDV T + H × E T

[0155] The parity check generation matrix G and the parity check matrix H are set to satisfy Equation 5.

[0156] [Equation 5]

[0157] H × G T = 0

[0158] Therefore, Equation 6 is derived.

[0159] [Equation 6]

[0160] H × R T = H × E T

[0161] The result of Equation 6 can correspond to the vector representation of the first syndrome SDR1.

[0162] Figure 16 An example of a default parity check matrix according to an exemplary embodiment is shown.

[0163] Refer to Figure 16 , the default parity check matrix PCMa can be represented by an alpha matrix α with exponentially increasing (i.e., sequential) values starting from zero 0 , α 1 , α 2 , α 3 , …, α q-1 . Here, q can be the number of bits in the codeword CW.

[0164] Figure 17 An example of a single-bit error included in the main data is shown.

[0165] Refer to Figure 17 , when the vector representation of the default parity check matrix PCMa corresponds to Ha and when the error vector in the case of a single-bit error included in the main data MD corresponds to E1, the error vector E1 can be represented by [0 0 1 0 … 0].

[0166] When performing a matrix multiplication operation on the transposed matrix of the default parity check matrix PCMa and the error vector E1, α can be obtained. 2 .

[0167] Figure 18 An example in which adjacent two-bit errors are included in the main data is shown.

[0168] Referring to Figure 18 , when the vector representation of the default parity check matrix PCMa corresponds to Ha and when the error vector in the case where adjacent two-bit errors are included in the main data MD corresponds to E2, the error vector E2 can be represented by [1 1 0 0…0].

[0169] When performing a matrix multiplication operation on the transposed matrix of the default parity check matrix PCMa and the error vector E2, 1 + α can be obtained. When finding the same α as 1 + α in the default parity check matrix PCMa Vy at that time, adjacent two-bit errors can be corrected by the column vector corresponding to α Vy .

[0170] Figure 19 An example of a parity check matrix used in the die ECC engine 400 according to some example embodiments is shown. Figure 11

[0171] In Figure 19 , it is assumed that the main data MD includes a plurality of sub-data units SDU1 to SDUx, and the parity data PRT includes 8-bit parity bits PB1 to PB8. In Figure 19 , it is assumed that x is a natural number equal to or greater than 8.

[0172] Referring to Figure 19 , the ECC-based parity check matrix PCMb can be divided into a plurality of code groups CG1 to CGx and PCG corresponding to the plurality of sub-data units SDU1 to SDUx and the parity data PRT. The code group PCG can include a plurality of column vectors PV1 to PV8 corresponding to the parity bits PB1 to PB8 of the parity data PRT.

[0173] Figure 20 An example of the parity check matrix PCM shown in Figure 19 according to some example embodiments is shown.

[0174] In Figure 20 , it is assumed that the main data MD includes 128 data bits d0 to d127, and the parity bits PB1 to PB8 correspond to the data bits d128 to d135. That is, it is assumed that Figure 19 x in

[0175] Reference Figure 20 ,the data bits d0 to d127 of the main data MD can be divided into the first sub-data unit SDU1 to the sixteenth sub-data unit SDU16. Each of the first sub-data unit SDU1 to the sixteenth sub-data unit SDU16 includes 8 data bits.

[0176] The parity check matrix PCM can include the first code group CG1 to the sixteenth code group CG16 corresponding to the first sub-data unit SDU1 to the sixteenth sub-data unit SDU16 respectively, and a code group PCG corresponding to the parity bits PB1 to PB8 (i.e., data bits d128 to d135).

[0177] Figures 21A to 21E shows an example configuration of the Figure 20 parity check matrix PCM according to one or more embodiments.

[0178] Reference Figures 21A to 21E ,the parity check matrix PCM can include the first code group CG1 to the sixteenth code group CG16 corresponding to the first sub-data unit SDU1 to the sixteenth sub-data unit SDU16 respectively, and a code group PCG corresponding to the parity bits PB1 to PB8 (i.e., data bits d128 to d135).

[0179] The first code group CG1 to the sixteenth code group CG16 can include column vectors CV11 to CV18, CV21 to CV28, CV31 to CV38, CV41 to CV48, CV51 to CV58, CV61 to CV68, CV71 to CV78, CV81 to CV88, CV91 to CV98, CV101 to CV108, CV111 to CV118, CV121 to CV128, CV131 to CV138, CV141 to CV148, CV151 to CV158, and CV161 to CV168, and the code group PCG includes column vectors PV1 to PV8.

[0180] The column vectors CV11 to CV18 correspond to the data bits d0 to d7. The column vectors CV21 to CV28 correspond to the data bits d8 to d15. The column vectors CV31 to CV38 correspond to the data bits d16 to d23. The column vectors CV41 to CV48 correspond to the data bits d24 to d31. The column vectors CV51 to CV58 correspond to the data bits d32 to d39. The column vectors CV61 to CV68 correspond to the data bits d40 to d47. The column vectors CV71 to CV78 correspond to the data bits d48 to d55. The column vectors CV81 to CV88 correspond to the data bits d56 to d63. The column vectors CV91 to CV98 correspond to the data bits d64 to d71. The column vectors CV101 to CV108 correspond to the data bits d72 to d79. The column vectors CV111 to CV118 correspond to the data bits d80 to d87. The column vectors CV121 to CV128 correspond to the data bits d88 to d95. The column vectors CV131 to CV138 correspond to the data bits d96 to d103. The column vectors CV141 to CV148 correspond to the data bits d104 to d111. The column vectors CV151 to CV158 correspond to the data bits d112 to d119. The column vectors CV161 to CV168 correspond to the data bits d120 to d127. The column vectors PV1 to PV8 correspond to the data bits d128 to d135.

[0181] Figure 15 The syndrome generation circuit 440 in can generate a first sub-check matrix ( Figure 26A HS1 in Figure 26A ) and a second sub-check matrix ( Figure 26A HS2 in Figure 26A ) by using the column vectors CV11 to CV168 and PV1 to PV8 of the parity check matrix PCM.

[0182] Figure 22A and Figure 22B shows an example of the first sub-check matrix generated by using the parity check matrix, but the embodiment is not limited thereto.

[0183] When the target page is coupled to the even digit line, the syndrome generation circuit 440 in the ECC decoder 430 (refer to Figure 15 ) can generate a first sub-check matrix ( Figure 26A HS1 in Figure 26A ) by using the column vectors CV11 to CV168 and PV1 to PV8 of the parity check matrix PCM to be applied.

[0184] Refer to Figure 22A and Figure 22B , the syndrome generation circuit 440 ( Figure 15 ) can, by Figures 21A to 21EThe first sub-check matrix HS1 is generated by performing an exclusive OR operation on adjacent (2i - 1)-th column vectors and (2i)-th column vectors among the column vectors CV11 to CV168 and PV1 to PV8 in []. Here, i is one of 1 to k / 2, k is an even number and is the number of data bits in each of the sub-data units SDU1 to SDU16. The first sub-check matrix HS1 may include even column vectors eCV1 to eCV68.

[0185] For example, the syndrome generation circuit 440 may generate an even column vector eCV1 by performing an exclusive OR operation on column vectors CV11 and CV12, and may generate an even column vector eCV5 by performing an exclusive OR operation on column vectors CV21 and CV22.

[0186] Figure 23A and Figure 23B shows an example of a second sub-check matrix generated by using a parity check matrix according to one or more embodiments.

[0187] When the target page is coupled to an odd-numbered bit line, the syndrome generation circuit 440 in the ECC decoder 430 ( Figure 15 ) may generate a second sub-check matrix ( Figure 26A HS2 in []) by using the column vectors CV11 to CV168 and PV1 to PV8 of the parity check matrix HS to be applied.

[0188] Referring to Figure 23A and Figure 23B , the syndrome generation circuit 440 may generate the second sub-check matrix HS2 by performing an exclusive OR operation on adjacent (2i)-th column vectors and (2i + 1)-th column vectors among the column vectors CV11 to CV168 and PV1 to PV8 in Figures 21A to 21E and by performing an exclusive OR operation on non-adjacent k-th column vectors and first column vectors in each of a plurality of sub-data units. Here, i is one of 1 to k / 2, k is an even number and is the number of data bits in each of the sub-data units SDU1 to SDU16. The second sub-check matrix HS2 may include odd column vectors oCV1 to oCV68.

[0189] For example, the syndrome generation circuit 440 ( Figure 15 ) may generate an odd column vector oCV1 by performing an exclusive OR operation on column vectors CV12 and CV13.

[0190] Figure 24 and Figure 25 shows an example of generating an odd column vector according to one or more embodiments.

[0191] Referring to Figure 24 , the syndrome generation circuit 440 ( Figure 15The odd column vector oCV4 can be generated by performing an exclusive OR operation on the column vectors CV18 and CV11.

[0192] Referring to Figure 25 , the syndrome generator circuit 440 ( Figure 15 ) can generate the odd column vector oCV68 by performing an exclusive OR operation on the column vectors PV8 and PV1.

[0193] Figure 26A FIG. Figure 15 is a schematic block diagram showing an example of the syndrome generator circuit 440 in the ECC decoder 430 according to some example embodiments.

[0194] Referring to Figure 26A , the syndrome generator circuit 440 may include a first syndrome generator 445, a sub-check matrix generator 450, a second syndrome generator 460, a third syndrome generator 465, a multiplexer (MUX) 467, and a selection signal generator 468.

[0195] The first syndrome generator 445 may generate a first syndrome SDR1 by applying a parity check matrix PCM to the read codeword CW. The sub-check matrix generator 450 may generate a first sub-check matrix HS1 based on a first part of the parity check matrix PCM, as described with reference to Figure 22A and Figure 22B , and may generate a second sub-check matrix HS2 based on a second part of the parity check matrix PCM, as described with reference to Figure 23A and Figure 23B . The second syndrome generator 460 may generate a second syndrome SDR2 by applying the first sub-check matrix HS1 to the read codeword CW. The third syndrome generator 465 may generate a third syndrome SDR3 by applying the second sub-check matrix HS2 to the read codeword CW.

[0196] The multiplexer 467 may receive the second syndrome SDR2 and the third syndrome SDR3, and may select one of the second syndrome SDR2 and the third syndrome SDR3 based on the least significant bit LSB_RA of the row address. The selection signal generator 468 may receive the first syndrome SDR1 and the output of the multiplexer 467, and may generate a selection signal SS based on the logic levels of the first syndrome SDR1 and one of the second syndrome SDR2 and the third syndrome SDR3.

[0197] If the parity check matrix PCM corresponds to a single error correction (SEC) code, the first syndrome SDR1 and the second syndrome SDR2 cannot have non-zero values simultaneously, and the first syndrome SDR1 and the third syndrome SDR3 cannot have non-zero values simultaneously. Therefore, when the read codeword CW includes a single bit error, one of the second syndrome SDR2 and the third syndrome SDR3 has a non-zero value. Additionally, when the read codeword CW does not include an error, the first syndrome SDR1 and the second syndrome SDR2 have non-zero values simultaneously, or the first syndrome SDR1 and the third syndrome SDR3 have non-zero values simultaneously. Therefore, the selection signal generator 468 can determine the logic level of the selection signal SS based on the above description.

[0198] Figure 26B is an example of a default parity check matrix generated based on a primitive polynomial according to an exemplary embodiment.

[0199] Figure 26B shows a default parity check matrix PCMc generated based on the primitive polynomial represented by Equation 7 below.

[0200] [Equation 7]

[0201] g1(x) = x 8 + x 6 + x 3 + x 2 + 1

[0202] When assuming that the alpha matrix α is a solution of Equation 7, the equation -α 8 = α 6 + α 3 + α 2 + 1 is obtained. Therefore, when the index Vj indicating the exponent of the alpha matrix α gradually increases from "0" to "255", the patterns of the Galois field GF(2 8 ) do not overlap when the index Vj has one of "0" to "254". The pattern of the Galois field GF(2 8 ) in the case where the index Vj has "255" is the same as the pattern of the Galois field GF(2 8 ) in the case where the index Vj has "0".

[0203] Additionally, when the index Vj is 222, the equation α 222 = α 7 + 1 is obtained.

[0204] Figure 26C is a table showing candidate primitive polynomials for generating a default parity check matrix according to an exemplary embodiment.

[0205] Refer to Figure 26C , in Table TB2, the candidate primitive polynomial candidate g(x), the decimal value of the candidate primitive polynomial candidate g(x), the index Vj indicating the exponent of the alpha matrix α, and the remainder mod(Vj, 15) obtained by dividing the index Vj by 15 are shown.

[0206] Among the candidate primitive polynomials candidate g(x), the candidate primitive polynomial x with a remainder of 8 8 +x 6 +x 3 +x 2 +1 and x 8 +x 6 +x 5 +x 3 +x 2 +1 can be used to generate a primitive polynomial, and in Figure 26A x 8 +x 6 +x 3 +x 2 +1 is used.

[0207] Figure 26D is a schematic block diagram showing an example of the syndrome generation circuit in the ECC decoder 430 according to some example embodiments. Figure 15

[0208] Refer to Figure 26D , the syndrome generation circuit 440a may include a first syndrome generator 445a, a check matrix generator 450a, a second syndrome generator 460a, a third syndrome generator 465a, a multiplexer 467a, and a selection signal generator 468a.

[0209] The check matrix generator 450a may receive the default parity check matrix PCMc and may generate Figures 21A to 21E the parity check matrix PCM of, the parity check matrix PCM having a first column vector among a plurality of column vectors, the first column vector having a remainder obtained by dividing the result of the power of the alpha matrix by 2k - 1, the remainder being less than k (k is the number of data bits in each of a plurality of sub-data units), and the check matrix generator 450a may provide the parity check matrix PCM to the first syndrome generator 445a.

[0210] The check matrix generator 450a may generate Figure 22A and Figure 22BThe first sub-check matrix HS11, the first sub-check matrix HS11 has a second column vector among a plurality of column vectors, the second column vector has a remainder obtained by dividing the result of the power of the alpha matrix by 2k - 1, the remainder is equal to or greater than k and less than 2k - 1 and is even, and the check matrix generator 450a can provide the first sub-check matrix HS11 to the second syndrome generator 460a.

[0211] The check matrix generator 450a can generate Figure 23A and Figure 23B a second sub-check matrix HS12 of, the second sub-check matrix HS12 has a third column vector among a plurality of column vectors and a column vector of the 1 + α k-1 type, the third column vector has a remainder obtained by dividing the result of the power of the alpha matrix by 2k - 1, the remainder is equal to or greater than k and less than 2k - 1 and is odd, and the check matrix generator 450a can provide the second sub-check matrix HS12 to the third syndrome generator 465a.

[0212] The first syndrome generator 445a can generate a first syndrome SDR11 by applying the parity check matrix PCM to the read codeword CW. The second syndrome generator 460a can generate a second syndrome SDR12 by applying the first sub-check matrix HS11 to the read codeword CW. The third syndrome generator 465a can generate a third syndrome SDR13 by applying the second sub-check matrix HS12 to the read codeword CW.

[0213] The multiplexer 467a can receive the second syndrome SDR12 and the third syndrome SDR13, and can select one of the second syndrome SDR12 and the third syndrome SDR13 based on the LSB LSB_RA of the row address. The selection signal generator 468a can receive the first syndrome SDR11 and the output of the multiplexer 467a, and can generate a selection signal SS based on the logic levels of the first syndrome SDR11 and one of the second syndrome SDR12 and the third syndrome SDR13.

[0214] If the parity check matrix PCM corresponds to a single error correction (SEC) code, the first syndrome SDR11 and the second syndrome SDR12 cannot both have non-zero values simultaneously, and the first syndrome SDR11 and the third syndrome SDR13 cannot both have non-zero values simultaneously. Therefore, when the read codeword CW includes a single bit error, one of the second syndrome SDR12 and the third syndrome SDR13 has a non-zero value. Additionally, when the read codeword CW does not include an error, the first syndrome SDR11 and the second syndrome SDR12 both have non-zero values simultaneously, or the first syndrome SDR11 and the third syndrome SDR13 both have non-zero values simultaneously. Therefore, the selection signal generator 468 can determine the logic level of the selection signal SS based on the above description.

[0215] When the main data MD supplied to Figure 15 the ECC decoder 430 in Figure 15 includes a single bit error, one of the bits of the error vector has a high level and the other bits of the error vector have a low level. Therefore,

[0216] the ECC decoder 430 in Figure 15 can correct the single bit error in the main data MD based on the first syndrome SDR11.

[0217] When the main data MD supplied to Figure 15 the ECC decoder 430 in k-1 includes adjacent two-bit errors and the least significant bit LSB_RA of the row address is at a low level, the ECC decoder 430 can correct the adjacent two-bit errors in the main data MD based on the second syndrome SDR12, which is generated by the column vector corresponding to 1 + α.

[0218] When the main data MD supplied to 7 the ECC decoder 430 in

[0219] includes adjacent two-bit errors or non-adjacent two-bit errors (occurring in non-adjacent k-th storage unit and the first storage unit) and the least significant bit LSB_RA of the row address is at a high level, the ECC decoder 430 can correct the adjacent two-bit errors or non-adjacent two-bit errors in the main data MD based on the third syndrome SDR13, which is generated by the column vector having a remainder equal to or greater than k and less than 2k - 1 and being odd, and the column vector of the 1 + α Figure 26B type.

[0218] When the main data MD includes non-adjacent two-bit errors, performing a matrix multiplication operation on the default parity check matrix PCMc and the transposed matrix of the error vector E2 can obtain 1 + α 7

[0219] As described with reference to Figure 26B 1 + α 7 can correspond to α 222。The ECC decoder 430 can correct non-adjacent two-bit errors by assigning the column vectors with 1+α in the column vectors of the default parity check matrix PCMc 7 to the third syndrome SDR13.

[0220] When non-adjacent two-bit errors occur in the sub-data unit, the ECC decoder 430 can correct the non-adjacent two-bit errors by assigning the column vectors with 1+α 7 to the third syndrome SDR13.

[0221] For example, when non-adjacent two-bit errors (data bits d15 and d22) occur in a sub-data unit, the equation α 15 +α 22 =α 15 (1+α 7 )=α 237 can be obtained. Additionally, when non-adjacent two-bit errors (data bits d30 and d37) occur in a sub-data unit, the equation α 30 +α 37 =α 30 (1+α 7 )=α 252 can be obtained. The remainders obtained by dividing 237 and 252 by 15 respectively correspond to 12. When non-adjacent two-bit errors (the k-th data bit and the first data bit) occur in a sub-data unit, the column vector for correcting the non-adjacent two-bit errors can be assigned to the corresponding code group by using the equation 1+α 7 =α 222 .

[0222] Figure 27A is a schematic block diagram showing an example of the selection circuit 490 in the Figure 15 ECC decoder according to some example embodiments.

[0223] Referring to Figure 27A , the selection circuit 490 can include a first multiplexer 491 and a second multiplexer 493.

[0224] The first multiplexer 491 can receive the second output data DOUT2 and the third output data DOUT3, and can select one of the second output data DOUT2 and the third output data DOUT3 in response to the LSB LSB_RA of the row address.

[0225] When the target page is coupled to an even-numbered bit line, the first multiplexer 491 may provide a second output data DOUT2, and when the target page is coupled to an odd-numbered bit line, the first multiplexer 491 may provide a third output data DOUT3. The second multiplexer 493 may receive the main data MD, the first output data DOUT1, and the output of the first multiplexer 491, may select one of the main data MD, the first output data DOUT1, and the output of the first multiplexer 491 in response to a selection signal SS, and may output the selected data as the main data MD or the corrected main data C_MD.

[0226] Figure 27B is a schematic block diagram showing an example of a first corrector in an Figure 15 ECC decoder according to some example embodiments.

[0227] Referring to Figure 27B , the first corrector 470 may include an error-locating polynomial (ELP) calculator 471, an error-locating (EL) calculator 472, and a data corrector 473.

[0228] The error-locating polynomial calculator 471 may calculate coefficients ELP of an error-locating polynomial based on a first syndrome SDR1 and provide the coefficients ELP of the error-locating polynomial to the error-locating calculator 472. The error-locating calculator 472 may calculate an error location based on the coefficients ELP of the error-locating polynomial and provide an error location signal ELS indicating the error location to the data corrector 473. The data corrector 473 may correct a single-bit error in the main data MD based on the error location signal ELS and provide a first output data DOUT1.

[0229] Figure 28 is a flowchart showing a method of operating a semiconductor memory device according to some example embodiments.

[0230] Referring to Figures 5 to 28 , in a method of operating a semiconductor memory device 200 including a memory cell array 310, the on-die ECC engine 400 generates parity data PRT based on main data MD by using an ECC-based parity generation matrix PGM (operation S110).

[0231] The on-die ECC engine 400 stores the main data MD and the parity data PRT in a target page of the memory cell array 300 via an I / O gating circuit 290 (operation S130). The on-die ECC engine 400 reads the main data MD and the parity data PRT from the target page of the memory cell array 300 via the I / O gating circuit 290 (operation S150).

[0232] The on-die ECC engine 400 generates a first syndrome SDR1, a second syndrome SDR2, and a third syndrome SDR3 based on the main data MD by using an ECC-based parity check matrix PCM (operation S170). The parity check matrix PCM may include a plurality of column vectors, and the plurality of column vectors may be divided into a plurality of code groups corresponding to a plurality of sub-data units and parity data in the main data.

[0233] The on-die ECC engine 400 corrects a single-bit error in the main data MD, or an adjacent two-bit error in the main data MD (occurring in two adjacent memory cells), or a non-adjacent two-bit error in the main data MD (occurring in the last memory cell and the first memory cell of a sub-data unit) by using the first syndrome SDR1 and one of the second syndrome SDR2 and the third syndrome SDR3 selected based on the LSB of the row address of a specified target page (operation S190).

[0234] Therefore, the on-die ECC engine and the semiconductor memory device including the on-die ECC engine can correct a single-bit error, an adjacent two-bit error, or a non-adjacent two-bit error by applying different syndromes to the single-bit error and the two-bit error by using one parity check matrix, thereby improving the error correction efficiency.

[0235] Figure 29 FIG. is a schematic block diagram showing a semiconductor memory device 800 according to some example embodiments.

[0236] Referring to Figure 29 , the semiconductor memory device 800 may include at least one buffer die 810 and a plurality of memory dies 820-1 to 820-r (r is a natural number equal to or greater than 3) for providing soft error analysis and correction functions in a stacked chip structure.

[0237] The plurality of memory dies 820-1 to 820-r are stacked on the buffer die 810 and transfer data through a plurality of through-silicon via (TSV) lines.

[0238] Each of the plurality of memory dies 820-1 to 820-r may include a cell core 821 for storing data and a cell core ECC engine 823 that generates transmission parity bits (i.e., transmission parity data) based on the transmission data to be sent to at least one buffer chip 810. The cell core 821 may include a plurality of memory cells having a DRAM cell structure. The cell core ECC engine 823 may adopt Figure 11The ECC engine 400 on the die. Therefore, the unit core ECC engine 823 can correct single-bit errors, adjacent two-bit errors, or non-adjacent two-bit errors by applying different syndromes to single-bit errors and two-bit errors using a parity check matrix, thereby improving the error correction efficiency.

[0239] The buffer die 810 may include a via ECC engine 812 that uses transmission parity bits to correct transmission errors and generate error-corrected data when a transmission error is detected in the transmission data received through the TSV lines.

[0240] The buffer die 810 may further include a data I / O buffer 816. The data I / O buffer 816 may temporarily store the main data MD from the via ECC engine 812 and output the main data MD to the outside.

[0241] The semiconductor memory device 800 may be a stacked chip type memory device or a stacked memory device that transmits data and control signals through TSV lines. The TSV lines may also be referred to as "through electrodes".

[0242] The unit core ECC engine 823 may perform error correction on the data output from the r-th memory die 820-r before transmitting the transmission data.

[0243] The data TSV line group 832 formed at a memory die 820-p may include TSV lines L1, L2,..., Lr, and the parity check TSV line group 834 may include TSV lines Ls1 to Lst (s is a natural number, and t is a natural number greater than 1). The TSV lines L1, L2,..., Lr of the data TSV line group 832 and the parity check TSV lines Lsl to Lst of the parity check TSV line group 834 may be connected to microbumps MCB (e.g., solder bumps, C4 connections, etc.) formed correspondingly between the memory dies 820-1 to 820-r.

[0244] The semiconductor memory device 800 may have a three-dimensional (3D) chip structure or a 2.5D chip structure to communicate with an external host (not explicitly shown) through a data bus B10. The buffer die 810 may be connected to a memory controller through the data bus B10.

[0245] According to an exemplary embodiment, as Figure 29 shown, the unit core ECC engine 823 may be included in the memory die, and the via ECC engine 812 may be included in the buffer die. Therefore, soft data failures can be detected and corrected. Soft data failures may include transmission errors caused by noise when transmitting data through the TSV lines.

[0246] Figure 30 is a perspective view showing a configuration diagram of a semiconductor package 900 including a stacked memory device according to an exemplary embodiment.

[0247] Referring Figure 30 , the semiconductor package 900 may include one or more stacked memory devices 910 and a graphics processing unit (GPU) 920.

[0248] The stacked memory device 910 and the GPU 920 may be mounted on an interposer 930, and the interposer on which the stacked memory device 910 and the GPU 920 are mounted may be mounted on a package substrate 940, and the package substrate 940 is mounted on solder balls 950. The GPU 920 may correspond to a semiconductor device that can perform a memory control function, and for example, the GPU 920 may be implemented as an application processor (AP). The GPU 920 may include a memory controller CTRL 925.

[0249] The stacked memory device 910 may be implemented in various forms, and the stacked memory device 910 may be a memory device in the form of a high bandwidth memory (HBM) in which multiple layers are stacked. Accordingly, the stacked memory device 910 may include a buffer die and multiple memory dies, and each of the multiple memory dies includes the above-described unit core and unit core ECC engine.

[0250] Multiple stacked memory devices 910 may be mounted on the interposer 930, and the GPU 920 may communicate with the multiple stacked memory devices 910. For example, each of the stacked memory device 910 and the GPU 920 may include a physical area, and communication may be performed between the stacked memory device 910 and the GPU 920 through the physical area. Meanwhile, when the stacked memory device 910 includes a direct access area, a test signal may be provided into the stacked memory device 910 through a conductive device (e.g., solder ball 950) mounted under the package substrate 940 and the direct access area.

[0251] Figure 31 is a schematic block diagram showing at least a part of a storage system 1000 having a four-column storage module according to an exemplary embodiment.

[0252] Referring Figure 31 , the storage system 1000 may include a storage controller 1010 and / or storage modules 1020 and 1030. Although Figure 31 two storage modules are depicted in, more or fewer storage modules may be included in the storage system 1000 according to some exemplary embodiments.

[0253] The storage controller 1010 may control the storage modules 1020 and / or 1030 to execute commands provided from the processor and / or the host. The storage controller 1010 may be implemented using processing circuitry (e.g., a processor) and / or may be implemented with a host, an application processor, or a system-on-chip (SoC). For signal integrity, a source termination may be implemented using a resistor RTT on the bus 1040 of the storage controller 1010. The resistor RTT may be coupled to the power supply voltage VDDQ. The storage controller 1010 may include a transmitter 1011 and a receiver 1013. The transmitter 1011 may transmit signals to at least one of the storage modules 1020 and / or 1030 (via the bus 1040), and the receiver 1013 may receive signals from at least one of the storage modules 1020 and / or 1030 (via the bus 1040). The storage controller 1010 may include a CPU 1015.

[0254] The storage modules 1020 and 1030 may be referred to as a first storage module 1020 and a second storage module 1030. The first storage module 1020 and the second storage module 1030 may be coupled to the storage controller 1010 via the bus 1040. Each of the first storage module 1020 and the second storage module 1030 may include a plurality of semiconductor storage devices and / or registered clock drivers. The first storage module 1020 may include storage columns RK1 and RK2, and the second storage module 1030 may include storage columns RK3 and RK4.

[0255] The storage column RK1 may include semiconductor storage devices 1021 and 1022, and the storage column RK2 may include semiconductor storage devices 1023 and 1024. Although not shown, each of the storage columns RK3 and RK4 may include semiconductor storage devices. Each of the semiconductor storage devices 1021, 1022, 1023, and 1024 may employ Figure 3 the semiconductor storage device 200.

[0256] Each of the semiconductor storage devices 1021, 1022, 1023, and 1024 may be connected to the storage controller 1010 via the bus 1040.

[0257] Each of the semiconductor storage devices 1021, 1022, 1023, and 1024 may include a memory cell array and a die-on ECC engine (e.g., Figure 11 the die-on ECC engine 400 shown in

[0258] Therefore, the on-die ECC engine in the semiconductor memory device according to the exemplary embodiment can correct a single-bit error, an adjacent two-bit error, or a non-adjacent two-bit error by applying different syndromes to the single-bit error and the two-bit error using one parity check matrix, thereby improving the error correction efficiency.

[0259] Aspects of the present disclosure can be applied to systems using semiconductor memory devices employing volatile memory cells. For example, aspects of the inventive concept can be applied to systems using a semiconductor memory device as a working memory, such as smart phones, navigation systems, laptop computers, desktop computers, and game consoles.

[0260] The foregoing is illustrative of the exemplary embodiments and is not to be construed as limiting thereof. Although some exemplary embodiments have been described, those skilled in the art will readily appreciate that various modifications can be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims.

Claims

1. An error correction code (ECC) engine for a semiconductor memory device, the ECC engine comprising: an ECC encoder configured to generate parity data based on main data according to an ECC based on a primitive polynomial, and configured to store a codeword including the main data and the parity data in a target page of a memory cell array; as well as The ECC decoder is configured as: reading the codeword from the target page based on an address to generate a syndrome; as well as Correcting at least one erroneous bit in the read codeword based on the syndrome by applying corresponding different syndromes to a single bit error in the read codeword, an adjacent bit error occurring in an adjacent memory cell in the target page, and a non-adjacent bit error occurring in a non-adjacent memory cell in the target page, The ECC decoder is further configured to generate the different syndromes based on a parity check matrix, the parity check matrix being based on a default parity check matrix generated according to the primitive polynomial, and The primitive polynomial has an alpha matrix as a solution belonging to the Galois field.

2. The ECC engine according to claim 1, wherein: The main data includes a plurality of sub-data units, each of the plurality of sub-data units includes a plurality of data bits; The default parity-check matrix includes a plurality of column vectors, and the plurality of column vectors are divided into a plurality of code groups corresponding to the plurality of sub-data units and the parity-check data; The plurality of column vectors correspond to the results of raising the alpha matrix to powers; and The alpha matrix has index values ​​that gradually increase from zero.

3. The ECC engine according to claim 2, wherein: Each of the plurality of column vectors has an element for each of the results of applying the primitive polynomial to a power of the alpha matrix.

4. The ECC engine according to claim 3, wherein: The ECC decoder is further configured to: generating the parity-check matrix, the parity-check matrix having a first column vector of the plurality of column vectors, the first column vector having a remainder obtained by dividing a result of raising the alpha matrix to a power by 2k-1, the remainder being less than k, k being the number of data bits in each of the plurality of sub-data units; generating a first sub-check matrix having a second column vector among the plurality of column vectors, the second column vector having a remainder obtained by dividing a result of raising the alpha matrix to power by 2k-1, the remainder being equal to or greater than k and less than 2k-1, and the remainder being an even number; as well as Generate a second sub-check matrix, the second sub-check matrix having a third column vector among the plurality of column vectors and a matrix having 1+α k-1 A column vector of type α, the third column vector has a remainder obtained by dividing the result of raising the alpha matrix to the power of 2k-1, the remainder is equal to or greater than k and less than 2k-1, and the remainder is an odd number, and α is the alpha matrix.

5. The ECC engine according to claim 4, wherein: The ECC decoder is further configured to: generating a first syndrome of the different syndromes by applying the parity-check matrix to the read codeword; In response to the least significant bit (LSB) of the row address of the address being at a low level, generating a second syndrome among the different syndromes by applying the first sub-check matrix to the read codeword; and In response to the LSB of the row address being at a high level, a third syndrome among the different syndromes is generated by applying the second sub-check matrix to the read codeword.

6. The ECC engine according to claim 5, wherein: The ECC decoder is further configured to: correcting the single bit error in the primary data based on the first syndrome; In response to the target page being even-numbered, correcting the adjacent bit errors based on the second syndrome; and In response to the target page being odd-numbered, the adjacent bit error or the non-adjacent bit error is corrected based on the third syndrome.

7. The ECC engine according to claim 5, wherein: The ECC decoder is further configured to correct the adjacent bit error by using a column vector corresponding to a 1+α type among the plurality of column vectors.

8. The ECC engine according to claim 5, wherein: The ECC decoder is further configured to: by using the plurality of column vectors having the 1+α k-1 A column vector of type to correct the non-adjacent bit errors.

9. The ECC engine of claim 1, wherein: The main data includes a plurality of sub-data units, each of the plurality of sub-data units includes a plurality of data bits; and The parity-check matrix includes a plurality of column vectors, the plurality of column vectors being divided into a plurality of code groups corresponding to the plurality of sub-data units and the parity-check data, and Wherein, the ECC decoder is further configured as: generating a first syndrome by applying the parity-check matrix to the codeword; In response to a least significant bit (LSB) of a row address of the address being at a low level, generating a second syndrome by applying a first sub-check matrix to the codeword, the first sub-check matrix being generated according to the parity-check matrix; and In response to the LSB of the row address being at a high level, a third syndrome is generated by applying a second sub-parity check matrix different from the first sub-parity check matrix to the codeword, the second sub-parity check matrix being generated according to the parity check matrix.

10. The ECC engine according to claim 9, wherein: The ECC decoder is further configured to: correcting the single bit error in the primary data based on the first syndrome; In response to the target page being even-numbered, correcting the adjacent bit errors based on the second syndrome; and In response to the target page being odd-numbered, the adjacent bit error or the non-adjacent bit error is corrected based on the third syndrome.

11. The ECC engine according to claim 9, wherein: The ECC decoder is further configured to: generating the first sub-check matrix by performing an XOR operation on a (2i-1)th column vector and a (2i)th column vector among the plurality of column vectors, wherein i is one of 1 to k / 2, k is an integer and is the number of data bits in each of the plurality of sub-data units; and In response to an LSB of the row address of the address being at a low level, applying the first sub-check matrix to the main data in the read codeword.

12. The ECC engine according to claim 9, wherein: The ECC decoder is further configured to: generating the second sub-check matrix by performing an XOR operation on a (2i)th column vector and a (2i+1)th column vector among the plurality of column vectors and performing an XOR operation on a non-adjacent kth column vector and a first column vector in each of the plurality of sub-data units, wherein i is one of 1 to k / 2-1, k is an even number and is the number of data bits in each of the plurality of sub-data units; and In response to the LSB of the row address of the address being at a high level, applying the second sub-check matrix to the main data in the read codeword.

13. The ECC engine according to claim 1, wherein: The ECC decoder comprises: a syndrome generation circuit, configured to generate a first syndrome, a second syndrome, and a third syndrome based on the parity check matrix and the read codeword, and configured to generate a selection signal based on the first syndrome, the least significant bit LSB of the row address of the address, and one of the second syndrome and the third syndrome; a first corrector configured to: provide first output data by correcting the single bit error in the primary data based on the first syndrome; a second corrector configured to: in response to the LSB of the row address being at a low level, provide second output data by correcting the adjacent bit errors in the main data based on the second syndrome; A third corrector configured to: provide third output data by correcting the adjacent bit error or the non-adjacent bit error in the main data based on the third syndrome in response to the LSB of the row address being at a high level; and A selection circuit is configured to select one of the main data, the first output data, the second output data, and the third output data in response to the selection signal and the LSB of the row address, and provide corrected main data or the main data.

14. The ECC engine according to claim 13, wherein: The syndrome generation circuit comprises: A first syndrome generator configured to generate the first syndrome by applying the parity check matrix to the read codeword; a sub-check matrix generator configured to generate a first sub-check matrix based on a first portion of the parity-check matrix, and configured to generate a second sub-check matrix based on a second portion of the parity-check matrix; A second syndrome generator, configured to: generate the second syndrome by applying the first sub-check matrix to the read codeword; A third syndrome generator, configured to: generate the third syndrome by applying the second sub-check matrix to the read codeword; a multiplexer configured to: select one of the second syndrome and the third syndrome based on the LSB of the row address; and The selection signal generator is configured to generate the selection signal based on the first syndrome and an output of the multiplexer.

15. A semiconductor memory device comprising: a memory cell array including a plurality of volatile memory cells connected to a plurality of word lines and a plurality of bit lines; The ECC engine is configured as follows: generating parity data based on the primary data according to the ECC based on the primitive polynomial; storing a codeword including the main data and the parity data in a target page of the memory cell array; reading the codeword from the target page based on an address to generate a syndrome; as well as Correcting at least one erroneous bit in the read codeword based on the syndrome by applying corresponding different syndromes to a single bit error in the read codeword, an adjacent bit error occurring in an adjacent memory cell in the target page, and a non-adjacent bit error occurring in a non-adjacent memory cell in the target page; as well as A control logic circuit is configured to: control the ECC engine based on a command and the address, and The ECC engine is further configured to generate the different syndromes based on a parity check matrix, the parity check matrix being based on a default parity check matrix generated according to the primitive polynomial, and The primitive polynomial has an alpha matrix as a solution belonging to the Galois field.

16. The semiconductor memory device according to claim 15, wherein: The main data includes a plurality of sub-data units, each of the plurality of sub-data units includes a plurality of data bits; The default parity-check matrix includes a plurality of column vectors, and the plurality of column vectors are divided into a plurality of code groups corresponding to the plurality of sub-data units and the parity-check data; The plurality of column vectors correspond to results of raising the alpha matrix to powers; The alpha matrix has index values ​​that gradually increase from zero; and Each of the plurality of column vectors has an element for each of the results of applying the primitive polynomial to a power of the alpha matrix.

17. The semiconductor memory device according to claim 16, wherein: The ECC engine includes an ECC decoder configured to apply corresponding different syndromes to the single bit error, the adjacent bit error, and the non-adjacent bit error, and Wherein, the ECC decoder is further configured as: generating the parity-check matrix, the parity-check matrix having a first column vector of the plurality of column vectors, the first column vector having a remainder obtained by dividing a result of raising the alpha matrix to a power by 2k-1, the remainder being less than k, k being the number of data bits in each of the plurality of sub-data units; generating a first sub-check matrix having a second column vector among the plurality of column vectors, the second column vector having a remainder obtained by dividing a result of raising the alpha matrix to power by 2k-1, the remainder being equal to or greater than k and less than 2k-1, and being an even number; and Generate a second sub-check matrix, the second sub-check matrix having a third column vector among the plurality of column vectors and a matrix having 1+α k-1 A column vector of type α, the third column vector has a remainder obtained by dividing the result of raising the alpha matrix to the power of 2k-1, the remainder is equal to or greater than k and less than 2k-1, and the remainder is an odd number, and α is the alpha matrix.

18. The semiconductor memory device according to claim 17, wherein: The ECC decoder is further configured to: generating a first syndrome by applying the parity-check matrix to the read codeword; In response to a least significant bit (LSB) of a row address of the address being at a low level, generating a second syndrome by applying the first sub-check matrix to the read codeword; In response to the LSB of the row address being at a high level, generating a third syndrome by applying the second sub-check matrix to the read codeword; correcting the single bit error in the primary data based on the first syndrome; In response to the target page being even-numbered, correcting the adjacent bit errors based on the second syndrome; and In response to the target page being odd-numbered, the adjacent bit error or the non-adjacent bit error is corrected based on the third syndrome.

19. The semiconductor memory device according to claim 15, further comprising: An input / output I / O gating circuit is connected between the ECC engine and the storage cell array, The memory cell array includes a plurality of sub-array blocks in a first direction and in a second direction intersecting the first direction. The main data includes a plurality of sub-data units, each of which includes a plurality of data bits, and The control logic circuit is configured to: control the I / O gating circuit to store the plurality of sub-data units and the parity check data in a target sub-array block from the plurality of sub-array blocks.

20. A semiconductor memory device, comprising: a memory cell array including a plurality of volatile memory cells connected to a plurality of word lines and a plurality of bit lines; The ECC engine is configured as follows: generating parity data based on the primary data according to the ECC based on the primitive polynomial; storing a codeword including the main data and the parity data in a target page of the memory cell array; reading the codeword from the target page based on an address to generate a syndrome; as well as Correcting at least one erroneous bit in the read codeword based on the syndrome by applying corresponding different syndromes to a single bit error in the read codeword, an adjacent bit error occurring in an adjacent memory cell in the target page, and a non-adjacent bit error occurring in a non-adjacent memory cell in the target page; as well as a control logic circuit configured to control the ECC engine based on a command and the address, wherein the ECC engine comprises an ECC decoder configured to generate the different syndromes based on a parity check matrix based on a default parity check matrix generated according to the primitive polynomial, wherein the primitive polynomial has an alpha matrix as a solution belonging to a Galois field, and Wherein, the ECC decoder is further configured as: generating a first sub-check matrix and a second sub-check matrix by using the parity-check matrix based on the least significant bit (LSB) of the row address of the address; In response to the LSB of the row address being at a low level, correcting the adjacent bit error by applying the first sub-check matrix to the read codeword; and In response to the LSB of the row address being at a high level, the adjacent bit error or the non-adjacent bit error is corrected by applying the second sub-check matrix to the read codeword.

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