RRAM test method, device and system

Abstract

The invention provides an RRAM test method, device and system. The RRAM test method is used for a test board. The test board comprises memristor arrays arranged in B rows and W columns, and an FPGA (Field Programmable Gate Array). The method comprises the following steps: an upper computer displays a parameter setting interface of a current test of the RRAM; the parameter setting interface displays to-be-input parameters; receiving parameter data input for the to-be-input parameter and an address of the to-be-tested memristor input by a user, and generating and sending an upper computer instruction; the memristors to be tested are one or more memristors in the memristor array; the FPGA generates a driving signal of the address of the memristor to be tested according to a register protocol agreed by the upper computer and the FPGA and the received instruction of the upper computer; sending the driving signal to the memristor to be tested; and receiving a backflow signal of the memristor to be tested, and performing the current test.

Description

Technical Field

[0001] This application relates to the technical field of RRAM (Resistive Random - Access Memory, also known as memristor) testing, and particularly to a testing method, device, and system for RRAM. Background Art

[0002] The existing - technology memristor is a resistive device with a "memory" function. Its resistance value changes with the magnitude and direction of the passing current, and remains unchanged after power - off. This characteristic is highly similar to the plasticity of synapses between biological neurons. The memristor simulates the dynamic adjustment and storage of synaptic weights by changing the resistance value, and directly affects the capacity of the neural network through physical characteristics, such as the number of neurons, synaptic scale, and complexity. Among them, the weight of the simulated synapse corresponds to the weight of the above - mentioned neural network. In this regard, to achieve a capacity of 1024M in the existing technology, if a larger - scale neural network needs to be processed, multiple chips need to be spliced and integrated together. Thus, more chips are used and more space is occupied. Summary of the Invention

[0003] This application provides a testing method, device, and system for RRAM.

[0004] This application provides a testing method for RRAM, which is used for a test board; the test board includes a memristor array arranged in B rows and W columns, and an FPGA. The testing method for RRAM includes: The host computer displays the parameter - setting interface for the current test of RRAM; the parameters to be input displayed on the parameter - setting interface; receives the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generates and sends a host - computer instruction; the memristor to be tested is one or more memristors in the memristor array; The FPGA generates a driving signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA, based on the received host - computer instruction; gives the driving signal to the memristor to be tested; receives the return signal of the memristor to be tested and conducts the current test.

[0005] Furthermore, the parameter - setting interface displays a chart corresponding to a switch array arranged in B rows and W columns, which corresponds to each memristor in the memristor array; the switch array is used to control the switches of the memristors to be tested; Receiving parameter data input for the to-be-input parameter and the address of the memristor to be tested input by the user, includes: if it is detected that the user operates in the chart, determining the address of the memristor to be tested; wherein, while selecting the address of the memristor to be tested in the chart, it is automatically filled at the memristor input position in the parameter setting interface.

[0006] Further, the if it is detected that the user operates in the chart, determining the address of the memristor to be tested, includes: detecting the first position selected by the user in the chart as the starting position of the selected area of the memristor to be tested; detecting that the user moves and drags from the selected first position to the second position and stops, as the ending position of the selected area of the memristor to be tested; taking the address of the memristor within the area selected between the starting position and the ending position as the address of the memristor to be tested; Or, Taking the positions successively selected by the user in the chart as the address of the memristor to be tested.

[0007] Further, the chart displayed by the parameter setting interface arranged in B rows and W columns corresponds to each memristor in the memristor array; the switch array is used to control the switches of the memristors to be tested; Receiving parameter data input for the to-be-input parameter and the address of the memristor to be tested input by the user, includes: obtaining the address of the memristor to be tested from the local; automatically importing and filling the address of the memristor to be tested at the memristor input position in the parameter setting interface, and correspondingly displaying it in the selected area in the chart.

[0008] Further, the chart displayed by the parameter setting interface arranged in B rows and W columns corresponds to each memristor in the memristor array; Receiving parameter data input for the to-be-input parameter and the address of the memristor to be tested input by the user, includes: receiving the address of the memristor to be tested input by the user at the memristor input position in the parameter setting interface; the address of the memristor to be tested is correspondingly displayed in the selected area in the chart.

[0009] Further, the host computer displays the parameter setting interface for the current test of the RRAM, includes: the host computer receives the current test selected from multiple memristor tests and displays the parameter setting interface for the current test; the multiple memristor tests include two or more of the read-write test, weight modulation, identification test, and multi-functional test integrated in the host computer.

[0010] Further, after the current test, the method further includes: when receiving a parameter setting interface for switching to the next test as the parameter setting interface for this test, if it is detected that there is saved data from the previous test, extracting the saved data that can be used in this test and automatically filling it into the parameter setting interface for this test; wherein, the saved data refers to the data saved at the end of the previous test; the saved data used in this test includes the address of the memristor to be tested.

[0011] Further, when the current test includes an identification test, the receiving of the parameter data input for the parameter to be input includes: receiving a batch import instruction; importing the parameter data from the local according to the batch import instruction; the parameter data includes horizontal voltage parameter data and pulse width parameter data.

[0012] Further, the test board includes a control circuit; the control circuit includes a digital-to-analog converter (DAC) chip and an analog-to-digital converter (ADC) chip; generating a drive signal for the address of the memristor to be tested according to the received host computer instruction in accordance with the register protocol agreed upon by the host computer and the FPGA; supplying the drive signal to the memristor to be tested; receiving the feedback signal of the memristor to be tested and performing the current test, including: generating any voltage data for the word line (WL) control line required by the user according to the host computer instruction; the any voltage data includes any voltage value or any voltage curve, and supplying it to the WL pin of the RRAM chip by driving the DAC chip; and, generating any voltage data for the bit line (BL) required by the user according to the host computer instruction; the voltage data includes a voltage value or a voltage curve, and supplying it to the BL pin and / or the source line (SL) pin of the RRAM chip by driving the DAC chip and a switch; generating voltage data for the BL pin and / or the SL pin required by the user according to the host computer instruction, and reading back the current value by driving the switch and the ADC chip.

[0013] This application provides a test method for RRAM, which is applied to a host computer in the test method for RRAM as described above, and includes: displaying a parameter setting interface for the current test of the RRAM; the parameters to be input displayed on the parameter setting interface. Receiving the parameter data input for the parameter to be input and the address of the memristor to be tested input by the user, generating and sending a host computer instruction; the memristor to be tested is one or more memristors in a memristor array arranged in rows of B and columns of W in the test board, so that the FPGA generates a drive signal for the address of the memristor to be tested according to the received host computer instruction in accordance with the register protocol agreed upon by the host computer and the FPGA; supplying the drive signal to the memristor to be tested; receiving the feedback signal of the memristor to be tested and performing the current test.

[0014] The present application provides a test device for RRAM, which is used to implement the test method for RRAM as described above. The test device for RRAM includes: a parameter setting interface that displays the current test parameters of the RRAM; the parameters to be input displayed on the parameter setting interface; receives the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generates and sends a host computer instruction; the memristor to be tested is one or more memristors in a memristor array arranged in B rows and W columns on a test board, so that the FPGA generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA based on the received host computer instruction; gives the drive signal to the memristor to be tested; receives the return signal of the memristor to be tested, and performs the current test.

[0015] The present application provides a test system for RRAM, including: a test board, which includes a memristor array arranged in B rows and W columns; a host computer, which is used to display a parameter setting interface for the current test of the RRAM; the parameters to be input displayed on the parameter setting interface; receives the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generates and sends a host computer instruction; the memristor to be tested is one or more memristors in the memristor array; an FPGA, which is used to generate a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA based on the received host computer instruction; gives the drive signal to the memristor to be tested; receives the return signal of the memristor to be tested, and performs the current test.

[0016] Further, the FPGA drive in the FPGA includes a processing system PS side and a programmable logic PL side connected to the PS side. The PS side is connected to the host computer and is used for the functions of communication between the PS side and the host computer and storing register instructions; each module in the PL drives the corresponding hardware module by reading the data in the RRAM; Further, the FPGA drive includes a programmable logic PL side. The PL side is connected to the host computer and is used for the functions of communication between the PL side and the host computer, storing register instructions, and each module in the PL drives the corresponding hardware module by reading the data in the RRAM.

[0017] Further, the FPGA driver in the FPGA includes a processing system PS side and a programmable logic PL side connected to the PS side. The host computer is further configured to convert the to-be-input parameters into hexadecimal instructions according to the register protocol and transmit them to the PS side of the FPGA through a network port; the PS side stores the data in the RRAM and waits for the PL side to read it; the PL side reads the data stored in the RRAM by the PS side and returns it to the data of the host computer; after the PL side reads the data, according to the register protocol agreed by the FPGA included in the host computer instruction, it drives the corresponding DAC chip and ADC chip, and stores the register protocol agreed by the FPGA in the RRAM array.

[0018] Further, the memristor array has a memory function; the memory function is used to indicate that after the conductance value of the memristor array is successfully set, it will not be lost when powered off; the FPGA is configured to convert the image input by the user into a voltage signal and apply it to the target end of the memristor array to obtain the current value read by the target end; the current value is used to reflect the operation result; the operation result is transmitted to the host computer or drives the braking device to make a response.

[0019] The present application provides a computer-readable storage medium, on which a program is stored, and when the program is executed by a processor, the method described in any one of the above is implemented.

[0020] The present application provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by a processor, the method described in any one of the above is implemented.

[0021] In some embodiments, the test method of the RRAM of the present application controls the host computer, the FPGA, and a test board including a memristor array arranged in B rows and W columns. The FPGA generates a driving signal for the address of the memristor to be tested according to the received host computer instruction according to the register protocol agreed by the host computer and the FPGA; gives the driving signal to the memristor to be tested; receives the return signal of the memristor to be tested and performs the current test. Since the memristor array includes a plurality of memristors and has a large capacity, it can process larger-scale neural networks, and the memristor array is integrated in the test board, occupying less space. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1a is a schematic structural diagram of an RRAM test system to which the RRAM test method provided by the embodiment of the present application is applied; Figure 1b is Figure 1a a specific structural diagram in the RRAM test system shown; Figure 1c is Figure 1aSchematic diagram of a preset memristor array in the RRAM test system shown; Figure 2 Flow schematic diagram of the RRAM test method provided by the embodiment of the present application; Figure 3 As shown Figure 2 Schematic diagram of the host computer display recognition test of the RRAM test method shown; Figure 4 As shown Figure 2 Schematic diagram of the host computer display read-write test of the RRAM test method shown; Figure 5 As shown Figure 2 Schematic diagram of the host computer display weight modulation test of the RRAM test method shown; Figure 6 As shown Figure 2 Schematic diagram of the host computer display multi-functional test of the RRAM test method shown; Figure 7a As shown Figure 2 Logic flow diagram of the read-write test in the RRAM test method shown; Figure 7b As shown Figure 2 Logic flow diagram of the weight modulation in the RRAM test method shown; Figure 7c As shown Figure 2 Logic flow diagram of the recognition test in the RRAM test method shown; Figure 7d As shown Figure 2 Logic flow diagram of the multi-functional test in the RRAM test method shown; Figure 8 As shown Figure 2 Schematic diagram of the pulse displayed by the host computer in the RRAM test method shown; Figure 9a As shown Figure 2 Change of the control voltage in the process of enhanced linear scanning in the RRAM test method shown; Figure 9b As shown Figure 2 Change of the control voltage in the process of suppressed linear scanning in the RRAM test method shown; Figure 10 Flow schematic diagram of the RRAM test method provided by the embodiment of the present application applied to the host computer; Figure 11 Structure schematic diagram of the host computer provided by the embodiment of the present application. Detailed implementation manners

[0023] Exemplary embodiments will be described in detail herein, and examples thereof are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with one or more embodiments of this specification. On the contrary, they are merely examples of devices and methods consistent with some aspects of one or more embodiments of this specification as detailed in the appended claims.

[0024] It should be noted that: in other embodiments, the steps of the corresponding method are not necessarily executed in the order shown and described in this specification. In some other embodiments, the steps included in the method may be more or less than those described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step for description in other embodiments.

[0025] To solve the above technical problem of a large number of chips and large space occupation, an embodiment of the present application provides a testing method for RRAM, which controls a host computer, an FPGA (Field-Programmable Gate Array), and a test board including a memristor array arranged in B rows and W columns. The FPGA generates a driving signal for the address of the memristor to be tested according to the received host computer instruction in accordance with the register protocol agreed upon by the host computer and the FPGA; gives the driving signal to the memristor to be tested; receives the return signal of the memristor to be tested, and performs the current test. Since the memristor array (also referred to as the RRAM array) includes a plurality of memristors and has a large capacity, it can process a larger-scale neural network, and moreover, the memristor array is integrated in the test board, occupying less space.

[0026] Figure 1a It is a schematic structural diagram of a testing system for RRAM to which the testing method for RRAM provided by an embodiment of the present application is applied. Figure 1b For Figure 1a The specific structural diagram in the shown testing system for RRAM.

[0027] As Figure 1a shown, the testing system for RRAM to which the testing method for RRAM is applied may include, but is not limited to, a host computer and a test board. The test board includes an FPGA and a control circuit.

[0028] Among them, the test board includes a memristor array (which can also be called a non-volatile memory array) arranged in B rows and W columns. The memristor array for the test board is being tested. Here, B represents the row number, W represents the column number, and B and W are each greater than or equal to 1. Exemplarily, B rows can be 32 rows. W columns can be 32 columns. 32 rows and 32 columns is 1 kb. Of course, B and W can also be integer multiples greater than 32. For example, B is 32 4, and W is 32 4, which means 4 kb, equivalent to 4 arrays spliced together and selected by a chip select signal. Of course, the sizes of B and W depend on the design scale of the chip and can also be 1 megabyte (M).

[0029] When the user uses it, the address of the memristor input changes. With the development of integrated circuits, mobile communications, and the Internet of Things, the demand for non-volatile memories is increasingly shifting towards large capacity, low power consumption, high density, and low cost. Metal oxide resistive switching devices are a very promising new type of non-volatile memory, and their typical structure is metal electrode - oxide - metal electrode. Under the excitation of an external electric field, the non-volatile memory can reversibly transform between high and low resistance states, and its high and low resistance states can still be maintained after the electric field is removed.

[0030] Continue as Figure 1b shown, the control circuit can include but is not limited to a digital-to-analog conversion chip, an amplification circuit, a clock generation chip, and a switching circuit connected to the RRAM chip. Among them, the switching circuit can include a switch matrix. The control circuit can be used for a series of memristor artificial intelligence chips (with address selection lines and WL (Word Line), BL (abbreviation for Bit Line), SL (abbreviation for source line) read and write lines).

[0031] Among them, the FPGA gives a hexadecimal code 8000 and codes for configuring the chip working mode, etc. to the digital-to-analog conversion chip. The digital-to-analog conversion chip is used to convert the digital quantity used by the FPGA and the analog quantity used by the hardware circuit, and generate a corresponding voltage to be connected to the amplification circuit as the input of the amplification circuit. Since the digital-to-analog conversion chip only has the conversion ability, the final obtained voltage and current are very small. Therefore, through the above amplification circuit, the voltage and current transmitted by the digital-to-analog conversion chip are amplified and then given to the specific terminals of the RRAM chip. The above clock generation chip is used to generate high-precision clocks for all chips and control the rhythm of all signals. Since the RRAM chip requires a relatively high clock precision (pulse width 10 ns), it is calculated that the ADC clock is as high as 800 Mhz. Therefore, a separate clock generation chip is required. And, the above switching circuit is used to switch the chips connected to the specific terminals of the RRAM chip to control the devices connected to WL, BL, and SL that are not connected, that is, to switch between read mode and write mode, etc.

[0032] Figure 1c For Figure 1a Schematic diagram of a preset memristor array in the test system of the RRAM shown in the figure.

[0033] As Figure 1c Shown in the figure, through an integrated circuit of memristors and transistors, matrix multiplication of the linear weight coefficient column in the line speed parameter matrix and the matrix composed of each input variable is realized, and the memristor array with j = 0 is the reference column. Among them, BL is the bit line of the memristor array, which realizes the control of the input voltage, and WL is the external control signal of the memristor array.

[0034] Based on this, continue as Figure 1a 、 Figure 1b And Figure 1c Shown in the figure, the host computer communicates with the FPGA through a fixed communication protocol. Among them, the fixed communication protocol can include but is not limited to TCP (Transmission Control Protocol) and / or UDP (User Datagram Protocol). The front-end interface of the host computer is developed with vue (pronounced / vjuː / , similar to view, a JavaScript framework for building user interfaces based on standard HTML, CSS, and JavaScript, which provides a declarative and component-based programming model and can efficiently develop user interfaces), and the back-end is developed with the go (also known as Golang, an open-source programming language) language. The main function interfaces of the host computer include four parts: read-write test, weight modulation, recognition test, and multi-functional test.

[0035] Each functional host computer realizes the following various tests through the following operation logic: Read-write test: Supports FORMING, SET, and RESET (restore a certain system or state to the initial or default state) operations for a single device. Specifically, the voltages, pulse widths, and the number of pulses of BL, SL, and WL can be set, and the read-back current data can be displayed and saved. Among them, the FORMING process refers to the process in which the RRAM jumps from the initial high-resistance state to the low-resistance state for the first time. On the contrary, the RRAM in the low-resistance state can be converted to the high-resistance state after being applied with a certain voltage excitation. The process of jumping from the low-resistance state to the high-resistance state is called RESET. The RRAM that enters the high-resistance state after the RESET process can also be converted to the low-resistance state by applying a voltage excitation, and this process, which is different from the first high-resistance state to low-resistance state jump, is called the SET process.

[0036] Weight modulation: With other pulse parameters unchanged, one parameter (WL, BL, SL voltage value, pulse width, or number of pulses) increases or decreases by a certain amplitude. When the current resistance value is smaller than the target resistance value, change the parameter value and perform the SET loop operation; conversely, change the parameter value and perform the RESET loop operation. If the target resistance value tolerance range is not reached after exceeding the modulation times, it indicates modulation failure; otherwise, it indicates modulation success.

[0037] The gate voltage modulation in the above weight modulation means that with other pulse parameters unchanged, the RESET and SET gate voltages (the SET gate voltage is the key point) can increase or decrease by a certain amplitude. When the current resistance value is smaller than the target resistance value, perform the RESET loop operation with the gate voltage increasing; conversely, perform the SET loop operation with the gate voltage increasing.

[0038] The amplitude modulation in weight modulation means that with other pulse parameters unchanged, the BL and SL voltages of RESET and SET can increase or decrease by a certain amplitude. When the current resistance value is smaller than the target resistance value, perform the RESET loop operation with the SL voltage increasing, and the BL voltage is 0V; conversely, perform the SET loop operation with the BL voltage increasing, and the SL voltage is 0V.

[0039] The pulse width modulation in weight modulation means that with other pulse parameters unchanged, the pulse widths of RESET and SET can increase or decrease in a certain step. When the current resistance value is smaller than the target resistance value, perform the RESET loop operation with the pulse width increasing, and the BL voltage is 0V; conversely, perform the SET loop operation with the pulse width increasing, and the SL voltage is 0V.

[0040] The pulse modulation in weight modulation means that during the cyclic modulation process, the SET and RESET parameters remain unchanged, and only the number of applied SET and RESET pulses is changed. When the current resistance value is smaller than the target resistance value, perform the RESET loop operation, and the BL voltage is 0V; conversely, perform the SET loop operation, and the SL voltage is 0V.

[0041] Identification test: Essentially, it simultaneously turns on multiple rows and columns of devices to achieve matrix multiplication and addition operations. It is possible to set in the software interface which rows and columns to turn on and batch import 32 BL or SL voltage vectors. The currents read from the 32 BL or SL terminals are displayed in the form of a histogram, and the current data can be saved, and the data saving path can be selected.

[0042] The multi-functional test includes retention test, DC cycle test, and yield test: Retention test refers to performing a read operation at regular intervals, with the same pulse parameters for each read operation, saving the read resistance data, and observing the retention of the device; DC cycle test is essentially a pulse operation, which means that a single device is first subjected to a RESET cycle operation with an increasing SL voltage, then a RESET cycle operation with a decreasing SL voltage, followed by a SET cycle operation with an increasing BL voltage, and finally a SET cycle operation with a decreasing BL voltage. This is called a cycle, and the current change of the device during RESET and SET is read from the SL end. The number of cycles can be set, and the SET parameters and RESET parameters can be set; yield test refers to the percentage of normal SET and RESET cycles that can be performed after the entire array is formed.

[0043] Continue as Figure 1a , Figure 1b and Figure 1c As shown in the figure, FPGA development is divided into two parts: PS (Processing System) and PL (Programmable Logic).

[0044] The PS side implements the communication with the host computer and the register storage instruction function. Each module in the PL side drives the corresponding hardware module by reading the data in the RRAM: The function of the WL control line voltage configuration module is to generate any voltage value or any voltage curve of the WL control line required by the user according to the host computer instruction, and provide it to the WL pin of the RRAM chip by driving the DAC (Digital-to-Analog Converter) chip; The function of the BL / SL write voltage control module is to generate the BL voltage value or voltage curve required by the user according to the host computer instruction, and provide it to the BL / SL pin of the RRAM chip by driving the high-speed DAC chip and the switch; where " / " means "and / or".

[0045] The function of the BL / SL voltage reading module is to generate the BL / SL voltage value or any voltage curve required by the user according to the instructions of the host computer, and read back the current value by driving the switch and the high-speed ADC (Analog-to-Digital Converter) chip; at the same time, it also needs to cooperate with the switch module to turn off the switch on the unused line to reduce the crosstalk between the lines.

[0046] This article encapsulates the low-level control logic through the host computer to facilitate high-level development and expansion.

[0047] Figure 2 The figure is a flow chart of a RRAM testing method provided in an embodiment of the present application.

[0048] As Figure 2 shown, the test method for the RRAM is used for a test board; the test board includes a memristor array arranged in B rows and W columns, and may include but is not limited to the following steps 110 to 120: Step 110, the host computer displays the parameter setting interface for the current test of the RRAM; the parameters to be input displayed on the parameter setting interface; receives the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generates and sends a host computer instruction; the memristor to be tested is one or more memristors in the memristor array. Among them, the faulty memristors may not be displayed.

[0049] In this article, when the current test is a single test, it is default to directly display the parameter setting interface for this current test.

[0050] Figure 3 As shown Figure 2 is a schematic diagram of the host computer display for identifying the test of the RRAM test method shown.

[0051] As Figure 3 shown, the test list may include multiple tests, and the multiple tests include the current test such as the identification test 111. Another example of the current test is the read / write test 112, as shown below Figure 4 shown, another example of the current test is the weight test 113, as shown below Figure 5 shown, another example of the current test is the multi-functional test 114, as shown below Figure 6 shown. The options for each of the multiple tests are displayed. By clicking on the options for each test, it is then switched to the options for the clicked test. The options include the options for each test, such as the options for the read / write test, the options for the weight modulation, the options for the identification test, or the options for the multi-functional test, Figures 3 to 5 only indicates the option for one "multi-functional test" as an example. Figure 6 only indicates the option for one "read / write test" as an example.

[0052] Step 120, the FPGA generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA, based on the received host computer instruction; gives the drive signal to the memristor to be tested; receives the return signal of the memristor to be tested and conducts the current test.

[0053] It should be noted that the register protocol (as shown in Table 1 below) is the core of the communication between the host computer and the FPGA, and by defining the format, rules, and timing of data exchange, it ensures that the two can interact efficiently and reliably.

[0054] As Figure 3 shown,Figure 3 Select the option corresponding to the test category: On each test page, four test categories, namely read-write test, weight modulation, recognition test, and multi-functional test, are fixedly displayed. The test categories are presented in the form of TABs. When initially entering the test page, there is no data under each test category; the data for each test category is independent. When switching test categories, the data under the test category is retained; only when the user clicks to close the device test page will the data be cleared the next time it is opened. For example Figure 3 The status of device number 14 is normal. As a programming interface for users, the address of the RRAM array required by the user and the required conductance value can be sent to the FPGA according to the register protocol agreed upon by the host computer and the FPGA. The format of the register instruction uses a 64-bit hexadecimal number, as shown in Table 1 below. Specifically, it includes a 16-bit fixed instruction header 55d5, a 1-bit read-write bit where 0 represents writing to the FPGA register and 1 represents reading back FPGA data, a 15-bit register address, and a 32-bit register data. The register instruction information is shown in Table 1.

[0055] Table 1 Register Instruction Information

[0056] Among them, in the above Table 1, the above register instruction information includes fixed bits, register addresses, and data bits. Among them, the information of the register is in hexadecimal, the fixed bit is 55aa, the register address is 000C, etc., and the remaining other bits 000000001 are data bits. The FPGA design in this article stipulates the above register information.

[0057] Based on this, the above register protocol can have the following functions: (1) Data communication: The register protocol defines how the FPGA and the host computer exchange data through registers. The host computer can access the internal registers of the FPGA through specific addresses, write control commands or data; while the FPGA can read or modify data through the registers and return it to the host computer.

[0058] (2) Control and configuration: The register protocol allows the host computer to control the behavior of the FPGA by writing to the FPGA registers. For example, the host computer can start or stop a certain module inside the FPGA, change the processing mode, or change the signal processing method by setting certain bits of the register.

[0059] (3) Status feedback: The FPGA can report its current status, operation results, or processing progress to the host computer by reading certain registers. In this way, the host computer can timely understand the working conditions of the FPGA and make corresponding processing. Among them, the register protocol for the instructions between the above host computer and the FPGA is shown in Table 2:

[0060] Table 2 Register Protocol for Host Computer and FPGA Instructions

[0061] Next, it should also be noted that the above step 120 may include, but is not limited to: generating any voltage value or any voltage curve of the word line WL control line required by the user according to the host computer instruction, and giving it to the WL pin of the RRAM chip by driving the digital-to-analog converter DAC chip; and generating the bit line BL voltage value or voltage curve required by the user according to the host computer instruction, and giving it to the BL pin and / or the source line SL pin of the RRAM chip by driving the DAC chip and the switch; generating the BL and / or SL voltage value or any voltage curve required by the user according to the host computer instruction, and reading back the current value by driving the switch and the analog-to-digital converter ADC chip.

[0062] Continue as Figure 3 shown, the parameter setting interface displays the chart corresponding to the switch array arranged in B rows and W columns, which corresponds to each memristor in the memristor array. The chart corresponding to the switch array is pre-associated with the memristor array, so the switch array can be a switch for controlling the memristor to be tested. In this way, in this article, by establishing in advance a way to control each memristor, the chart 13 of the switch array corresponding to each memristor is integrated on the host computer. In this way, each memristor can be correspondingly controlled by selecting the switch in the switch array of the chart. Of course, one memristor can be selected at a time, or multiple memristors can be selected, depending on the actual situation, and it is not limited here.

[0063] Based on this, combined with Figure 4 shown, in the above step 110, if it is detected that the user operates in the chart, the address of the memristor to be tested is determined; among them, while selecting the address of the memristor to be tested in the chart, it is automatically filled in the memristor input position 21 in the parameter setting interface. In this way, the parameter data input for the to-be-input parameter and the address of the memristor to be tested input by the user can be received.

[0064] The above determination of the address of the memristor to be tested if it is detected that the user operates in the chart can be implemented by at least any one of the following methods: In an alternative approach, the first position where the user is detected to select on the graph is taken as the starting position of the box selection area of the memristor to be tested; the position where the user is detected to move and drag from the first selected position to the second position and then stop is taken as the ending position of the selection area of the memristor to be tested; the addresses of the memristors within the area boxed between the starting position and the ending position are taken as the addresses of the memristors to be tested. Exemplarily, for instance, after the user clicks on the first position and then drags the mouse or the selection box to the second position, the boxed area is obtained, and the addresses of the memristors within the boxed area are taken as the addresses of the memristors to be tested, so that after the current test and subsequent parameter settings, these memristors to be tested can be turned on.

[0065] Among them, the "first" in the "first position" and the "second" in the "second position" are used to distinguish any two different positions of the switch array in the graph, so as to conveniently determine the memristors to be tested at one time.

[0066] In the second alternative approach, the positions where the user is detected to select one by one on the graph are taken as the addresses of the memristors to be tested. For example, by clicking one by one on the graph and recording the positions of each click as the addresses of the memristors to be tested, so that after the current test and subsequent parameter settings, these memristors to be tested can be turned on.

[0067] Of course, the above selection methods may include but are not limited to selecting adjacent ones one by one or selecting with any position in between. In this way, it is convenient for the user to select the memristors to be tested one by one according to their own wishes.

[0068] Figure 4 Shown as Figure 2 The schematic diagram of the host computer display read-write test of the RRAM test method shown.

[0069] As Figure 4 Shown, in the third alternative approach, in the first step, obtain the addresses of the memristors to be tested from the local. In the second step, automatically import and fill the addresses of the memristors to be tested into the memristor input position 21 within the parameter setting interface and correspondingly display them in the selected area in the graph. Among them, the memristor input position 21 is the Figure 4 selected coordinates shown.

[0070] In the fourth alternative approach, receive the addresses of the memristors to be tested input by the user in the memristor input position 21 within the parameter setting interface; the addresses of the memristors to be tested are correspondingly displayed in the selected area in the graph. In this way, the memristors to be tested can be directly input according to the user's needs, meeting the user's requirements.

[0071] When any memristor fails, the switch array in the corresponding chart displays a fault identifier, which is different from the normal identifier of the memristor. Among them, the fault identifier is used to indicate that the memristor is abnormal. The normal identifier is used to indicate that the memristor is normal. Of course, the fault identifier or the normal identifier can be distinguished by color, text, etc., which is not limited here. For example, the color of the normal identifier of the memristor is that the chart of the switch array shows no color. The color of the fault identifier of the memristor is gray. For another example, the character of the fault identifier of the memristor is "f" (abbreviation of fault, meaning fault).

[0072] Based on this, in the fifth optional method, the first position detected by the user's selection in the chart is used as the starting position of the selected area of the memristor to be tested; the position where the user is detected to move and drag from the first selected position to the second position and stop is used as the ending position of the selected area of the memristor to be tested; automatically delete the switch array corresponding to the fault identifier in the addresses of the memristors within the selected area between the starting position and the ending position, and use the addresses of the memristors within the selected area between the starting position and the ending position after deletion as the addresses of the memristors to be tested. In this way, abnormal memristors can be excluded and normal memristors can be batch-tested.

[0073] Figure 5 As shown in Figure 2 the schematic diagram of the host computer displaying the weight modulation test of the RRAM test method shown. Figure 6 As shown in Figure 2 the schematic diagram of the host computer displaying the multi-functional test of the RRAM test method shown.

[0074] Combined with Figures 2 to 4 , and Figure 5 and Figure 6 shown, the parameter setting interface of the current test of the RRAM displayed by the host computer in step 110 above can be displayed in the following way: when the host computer receives the current test selected from multiple memristor tests, display the parameter setting interface of the current test; multiple memristor tests include two or more of the read-write test, weight modulation, identification test, and multi-functional test integrated in the host computer.

[0075] As an embodiment, after the current test, the method may further include but is not limited to: when receiving the parameter setting interface switched to the next test as the parameter setting interface of this test, if it is detected that there is saved data in the previous test, extract the saved data that can be used in this test and automatically fill it in the parameter setting interface of this test; where the saved data refers to the data saved at the end of the previous test; the saved data used in this test includes the addresses of the memristors to be tested.

[0076] It should be noted that detecting the existence of saved data in the previous test may include, but is not limited to, the following examples: Example 1: Receiving an instruction from the user to save the address of the memristor to be tested in the current test.

[0077] Example 2: Receiving an instruction to save the default settings.

[0078] In the embodiments of the present application, it is possible to perform the next test on the address of the same memristor to be tested, realizing the sharing of test data without the user having to re-enter the test data.

[0079] Continue to refer to Figure 3 In the embodiment shown, when the above-mentioned current test includes an identification test, receiving parameter data input for the parameter to be input, including: receiving a batch import instruction; importing parameter data from the local according to the batch import instruction; the parameter data includes horizontal voltage parameter data and pulse width parameter data. In this way, parameter data can be imported from the local, reducing the operations of user input and improving the user usage efficiency.

[0080] In another embodiment, before the upper computer displays the parameter setting interface for the current test of the RRAM, the method further includes: displaying the login interface for the current test of the RRAM; receiving the login information input by the user for the login interface; after verifying that the login information is passed, the upper computer displays the parameter setting interface for the current test of the RRAM.

[0081] In the embodiments of the present application, receiving the experimental deployment requirements of the RRAM input by the user on the upper computer, the specific implementation may include the following steps: Step 1: The user maps the parameters of network models such as fuzzy control algorithms, neural network algorithms (BNN, SNN, RNN, CNN, etc.) into a set of conductance values within the RRAM conductance value range at a certain ratio, and gives the corresponding BL, SL, WL voltage values. Fill them in the upper computer, and the upper computer sends them to the FPGA after receiving the instruction for preprocessing. Through the DoReadTest processing logic, judge whether the parameters are compliant. If not, it is considered an error. If so, asynchronously loop and send messages to the Client side. Asynchronously record the operation logs, and the relevant operations are performed by the client Client, and the server Server stores the data. In this way, the upper computer serves as the server side and the FPGA serves as the client side. The stored parameters can be any data transmitted through the network port, such as: the device number of the FPGA, the voltage value sent to the FPGA, the read current value, etc.

[0082] After the FPGA and the hardware execute the relevant operations in response to the instruction, the upper computer makes the next judgment on the returned instruction and the test type selected by the user. This part is implemented by the backend part of the upper computer. The logical process for the read-write test is as Figure 7a The logical process for weight modulation is asFigure 7b The logical flow of the recognition test is as follows Figure 7c and the logical flow chart of the multi-functional test is as follows Figure 7d shown in the figure

[0083] Referring to Kirchhoff's current law, according to the voltage values after quantization of each input variable, input them into the preset memristor array to obtain the current values of each column Taking the determination of the linear velocity output matrix as an example, it is as follows where represents the conductance values of each memristor in the array opened by the host computer is the conductance value of each memristor in the reference column represents the row represents traversing once from 0 to λ as an integer takes values from 0 to λ, and λ represents the number of input variables represents the column is the product of the conductance value after quantization of each linear weight coefficient in the j-th row of the linear velocity parameter matrix implemented by the memristor array and the voltage value after quantization of each input variable, that is, the current value output from the j-th column is the voltage value corresponding to the input variable Vi obtained through the preset voltage quantization ratio

[0084] The host computer user selects the recognition test and inputs the voltage value as needed. The host computer sends the parameters to the FPGA according to the register protocol shown in Table 1 through the network UDP (User Datagram Protocol) protocol. The register instruction consists of the following parts: 16-bit fixed instruction header hex55d5 + 1-bit read / write flag (0: read, 1: write) + 15-bit register address + 32-bit register data. After waiting for the hardware response, the host computer reads back the current value and displays it

[0085] Step 2: After the PS side of the FPGA receives the host computer instruction, it writes it into the RRAM, and the PL side configures each module by reading the data in the RRAM

[0086] such as Figure 1bAs shown, for example: The WL control line voltage configuration module corresponds to driving the AD5532 chip on the hardware circuit. First, it initializes and configures the AD5532 through the SPI (Serial Peripheral Interface) protocol, and then continuously sends level values to the chip pins according to the rhythm of the counter based on the data in the register. The BL / SL write voltage control module corresponds to driving the AD (Analog Devices) 9148 chip on the hardware circuit (this chip is a high-speed DAC chip, and the FPGA needs to pre-burn the driver program for the clock module AD9516. In this patent, a 100Mhz configuration is adopted, so the control accuracy of the chip reaches 1ns), and then continuously sends level values to the chip pins according to the rhythm of the counter based on the data in the register. The read voltage control configuration module corresponds to driving the LTM511 chip on the hardware circuit. An innovation point of this module is to automatically judge whether the data read back from the chip is correct, and then perform preliminary averaging of multiple read data and transmit it to the host computer. The specific logic is as follows: The FPGA first configures the ADC chip into the test mode, reads back the signals of 16 pins of the ADC chip and compares them with the PATTERN written by the chip configuration mode. If the comparison is correct 1024 times in a loop, it is considered that the read current value and the clock are both accurate, and then it switches to the normal mode to read the current. The current averaging is to accumulate the currents read back 4 times, shift the accumulated result 2 bits to the left (the effect of dividing by 4), and write it into the register, waiting for the host computer to read.

[0087] The row and column selection module automatically opens the corresponding switches according to the rows and columns given by the host computer. The signal transmission of all modules in step two is as Figure 1a 、 Figure 1b and Figure 1c shown in the cfg_main framework.

[0088] Step three: The FPGA transmits the data to the host computer through the network port controlled by the phy (Physical Layer Chip) chip, and the host computer displays it. The schematic diagram of the pulse is as Figure 8 shown. The signals on the hardware circuit can be detected by an oscilloscope or a voltmeter.

[0089] Other embodiments of this application, for example: The implementation of the write verification logic: Figure 9a For enhancing the change of the control voltage in the process of linear scanning. Figure 9b For suppressing the change of the control voltage in the process of linear scanning. As Figure 9a shown, Vgs is the voltage difference between the WL and SL terminals, and Vbs is the voltage difference between the BL and SL terminals. Figure 9aIt is shown that with the SL voltage and the BL voltage remaining unchanged, the voltage of WL is increased to perform a SET operation with an increasingly higher voltage until the target conductance value is reached. As Figure 9b shown, each time a complete RESET is first performed, and then a SET is carried out until the target conductance value is reached.

[0090] Generally, before performing write verification, the host computer first determines whether the device is within the target conductance value. If it is within the range of the target conductance value, the process ends. Among them, the range of the target conductance value depends on the user input parameters. For example, the user inputs: the target conductance value is 100 uS (the target resistance value is 10 kΩ, and the resistance value and the conductance value are reciprocal relationships), and the tolerance range is: 1%. Then the range of the target conductance value is: 99.00 uS to 101.00 uS.

[0091] In this regard, it is determined whether the memristor reaches the range of the target conduction value. If so, it indicates success and the process ends. If not, continue with SET or REST until the maximum number of attempts is reached and still not successful, then the process ends.

[0092] Specifically, the scanning process corresponding to SET is to give the memristor a SET voltage once, and then record the current write count n and read the conductance value for judgment: determine whether the read conductance value reaches the range of the target conduction value; if so, it indicates successful writing; if not, after increasing or decreasing the voltage, continue the scanning corresponding to SET and update the write count n + 1 until the maximum write count, that is, N cycles, and the read conductance value does not reach the range of the target conduction value, then it indicates failed writing.

[0093] The scanning process corresponding to RESET is to give the memristor a RESET voltage and then a SET voltage after that, so as to alternately apply the RESET voltage and the SET voltage to the memristor, and then record the current write count n and read the conductance value for judgment: determine whether the read conductance value reaches the range of the target conduction value; if so, it indicates successful writing; if not, after increasing or decreasing the voltage, continue the RESET scanning and update the write count n + 1 until the maximum write count, that is, N cycles, and the read conductance value does not reach the range of the target conduction value, then it indicates failed writing. Each scanning control curve of a SET or a RESET is a cycle. If after N cycles, the target value still cannot be reached, it is considered that the RRAM device cannot reach the target conductance value.

[0094] Based on the same inventive concept as the above method, an embodiment of the present application further provides a test method for RRAM, as Figure 10 shown, the host computer applied to the above RRAM test method may include but is not limited to the following steps 210 to step 220: Step 210: Display the parameter setting interface for the current RRAM test; the parameters to be input displayed on the parameter setting interface.

[0095] Step 220: Receive the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generate and send a host computer instruction; the memristor to be tested is one or more memristors in the memristor array arranged in B rows and W columns on the test board, so that the FPGA generates a driving signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA based on the received host computer instruction; send the driving signal to the memristor to be tested; receive the feedback signal of the memristor to be tested, and perform the current test.

[0096] Based on the same inventive concept as the above method, an embodiment of the present application further provides a test device for RRAM. The test device for RRAM is used to implement the test method for RRAM as described above. The test device for RRAM includes: A display module, configured to display the parameter setting interface for the current RRAM test; the parameters to be input displayed on the parameter setting interface; A processing module, configured to receive the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generate and send a host computer instruction; the memristor to be tested is one or more memristors in the memristor array arranged in B rows and W columns on the test board, so that the FPGA generates a driving signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA based on the received host computer instruction; send the driving signal to the memristor to be tested; receive the feedback signal of the memristor to be tested, and perform the current test.

[0097] As an embodiment, the above device further includes: a detection module, configured to, after performing the current test, when receiving the parameter setting interface switched to the next test as the parameter setting interface for this test, if it detects that there is saved data in the previous test, extract the saved data that can be used in this test and automatically fill it in the parameter setting interface for this test; wherein, the saved data refers to the data saved at the end of the previous test; the saved data used in this test includes the address of the memristor to be tested.

[0098] Based on the same inventive concept as the above method, an embodiment of the present application further provides a test system for RRAM, which may include but is not limited to a test board, a host computer, and an FPGA; wherein, The test board includes a memristor array arranged in B rows and W columns; The host computer is used to display the parameter setting interface for the current test of the RRAM; the parameters to be input displayed on the parameter setting interface; receive the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, and generate and send host computer instructions; the memristor to be tested is one or more memristors in the memristor array. The FPGA is used to generate a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA, based on the received host computer instructions; supply the drive signal to the memristor to be tested; receive the return signal of the memristor to be tested and perform the current test.

[0099] As an embodiment, the FPGA drive in the FPGA includes a processing system PS side and a programmable logic PL side connected to the PS side. The PS side is connected to the host computer and is used for the functions of communication between the PS side and the host computer and storing register instructions; each module in the PL drives the corresponding hardware module by reading the data in the RRAM.

[0100] The FPGA multiply-accumulate operation method in the related art involves a large number of multiplication and addition operations, and these operations require a certain amount of logic resources in the FPGA. Especially when the bit width of the operation data is large, the required resources will increase significantly.

[0101] In the embodiment of the present application, the weights of the set model are received from the user input and quantized into the conductance values of the memristors. The memristors at the corresponding coordinates are modulated to the corresponding conductance values. In this step, the host computer provides a visual correspondence between the memristors and the coordinates, and the user can select by dragging.

[0102] As an embodiment, the host computer converts the information input by the user into a hexadecimal instruction according to the register protocol and transmits it to the PS side of the FPGA through the network port (for example: 55aa 0050 0000 0001). The PS side stores the data in the RRAM and waits for the PL side to read it. Similarly, the data returned to the host computer is also stored in the RRAM by the PL side and waits for the PS side to read it, realizing data interaction in different clock domains. The protocol for data transmission is the AXI (Advanced eXtensible Interface) protocol (as Figure 1b shown). After receiving the data, the PL side drives the corresponding DAC chip and ADC chip according to the information contained in the instruction (refer to the register protocol instruction table), and then stores the information in the RRAM array without the need to allocate additional storage space.

[0103] As an example, after the conductance value is successfully set, it will not be lost after the hardware device is powered off. When in use, power on the memristor array, convert the user-input image into a voltage signal and apply it to the target end of the memristor array, such as the BL / SL end. The current value read at the SL / BL end can reflect the operation result, and then the operation result can be transmitted to the host computer or drive the braking device to make a response. It is used in scenarios such as edge computing with low power consumption and fast response. The driven braking devices include traffic signal recognition, robotic arm control, robot navigation, etc.

[0104] Exemplarily, the FPGA development is divided into two parts: the PS end and the PL end. The PS end realizes the communication with the host computer and the function of storing instructions in registers. The block diagram of the PS end is as Figure 5 shown. After the host computer receives the instruction, it performs preliminary parsing. If it is a write instruction, the data is written into the RRAM according to the corresponding register address. If it is a read-back data instruction, the data is taken out from the register and transmitted to the host computer through Ethernet. Each module in the PL end drives the corresponding hardware module by reading the data in the RRAM: The function of the WL control line voltage configuration module is to generate any voltage value or any voltage curve of the WL control line required by the user according to the host computer instruction, and give it to the WL pin of the RRAM chip by driving the DAC chip; The function of the BL / SL write voltage control module is to generate the BL voltage value or voltage curve required by the user according to the host computer instruction, and give it to the BL / SL pin of the RRAM chip by driving the high-speed DAC chip and the switch; The function of the SL / SL read voltage module is to generate the BL / SL voltage value or any voltage curve required by the user according to the host computer instruction, and read back the current value by driving the switch and the high-speed ADC chip; At the same time, the switch module is also required to cooperate to turn off the switch on the unused line to reduce the crosstalk between the lines.

[0105] In the embodiment of the present application, each module in the PL is convenient for transplantation and expansion.

[0106] As an example, the FPGA drive includes the programmable logic PL end. The PL end is connected to the host computer and is used for the PL end to communicate with the host computer, the function of storing instructions in registers, and each module in the PL drives the corresponding hardware module by reading the data in the RRAM. In this way, without including the PS end and directly using the PL end, communication between the host computer and the FPGA can also be realized.

[0107] For the implementation processes of the functions and roles of each module / sub-module / unit in the above-mentioned device and system, please refer to the implementation processes of the corresponding steps in the above-mentioned method for details. The same technical effects can be achieved and will not be elaborated here.

[0108] Specifically, the host computer can be: a desktop computer, a portable computer, a PDA (Personal Digital Assistant), etc. Any host computer that can implement the embodiments of the present application falls within the protection scope of the present application and is not limited herein.

[0109] Figure 11 The following is a schematic structural diagram of the host computer 50 provided by the embodiments of the present application.

[0110] As Figure 11 shown, the host computer 50 includes one or more processors 51, which are used to implement the above-described test method of the RRAM applied to the host computer.

[0111] In some embodiments, the above-mentioned host computer 50 may include a storage medium 59. For example, a computer-readable storage medium may store a program that can be called by the processor 51, and may include a non-volatile storage medium. In some embodiments, the host computer 50 may include a memory 58 and an interface 57. In some embodiments, the host computer 50 may also include other hardware according to actual applications.

[0112] The computer-readable storage medium of the embodiments of the present application stores a program thereon, and when the program is executed by the processor 51, it is used to implement the above-described test method of the RRAM.

[0113] The present application provides a computer program product, including a computer program / instructions, and when the computer program / instructions are executed by the processor, the method described in any one of the above is implemented.

[0114] The embodiments of the present application also provide a computer program, which is stored in a computer-readable storage medium, for example, Figure 11 the storage medium 59, and when the processor executes the computer program, it causes the processor 51 to execute the method described above.

[0115] The present application may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain program code. Computer-readable storage media include both permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. The information may be computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include but are not limited to: phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0116] The above are only the preferred embodiments of this specification and are not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification shall be included within the scope of protection of this specification.

Claims

1. A test method for RRAM, characterized in that, For a test board; The test board includes a memristor array arranged in B rows and W columns, and an FPGA. The test method for the RRAM includes: The host computer displays a parameter setting interface for the current test of the RRAM; the parameters to be input displayed on the parameter setting interface; receives parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, and generates and sends a host computer instruction; the memristor to be tested is one or more memristors in the memristor array; The FPGA generates a driving signal for the address of the memristor to be tested according to the received host computer instruction in accordance with the register protocol agreed upon by the host computer and the FPGA; gives the driving signal to the memristor to be tested; receives the return signal of the memristor to be tested and conducts the current test.

2. The test method of the RRAM according to claim 1, characterized in that, The parameter setting interface displays a chart corresponding to a switch array arranged in B rows and W columns, corresponding to each memristor in the memristor array; the switch array is used to control the switch of the memristor to be tested; The receiving the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user includes: If it is detected that the user operates in the chart, the address of the memristor to be tested is determined; wherein, while selecting the address of the memristor to be tested in the chart, it is automatically filled in the memristor input position in the parameter setting interface.

3. The test method of the RRAM according to claim 2, characterized in that, The if it is detected that the user operates in the chart, the address of the memristor to be tested is determined, includes: Taking the first position selected by the user in the chart as the starting position of the selected area of the memristor to be tested; taking the position where the user moves and drags from the selected first position to the second position and stops as the ending position of the selected area of the memristor to be tested; taking the addresses of the memristors within the area selected between the starting position and the ending position as the address of the memristor to be tested; Or, Taking the positions successively selected by the user in the chart as the address of the memristor to be tested.

4. The test method of the RRAM according to claim 1, wherein The parameter setting interface displays a chart corresponding to a switch array arranged in B rows and W columns, corresponding to each memristor in the memristor array; the switch array is used to control the switch of the memristor to be tested; The receiving the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user includes: Obtaining the address of the memristor to be tested from the local; Automatically importing and filling the address of the memristor to be tested in the memristor input position in the parameter setting interface, and correspondingly displaying it in the selected area in the chart.

5. The test method of the RRAM according to claim 1, wherein The parameter setting interface displays a chart arranged in B rows and W columns, corresponding to each memristor in the memristor array; The receiving the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user includes: Receiving the address of the memristor to be tested input by the user in the memristor input position in the parameter setting interface; The address of the memristor to be tested is correspondingly displayed in the selected area in the chart.

6. The test method of the RRAM according to any one of claims 1 to 5, characterized in that, The host computer displays a parameter setting interface for the current test of the RRAM, includes: The host computer receives the current test selected from multiple memristor tests and displays the parameter setting interface of the current test; the multiple memristor tests include two or more of the read-write test, weight modulation, recognition test, and multi-functional test integrated in the host computer.

7. The test method of the RRAM according to claim 6, characterized in that, After performing the current test, the method further includes: When receiving the parameter setting interface for switching to the next test as the parameter setting interface for this test, if it is detected that there is saved data in the previous test, the saved data that can be used in this test is extracted and automatically filled in the parameter setting interface for this test; Wherein, the saved data refers to the data saved at the end of the previous test; the saved data used in this test includes the address of the memristor to be tested.

8. The testing method of the RRAM according to any one of claims 1 to 4, characterized in that, When the current test includes a recognition test, the receiving of the parameter data input for the to-be-input parameters includes: receiving a batch import instruction; importing parameter data from the local according to the batch import instruction; the parameter data includes horizontal voltage parameter data and pulse width parameter data.

9. The test method of the RRAM according to any one of claims 1 to 4, characterized in that The test board includes a control circuit; the control circuit includes a digital-to-analog converter (DAC) chip and an analog-to-digital converter (ADC) chip; Generating a driving signal for the address of the memristor to be tested according to the instruction received from the host computer in accordance with the register protocol agreed upon by the host computer and the FPGA; Giving the driving signal to the memristor to be tested; Receiving the feedback signal of the memristor to be tested and performing the current test, including: Generating any voltage data of the word line (WL) control line required by the user according to the host computer instruction; the any voltage data includes any voltage value or any voltage curve, and is given to the WL pin of the RRAM chip by driving the DAC chip; And generating the bit line (BL) voltage data required by the user according to the host computer instruction; the voltage data includes a voltage value or a voltage curve, and is given to the BL pin and / or the source line (SL) pin of the RRAM chip by driving the DAC chip and the switch; Generating the voltage data of the BL pin and / or the SL pin required by the user according to the host computer instruction, and reading back the current value by driving the switch and the ADC chip.

10. A testing method for RRAM, characterized in that, A host computer applied to the test method of the RRAM according to any one of claims 1 to 9, includes: Displaying the parameter setting interface of the current RRAM test; the to-be-input parameters displayed on the parameter setting interface; Receiving the parameter data input for the to-be-input parameters and the address of the memristor to be tested input by the user, generating and sending a host computer instruction; the memristor to be tested is one or more memristors in the memristor array arranged in B rows and W columns in the test board, so that the FPGA generates a driving signal for the address of the memristor to be tested according to the instruction received from the host computer in accordance with the register protocol agreed upon by the host computer and the FPGA; giving the driving signal to the memristor to be tested; receiving the feedback signal of the memristor to be tested and performing the current test.

11. A test device for RRAM, characterized in that, A test device for the RRAM used to implement the test method of the RRAM according to claim 10, includes: Display the parameter setting interface for the current RRAM test; the parameters to be input displayed on the parameter setting interface; Receive the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generate and send a host computer instruction; the memristor to be tested is one or more memristors in the memristor array arranged in B rows and W columns on the test board, so that the FPGA generates a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA based on the received host computer instruction; give the drive signal to the memristor to be tested; receive the return signal of the memristor to be tested and perform the current test.

12. A test system for RRAM, characterized in that, Include: A test board, including a memristor array arranged in B rows and W columns; A host computer, used to display the parameter setting interface for the current RRAM test; The parameters to be input displayed on the parameter setting interface; receive the parameter data input for the parameters to be input and the address of the memristor to be tested input by the user, generate and send a host computer instruction; the memristor to be tested is one or more memristors in the memristor array; An FPGA, used to generate a drive signal for the address of the memristor to be tested according to the register protocol agreed upon by the host computer and the FPGA based on the received host computer instruction; Give the drive signal to the memristor to be tested; Receive the return signal of the memristor to be tested and perform the current test.

13. The test system for RRAM according to claim 12, wherein The FPGA drive in the FPGA includes a processing system PS side and a programmable logic PL side connected to the PS side; The PS side is connected to the host computer and is used for the PS side to communicate with the host computer and the function of storing register instructions; Each module in the PL drives the corresponding hardware module by reading the data in the RRAM.

14. The test system for RRAM according to claim 12, characterized in that, The FPGA drive includes a programmable logic PL side; The PL side is connected to the host computer and is used for the PL side to communicate with the host computer, the function of storing register instructions, and each module in the PL drives the corresponding hardware module by reading the data in the RRAM.

15. The test system of the RRAM according to claim 12, wherein The FPGA drive in the FPGA includes a processing system PS side and a programmable logic PL side connected to the PS side; The host computer is also used to convert the parameters to be input into hexadecimal instructions according to the register protocol and transmit them to the PS side of the FPGA through the network port; The PS side stores the data in the RRAM address and waits for the PL side to read; The PL side reads the data stored by the PS side in the RRAM address and returns the data to the host computer; After the PL side reads the data, according to the register protocol agreed upon by the FPGA included in the host computer instruction, it drives the corresponding DAC chip and ADC chip, and stores the register protocol agreed upon by the FPGA in the RRAM array.

16. The test system for RRAM according to claim 12, characterized in that, The memristor array has a memory function; the memory function is used to indicate that after the conductance value of the memristor array is successfully set, the power-off will not be lost; The FPGA is used to convert the image input by the user into a voltage signal and apply it to the target end of the memristor array to obtain the current value read by the target end; the current value is used to reflect the operation result. Transmit the operation result to the host computer or drive the braking device to make a response.

Images