Formation method of semiconductor structure, readable storage medium and semiconductor processing equipment

Abstract

The invention discloses a semiconductor structure forming method, a readable storage medium and semiconductor processing equipment. The forming method comprises the steps that S1, a substrate is provided and comprises a dielectric layer and a mask layer located above the dielectric layer, and the mask layer is provided with an opening pattern; s2, vertically etching the dielectric layer below the opening for a set time; s3, transversely etching the mask layer to enlarge the key size of the mask layer; and S4, continuing to vertically etch the dielectric layer until a contact hole with a high aspect ratio structure is formed. According to the method, the transverse etching step is inserted into the vertical etching step, the key size of the mask layer is enlarged, the arch structure formed before transverse etching is opened, the position of the arch structure formed by continuous vertical etching is moved downwards, and the situation that a filling material in the filling layer is exposed in a gap formed in the subsequent filling step is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and particularly to a method for forming a semiconductor structure, a readable storage medium, and a semiconductor processing device. Background Art

[0002] Advanced semiconductor devices, especially high-density memory chips 3D NAND and DRAM, usually contain a large number of contact holes with high aspect ratios (High Aspect Ratio Contact, HARC) structures. However, during the formation process of the contact holes with high aspect ratios (HARC), a bow structure is likely to be formed on the sidewalls near the opening of the contact holes. In the subsequent filling step (for example, filling a conductive material), the bow structure will cause voids to form in the filling layer, exposing the filling material inside the filling layer. In the next planarization step, for example, the chemical mechanical polishing step (CMP), the filling material exposed by the voids is easily damaged by the chemical solution, resulting in a decrease in the device yield. Summary of the Invention

[0003] The object of the present invention is to improve the formation process of semiconductor structures, especially contact holes with high aspect ratios, so that the position of the bow structure formed in the contact holes with high aspect ratios is shifted downward, avoiding the exposure of the filling material inside due to the voids formed by the filling of the bow structure.

[0004] To achieve the above object, the present invention provides a method for forming a semiconductor structure, including:

[0005] S1, providing a substrate placed in a chamber of a semiconductor processing device, the substrate including a dielectric layer and a mask layer located above the dielectric layer, and the mask layer being provided with an opening pattern;

[0006] S2, vertically etching the dielectric layer below the opening for a set time to form a bow structure;

[0007] S3, laterally etching the mask layer to expand the critical dimension of the mask layer;

[0008] S4, continuing to vertically etch the dielectric layer until a contact hole with a high aspect ratio structure is formed.

[0009] Optionally, the set time is 10% - 80% of the total vertical etching duration, and the total vertical etching duration is the total time consumed in steps S2 and S4.

[0010] Optionally, the set time is 20% - 80% of the total vertical etching duration.

[0011] Optionally, the set time is 20% - 50% of the total vertical etching duration.

[0012] Optionally, the dielectric layer includes a stepped structure.

[0013] Optionally, the dielectric layer is a dielectric layer formed of a single material.

[0014] Optionally, in step S3, the source radio frequency power is greater than the bias radio frequency power.

[0015] Optionally, by controlling at least one of the chamber pressure, the source radio frequency power, the bias radio frequency power, the process gas, and the etching time, the ratio of the thickness loss amount to the critical dimension increase amount of the mask layer in step S3 is adjusted.

[0016] Optionally, by increasing the chamber pressure or the source radio frequency power, the ratio is reduced.

[0017] Optionally, in step S3, the process gas used includes oxygen.

[0018] Optionally, the process gas does not contain an inert gas or nitrogen.

[0019] Optionally, a fluorocarbon gas is added to the process gas to reduce the ratio.

[0020] Optionally, the fluorocarbon gas is any one or more of C4F6, C4F8, or CF4.

[0021] Optionally, in step S3, the chamber pressure is 10 mT to 300 mT; the source radio frequency power is 200 W - 2000 W; the bias radio frequency power is 200 W - 2000 W; in the process gas used, the flow rate of oxygen is 50 - 1500 sccm, the flow rate of the fluorocarbon gas is 0 - 500 sccm, and the flow rate of the inert gas or nitrogen is 0 - 1500 sccm; the etching time is 10 s to 120 s.

[0022] Optionally, the aspect ratio of the contact hole is not less than 10:1.

[0023] Optionally, an etch stop layer is provided under the dielectric layer.

[0024] Optionally, the forming method further includes S5, removing the mask layer, filling a conductive material in the contact hole, and planarizing the surface of the semiconductor structure.

[0025] Another object of the present invention is to provide a readable storage medium, on which a program or instructions are stored, and when the program or instructions are executed by a processor, the forming method of the semiconductor structure described above is implemented.

[0026] Another object of the present invention is to provide a semiconductor processing apparatus, including: a processor, a memory, and a program or instruction stored on the memory and executable on the processor, and when the program or instruction is executed by the processor, the method for forming the semiconductor structure described above is implemented.

[0027] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:

[0028] 1) Insert the step S3 of the lateral etching mask layer in the main etching process (steps S2, S4) to expand the critical dimension of the mask layer. The expansion of the critical dimension of the mask layer can not only open the bow-shaped structure formed in step S2, but also facilitate the position of the bow-shaped structure formed by the subsequent vertical etching in step S4 to move downward away from the mask layer, avoiding the exposure of the filling material inside the filling layer by the voids formed in the subsequent filling step, thereby preventing the filling material inside the filling layer from being damaged.

[0029] 2) When the time for inserting step S3 is set to 10% - 80%, while the downward displacement amount of the position of the bow-shaped structure away from the mask layer is sufficient, the BCD is also large enough to meet the process requirements.

[0030] 3) By controlling at least one of the chamber pressure, source RF power, bias RF power, process gas, and etching time, the ratio of the thickness loss amount and the critical dimension increase amount of the mask layer in the lateral etching of step S3 can be adjusted, and under the condition that the critical dimension increase amount meets the process requirements, the process condition with the minimum thickness loss of the mask layer can be obtained. Description of the Drawings

[0031] Figure 1 It is a schematic diagram of the state of HARC in the steps of forming HARC, filling, and planarizing by the conventional method.

[0032] Figure 2 It is a schematic diagram of the principle of forming the bow-shaped structure of HARC.

[0033] Figure 3 It is a schematic diagram of the state of forming HARC by Method A.

[0034] Figure 4 It is a schematic diagram of the state of HARC in the steps of forming HARC, filling, and planarizing by Method B.

[0035] Figure 5 It is a flowchart of a method for forming a semiconductor structure according to the present invention.

[0036] Figure 6 It is a schematic diagram of the state of HARC in the steps of forming HARC, filling, and planarizing by the method of the present invention.

[0037] Figures 7 - 9 Local scanning electron microscope images of the HARC prepared in Comparative Examples 1 to 3, where a represents the top of the HARC and b represents the bottom of the HARC.

[0038] Figures 10 - 14 Local scanning electron microscope images of the HARC prepared in Examples 1 - 5, where a represents the top of the HARC and b represents the bottom of the HARC.

[0039] Figure 15 Schematic diagram showing the corresponding relationship between the thickness loss (Mask loss) of the mask layer and the increase in the critical dimension (ΔCD) of the mask layer after the lateral etching in Examples 6 - 12.

[0040] Figure 16 Flow chart of another method for forming a semiconductor structure of the present invention.

[0041] Reference signs:

[0042] HARC 1

[0043] Bow-shaped structure 11

[0044] Void 12

[0045] Stacked layer 13

[0046] Filling layer 2

[0047] Chemical solution 3

[0048] Mask layer 10

[0049] Dielectric layer 20

[0050] Substrate 30

[0051] Ion 4. Detailed implementation manners

[0052] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0053] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0054] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installation", "connection", "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be a direct connection, or an indirect connection through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0055] With the surge in the demand for high storage density storage devices, the manufacturing process of high aspect ratio structures has become increasingly important. Since there are multiple subsequent processes after forming a high aspect ratio contact hole (hereinafter referred to as "HARC"), the morphology and size problems of the HARC may affect the subsequent processes, thereby leading to a decrease in device yield. For example, in the process of forming a metal interconnect structure, after forming the HARC, it is necessary to fill the conductive metal in the HARC and then perform a planarization process to remove the redundant filled metal. When there are defects in the HARC, it may lead to a decrease in device yield in the subsequent filling process and planarization process.

[0056] As Figure 1 shown, when the top sidewall of the HARC 1 in the dielectric layer 20 has a bow-shaped structure 11 ( Figure 1 as shown in a) of the figure), the filling layer 2 filling the HARC is likely to form voids 12 ( Figure 1 as shown in b) of the figure), and the voids 12 expose the internal filling material of the filling layer 2. In the planarization step, the chemical solution 3 is likely to penetrate into the interior of the filling layer 2 through the voids 12 and erode the filling material ( Figure 1 as shown in c) of the figure), thereby causing device damage and a decrease in yield. The definition of the high aspect ratio described herein is that the ratio of the depth to the width of the hole is not less than 10:1.

[0057] The present invention has found that during the formation of HARC, edge defects of the mask layer 10 and / or the accumulation layer 13 formed by the accumulation of polymers on the sidewalls of HARC may trigger ion scattering, thereby destroying the collimation of plasma bombardment, resulting in the etching of the top sidewalls of HARC 1 by the plasma, and thus forming a bow structure 11 in the dielectric layer 20 (etching main body layer) on the top sidewalls of the HARC 1, as Figure 2 shown. Moreover, as the etching progresses and the etching time extends, the thickness of the remaining mask layer 10 decreases, and the thickness of the accumulation layer 13 accumulated on the sidewalls increases, and the bow structure 1 gradually transfers downward, that is, moves downward. The downward direction described herein refers to the direction away from the mask layer 10.

[0058] To solve this problem, usually two methods, method A or method B, are adopted in the prior art.

[0059] Method A is to increase the selectivity of the etching main body layer (dielectric layer 20) to the mask layer 10 by adjusting the chemical gas combination, so as to increase the thickness of the remaining mask layer, so that the bow structure 11 does not transfer downward but remains in the mask layer 10 (as Figure 3 shown). When the remaining mask layer 11 is removed for subsequent processes, the bow structure 11 disappears accordingly, and a HARC 1 without a bow structure is obtained. However, for the formation of HARC 1, this method has two problems:

[0060] 1) It is difficult for the mask layer thickness to meet the requirements of the etching process. Specifically, because the etching main body layer to be etched for forming HARC is very thick, the thickness of the mask layer consumed by the etching itself is relatively large; moreover, as the thickness of the mask layer consumed by the etching increases, the depth of downward transfer of the bow structure also increases, so a thicker remaining mask layer thickness is required to retain the bow structure in the mask layer. The required mask layer thickness of this method is too large and is difficult to achieve in the actual application of forming a characteristic structure with a high aspect ratio.

[0061] 2) The bottom critical dimension (BCD) is too small or even causes the etching to stop, which will cause an increase in the resistance of the contact hole or even an open circuit. Specifically, due to the high selectivity of the etching main body layer to the mask layer, the critical dimension (CD) of forming HARC has a tendency to gradually become narrower downward; moreover, the high selectivity makes the thickness of the remaining mask layer increase, and the thicker remaining mask layer further increases the aspect ratio, making the BCD smaller.

[0062] Method B is that after the main etching (ME) is completed, the top sidewall of HARC 1 has a bow-shaped structure 11, such as Figure 4 As shown in a; first expand the CD of the mask layer 10, such as Figure 4 Then break open the arched structure 11 at the top of the etched main layer, as shown in b; Figure 4 However, for forming HARC, this method also has the problem of reducing BCD: because expanding the CD of the mask layer requires consuming a considerable thickness of the mask layer, that is, the thickness of the remaining mask layer after the main etching is required to increase, and this part of the increased remaining mask layer thickness is often obtained by increasing the selectivity ratio of the etching main layer to the mask, so it will also form a more gradually narrowed structure, resulting in BCD being difficult to meet production requirements.

[0063] To this end, the present invention designs a process, in which, in the main etching process for forming HARC, a step of lateral etching of the mask layer to expand the CD of the mask layer is inserted, so that the arched structure continues to be transferred downward, for example, to the middle side wall of the HARC, so that the gap formed by the filling step is located in the middle of the filling layer, that is, the gap is inside the filling layer. Therefore, in the subsequent planarization process, the chemical solution is not easy to penetrate into the gap, so as not to damage the filling material inside the filling layer, thereby avoiding the decrease in the yield of the device. Furthermore, the present invention is also conducive to obtaining a larger BCD by expanding the CD of the mask layer by lateral etching. The following is an explanation in conjunction with the accompanying drawings.

[0064] like Figures 5 - 6 As shown, the present invention provides a method for forming a semiconductor structure, comprising:

[0065] Step S1, providing a substrate, and placing it in a chamber of a semiconductor processing device, wherein the substrate comprises a dielectric layer and a mask layer located above the dielectric layer, wherein the mask layer is provided with an opening pattern, and the opening pattern defines the distribution and size of the HARC.

[0066] The dielectric layer 20, as the etching main layer, can be a dielectric layer formed of a single material, such as a silicon oxide layer. In some embodiments, the dielectric layer can have a stepped structure, such as a silicon oxide layer having a stepped structure. In some embodiments, the dielectric layer 20 can also be composed of multiple materials.

[0067] The mask layer 10 is used as a protective layer for etching the dielectric layer, and its material may be amorphous carbon, titanium nitride, etc.

[0068] The dielectric layer 20 is formed on a substrate 30 , and the substrate 30 may be a wafer or other semiconductor or conductor material, which is not limited here. In one embodiment, an etching stop layer is provided between the substrate 30 and the dielectric layer 20 .

[0069] Step S2, vertically etch the dielectric layer below the opening for a set time to form an arcuate structure.

[0070] Using the mask layer 10 as a protective layer, vertically etch the dielectric layer 20 exposed by the opening pattern with conventional etching gas and etching method, and pause the etching at a predetermined time. At this time, the dielectric layer 20 is not etched through and the substrate 30 is not exposed. A partial cross-sectional view of the formed HARC 1 is as shown in Figure 6 a of. Since polymers are deposited on the sidewalls of the top of the HARC, ion scattering is caused, and the scattered plasma etches the sidewalls of the HARC. Therefore, an arcuate structure 11 is formed in step S2.

[0071] The present invention finds that as the set time of step S2 is advanced, the neck depth of the arcuate structure 11 formed after the vertical etching in step S2 gradually decreases, and the pause position of the arcuate structure 11 moves from the dielectric layer 20 to the mask layer 10 direction. The arcuate structure 11 can be located in the mask layer 10, can also be located in the dielectric layer 20, or can be located in both the mask layer 10 and the dielectric layer 20 at the same time, that is, the arcuate structure 11 straddles the mask layer 10 and the dielectric layer 20.

[0072] Step S3, laterally etch the mask layer to expand the critical dimension of the mask layer.

[0073] In step S3, clean the polymers attached to the sidewalls, remove the accumulation layer 13, and laterally etch the mask 10 to expand the CD of the mask layer 10, as shown in Figure 6 b of. Then, in the subsequent continuous vertical etching, the arcuate structure 11 can be opened. Moreover, the expansion of the CD of the mask layer is also beneficial to the expansion of the BCD of the HARC.

[0074] The mask layer 10 can be dry-etched with a process gas to expand the CD of the mask layer 10. The process gas includes oxygen.

[0075] In order to limit that the lateral etching mainly occurs in the mask layer 10 and mainly etches the mask layer 10 with less consumption of the thickness of the mask layer, the source RF power can be set to be greater than the bias RF power.

[0076] When laterally etching the mask layer, it will inevitably cause a thickness loss (mask loss) of the mask layer 10, as shown in Figure 6As shown in b). When expanding the CD of the mask layer 10, it is necessary to minimize the thickness loss of the mask layer. To this end, the present invention also adjusts the ratio of the thickness loss amount and the critical dimension increase amount (mask loss / ΔCD) of the mask layer 10 described in step S3 by controlling at least one of the chamber pressure, source RF power, bias RF power, process gas, and etching time.

[0077] When increasing the chamber pressure or source RF power, the ratio can be reduced, that is, when the critical dimension increase amount of the mask layer is constant, the thickness loss amount of the mask layer is reduced.

[0078] When adding an inert gas or nitrogen to the process gas, the ratio will be increased, that is, when the critical dimension increase amount of the mask layer is constant, the thickness loss amount of the mask layer is increased.

[0079] When adding a fluorocarbon gas (the expression is C x F y , where x>0, y>0) to the process gas, the ratio can be reduced. The fluorocarbon gas is any one or more of C4F6, C4F8, or CF4.

[0080] Step S4, continue to vertically etch the dielectric layer until a contact hole with a high aspect ratio structure is formed.

[0081] Vertically etch the structure after the CD of the mask layer is laterally etched and expanded in step S3 to cut open the bow-shaped structure formed in step S2. As the vertical etching progresses, a new bow-shaped structure 11 with a downward shift in position is formed in the direction towards the bottom of the HARC. As Figure 6 shown in c), the HARC etched by the method of the present invention has a "vase" shape, and the position of the bow-shaped structure is significantly shifted downward. Correspondingly, the void 12 formed in the subsequent filling step will also shift downward. As Figure 6 shown in d), therefore, the chemical solution cannot contact the void 12 in the subsequent planarization step, and there is no problem of damage to the exposed internal filling material.

[0082] The vertical etching in step S2 and the continued vertical etching step in step S4 together are equivalent to the main etching (ME) in conventional etching. In the present invention, a lateral etching step is inserted during the main etching (i.e., the vertical etching steps S2 and S4). By means of lateral etching, the CD of the mask layer is enlarged. In step S4, the vertical etching is continued to open the bow-shaped structure, and a bow-shaped structure with a downward shift in position is formed. Among them, the lateral etching step is crucial, and the insertion time point of the lateral etching step is particularly important. As described above, in method B, after the main etching is completed (after step S4), the lateral etching for enlarging the CD of the mask layer is carried out, and the BCD of the formed HARC is small, which does not meet the process requirements. And enlarging the CD of the mask layer before the start of the main etching is actually equivalent to the existing etching method without process improvement. Because the CD of the mask layer needs to meet the feature size requirements of HARC and cannot be enlarged arbitrarily.

[0083] In order to find the appropriate insertion time point, the present invention selects five time points for inserting the lateral etching: 90% ME (the set time is 90% of the total duration of the vertical etching), 80% ME, 50% ME, 20% ME, 10% ME as examples, and the aforementioned two methods (method A and method B) as comparative examples, and conducts comparative experiments with the existing etching process without improvement. The neck depth of the bow-shaped structure of the formed HARC and the BCD of the contact hole are shown in Figures 7 - 14 and Table 1.

[0084] The main etching process conditions described in this article can be: chamber pressure 10 - 100 mT; source power 200 - 2000 W; bias power 500 - 5000 W; C4F6 gas flow rate 5 - 100 sccm; C4F8 gas flow rate 5 - 100 sccm; CH2F2 gas flow rate 5 - 100 sccm; O2 gas flow rate 5 - 100 sccm; Ar gas flow rate 50 - 1000 sccm.

[0085] For the sake of easy comparison, the specific main etching process conditions in Comparative Examples 1 - 3 and Examples 1 - 5 below are: chamber pressure 30 mT; source power 1000 W; bias power 3000 W; C4F6 gas flow rate 10 sccm; C4F8 gas flow rate 10 sccm; CH2F2 gas flow rate 20 sccm; O2 gas flow rate 20 sccm; Ar gas flow rate 100 sccm.

[0086] Comparative Example 1

[0087] Without process improvement, the main etching is carried out by using a conventional etching method to form HARC. As Figure 7 shown, a bow-shaped structure is formed at the top of the HARC ( Figure 7 a)), and the critical dimension at the bottom of the HARC gradually becomes smaller ( Figure 7 b)).

[0088] Comparative Example 2

[0089] Using the aforementioned Method A, the selectivity of the dielectric layer to the mask layer is increased, and the main etching forms HARC, leaving the bow-shaped structure in the mask layer. As Figure 8 shown, there is no bow-shaped structure on the sidewall of HARC ( Figure 8 a) of, but the critical dimension at the bottom of HARC gradually decreases ( Figure 8 b) of, resulting in premature termination of etching.

[0090] Comparative Example 3

[0091] Using the aforementioned Method B, after the main etching is completed, the bow-shaped structure in HARC is processed: first, the CD of the mask layer is enlarged, and then the bow-shaped structure is broken open, so that the bow-shaped structure in HARC disappears ( Figure 9 a) of, but the critical dimension at the bottom of HARC still gradually decreases ( Figure 9 b) of, which does not meet the process requirements.

[0092] Example 1

[0093] Step S1: Provide a substrate and place it in the chamber of a semiconductor processing equipment. The substrate includes a dielectric layer and a mask layer located above the dielectric layer, and the mask layer is provided with an opening pattern.

[0094] Step S2: Vertically etch the dielectric layer below the opening for a set time and pause the main etching; the set time is 90% of ME, that is, the insertion time point of the following step S3 is 90% of the main etching time.

[0095] Step S3: Horizontally etch the mask layer to expand the CD of the mask layer to the requirement of the top critical dimension of HARC for the process, and during this process, minimize the thickness loss of the mask layer. The process conditions for the horizontal etching are: the chamber pressure is 30 mT; the source RF power is 1000 W; the bias RF power is 500 W; in the process gas used, the flow rate of oxygen is 750 sccm; the etching time is 20 s.

[0096] S4: Continue to vertically etch the dielectric layer until a contact hole (HARC) with a target high aspect ratio structure is formed. The formed HARC is as Figure 10 shown.

[0097] Example 2

[0098] The set time is 80% of ME, and other conditions are the same as those in Example 1. The formed HARC is as Figure 11 shown.

[0099] Example 3

[0100] The set time is 50% ME, and other conditions are the same as in Example 1. The formed HARC is as Figure 12 shown.

[0101] Example 4

[0102] The set time is 20% ME, and other conditions are the same as in Example 1. The formed HARC is as Figure 13 shown.

[0103] Example 5

[0104] The set time is 10% ME, and other conditions are the same as in Example 1. The formed HARC is as Figure 14 shown.

[0105] Table 1: Comparison of experimental results of Comparative Examples 1-3 and Examples 1-5

[0106]

[0107] Combined Figures 7 - 14 with the data in Table 1, it can be seen that: the neck depth of the bow-shaped structure in Comparative Example 1 (the distance from the starting position of the bow-shaped structure to the top surface of the dielectric layer 20) is only 99 nm, and there is a risk of exposure of the internal filling material. No bow-shaped structure appears in Comparative Example 2, but the BCD is too small, resulting in the stop of etching. The bow-shaped structure in Comparative Example 3 is completely broken open, but the BCD is only 55 nm, which may cause an increase in the resistance of the contact hole or even an open circuit. It is significantly reduced compared to the BCD of 131 nm in Comparative Example 1.

[0108] In Example 1 of the present invention, since the vertical etching time in step S4 is only 10% ME (the set time is 90% ME), the bow-shaped structure formed in step S2 is not completely opened, and the neck depth is 181 nm, which is less than 100 nm lower than that in Comparative Example 1. Examples 2-5 all present a "vase" shape. Compared with Comparative Example 1, the neck depth is lowered by more than 300 nm. As the time point of the inserted horizontal etching moves forward in Examples 2-5 (80% ME → 50% ME → 20% ME → 10% ME), the BCD gradually increases and then starts to decrease (77 nm → 92 nm → 107 nm → 80 nm). The decrease in the BCD of Example 5 is because the vertical etching time in step S2 is only 10% ME, and the BCD is not fully enlarged before the vertical etching in step S4. Optimally, the BCD of Example 4 is the largest at 107 nm, significantly greater than 55 nm in Comparative Example 3 and close to 131 nm in Comparative Example 1.

[0109] It can be seen that within the insertion time range of 10% ME to 80% ME, the neck depth moves down by more than 300 nm, which is significantly lower than that of Comparative Example 1, and the exposure of the internal filling material can be avoided; and the BCD can also meet the requirements of subsequent processes. That is to say, when determining the insertion time, at least the amount of neck depth downward movement and the BCD value need to be considered, and when the set time is 10% to 80% of the total vertical etching duration, both the amount of neck depth downward movement and the BCD value can meet the requirements of the present invention. When the set time is 20% to 50% of the total vertical etching duration, not only can the bow-shaped structure of HARC move down significantly, but the BCD of HARC is also larger, which can better reduce the resistance of the contact hole. In some embodiments, the range of the insertion time can be 10% ME to 80% ME, 10% ME to 20% ME, 10% ME to 50% ME, 20% ME to 80% ME, 20% ME to 50% ME, or 50% ME to 80% ME. When there is no special description for the above ranges, the endpoint values are included, but it should be understood that when there is a special description, the above ranges may not include the endpoint values.

[0110] Since the polymer and mask material attached to the sidewalls of the HARC are etched laterally, a certain thickness of the mask material is also consumed longitudinally. Because in step S4, it is still necessary to continue to vertically etch the dielectric layer 20 with the help of the mask layer, it is expected to obtain a larger CD of the mask layer (i.e., Figure 6 the Trim CD in ) with less consumption of the longitudinal mask layer thickness (Mask loss). The experimental results of the lateral etching obtained by the same steps S1-S3 of Example 3 (the lateral etching insertion time point is 50% ME) are used as Comparative Example 6. By adjusting the chamber pressure, bias voltage, or source power, process gas combination (oxygen O2, nitrogen N2, and carbon tetrafluoride CF4), and etching time of the lateral etching step, a series of experiments were carried out to monitor the morphology of the mask layer, which are Examples 7 to 12 respectively, to explore suitable lateral etching process conditions. After the lateral etching of Examples 6-12 is completed, the thickness loss amount (Mask loss) of the mask layer, the CD (Trim CD) after the mask layer is enlarged, and the ratio (loss / ΔCD) of the thickness loss amount of the mask layer to the increase amount of the critical dimension of the mask layer (ΔCD) are shown in Table 2 and Figure 15 as shown.

[0111] Example 6

[0112] Same as steps S1-S3 of Example 3.

[0113] Example 7

[0114] Based on Example 6, the chamber pressure was increased from 30 mT to 60 mT. It can be seen that when the chamber pressure increases, compared with Example 6, the thickness loss of the mask layer decreases, and the increase in critical dimension increases slightly.

[0115] Example 8

[0116] Based on Example 6, the bias power was reduced from 500 W to 200 W. It can be seen that when the bias power decreases, compared with Example 6, the thickness loss of the mask layer decreases, and the increase in critical dimension decreases.

[0117] Example 9

[0118] Based on Example 6, the source power was increased from 1000 W to 2000 W. It can be seen that when the source power increases, compared with the results of Example 6, the thickness loss of the mask layer increases, and the increase in critical dimension increases.

[0119] Example 10

[0120] Based on Example 6, the gas mixture was changed from 750 sccm O2 to 250 sccm O2 / 500 sccm N2. It can be seen that when the proportion of oxygen decreases and the proportion of N2 increases, compared with the results of Example 6, the thickness loss of the mask layer decreases, and the increase in critical dimension decreases. Since the concentration of oxygen radicals decreases, the isotropic etching weakens accordingly, and thus both the vertical etching rate and the horizontal etching rate decrease.

[0121] Example 11

[0122] Based on Example 6, the gas mixture was changed from 750 sccm O2 to 500 sccm O2 / 250 sccm CF4. It can be seen that when the proportion of oxygen decreases and the proportion of fluorocarbon gas increases, compared with the results of Example 6, the thickness loss of the mask layer decreases, and the increase in critical dimension decreases.

[0123] Example 12

[0124] Based on Example 6, the horizontal etching time was extended from 20 s to 30 s. It can be seen that as the horizontal etching time extends, compared with the results of Example 6, the thickness loss of the mask layer increases, and the increase in critical dimension increases.

[0125] Table 2: Parameter changes of the mask layer after horizontal etching in Examples 6 - 12

[0126]

[0127] Combined with the data in Table 2, it can be seen that: the increase in critical dimension and the thickness loss of the mask layer show an obvious positive correlation, but not a strict proportional relationship, such as Figure 15As shown. From the experimental data of Example 7 and Example 9, it can be seen that higher chamber pressure and higher source power generate higher plasma density, enhancing the etching isotropy, and both the longitudinal etching (corresponding to the thickness loss of the mask layer) and the lateral etching (corresponding to the enlarged critical dimension) will be faster. That is to say, by appropriately adjusting the process parameters, a larger enlarged critical dimension can be obtained with less thickness loss of the mask layer.

[0128] After repeated experimental comparisons, the process conditions for the lateral etching in step S2 of the present invention are as follows: the chamber pressure is 10 mT to 300 mT; the source radio frequency power is 200 W - 2000 W; the bias radio frequency power is 200 W - 2000 W; in the process gas used, the flow rate of oxygen is 50 - 1500 sccm, the flow rate of fluorocarbon gas is 0 - 500 sccm, and the flow rate of inert gas or nitrogen is 0 - 1500 sccm; the etching time is 10 s to 120 s.

[0129] As Figure 16 shown, the forming method of the present invention further includes step S5 of removing the mask layer, filling a conductive material in the contact hole, and planarizing the surface of the semiconductor structure.

[0130] Since the bow-shaped structure of the HARC formed by the present invention moves down more and is close to the middle of the HARC, in the filling step, the voids formed are inside the filling layer and do not expose the filling material. During the subsequent planarization process, the chemical solution is not likely to penetrate into the voids, thus not damaging the filling material inside the filling layer and not causing device damage.

[0131] The present invention also provides a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the forming method of the semiconductor structure described above is implemented.

[0132] The present invention also provides a semiconductor processing device, including: a processor, a memory, and a program or instruction stored on the memory and executable on the processor, and when the program or instruction is executed by the processor, the forming method of the semiconductor structure described above is implemented.

[0133] In summary, the present invention designs a method for forming a semiconductor structure. In the etching process of forming a high aspect ratio contact hole (HARC), a step of inserting a lateral etching mask layer is inserted at a set time point of the main etching step. When the main etching is continued, the bow-shaped structure is opened. As the main etching progresses, the position of the re-formed bow-shaped structure moves downward away from the mask layer. The forming method of the present invention avoids exposing the filling material inside the filling layer due to the voids formed in the subsequent filling step, thereby preventing the filling material inside the filling layer from being damaged. Further, by setting the time of the insertion step S3 to be 10% to 80%, while the downward displacement amount of the position of the bow-shaped structure away from the mask layer is sufficient, the BCD is also large enough to meet the process requirements.

[0134] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be recognized that the above description should not be considered as a limitation of the present invention. After those skilled in the art have read the above content, various modifications and substitutions of the present invention will be obvious. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: S1, providing a substrate placed in a chamber of a semiconductor processing device, the substrate including a dielectric layer and a mask layer located above the dielectric layer, the mask layer being provided with an opening pattern; S2, vertically etching the dielectric layer below the opening for a set time to form an arcuate structure; S3, laterally etching the mask layer to enlarge the critical dimension of the mask layer; S4, continuing to vertically etch the dielectric layer until a contact hole with a high aspect ratio structure is formed.

2. The method for forming a semiconductor structure according to claim 1, wherein The set time is 10% - 80% of the total vertical etching duration, and the total vertical etching duration is the total time consumed in steps S2 and S4.

3. The method for forming a semiconductor structure according to claim 2, wherein, The set time is 20% - 80% of the total vertical etching duration.

4. The method for forming a semiconductor structure according to claim 3, wherein, The set time is 20% - 50% of the total vertical etching duration.

5. The method for forming a semiconductor structure according to claim 1, wherein, The dielectric layer includes a stepped structure.

6. The method for forming a semiconductor structure according to claim 1, wherein The dielectric layer is a dielectric layer formed of a single material.

7. The method for forming a semiconductor structure according to claim 1, wherein, In step S3, the source RF power is greater than the bias RF power.

8. The method for forming a semiconductor structure according to claim 1, wherein, By controlling at least one of the chamber pressure, source RF power, bias RF power, process gas, and etching time, the ratio of the thickness loss amount and the critical dimension increase amount of the mask layer in step S3 is adjusted.

9. The method for forming a semiconductor structure according to claim 8, wherein, By increasing the chamber pressure or source RF power, the ratio is reduced.

10. The method for forming a semiconductor structure according to claim 8, wherein, In step S3, the process gas used includes oxygen.

11. The method for forming a semiconductor structure according to claim 10, wherein, The process gas does not contain inert gas or nitrogen.

12. The method for forming a semiconductor structure according to claim 10, wherein, Adding a carbon fluoride gas to the process gas reduces the ratio.

13. The method for forming a semiconductor structure according to claim 12, wherein The carbon fluoride gas is any one or more of C4F6, C4F8, or CF4.

14. The method for forming a semiconductor structure according to claim 1, wherein, In step S3, the chamber pressure is 10 mT - 300 mT; the source RF power is 200 W - 2000 W; the bias RF power is 200 W - 2000 W; in the process gas used, the flow rate of oxygen is 50 - 1500 sccm, the flow rate of carbon fluoride gas is 0 - 500 sccm, and the flow rate of inert gas or nitrogen is 0 - 1500 sccm; the etching time is 10 s - 120 s.

15. The method for forming a semiconductor structure according to claim 1, wherein, The aspect ratio of the contact hole is not less than 10:

1.

16. The method for forming a semiconductor structure according to claim 1, wherein, An etch stop layer is provided below the dielectric layer.

17. The method for forming a semiconductor structure according to claim 1, wherein, The forming method further includes S5, removing the mask layer, filling a conductive material in the contact hole, and planarizing the surface of the semiconductor structure.

18. A readable storage medium, characterized in that, A program or instruction is stored on the readable storage medium, and when the program or instruction is executed by a processor, the forming method of the semiconductor structure according to any one of claims 1 to 17 is implemented.

19. A semiconductor processing apparatus, characterized in that, Including: A processor, a memory, and a program or instruction stored on the memory and executable on the processor, and when the program or instruction is executed by the processor, the forming method of the semiconductor structure according to any one of claims 1 to 17 is implemented.

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