Semiconductor structure and preparation method thereof
By using a barrier layer to coat the silicon nitride layer during semiconductor device manufacturing, the problem of dielectric layer cracking caused by the stress difference between silicon nitride materials and metal materials is solved, and the stability and reliability of the semiconductor structure are improved.
Patent Information
- Application Number
- CN202510369014.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-26
- Publication Date
- 2025-06-27
AI Technical Summary
During the manufacturing process of existing semiconductor devices, the stress differences between silicon nitride materials and metal materials lead to machine downtime and dielectric layer cracking.
Through two photolithography and deposition of the barrier layer, the silicon nitride layer is completely coated to form a barrier layer to isolate the stress differences between the silicon nitride layer and the metal material.
Effectively alleviate the stress differences between the silicon nitride layer and the metal material, reduce the cracking problem of dielectric layer caused by excessive stress, and avoid the precipitation of hydrogen elements in the silicon nitride layer, and improve the stability and reliability of signal transmission and energy transmission of semiconductor structures.
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Figure CN120221504A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a semiconductor structure and a method for preparing the same. Background Art
[0002] During the manufacturing process of semiconductor devices, the preparation of the isolation layer plays a crucial role in the performance of semiconductor devices. Refer to Figure 1 which schematically shows an existing semiconductor structure. Among them, the preparation steps of this structure mainly include:
[0003] (1) Deposit a support dielectric layer 120 and a silicon nitride layer 130 on the bottom metal layer 110;
[0004] (2) Form a photoresist layer and perform photolithography to open a via pattern;
[0005] (3) Etch the silicon nitride layer 130 and the support dielectric layer 120 to the bottom metal layer 110 to form a via;
[0006] (4) Fill the via and perform polishing to form a metal plug 140;
[0007] (5) Deposit a metal material on the top surface of the polished device structure to form a top metal layer 150.
[0008] In the semiconductor device prepared by the above existing process flow, since the silicon nitride material itself has compressive stress and the metal material itself has tensile stress, due to the opposite stress manifestations of these two materials, problems such as machine downtime and dielectric layer cracking caused by excessive stress are likely to occur.
[0009] Therefore, it is necessary to provide a semiconductor structure and a method for preparing the same. Summary of the Invention
[0010] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a semiconductor structure and a method for preparing the same, which are used to solve the stress problem between the silicon nitride material and the metal material in the prior art.
[0011] To achieve the above purpose and other related purposes, the present invention provides a method for preparing a semiconductor structure, including the following steps:
[0012] Provide a semiconductor substrate, the semiconductor substrate includes a bottom metal layer, a support dielectric layer located on the surface of the bottom metal layer, and a silicon nitride layer located on the surface of the support dielectric layer;
[0013] Form a first photoresist layer on the surface of the semiconductor substrate and perform first photolithography to form a first via pattern;
[0014] Perform a first etching process to form a first through-hole penetrating the silicon nitride layer;
[0015] Form a barrier layer on the surface of the silicon nitride layer, and the barrier layer fills the first through-hole;
[0016] Form a second photoresist layer on the surface of the barrier layer, and perform a second photolithography to form a second through-hole pattern;
[0017] Perform a second etching process to form a second through-hole penetrating the barrier layer and the support dielectric layer, and the sidewall of the silicon nitride layer is isolated from the second through-hole by the barrier layer;
[0018] Form a metal plug filling the second through-hole, and the metal plug is in contact with the underlying metal layer;
[0019] Form a top metal layer on the surface of the barrier layer, and the top metal layer is in contact with the metal plug.
[0020] Optionally, the barrier layer includes a silicon oxide barrier layer; the thickness of the barrier layer includes
[0021] Optionally, the support dielectric layer includes a silicon oxide dielectric layer, a silicon oxynitride transition layer is further included between the silicon nitride layer and the silicon oxide dielectric layer, and a silicon oxynitride bottom antireflection layer is further included between the silicon nitride layer and the first photoresist layer.
[0022] Optionally, the method for forming the barrier layer includes the HDPCVD method.
[0023] Optionally, a planarization process step is further included after the step of forming the barrier layer and / or the metal plug.
[0024] Optionally, the surface of the underlying metal layer and / or the surface of the metal plug further includes a Ti / TiN stack.
[0025] The present invention also provides a semiconductor structure, and the semiconductor structure includes:
[0026] A semiconductor substrate, the semiconductor substrate includes an underlying metal layer, a support dielectric layer located on the surface of the underlying metal layer, and a silicon nitride layer located on the surface of the support dielectric layer;
[0027] A first through-hole, the first through-hole penetrates the silicon nitride layer;
[0028] A barrier layer, the barrier layer covers the surface of the silicon nitride layer and fills the first through-hole;
[0029] A second through hole that penetrates the barrier layer and the support dielectric layer, and the side wall of the silicon nitride layer is isolated from the second through hole by the barrier layer;
[0030] A metal plug that fills the second through hole and contacts the bottom metal layer;
[0031] A top metal layer that is located on the surface of the barrier layer and contacts the metal plug.
[0032] Optionally, the barrier layer includes a silicon oxide barrier layer; the thickness of the barrier layer includes
[0033] Optionally, the support dielectric layer includes a silicon oxide dielectric layer. There is also a silicon oxynitride transition layer between the silicon nitride layer and the silicon oxide dielectric layer, and there is also a silicon oxynitride bottom anti-reflection layer between the silicon nitride layer and the first photoresist layer.
[0034] Optionally, the surface of the bottom metal layer and / or the surface of the metal plug further includes a Ti / TiN stack.
[0035] As described above, the semiconductor structure and its manufacturing method of the present invention completely coat the silicon nitride layer through two lithographies and the deposition of the barrier layer, effectively alleviating the stress difference between the silicon nitride layer and the metal material, and reducing the problem of dielectric layer cracking caused by excessive stress; the semiconductor structure with the barrier layer can avoid the precipitation of hydrogen elements in the silicon nitride layer during the testing process, thereby improving the stability and reliability of signal transmission and energy transmission of the semiconductor structure. Description of the Drawings
[0036] Figure 1 Shows a schematic structural diagram of a semiconductor device in the prior art.
[0037] Figure 2 Shows a process flow chart of the manufacturing of a semiconductor device in an embodiment of the present invention.
[0038] Figure 3 Shows a schematic structural diagram of a semiconductor substrate in an embodiment of the present invention.
[0039] Figure 4 Shows a schematic structural diagram after forming a first via pattern in an embodiment of the present invention.
[0040] Figure 5 Shows a schematic structural diagram after forming a first through hole in an embodiment of the present invention.
[0041] Figure 6 Shows a schematic structural diagram after forming a barrier layer in an embodiment of the present invention.
[0042] Figure 7It shows a schematic structural diagram after forming the second via hole pattern in the embodiment of the present invention.
[0043] Figure 8 It shows a schematic structural diagram after forming the second via hole in the embodiment of the present invention.
[0044] Figure 9 It shows a schematic structural diagram after forming the metal plug in the embodiment of the present invention.
[0045] Figure 10 It shows a schematic structural diagram after forming the top metal layer in the embodiment of the present invention.
[0046] Explanation of reference numerals
[0047] 110 Bottom metal layer
[0048] 120 Support dielectric layer
[0049] 130 Silicon nitride layer
[0050] 140 Metal plug
[0051] 150 Top metal layer
[0052] 100 Semiconductor substrate
[0053] 101 Bottom metal layer
[0054] 102 Ti / TiN stack
[0055] 103 Silicon oxide dielectric layer
[0056] 104 Silicon oxynitride transition layer
[0057] 105 Silicon nitride layer
[0058] 106 Silicon oxynitride bottom anti-reflection layer
[0059] 210 First photoresist layer
[0060] 211 First via hole pattern
[0061] 220 Second photoresist layer
[0062] 221 Second via hole pattern
[0063] 310 First via hole
[0064] 320 Second via hole
[0065] 400 Silicon oxide barrier layer
[0066] 500 Metal plug
[0067] 600 Top metal layer Detailed Implementation Modes
[0068] The following describes the implementation modes of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0069] When detailing the embodiments of the present invention, for ease of description, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.
[0070] For convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on", etc. may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. Embodiments may include those in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Additionally, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers.
[0071] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention schematically. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.
[0072] As Figure 2 , this embodiment provides a method for preparing a semiconductor structure, including the following steps:
[0073] S1: Provide a semiconductor substrate, where the semiconductor substrate includes a bottom metal layer, a support dielectric layer on the surface of the bottom metal layer, and a silicon nitride layer on the surface of the support dielectric layer;
[0074] S2: Form a first photoresist layer on the surface of the semiconductor substrate and perform first lithography to form a first via pattern;
[0075] S3: Perform a first etching process to form a first via penetrating the silicon nitride layer;
[0076] S4: Form a barrier layer on the surface of the silicon nitride layer, and the barrier layer fills the first through-hole;
[0077] S5: Form a second photoresist layer on the surface of the barrier layer, and perform second photolithography to form a second through-hole pattern;
[0078] S6: Perform a second etching process to form a second through-hole penetrating the barrier layer and the support dielectric layer, and the sidewall of the silicon nitride layer is isolated from the second through-hole by the barrier layer;
[0079] S7: Form a metal plug filling the second through-hole, and the metal plug is in contact with the bottom metal layer;
[0080] S8: Form a top metal layer on the surface of the barrier layer, and the top metal layer is in contact with the metal plug.
[0081] In this embodiment, through two photolithographies and the deposition of the barrier layer, the silicon nitride layer is completely coated, which can effectively relieve the stress difference between the silicon nitride layer and the metal material and reduce the problem of dielectric layer cracking caused by excessive stress; the semiconductor structure with the barrier layer can avoid the precipitation of hydrogen (H) elements in the silicon nitride layer during the test, thereby improving the stability and reliability of signal transmission and energy transmission of the semiconductor structure.
[0082] Refer to Figure 2 and Figure 3 , perform step S1 to provide a semiconductor substrate 100, where the semiconductor substrate 100 includes a bottom metal layer 101, a support dielectric layer on the surface of the bottom metal layer 101, and a silicon nitride layer 105 on the surface of the support dielectric layer.
[0083] Specifically, the material of the bottom metal layer 101 may include, for example, Al metal, Cu metal, AlCu metal, etc., and the support dielectric layer may include, for example, a silicon oxide dielectric layer 103, a hafnium oxide dielectric layer, etc.
[0084] Furthermore, preferably, the surface of the bottom metal layer 101 has a Ti / TiN stack 102 to improve the adhesion between the bottom metal layer 101 and the support dielectric layer through the Ti / TiN stack 102 and prevent the metal diffusion of the bottom metal layer 101.
[0085] Furthermore, preferably, a silicon oxynitride transition layer 104 is further included between the silicon nitride layer 105 and the silicon oxide dielectric layer 103 to play a role of transition buffering through the silicon oxynitride transition layer 104 and facilitate the combination between the silicon nitride layer 105 and the silicon oxide dielectric layer 103.
[0086] Further, preferably, the upper surface of the silicon nitride layer 105 further has a silicon oxynitride bottom anti-reflection layer 106 to facilitate the photolithography of the subsequent photoresist layer and form a photolithography pattern with a good topography.
[0087] In this embodiment, the surface of the bottom metal layer 101 has the Ti / TiN stack 102; the support dielectric layer is the silicon oxide dielectric layer 103 with a thickness of , such as and so on; the thickness of the silicon nitride layer 105 is , such as and so on; the lower surface of the silicon nitride layer 105 has the silicon oxynitride transition layer 104 with a thickness of , such as and so on; the upper surface of the silicon nitride layer 105 has the silicon oxynitride bottom anti-reflection layer 106 with a thickness of approximately . The specific structure and material selection of the semiconductor substrate 100 are not overly restricted here.
[0088] Next, referring to Figure 2 and Figure 4 , perform step S2 to form a first photoresist layer 210 on the surface of the semiconductor substrate 100 and perform first photolithography to form a first via pattern 211.
[0089] Specifically, in this embodiment, the first photoresist layer 210 is a photoresist layer, and the specific type of the photoresist layer is not overly restricted here. After the first photolithography, the first via pattern 211 can be formed in the first photoresist layer 210 to facilitate the subsequent etching of the via. The number, distribution, and topography of the first via pattern 211 are not overly restricted here.
[0090] Next, referring to Figure 2 and Figure 5 , perform step S3 to perform a first etching process to form a first via 310 penetrating through the silicon nitride layer 105.
[0091] Specifically, as Figure 5 , in this embodiment, using the patterned first photoresist layer 210 as a mask, perform the first etching process to etch the silicon oxynitride bottom anti-reflection layer 106 and the silicon nitride layer 105 until the silicon oxynitride transition layer 104 is exposed. Among them, the width of the formed first via 310 is denoted as width D. Among them, after forming the first via 310, there is also a step of removing the first photoresist layer 210, which is not elaborated here.
[0092] Next, referring to Figure 2 and Figure 6, perform step S4 to form a barrier layer on the surface of the silicon nitride layer 105, and the barrier layer fills the first through hole 310.
[0093] Specifically, the thickness of the barrier layer may include Such as etc. Among them, it is preferably to use High-Density Plasma Chemical Vapor Deposition (HDPCVD) to form the barrier layer, and the barrier layer may include a silicon oxide barrier layer 400, that is, to form the silicon oxide barrier layer 400 covering the bottom anti-reflection layer 106 of silicon oxynitride and filling the first through hole 310.
[0094] Among them, after depositing and forming the silicon oxide barrier layer 400, it preferably includes a planarization process step, such as Chemical Mechanical Polishing (CMP), to form the silicon oxide barrier layer 400 with a good flat surface, so as to facilitate the subsequent process. Specifically, the silicon oxide barrier layer 400 with a thickness of about may be deposited first to effectively fill the first through hole 310, and then polished to form the silicon oxide barrier layer 400 with a thickness of on the upper surface of the bottom anti-reflection layer 106 of silicon oxynitride.
[0095] Next, refer to Figure 2 and Figure 7 , perform step S5 to form a second photoresist layer 220 on the surface of the barrier layer, and perform second lithography to form a second through hole pattern 221.
[0096] Specifically, in this embodiment, the second photoresist layer 220 uses a photoresist layer, and the specific type of the photoresist layer is not overly limited here. After the second lithography, the second through hole pattern 221 corresponding to the first through hole 310 can be formed in the second photoresist layer 220 to facilitate the subsequent etching of the through hole. The number, distribution, and morphology of the second through hole pattern 221 need to consider the specific setting of the first through hole 310, which is not limited here.
[0097] Next, refer to Figure 2 and Figure 8 , perform step S6 to perform a second etching process to form a second through hole 320 penetrating the barrier layer and the support dielectric layer, and the side wall of the silicon nitride layer 105 is isolated from the second through hole 320 by the barrier layer.
[0098] Specifically, such as Figure 8, in this embodiment, the second photoresist layer 220 in a graphical form is used as a mask to perform the second etching process to etch the silicon oxide barrier layer 400, the silicon oxynitride transition layer 104, and the silicon oxide dielectric layer 103 until the Ti / TiN stack 102 is exposed. The width of the formed second via 320 is denoted as width d. Since the silicon oxide barrier layer 400 is reserved on the sidewall of the silicon nitride layer 105 to isolate the silicon nitride layer 105 from the metal plug prepared subsequently, the width D of the first via 310 is greater than the width d of the second via 320.
[0099] Next, referring to Figure 2 and Figure 9 , step S7 is performed to form a metal plug 500 filling the second via 320, and the metal plug 500 is in contact with the bottom metal layer 101.
[0100] Specifically, preferably, the Ti / TiN stack 102 is formed on the inner wall of the second via 320 before forming the metal plug 500 to improve the adhesion between the metal plug 500 and the dielectric layer through the Ti / TiN stack 102 and prevent the metal diffusion of the metal plug 500. The preparation method of the metal plug 500 may include, for example, the electroplating method, and the material may include, for example, tungsten metal, etc.
[0101] Furthermore, after preparing the metal plug 500, preferably, a planarization process step, such as CMP, is further included until the barrier layer is exposed to form the barrier layer with a good flat surface to facilitate the subsequent process.
[0102] Next, referring to Figure 2 and Figure 10 , step S8 is performed to form a top metal layer 600 on the surface of the barrier layer, and the top metal layer 600 is in contact with the metal plug 500.
[0103] Specifically, the material of the top metal layer 600 may include, for example, Al metal, Cu metal, AlCu metal, etc., and the thickness of the top metal layer 600 may include, for example, etc.
[0104] Among them, it should be noted that the silicon nitride layer 105 contains a relatively large amount of hydrogen (H) element, and the H element will react with the dangling bonds in the silicon nitride layer 105, making the silicon nitride layer 105 denser and showing a strong compressive stress. While metal materials, such as the top metal layer 600 and the metal plug 500, have tensile stress, so the stress manifestations of these two materials are opposite, which easily causes the machine to crash and the cracking of the dielectric layer. When the silicon oxynitride bottom anti-reflection layer 106 is retained, although the upper surface of the silicon nitride layer 105 is covered with the silicon oxynitride bottom anti-reflection layer 106, due to the relatively thin thickness of the silicon oxynitride bottom anti-reflection layer 106, it is difficult to play a good blocking role. Therefore, in this embodiment, by preparing the barrier layer, the silicon nitride layer 105 can be effectively coated to effectively relieve the stress difference between the silicon nitride layer 105 and the metal material, reduce the cracking problem of the dielectric layer caused by excessive stress, and the semiconductor structure with the barrier layer can avoid the precipitation of H element in the silicon nitride layer 105 during the test, thereby improving the stability and reliability of signal transmission and energy transmission of the semiconductor structure.
[0105] Such as Figures 3 to 10 , this embodiment also provides a semiconductor structure, which can be prepared by the above preparation process, but is not limited to this. In this embodiment, the semiconductor structure is directly prepared by the above preparation process, so the preparation, material, structure, etc. of the semiconductor structure can refer to the above preparation process.
[0106] Among them, the semiconductor structure includes:
[0107] A semiconductor substrate 100, the semiconductor substrate 100 includes a bottom metal layer 101, a support dielectric layer on the surface of the bottom metal layer 101, and a silicon nitride layer 105 on the surface of the support dielectric layer;
[0108] A first through hole 310, the first through hole 310 penetrates through the silicon nitride layer 105;
[0109] A barrier layer, the barrier layer covers the surface of the silicon nitride layer 105 and fills the first through hole 310;
[0110] A second through hole 320, the second through hole 320 penetrates through the barrier layer and the support dielectric layer, and the side wall of the silicon nitride layer 105 is isolated from the second through hole 320 by the barrier layer;
[0111] A metal plug 500, the metal plug 500 fills the second through hole 320 and is in contact with the bottom metal layer 101;
[0112] The top metal layer 600 is in contact with the metal plug 500 on the surface of the barrier layer. As an example, the barrier layer includes a silicon oxide barrier layer 400; the thickness of the barrier layer includes such as and so on.
[0113] As an example, the support dielectric layer includes a silicon oxide dielectric layer 103. There is also a silicon oxynitride transition layer 104 between the silicon nitride layer 105 and the silicon oxide dielectric layer 103, and there is also a silicon oxynitride bottom anti-reflection layer 106 between the silicon nitride layer 105 and the first photoresist layer 210.
[0114] In this embodiment, the surface of the bottom metal layer 101 has the Ti / TiN stack 102; the support dielectric layer uses the silicon oxide dielectric layer 103 with a thickness of such as and so on; the thickness of the silicon nitride layer 105 is such as and so on; the lower surface of the silicon nitride layer 105 has the silicon oxynitride transition layer 104 with a thickness of such as and so on; the upper surface of the silicon nitride layer 105 has the silicon oxynitride bottom anti-reflection layer 106 with a thickness of approximately
[0115] As an example, the surface of the metal plug 500 also includes a Ti / TiN stack 102 to improve the adhesion between the metal and the dielectric layer through the Ti / TiN stack 102 and prevent metal diffusion.
[0116] In summary, for the semiconductor structure and its manufacturing method of the present invention, through two lithographies and the deposition of the barrier layer, the silicon nitride layer is completely coated, effectively alleviating the stress difference between the silicon nitride layer and the metal material, and reducing the problem of dielectric layer cracking caused by excessive stress; the semiconductor structure with the barrier layer can avoid the precipitation of hydrogen elements in the silicon nitride layer during the testing process, thereby improving the stability and reliability of signal transmission and energy transmission of the semiconductor structure.
[0117] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.
Claims
1. A method for preparing a semiconductor structure, characterized in that: The following steps are involved: Providing a semiconductor substrate, the semiconductor substrate comprising an underlying metal layer, a supporting dielectric layer located on a surface of the underlying metal layer, and a silicon nitride layer located on a surface of the supporting dielectric layer; Forming a first photoresist layer on the surface of the semiconductor substrate, and performing a first photolithography to form a first through-hole pattern; Performing a first etching process to form a first through hole penetrating the silicon nitride layer; forming a barrier layer on the surface of the silicon nitride layer, wherein the barrier layer fills the first through hole; forming a second photoresist layer on the surface of the blocking layer, and performing a second photolithography to form a second through-hole pattern; Performing a second etching process to form a second through hole penetrating the barrier layer and the supporting dielectric layer, wherein the side wall of the silicon nitride layer is isolated from the second through hole by the barrier layer; forming a metal plug filling the second through hole, wherein the metal plug contacts the bottom metal layer; A top metal layer is formed on the surface of the barrier layer, and the top metal layer is in contact with the metal plug.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The barrier layer comprises a silicon oxide barrier layer; the thickness of the barrier layer comprises 3. The method for preparing a semiconductor structure according to claim 1, wherein: The supporting dielectric layer includes a silicon oxide dielectric layer, a silicon oxynitride transition layer is included between the silicon nitride layer and the silicon oxide dielectric layer, and a silicon oxynitride bottom anti-reflection layer is included between the silicon nitride layer and the first photoresist layer.
4. The method for preparing a semiconductor structure according to claim 1, wherein: The method of forming the barrier layer includes a HDPCVD method.
5. The method for preparing a semiconductor structure according to claim 1, wherein: After the step of forming the barrier layer and / or the metal plug, a planarization process step is further included.
6. The method for preparing a semiconductor structure according to claim 1, wherein: The surface of the underlying metal layer and / or the surface of the metal plug further includes a Ti / TiN stack.
7. A semiconductor structure, characterized in that: The semiconductor structure comprises: A semiconductor substrate, the semiconductor substrate comprising an underlying metal layer, a supporting dielectric layer located on a surface of the underlying metal layer, and a silicon nitride layer located on a surface of the supporting dielectric layer; a first through hole, wherein the first through hole penetrates the silicon nitride layer; a barrier layer, the barrier layer covering a surface of the silicon nitride layer and filling the first through hole; a second through hole, wherein the second through hole penetrates the barrier layer and the supporting dielectric layer, and a side wall of the silicon nitride layer is isolated from the second through hole by the barrier layer; a metal plug, the metal plug filling the second through hole and contacting the bottom metal layer; A top metal layer is located on a surface of the barrier layer and contacts the metal plug.
8. The semiconductor structure according to claim 7, characterized in that: The barrier layer comprises a silicon oxide barrier layer; the thickness of the barrier layer comprises 9. The semiconductor structure according to claim 7, characterized in that: The supporting dielectric layer includes a silicon oxide dielectric layer, a silicon oxynitride transition layer is included between the silicon nitride layer and the silicon oxide dielectric layer, and a silicon oxynitride bottom anti-reflection layer is included between the silicon nitride layer and the first photoresist layer.
10. The semiconductor structure according to claim 7, wherein: The surface of the underlying metal layer and / or the surface of the metal plug further includes a Ti / TiN stack.