Chip packaging structure and chip packaging method

Abstract

The present application provides a chip packaging structure and a chip packaging method, which relate to the field of semiconductor packaging technology. The chip packaging structure includes a chip, a substrate and an adhesive layer, wherein a step portion is provided at the bottom of the chip; and a first groove is provided at the substrate. The chip is installed in the first groove, wherein the step portion abuts against the substrate, and there is a gap between the bottom of the chip and the bottom of the first groove; the chip and the substrate are electrically connected. The adhesive layer is provided between the step portion of the chip and the substrate. The chip packaging structure can reduce the contact area between the bottom of the chip and the adhesive layer, thereby avoiding stress delamination of the adhesive layer on the back of the chip, facilitating the discharge of bubbles in the adhesive layer, improving the bonding strength between the adhesive layer and the chip, and at the same time reducing the chip height, thereby reducing the overall packaging height.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure and a chip packaging method. Background Art

[0002] SIP designs typically utilize a core-less substrate design, meaning a coreless substrate is used to reduce substrate thickness. The lack of a copper core layer in core-less substrates can lead to warping of the package substrate structure during thermal processing, causing delamination of the adhesive layer between the chip and substrate. In existing technologies, the silver paste or adhesive layer is located in a groove. Due to the large adhesive layer area at the bottom of the chip, gases trapped in the adhesive layer cannot be expelled during baking. Furthermore, the thermal process exacerbates the voids created by bubbles, ultimately leading to delamination and shedding, severely impacting the performance of the packaged product. Summary of the Invention

[0003] The object of the present invention is to provide a chip packaging structure and a chip packaging method, which can improve the bonding strength between the chip and the adhesive layer, improve the delamination phenomenon, and enhance the packaging quality.

[0004] In a first aspect, the present invention provides a chip packaging structure, comprising:

[0005] A chip, wherein a step portion is provided at the bottom of the chip;

[0006] A substrate, wherein the substrate is provided with a first groove;

[0007] The chip is mounted in the first groove, wherein the step portion abuts against the substrate, and there is a gap between the bottom of the chip and the bottom of the first groove; the chip and the substrate are electrically connected;

[0008] An adhesive layer is provided between the step portion of the chip and the substrate.

[0009] In an optional embodiment, the step portion includes a first step and a second step located at different heights along the height direction, and the first step and / or the second step abuts against the substrate.

[0010] In an optional embodiment, a sidewall of the first groove is provided with a sink extending away from the first groove, and the first step is supported on the sink; the second step is closer to the bottom of the chip than the first step.

[0011] In an optional embodiment, the adhesive layer is provided between the sink and the first step;

[0012] The adhesive layer or plastic package is filled between the bottom of the chip and the first groove, and between the second step and the first groove.

[0013] In an optional embodiment, a first plastic package body and a second plastic package body are further included, and the first plastic package body covers the side of the chip away from the substrate; and the second plastic package body fills the gap between the bottom of the chip and the bottom of the first groove.

[0014] In an optional embodiment, there is a gap between the edge of the chip and the edge of the first groove.

[0015] In an optional embodiment, the chip has two oppositely arranged first edges and two oppositely arranged second edges; the sinking platform is provided on the side wall of the first groove at a position corresponding to the first edge; the first edge is abutted against the sinking platform; and there is a gap between the second edge and the side wall of the first groove.

[0016] In an optional embodiment, a second groove is provided on the substrate, and the second groove is located on the side of the first groove away from the chip; the projection area of ​​the second groove on the substrate is larger than the projection area of ​​the chip on the substrate; and the second groove is filled with a third plastic package.

[0017] In an optional embodiment, a first groove is opened on the substrate, the first groove is connected to the second groove, the first groove and the second groove are respectively filled with the third plastic package body, and a bottom cavity is formed between the bottom of the chip and the first groove.

[0018] In an optional embodiment, a sensing area is provided on a side of the chip facing the bottom cavity; and a step portion of the chip is sealed and connected to a groove wall of the first groove in a circumferential direction.

[0019] In an optional embodiment, a third groove is formed on the substrate along the periphery of the chip, and a second groove is further formed on the substrate, wherein the second groove communicates with the third groove and the first groove.

[0020] In an optional embodiment, a first pad is provided on the chip, a second pad is provided on the substrate, and the first pad and the second pad are electrically connected; and the third groove is located between the second pad and the chip.

[0021] In a second aspect, the present invention provides a chip packaging method for preparing a chip packaging structure as described in any one of the aforementioned embodiments.

[0022] The chip packaging structure provided by the embodiments of the present invention features a stepped portion at the bottom of the chip, reducing the contact area between the chip bottom and the adhesive layer. This facilitates the removal of bubbles from the colloid and prevents delamination caused by voids. A first recess is provided in the substrate to reduce the overall package height, and the stepped portion helps increase the bonding strength between the chip side and the sidewalls of the first recess.

[0023] The chip packaging method provided in the embodiment of the present invention is used to prepare the above-mentioned chip packaging structure, which is beneficial to preventing structural delamination, improving bonding strength, and thus improving packaging quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A first schematic diagram of a chip packaging structure provided by an embodiment of the present invention;

[0026] Figure 2 A schematic structural diagram of a chip of the chip packaging structure provided by an embodiment of the present invention;

[0027] Figure 3 A schematic structural diagram of a substrate of a chip packaging structure provided by an embodiment of the present invention;

[0028] Figure 4 A second schematic diagram of a chip packaging structure provided by an embodiment of the present invention;

[0029] Figure 5 A schematic diagram of another perspective of the second structure of the chip packaging structure provided by an embodiment of the present invention;

[0030] Figure 6 A third schematic diagram of a chip packaging structure provided by an embodiment of the present invention;

[0031] Figure 7 Another structural schematic diagram of a substrate of a chip packaging structure provided by an embodiment of the present invention;

[0032] Figure 8 A schematic diagram of another perspective of the third structure of the chip packaging structure provided by an embodiment of the present invention;

[0033] Figure 9 A fourth schematic diagram of a chip packaging structure provided by an embodiment of the present invention;

[0034] Figure 10 A fifth schematic diagram of a chip packaging structure provided by an embodiment of the present invention;

[0035] Figure 11 for Figure 10 A partial enlarged schematic diagram of point A in the middle;

[0036] Figure 12 A schematic diagram of another perspective of the fifth structure of the chip package structure provided by an embodiment of the present invention;

[0037] Figure 13 A schematic diagram of the manufacturing process of a chip packaging structure provided by an embodiment of the present invention.

[0038] Icons: 100-chip packaging structure; 110-chip; 111-step portion; 112-first step; 113-second step; 114-first pad; 115-first edge; 116-second edge; 117-sensing area; 118-conductive column; 120-substrate; 121-first groove; 122-sinking platform; 123-second pad; 124-wire bonding structure; 125-second groove; 126-first groove; 127-bottom cavity; 128-third groove; 129-second groove; 130-adhesive layer; 141-first plastic package; 142-second plastic package; 143-third plastic package. DETAILED DESCRIPTION

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0041] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0042] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" and the like indicate positions or locations based on the positions shown in the accompanying drawings, or the positions or locations in which the inventive product is typically placed when in use. These terms are intended solely to facilitate the description of the present invention and to simplify the description, and are not intended to indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third," etc., are used solely to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0043] Furthermore, terms such as "horizontal," "vertical," and "overhanging" do not necessarily imply that a component must be absolutely horizontal or overhanging, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but rather that it can be slightly tilted.

[0044] In the description of the present invention, it should also be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0045] The following embodiments of the present invention are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0046] A chip packaging structure and a chip packaging method proposed in the embodiments of the present invention are conducive to improving the bonding force between the chip and the adhesive layer, improving the delamination phenomenon, and enhancing the packaging quality.

[0047] Combine Figures 1 to 3The chip packaging structure 100 includes a chip 110, a substrate 120, and an adhesive layer 130. The chip 110 has a step 111 at its bottom, and the substrate 120 has a first groove 121. The chip 110 is mounted in the first groove 121, wherein the step 111 abuts against the substrate 120, and a gap is formed between the bottom of the chip 110 and the bottom of the first groove 121. The chip 110 and the substrate 120 are electrically connected. The adhesive layer 130 is disposed between the step 111 of the chip 110 and the substrate 120. The chip packaging structure 100 can reduce the contact area between the bottom of the chip 110 and the adhesive layer 130, thereby preventing the adhesive layer 130 from delaminating due to stress on the back side of the chip 110. This facilitates the discharge of bubbles in the adhesive layer, improves the bonding strength between the adhesive layer 130 and the chip 110, and reduces the height of the chip 110, thereby reducing the overall package height.

[0048] The step portion 111 includes a first step 112 and a second step 113 located at different heights along the height direction, and the first step 112 and / or the second step 113 are supported on the substrate 120. Optionally, a first solder pad 114 is provided on the front of the chip 110, and a step portion 111 is provided on the back of the chip 110, and the step portion 111 is stepped or serrated. The step portion 111 can extend from the back of the chip 110 to the side, so that the area of ​​the back of the chip 110 is reduced. This is conducive to reducing the contact area between the back of the chip 110 and the adhesive layer 130, thereby avoiding the problem of bubbles in the large-area adhesive layer being difficult to discharge. It is also conducive to increasing the bonding force between the side of the chip 110 and the side wall of the first groove 121, and the structure is more stable and reliable.

[0049] In this embodiment, the number of steps is two. In other embodiments, the number of steps may be one, three, four, five or more, which is not specifically limited here.

[0050] Optionally, a recessed platform 122 is formed on the sidewall of the first groove 121, extending away from the first groove 121. The first step 112 abuts against the recessed platform 122. The second step 113 is closer to the bottom of the chip 110 than the first step 112. Of course, in other embodiments, any one of the multiple steps 111 on the chip 110 may abut against the recessed platform 122, which is not specifically limited here.

[0051] Adhesive layer 130 is positioned between sink 122 and first step 112, reducing the contact area between the back of chip 110 and adhesive layer 130, facilitating the removal of bubbles, preventing voids, and improving bonding strength. The provision of first groove 121 and step 111 also helps reduce the overall package height. Furthermore, the stepped or serrated shape of step 111 increases the contact area between the side of chip 110 and adhesive layer 130, ensuring a more secure bond and enhancing bonding strength.

[0052] An adhesive layer 130 or a plastic package is filled between the bottom of the chip 110 and the first groove 121, and between the second step 113 and the first groove 121. It is understood that in the first groove 121, the gap between the chip 110 and the substrate 120 can be filled entirely with the adhesive layer 130, or entirely with the plastic package, or partially with the adhesive layer 130 and partially with the plastic package. After the adhesive layer 130 is provided between the sink 122 and the first step 112, a bottom cavity 127 is formed between the bottom of the chip 110 and the substrate 120 (see FIG. 1 ). Figure 6 The bottom cavity 127 can be filled with a plastic package or an adhesive layer 130, or the cavity structure can be retained. Figure 1 The bottom cavity 127 is shown as being filled with the adhesive layer 130 .

[0053] In some embodiments, one or more layers of sinkers 122 may be provided on the sidewalls of the first groove 121 along the height direction. Each layer of sinkers 122 may be a continuous boss structure or a staggered boss structure. The chip 110 may be installed on any layer of sinkers 122, without specific limitation.

[0054] It can be understood that a first pad 114 is provided on the chip 110, and a second pad 123 is provided on the substrate 120. The first pad 114 and the second pad 123 are electrically connected using a wire bonding structure 124. The chip packaging structure 100 also includes a first plastic package 141 and a second plastic package 142. The side of the chip 110 away from the substrate 120 is covered with the first plastic package 141; the first plastic package 141 protects the chip 110 and the wire bonding structure 124. The gap between the bottom of the chip 110 and the bottom of the first groove 121 is filled with the second plastic package 142. Figure 4 Specifically, the second plastic package 142 is filled between the bottom of the chip 110 and the first groove 121, and between the second step 113 and the first groove 121. This reduces the amount of adhesive layer 130 used, prevents delamination caused by bubbles and voids in the adhesive layer 130, and improves bonding strength. Furthermore, the front and back sides of the chip 110 are each covered with the plastic package, which balances stress on both sides of the chip 110 and alleviates warping. The structure of the first groove 121 also enhances the bonding strength between the substrate 120, the plastic package, and the chip 110.

[0055] Combine Figure 5 Optionally, there is a gap H between the edge of the chip 110 and the edge of the first groove 121. That is, the projected area of ​​the first groove 121 on the substrate 120 is larger than the projected area of ​​the chip 110 on the substrate 120. In this embodiment, the cross-sections of the chip 110 and the first groove 121 are respectively rectangular.

[0056] Chip 110 has two oppositely disposed first edges 115 and two oppositely disposed second edges 116. A recess 122 is provided on the sidewall of the first groove 121 at a position corresponding to the first edge 115; the first edge 115 rests on the recess 122; and a gap H is defined between the second edge 116 and the sidewall of the first groove 121. It is easy to understand that the first groove 121 has four sidewalls, two of which are disposed opposite each other. A gap is defined between the two sidewalls corresponding to the second edge 116 and the second edge 116. This gap facilitates the subsequent plastic encapsulation process, allowing the plastic encapsulation material to be filled from this gap into the bottom cavity 127 of the chip 110.

[0057] In this embodiment, the first pads 114 of chip 110 are arranged along first edge 115. First pads 114 and second pads 123 on substrate 120 are connected via bonding structures 124. In other words, bonding structures 124 are located on one side of first edge 115 of chip 110. The mold flow enters bottom cavity 127 through the gap at second edge 116. This prevents the mold flow from impacting bonding structures 124, preventing bonding structures 124 from contacting or breaking. First edge 115 is shorter than second edge 116, and adhesive layer 130 is positioned at first edge 115. This reduces the amount of adhesive used, reduces the contact area between adhesive layer 130 and chip 110, and avoids problems such as voids and delamination caused by difficulty in evacuating bubbles.

[0058] Of course, in some embodiments, there may be no gap between the edge of the chip 110 and the sidewall of the first groove 121 , ie, a sealed connection. In this way, a bottom cavity 127 may be formed on the side of the chip 110 close to the substrate 120 .

[0059] Optionally, a channel is provided on the substrate 120, and the channel can be opened along the upper surface or side surface of the substrate 120. The upper surface here refers to the side surface of the substrate 120 on which the chip 110 is mounted. The channel is connected to the bottom cavity 127 of the chip 110, so that the plastic encapsulation body can enter the bottom cavity 127 from the channel during the plastic encapsulation process to fill the bottom cavity 127. It should be noted that the channel design can replace the above-mentioned edge gap to form a flow channel structure filled with the plastic encapsulation body. Alternatively, in some chip packaging structures 100, there are both edge gaps and channel designs, which can accelerate the flow of the plastic encapsulation body, improve the filling performance, and also enhance the bonding force between the plastic encapsulation body and the substrate 120.

[0060] Combine Figures 6 to 8Optionally, a second groove 125 is defined on the substrate 120. The second groove 125 is located on the side of the first groove 121 away from the chip 110. The projected area of ​​the second groove 125 on the substrate 120 is larger than the projected area of ​​the chip 110 on the substrate 120. The second groove 125 is filled with a third plastic encapsulation material 143. The bottom of the second groove 125 is larger than the bottom of the first groove 121. The first groove 121 and the second groove 125 are provided independently. Optionally, the bottom width W1 of the second groove 125 is larger than the width W2 of the chip 110. In this embodiment, a step 111, namely a first step 112, is provided at the bottom of the chip 110. Because the second groove 125 is larger than the chip 110, after the third plastic encapsulation material 143 is subsequently filled, the area of ​​the third plastic encapsulation material 143 is larger than the area of ​​the chip 110. This facilitates better absorption of thermal stress from the plastic encapsulation, mitigates structural warping, and prevents delamination between the chip 110 and the adhesive layer 130.

[0061] Optionally, a first groove 126 is formed in the substrate 120, communicating with the second groove 125. The first groove 126 may be formed on the top surface or side of the substrate 120 and extend to communicate with the second groove 125. During the subsequent molding process, a plastic molding compound may flow from the first groove 126 into the second groove 125 to fill the second groove 125. Because the first groove 121 and the second groove 125 are independent of each other, a bottom cavity 127 is formed between the bottom of the chip 110 and the first groove 121. For ease of description, the plastic molding compound filling the second groove 125 is referred to as a third plastic molding compound 143. It will be understood that the first groove 126 and the second groove 125 are each filled with the third plastic molding compound 143. It will be readily understood that in some embodiments, the path, extension direction, cross-sectional shape, etc. of the first groove 126 in the substrate 120 can be flexibly designed according to practical needs and are not specifically limited herein.

[0062] Combine Figure 9 It is worth noting that the structure in which the bottom cavity 127 is formed at the bottom of the chip 110 is particularly suitable for a sensing chip 110, such as a surface acoustic wave filter chip 110. The bottom cavity 127 can serve as an acoustic cavity for the operation of the chip 110. Optionally, a sensing area 117 is provided on the side of the chip 110 facing the bottom cavity 127. The sensing area 117 is electrically connected to the first pad 114 via a conductive column 118 or an internal circuit.

[0063] Optionally, the step portion 111 of the chip 110 is sealed with the groove wall of the first groove 121 in the circumferential direction to improve the sealing of the bottom cavity 127. It can be understood that the step portions 111 around the chip 110 are all placed on the sink 122 of the substrate 120, that is, the adhesive layer 130 is provided along the circumference between the step portion 111 of the chip 110 and the sink 122, thereby sealing the gap between the edge of the chip 110 and the groove wall of the first groove 121.

[0064] Furthermore, the bottom cavity 127 can improve heat dissipation, act as a buffer, and reduce thermal effects and impact. During the baking and curing process, bubbles in the adhesive layer 130 can be discharged into the bottom cavity 127, thereby reducing bubbles in the adhesive layer 130, preventing the formation of voids, and avoiding delamination between the chip 110 and the substrate 120, thereby improving bonding strength and reliability.

[0065] Combine Figures 10 to 12 A third groove 128 is defined on substrate 120 along the periphery of chip 110. Substrate 120 also defines a second groove 129, which connects third groove 128 and first groove 121. Optionally, chip 110 defines a first pad 114, and substrate 120 defines a second pad 123. First pad 114 and second pad 123 are electrically connected using a wire bonding structure 124. Third groove 128 is located between second pad 123 and chip 110.

[0066] Optionally, a second groove 129 is formed on the side of the third groove 128 near the chip 110. During the plastic encapsulation process, the plastic encapsulation material can enter the bottom cavity 127 of the chip 110 along the third groove 128 and the second groove 129, and the second plastic encapsulation material 142 is filled in the bottom cavity 127 of the chip 110. The design of the third groove 128 and the second groove 129 can improve the fluidity of the plastic encapsulation material and enhance the bonding strength. The provision of the third groove 128 can also relieve stress, reduce warping, and prevent stress on the wire bonding structure, which may cause delamination and cracking of the bonding structure.

[0067] It should be noted that the design of the second groove 129 can be to arrange multiple grooves along the periphery of the chip 110. The third groove 128 can be an annular groove or a plurality of grooves. Each groove is connected to the second groove 129 respectively. During plastic sealing, the plastic sealing body can enter the cavity at the bottom of the chip 110 from all directions, thereby improving the fluidity and filling properties of the plastic sealing body. Optionally, in this embodiment, the two third grooves 128 are respectively arranged on the side of the two first edges 115, and the outlet of the second groove 129 is arranged on the side of the second edge 116, that is, to avoid the bonding structure 124, and the plastic sealing body enters the bottom cavity 127 from the side of the second edge 116 along the third groove 128 and the second groove 129, thereby reducing the mold flow impact on the bonding structure 124. After the plastic sealing body is filled, the bottom and periphery of the chip 110 are filled with the plastic sealing body, which can provide better support, buffering and heat dissipation.

[0068] Combine Figure 13 The embodiment of the present invention further provides a chip packaging method for preparing the above-mentioned chip packaging structure 100. The packaging method generally includes the following steps:

[0069] A chip 110 having a stepped portion 111 is provided. The stepped portion 111 may be formed at the bottom of the chip 110 by a dicing process.

[0070] A substrate 120 is provided with a first groove 121. A recess 122 is formed on the sidewall of the first groove 121. The stepped portion 111 of the chip 110 is secured to the recess 122 using an adhesive layer 130. A gap exists between the bottom of the chip 110 and the bottom of the first groove 121. This gap can be filled with the adhesive layer 130 or a plastic encapsulation material as needed. The chip 110 and the substrate 120 are electrically connected by wire bonding. A plastic encapsulation process is used to form a first plastic encapsulation material 141 on the substrate 120, which is then cut into individual chips.

[0071] In summary, the chip packaging structure 100 and chip packaging method provided by the embodiments of the present invention have the following beneficial effects:

[0072] In the chip packaging structure 100 and chip packaging method provided by the embodiment of the present invention, a sink 122 is provided on the side wall of the first groove 121 of the substrate 120, which is conducive to improving the bonding force between the chip 110, the adhesive layer 130 and the substrate 120. The provision of the step portion 111 on the chip 110 can reduce the overall packaging height and reduce the contact area between the bottom of the chip 110 and the adhesive layer 130, thereby avoiding the problem of stress delamination of the adhesive layer 130 on the back of the chip 110 and difficulty in discharging bubbles. The filling of the second plastic package 142 can balance the stress on both sides of the chip 110 and alleviate warping deformation. The design of the first groove 126, the second groove 129, etc. is conducive to improving the fluidity and filling properties of the plastic package, and plays a better role in support, buffering, heat dissipation and stress release.

[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some or all of the technical features therein. Any modifications, equivalent replacements, improvements, etc. made should be included in the scope of protection of the present invention.

Claims

1. A chip packaging structure, characterized in that: include: A chip, wherein a step portion is provided at the bottom of the chip; A substrate, wherein the substrate is provided with a first groove; The chip is mounted in the first groove, wherein the step portion abuts against the substrate, and there is a gap between the bottom of the chip and the bottom of the first groove; the chip and the substrate are electrically connected; an adhesive layer, the adhesive layer being provided between the step portion of the chip and the substrate; A third groove is formed on the substrate along the periphery of the chip. A second groove is also formed on the substrate, and the second groove communicates with the third groove and the first groove.

2. The chip packaging structure according to claim 1, wherein: The step portion includes a first step and a second step located at different heights along a height direction, and the first step and / or the second step abuts against the substrate.

3. The chip packaging structure according to claim 2, wherein: A sidewall of the first groove is provided with a sinking platform extending in a direction away from the first groove, and the first step is supported on the sinking platform; the second step is closer to the bottom of the chip than the first step.

4. The chip packaging structure according to claim 3, wherein: The adhesive layer is provided between the sink and the first step; The adhesive layer or plastic package is filled between the bottom of the chip and the first groove, and between the second step and the first groove.

5. The chip packaging structure according to claim 1, wherein: It also includes a first plastic package and a second plastic package. The first plastic package covers the side of the chip away from the substrate. The second plastic package is filled in the gap between the bottom of the chip and the bottom of the first groove.

6. The chip packaging structure according to claim 3, wherein: There is a gap between the edge of the chip and the edge of the first groove.

7. The chip packaging structure according to claim 6, wherein: The chip has two oppositely arranged first edges and two oppositely arranged second edges; the sinking platform is provided on the side wall of the first groove at a position corresponding to the first edge; the first edge is supported on the sinking platform; and there is a gap between the second edge and the side wall of the first groove.

8. The chip packaging structure according to claim 1, wherein: A second groove is formed on the substrate and is located on a side of the first groove away from the chip; a projection area of ​​the second groove on the substrate is larger than a projection area of ​​the chip on the substrate; and a third plastic package is filled in the second groove.

9. The chip packaging structure according to claim 8, wherein: A first groove is formed on the substrate, the first groove is connected to the second groove, the first groove and the second groove are respectively filled with the third plastic package body, and a bottom cavity is formed between the bottom of the chip and the first groove.

10. The chip packaging structure according to claim 9, wherein: A sensing area is provided on a side of the chip facing the bottom cavity; and a step portion of the chip is sealed and connected to a groove wall of the first groove in a circumferential direction.

11. The chip packaging structure according to any one of claims 1 to 10, characterized in that: A first pad is provided on the chip, a second pad is provided on the substrate, and the first pad and the second pad are electrically connected; the third groove is located between the second pad and the chip.

12. A chip packaging method, characterized in that: Used to prepare the chip packaging structure according to any one of claims 1 to 11.

Images