Power dividing circuit, power divider and antenna feed system

Abstract

The invention provides a mode-reconfigurable power division circuit, which comprises a first input branch, a second input branch, a third input branch and a fourth input branch, two ends of the second input branch are respectively connected to the first input branch through the first control element and the second control element; one end of the first output branch is connected to the other end of the first input branch, and the other end of the first output branch is a first output port; one end of the second output branch is connected to the other end of the first input branch, and the other end of the second output branch is a second output port; a third control element; and a fourth control element. When the first control element to the fourth control element are in a first state, the power dividing circuit works in a first mode to form a one-way path from the input port to the first output port, and when the first control element to the fourth control element are in a second state, the power dividing circuit works in a second mode to form a one-way path from the input port to the first output port. A bidirectional path from the input port to the first output port and the second output port is formed. The invention also provides a power divider and an antenna feed system.

Description

Technical Field

[0001] The present disclosure relates to the technical field of wireless antennas, and in particular, to a power distribution circuit, a power divider, and an antenna feeding system. Background Art

[0002] With the rapid development of large-scale multiple-input multiple-output (MIMO) technology and phased array antenna technology in 4G and 5G, the traditional power divider (i.e., power splitter) operating at a single frequency and in a fixed operating mode can no longer meet the development needs of microwave communication systems and the rapid development needs of modern reconfigurable array antenna technology.

[0003] The reconfigurable power divider has advantages such as reusability, adjustability, and flexibility, can adapt to the requirements of the array antenna for different operating frequencies and power division ratios, can achieve the effects that originally required multiple power dividers, and can even perform real-time control and scanning of the beam of the array antenna.

[0004] The overall structure of the power divider in the related art is complex and has disadvantages such as non-linearity and large power loss, is not suitable for high-power scenarios, and is limited by the architecture and cannot achieve a broadband architecture. Therefore, there is a need to implement a new type of power divider that can maintain a low reflection coefficient in a wider frequency range to meet the requirements of broadband communication systems or high-frequency circuits. Summary of the Invention

[0005] The present disclosure provides a power distribution circuit, a power divider, and an antenna feeding system.

[0006] In a first aspect, an embodiment of the present disclosure provides a power splitting circuit, including: a first input branch, one end of the first input branch being an input port; a second input branch, both ends of the second input branch being connected to the first input branch via a first control element and a second control element respectively; a first output branch, one end of the first output branch being connected to the other end of the first input branch, and the other end of the first output branch being a first output port; a second output branch, one end of the second output branch being connected to the other end of the first input branch, and the other end of the second output branch being a second output port; a third control element, one end of the third control element being connected to the first input branch; and a fourth control element, one end of the fourth control element being connected to the second output branch. When the first control element to the fourth control element are in a first state, the power splitting circuit operates in a first mode, forming a unidirectional path from the input port to the first output port. When the first control element to the fourth control element are in a second state, the power splitting circuit operates in a second mode, forming a bidirectional path from the input port to the first output port and the second output port respectively.

[0007] In a second aspect, embodiments of the present disclosure further provide a power divider circuit with reconfigurable modes, including a first sub-circuit, a second sub-circuit, and a third sub-circuit. Each of the first to third sub-circuits includes a power divider circuit according to the first aspect of the present disclosure. The input port of the first sub-circuit is the input port of the power divider circuit. The input port of the second sub-circuit is connected to the first output port of the first sub-circuit. The first output port and the second output port of the second sub-circuit are respectively the first output port and the second output port of the power divider circuit. The input port of the third sub-circuit is connected to the second output port of the first sub-circuit. The first output port and the second output port of the third sub-circuit are respectively the third output port and the fourth output port of the power divider circuit. When the first to fourth control elements of each of the first sub-circuit and the second sub-circuit are in a first state, the power divider circuit operates in a first mode, forming a unidirectional path from the input port of the power divider circuit to the first output port of the power divider circuit. When the first to fourth control elements of the first sub-circuit are in a first state and the first to fourth control elements of the second sub-circuit are in a second state, the power divider circuit operates in a second mode, forming a bidirectional path from the input port of the power divider circuit to the first output port and the second output port of the power divider circuit respectively. When the first to fourth control elements of the first sub-circuit are in a second state and the first to fourth control elements of each of the second sub-circuit and the third sub-circuit are in a first state, the power divider circuit operates in a third mode, forming a bidirectional path from the input port of the power divider circuit to the first output port and the third output port of the power divider circuit respectively. When the first to fourth control elements of each of the first sub-circuit and the second sub-circuit are in a second state and the first to fourth control elements of the third sub-circuit are in a first state, the power divider circuit operates in a fourth mode, forming a three-way path from the input port of the power divider circuit to the first to third output ports of the power divider circuit respectively. When the first to fourth control elements of each of the first sub-circuit and the third sub-circuit are in a second state and the first to fourth control elements of the second sub-circuit are in a first state, the power divider circuit operates in a fifth mode, forming a three-way path from the input port of the power divider circuit to the first output port, the third output port, and the fourth output port of the power divider circuit respectively. When the first to fourth control elements of each of the first to third sub-circuits are in a second state, the power divider circuit operates in a sixth mode, forming a four-way path from the input port of the power divider circuit to the first to fourth output ports of the power divider circuit respectively.

[0008] In a third aspect, an embodiment of the present disclosure further provides a mode-reconfigurable power divider circuit, including a first-stage cascaded circuit to an N-stage cascaded circuit connected in sequence, where N is a positive integer and N>1. The n-stage cascaded circuit includes 2 n-1 sub-circuits, where n is a positive integer and 1≤n≤N. Each sub-circuit of each cascaded circuit includes a power divider circuit according to the first aspect of the present disclosure. The input port of the sub-circuit of the first-stage cascaded circuit is the input port of the power divider circuit; the first output port of the k-th sub-circuit of the m-th cascaded circuit is connected to the input port of the (2k - 1)-th sub-circuit of the (m + 1)-th cascaded circuit, and the second output port of the k-th sub-circuit of the m-th cascaded circuit is connected to the input port of the 2k-th sub-circuit of the (m + 1)-th cascaded circuit, where m is a positive integer and 1≤m<N, and k is a positive integer and 1≤k≤2 m-1 ; the first output port and the second output port of each sub-circuit of the N-th cascaded circuit are respectively the first output port to the 2 N output ports of the power divider circuit.

[0009] In a fourth aspect, an embodiment of the present disclosure further provides a mode-reconfigurable power divider, including a substrate and a power divider circuit printed on the substrate, where the power divider circuit includes a power divider circuit according to any one of the first to third aspects of the present disclosure.

[0010] In a fifth aspect, an embodiment of the present disclosure further provides an antenna feeding system, including a power divider according to the fourth aspect of the present disclosure.

[0011] According to the power divider circuit of the embodiment of the present disclosure, by controlling the state of the control element, a unidirectional path from the input port to the first output port can be formed, or a bidirectional path from the input port to the first output port and the second output port respectively can be formed; in the case of cascading multiple power divider circuits, multiple different working modes such as a unidirectional path, a bidirectional path, a four-way path, or more paths can be formed. Based on the switching characteristics of the control element and the cooperation of multiple matching architectures, a broadband multi-mode reconfigurable power divider architecture is realized. Description of the Drawings

[0012] In the drawings of the embodiments of the present disclosure:

[0013] Figure 1 shows a schematic structural diagram of a traditional power divider;

[0014] Figure 2 shows a schematic principle diagram of a traditional T-shaped power divider;

[0015] Figure 3 shows a schematic structural diagram of a mode-reconfigurable power divider circuit according to an embodiment of the present disclosure;

[0016] Figure 4A shows the structural schematic diagram of a pattern-reconfigurable power divider circuit according to an embodiment of the present disclosure;

[0017] Figure 4B shows the structural schematic diagram of the pattern-reconfigurable power divider circuit according to an embodiment of the present disclosure when operating in the first mode;

[0018] Figure 4C shows the structural schematic diagram of the pattern-reconfigurable power divider circuit according to an embodiment of the present disclosure when operating in the second mode;

[0019] Figure 5 shows the physical structure diagram of a PIN diode;

[0020] Figure 6 shows the equivalent circuit diagram of a PIN diode in the forward bias state;

[0021] Figure 7 shows the equivalent circuit diagram of a PIN diode in the reverse bias state;

[0022] Figure 8 shows another structural schematic diagram of the pattern-reconfigurable power divider circuit according to an embodiment of the present disclosure. Detailed implementation manners

[0023] To enable those skilled in the art to better understand the technical solutions of the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0024] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings. However, the illustrated embodiments may be embodied in different forms and the present disclosure should not be construed as limited to the embodiments set forth below. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0025] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation to the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more obvious to those skilled in the art.

[0026] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of the ideal schematic diagrams of the present disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0027] Without conflict, the embodiments of the present disclosure and the features in the embodiments may be combined with each other.

[0028] The terms used in this disclosure are only for describing specific embodiments and are not intended to limit this disclosure. As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the related listed items. As used in this disclosure, the singular forms "a" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. As used in this disclosure, the terms "comprising", "made of", specify the presence of the stated features, wholes, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their groups.

[0029] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless this disclosure clearly so defines.

[0030] This disclosure is not limited to the embodiments shown in the drawings, but includes modifications to the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions, but are not intended to be restrictive.

[0031] With the rapid development of large-scale multiple-input multiple-output (MIMO) technology and phased array antenna technology in 4G and 5G, the traditional power divider that works at a single frequency and in a fixed operating mode can no longer meet the development needs of microwave communication systems and the rapid development needs of modern reconfigurable array antenna technology. The ultra-wideband, miniaturization, large capacity, high speed, multi-function, etc. of key devices in the antenna network have become research hotspots in this field.

[0032] In early microwave control circuits, the impedance of microwave semiconductor diodes that varies with the applied bias voltage was used to control the parameters in the circuit. With the development of semiconductor devices and the emergence of various new control devices, the performance of microwave control circuits has been greatly improved. With the continuous development of semiconductor processes and the continuous maturity of MMIC technology, switching technologies suitable for different frequency band index requirements have become very mature. Micro-electro-mechanical system (MEMS) switches have emerged one after another and play an important role in control circuits with the continuous maturity of the process. At the same time, in order to meet the needs of wireless communication, control circuits often require higher frequencies, wider bandwidths, and better performance.

[0033] As an important part of the front-end of radio frequency circuits, the research and design of power dividers are attracting increasing attention. In large-scale array antenna systems, phased array radar systems, and power combiners, power dividers with different power distribution ratios (i.e., power division ratios) are required. The working principle of radio frequency power dividers determines their disadvantage of large volume. The cascaded application of multiple radio frequency power dividers will further make the radio frequency front-end bulky and increase the production cost.

[0034] Figure 1 Fig. shows the structural schematic diagram of a traditional power divider.

[0035] Taking the T-junction as an example, the power divider with a T-junction is simply called a T-type power divider, which is one of the most common forms of power dividers. The T-type power divider has one input port Port1 and two output ports Port2 and Port3. As Figure 1 shown, the transmission characteristics of the T-type power divider can be analyzed through the S-parameters of the three-port elements. Since the structure of the T-type power divider does not contain anisotropic materials and is a passive device, its S-matrix can be expressed as follows:

[0036] Figure 2 Fig. shows the schematic diagram of a traditional T-type power divider.

[0037] As Figure 2 shown, the T-type power divider can be simplified to consist of one input port Port1, two output ports Port2 and Port3, and two transmission lines. Generally speaking, in order to perform impedance transformation, the two transmission lines are selected as λ / 4 impedance transformers. Thus, the input impedances of the upper and lower stubs are respectively: where, Z inU represents the input impedance of the upper stub, Z inL represents the input impedance of the lower stub, Z3 represents the characteristic impedance of the upper stub, Z2 represents the characteristic impedance of the lower stub, and Z0 represents the characteristic impedance of the input port.

[0038] To make the power divider matched at the input port Port1, the following conditions need to be met:

[0039]

[0040] If it is the case of equal power division, according to the above formula, the impedance values of the two λ / 4 impedance transformers can be obtained as: According to the reciprocity and lossless conditions, the S-parameters of the equal-division T-type power divider can be obtained as:

[0041] That is to say, when the energy is input from port Port1, the energies output at ports Port2 and Port3 are respectively 1 / 2 of the total energy, and the phase differs from that of the input port by 90°. When the energy is input into port Port2, 1 / 4 of the energy is reflected by the port, 1 / 4 of the energy is transmitted to port Port3, and 1 / 2 of the energy is transmitted to port Port1. In particular, when the energy is input from ports Port2 and Port3 simultaneously, if the energies input at the two ports are equal in amplitude and in phase, there is a maximum output at port Port1; if the energies input are equal in amplitude and opposite in phase, there is no output at port Port1.

[0042] The reconfigurable power divider has advantages such as multiplexing, adjustability, and flexibility, can adapt to the requirements of array antennas for different operating frequencies and power division ratios, can achieve the effects that originally required multiple power dividers, and can even achieve real-time control and scanning of the beam of the array antenna.

[0043] One reconfigurable power divider with reconfigurable power division paths and reconfigurable power division ratio can be used to replace multiple devices to reduce costs, improve performance and integration, and miniaturize the device size of the communication system. However, limited by the matching architecture, traditional reconfigurable power dividers can only achieve the function of a fixed power division ratio, resulting in limited overall performance, inability to achieve multiple functions through one architecture, low integration, and narrow operating bandwidth.

[0044] In the implementation of reconfigurable power division paths of the power divider, the core problem is to transmit the power of one port to any number of ports. To achieve this goal, there are currently two main methods: adjustable power division ratio and adjustable reflected power. The related technical solution proposes a reconfigurable power divider with these two adjustable methods of adjustable power division ratio and adjustable reflected power. Among them, each π-type equivalent transmission line constitutes an adjustable reflector. By adjusting the voltage applied to the varactor diode in the adjustable reflector, the power division paths and the power division ratio can be adjusted simultaneously, and the power division ratio is continuously adjustable within a certain range. It has the advantages of being easy to control the division paths and the division ratio and being easy to implement, and solves the problem that it is difficult for traditional power dividers to achieve simultaneous adjustment of power division paths and power division ratio. However, the reconfigurable technology based on varactor diodes introduces a DC bias circuit because the bias voltage on the varactor diode needs to be adjusted, resulting in disadvantages such as a complex overall structure of the power divider, non-linearity, and large power loss of the power divider, which is not suitable for high-power scenarios, and is limited by the influence and limitation of the architecture and cannot achieve a broadband architecture. In addition, the matching architecture used in each mode is complex, resulting in low key indicators of the power divider and large phase differences.

[0045] The related art also proposes a scheme with a switchable power division ratio. This scheme uses PIN diodes and a T-type power division architecture to implement a power divider with multiple operating modes. However, due to the simple architecture of this power divider and the single matching network, which only performs matching through the impedance change of the main signal transmission line, the change in the power division ratio and the covered bandwidth are limited. Moreover, the performance is poor when implementing an equal power division of 1 to 2 (i.e., the power division ratio is 1:1), and good broadband performance cannot be achieved.

[0046] A broadband reconfigurable power divider is a reconfigurable power divider whose functions or properties can be adjusted continuously or discretely. The current main implementation method is to load adjustable devices on the transmission line. The functions and various technical parameters of this power divider are mainly affected by the parameters of the transmission line. For example, the operating frequency of the power divider mainly depends on the electrical length of the λ / 4 transmission line, the power division ratio of the power divider mainly depends on the impedance ratio of the λ / 4 transmission line, and the port reflection coefficient of the power divider is mainly affected by the characteristic impedance of the transmission line. Therefore, the reconfiguration of the functions or properties of the power divider can be achieved by adjusting the equivalent impedance or equivalent phase shift of the transmission line.

[0047] In view of the above various problems, the present disclosure provides a broadband multi-mode reconfigurable power divider architecture through the design of a power division circuit. By using a multi-stub matching architecture, a wider bandwidth than that of a single stub is achieved by increasing the adjustment freedom, distributed compensation of the frequency response, optimizing the Smith chart path, and phase superposition. Through the cooperative action of multiple tuning points, a low reflection coefficient can be maintained in a wider frequency range, thus meeting the requirements of broadband communication systems or high-frequency circuits. According to the power divider architecture provided by the present disclosure, not only the function of reconfigurable power division ratio is realized, but also excellent performances such as broadband, low loss, and low cost are achieved.

[0048] Figure 3 FIG. shows a schematic structural diagram of a mode-reconfigurable power division circuit according to an embodiment of the present disclosure.

[0049] As Figure 3 shown, the mode-reconfigurable power division circuit according to an embodiment of the present disclosure includes a first input branch 301, a second input branch 302, a first output branch 303, and a second output branch 304.

[0050] One end of the first input branch 301 is the input port Port1; both ends of the second input branch 302 are connected to the first input branch 301 via the first control element S1 and the second control element S2 respectively; one end of the first output branch 303 is connected to the other end of the first input branch 301, and the other end of the first output branch 303 is the first output port Port2; one end of the second output branch 304 is connected to the other end of the first input branch 301, and the other end of the second output branch 304 is the second output port Port3. One end of the third control element S3 is connected to the first input branch 301, and one end of the fourth control element S4 is connected to the second output branch 304.

[0051] Figure 4A FIG. is a schematic structural diagram of a mode-reconfigurable power divider circuit according to an embodiment of the present disclosure. Figure 4B FIG. is a schematic structural diagram of the mode-reconfigurable power divider circuit according to an embodiment of the present disclosure when operating in the first mode, and Figure 4C FIG. is a schematic structural diagram of the mode-reconfigurable power divider circuit according to an embodiment of the present disclosure when operating in the second mode.

[0052] See Figure 3 and Figure 4A , the first input branch 301 can be equivalently regarded as a series circuit of the first stub TL1, the second stub TL2, and the third stub TL3, the second input branch 302 can be equivalently regarded as the fourth stub TL4, the first output branch 303 can be equivalently regarded as the fifth stub TL5, and the second output branch 304 can be equivalently regarded as the sixth stub TL6.

[0053] See Figure 3 and Figure 4B , when the first control element S1 to the fourth control element S4 are in the first state, the power divider circuit operates in the first mode, forming a unidirectional path from the input port Port1 to the first output port Port2.

[0054] According to an embodiment of the present disclosure, when the first control element S1 to the fourth control element S4 are simultaneously forward-conducted, it is approximately short-circuited to the ground in the circuit, and most of the signals are reflected back by the ground. The first stub TL1 and the second stub TL2 of the first input branch 301 shorten the electrical length due to the forward conduction of the third control element S3, and the second output port Port3 shortens the electrical length due to the forward conduction of the fourth control element S4, so that the signal is transmitted from the input port Port1 to the first output port Port2, that is, the 1to1 channel selection function is realized.

[0055] See Figure 3 and Figure 4C, when the first control element S1 to the fourth control element S4 are in the second state, the power divider circuit operates in the second mode, forming a bidirectional path from the input port Port1 to the first output port Port2 and the second output port Port3 respectively.

[0056] According to an embodiment of the present disclosure, when the first control element S1 to the fourth control element S4 are simultaneously reverse cutoff, it is approximately open circuit to the ground in the circuit, and the signal is transmitted from the input port Port1 to the first output port Port2 and the second output port Port3, that is, the 1-to-2 power distribution function is realized.

[0057] According to an embodiment of the present disclosure, the mode-reconfigurable power divider circuit uses stubs (microstrip lines) TL1 to TL6 and four control elements S1 to S4 to implement two operating modes (i.e., unidirectional mode and bidirectional mode), and provides a certain impedance matching conversion in each mode.

[0058] In the unidirectional mode, as Figure 4B shown, all control elements S1 to S4 are forward-biased. The second output port Port3 shortens the electrical length due to the forward conduction of the fourth control element S4, and the second stub TL2 and the third stub TL3 of the first input branch 301 shorten the electrical length due to the forward conduction of the third control element S3, thereby forming a double-tuned matching.

[0059] When all control elements S1 to S4 are reverse-biased, as Figure 4C shown, the circuit realizes the bidirectional mode. According to an embodiment of the present disclosure, the λ / 4 conversion lines (i.e., the fifth stub TL5 and the sixth stub TL6) have a characteristic impedance Z2, and are inserted between the impedance merging point and the end point (i.e., the output port), and together with the third stub TL3, directly convert the port impedance to the required Zin (e.g., 50 Ω), and then connect the first stub TL1, the second stub TL2, and the third stub TL3 with a characteristic impedance Z1 to provide an accurate impedance matching for the source port.

[0060] According to an embodiment of the present disclosure, as Figure 3 shown, one end of the first control element S1 is connected to the first input branch 301, the other end of the first control element S1 is connected to one end of the second input branch 302, one end of the second control element S2 is connected to the first input branch 301, and the other end of the second control element is connected to the other end of the second input branch 302. As Figure 4AAs shown, the control signal Vctr is applied to the other ends of the first control element S1 and the second control element S2 via the second input branch 302 (i.e., the fourth stub TL4), and the control signal Vctr is also applied to the other ends of the third control element S3 and the fourth control element S4. The first control element S1 to the fourth control element S4 are controlled by the control signal Vctr to be in a first state (e.g., forward bias or forward conduction) or a second state (e.g., reverse bias or reverse cut-off).

[0061] According to an embodiment of the present disclosure, as Figure 3 shown, the first input branch 301 has a "Ji" - shaped structure and includes a first straight portion 3011, a first bent portion 3012, a second bent portion 3013, and a second straight portion 3014 connected in sequence. The second input branch 302 has a straight - line structure and is on the same straight line as the first straight portion 3011 and the second straight portion 3014 of the first input branch.

[0062] According to an embodiment of the present disclosure, when the power - splitting circuit operates in the first mode and forms a unidirectional path from the input port Port1 to the first output port Port2, the first straight portion of the first input branch 301, the second input branch 302, and the second straight portion of the first input branch 301 form the input signal transmission line in the first mode; when the power - splitting circuit operates in the second mode and forms a bidirectional path from the input port Port1 to the first output port Port2 and the second output port Port3 respectively, each part of the first input branch 301 (i.e., the first straight portion 3011, the first bent portion 3012, the second bent portion 3013, and the second straight portion 3014) forms the input signal transmission line in the second mode. By appropriately configuring each part of the first input branch 301 and the second input branch 302, different impedance matches can be provided for the first mode and the second mode respectively.

[0063] According to an embodiment of the present disclosure, as Figure 3 shown, the first control element S1 is connected to the intersection of the first straight portion 3011 and the first bent portion 3012 of the first input branch 301, the second control element S2 is connected to the intersection of the second bent portion 3013 and the second straight portion 3014 of the first input branch 301, and the third control element S3 is connected to the intersection of the first bent portion 3012 and the second bent portion 3013 of the first input branch 301.

[0064] According to an embodiment of the present disclosure, as Figure 3 shown, the second output branch 304 has an "L" - shaped structure, and the fourth control element S4 is connected to the bending point of the "L" - shaped structure of the second output branch 304.

[0065] According to an embodiment of the present disclosure, referring to Figure 3 and Figure 4A , the first output branch 303 has an "L" - shaped structure, the power divider circuit further includes a stub TL7, and the stub TL7 is connected to the bending point of the "L" - shaped structure of the first output branch 303, and the stub TL7 is an open - circuit stub.

[0066] No control element is used on the first output port Port2, but a stub TL7 with a characteristic impedance of Z3 can be used to eliminate the phase difference between the two output ports Port2 and Port3.

[0067] According to an embodiment of the present disclosure, in order to achieve complete grounding, as Figure 3 shown, the power divider circuit may further include a first matching element (e.g., an additional patch) Pat1 and a second matching element Pat2 for canceling the parasitic inductance brought by the control elements S3 and S4. The first matching element Pat1 is connected to the first input branch 301 via the third control element S3. The second matching element Pat2 is connected to the second output branch 304 via the fourth control element S4.

[0068] According to an embodiment of the present disclosure, the first matching element Pat1 and the second matching element Pat2 may include (but are not limited to): microstrip lines, LC circuits, etc. By adjusting the first matching element Pat1 and the second matching element Pat2, the performance of the power divider within a wide band can be better realized. The architecture of the power divider circuit can be achieved by using four control elements (e.g., PIN diodes), which has low cost and can be applied to high - power scenarios.

[0069] Due to the inter - stage matching of the stubs (microstrip lines) TL1 to TL7, multi - stub matching realizes a wider bandwidth than single - stub by increasing the adjustment freedom, distributed compensation of the frequency response, optimizing the Smith chart path, and phase superposition. Through the synergistic effect of multiple tuning points, a low reflection coefficient can be maintained within a wider frequency range, thus meeting the requirements of broadband communication systems or high - frequency circuits.

[0070] According to an embodiment of the present disclosure, the first control element S1 to the fourth control element S4 include one of the following: radio - frequency relay, ferrite circulator, gallium arsenide field - effect transistor (GaAsFET), varactor diode, and PIN diode.

[0071] The biggest difference between the PIN diode and other diodes is that the PIN diode will not undergo non - linear rectification under the action of microwave - band signals, which is also a unique property of the PIN diode. Therefore, the PIN diode is an ideal microwave control device, Figure 5 shows the physical structure diagram of the PIN diode.

[0072] The equivalent circuit model of the PIN diode is affected by the die and the package. According to different applied bias voltages, the equivalent circuit of the PIN diode is also different. In the forward bias state, the equivalent circuit diagram is as shown in Figure 6 shown below. Figure 6 The left side shows the equivalent circuit diagram of the PIN diode under forward bias. Figure 6 The right side shows the simplified equivalent circuit diagram of the PIN diode under forward bias, which can be equivalent to a forward bias resistance R s ; In the reverse bias state, the equivalent circuit diagram is as shown in Figure 7 shown below. Figure 7 The left side shows the equivalent circuit diagram of the PIN diode under reverse bias. Figure 7 The right side shows the simplified equivalent circuit diagram of the PIN diode under reverse bias, which can be equivalent to a reverse bias high impedance capacitor C j .

[0073] According to an embodiment of the present disclosure, the first control element S1 to the fourth control element S4 include PIN diodes. Based on the working principle of the PIN diode, by using the different parameters of the PIN diode under forward bias and reverse bias, the reconfigurable matching network and the isolation impedance switching network have good matching performance and high isolation. The power splitter circuit can operate in a single - way mode, a two - way mode, or even a four - way mode, and each mode of the power splitter circuit has good performance.

[0074] The embodiment of the present disclosure provides a broadband reconfigurable power splitter circuit. Using the PIN diode as a control element, based on the basic working principle of the PIN diode and the transmission line theory, the PIN diode is respectively in the conducting state (i.e., the first state) and the cut - off state (i.e., the second state), so as to control the signal to pass through different paths and achieve the broadband reconfigurable power splitting function.

[0075] Figure 8 FIG. is a schematic diagram showing another structure of the mode - reconfigurable power splitter circuit according to an embodiment of the present disclosure.

[0076] As shown in Figure 8 shown, the mode - reconfigurable power splitter circuit according to an embodiment of the present disclosure includes a first sub - circuit 801, a second sub - circuit 802, and a third sub - circuit 803. Each of the first sub - circuit 801 to the third sub - circuit 803 respectively includes a power splitter circuit as shown in Figure 3 shown below.

[0077] The input port of the first sub-circuit 801 is the input port Port1 of the power splitter circuit; the input port of the second sub-circuit 802 is connected to the first output port of the first sub-circuit 801, and the first output port and the second output port of the second sub-circuit are respectively the first output port Port2 and the second output port Port3 of the power splitter circuit; the input port of the third sub-circuit 803 is connected to the second output port of the first sub-circuit 801, and the first output port and the second output port of the third sub-circuit are respectively the third output port Port4 and the fourth output port Port5 of the power splitter circuit.

[0078] When the first to fourth control elements of the first sub-circuit 801 and the second sub-circuit 802 are in the first state, the power splitter circuit operates in the first mode (i.e., single-path mode), forming a unidirectional path from the input port Port1 of the power splitter circuit to the first output port Port2 of the power splitter circuit.

[0079] According to Figure 3 In the illustrated embodiment, when the first to fourth control elements of the first sub-circuit 801 are in the first state, a unidirectional path is formed from the input port of the first sub-circuit 801 (i.e., the input port Port1 of the power splitter circuit) to the first output port of the first sub-circuit 801. Therefore, in this case, the signal does not enter the third sub-circuit 803 but only enters the second sub-circuit 802. When the first to fourth control elements of the second sub-circuit 802 are in the first state, a unidirectional path is formed from the input port of the second sub-circuit 802 (which is connected to the first output port of the first sub-circuit 801) to the first output port of the second sub-circuit 802 (i.e., the first output port Port2 of the power splitter circuit), thereby forming a unidirectional path from the input port Port1 of the power splitter circuit to the first output port Port2 of the power splitter circuit.

[0080] When the first to fourth control elements of the first sub-circuit 801 are in the first state and the first to fourth control elements of the second sub-circuit are in the second state, the power splitter circuit operates in the second mode (i.e., dual-path mode 1), forming a bidirectional path from the input port Port1 of the power splitter circuit to the first output port Port2 and the second output port Port3 of the power splitter circuit respectively.

[0081] According to Figure 3In the illustrated embodiment, when the first to fourth control elements of the first sub-circuit 801 are in the first state, a unidirectional path is formed from the input port of the first sub-circuit 801 (i.e., Port1, the input port of the power divider circuit) to the first output port of the first sub-circuit 801. Therefore, in this case, the signal does not enter the third sub-circuit 803 but only enters the second sub-circuit 802. When the first to fourth control elements of the second sub-circuit 802 are in the second state, a bidirectional path is formed from the input port of the second sub-circuit 802 (which is connected to the first output port of the first sub-circuit 801) to the first output port (i.e., Port2, the first output port of the power divider circuit) and the second output port (i.e., Port3, the second output port of the power divider circuit) of the second sub-circuit 802, thereby forming a bidirectional path from the input port Port1 of the power divider circuit to the first output port Port2 and the second output port Port3 of the power divider circuit.

[0082] When the first to fourth control elements of the first sub-circuit 801 are in the second state, and the first to fourth control elements of the second sub-circuit 802 and the third sub-circuit 803 are in the first state respectively, the power divider circuit operates in the third mode (i.e., dual-path mode 2), forming bidirectional paths from the input port Port1 of the power divider circuit to the first output port Port2 and the third output port Port4 of the power divider circuit respectively.

[0083] According to Figure 3 In the illustrated embodiment, when the first to fourth control elements of the first sub-circuit 801 are in the second state, a bidirectional path is formed from the input port of the first sub-circuit 801 (i.e., Port1, the input port of the power divider circuit) to the first and second output ports of the first sub-circuit 801. Therefore, in this case, the signal enters the second sub-circuit 802 and the third sub-circuit 803. When the first to fourth control elements of the second sub-circuit 802 are in the first state, a unidirectional path is formed from the input port of the second sub-circuit 802 (which is connected to the first output port of the first sub-circuit 801) to the first output port (i.e., Port2, the first output port of the power divider circuit) of the second sub-circuit 802; when the first to fourth control elements of the third sub-circuit 803 are in the first state, a unidirectional path is formed from the input port of the third sub-circuit 803 (which is connected to the second output port of the first sub-circuit 801) to the first output port (i.e., Port4, the third output port of the power divider circuit) of the third sub-circuit 803, thereby forming a bidirectional path from the input port Port1 of the power divider circuit to the first output port Port2 and the third output port Port4 of the power divider circuit.

[0084] When the first to fourth control elements of the first sub-circuit 801 and the second sub-circuit 802 are in the second state, and the first to fourth control elements of the third sub-circuit 803 are in the first state, the power divider circuit operates in the fourth mode (i.e., three-way mode 1), forming a three-way path from the input port Port1 of the power divider circuit to the first to third output ports Port2 to Port4 of the power divider circuit.

[0085] According to Figure 3 In the embodiment shown, when the first to fourth control elements of the first sub-circuit 801 are in the second state, a two-way path is formed from the input port of the first sub-circuit 801 (i.e., the input port Port1 of the power divider circuit) to the first and second output ports of the first sub-circuit 801. Therefore, in this case, the signal enters the second sub-circuit 802 and the third sub-circuit 803. When the first to fourth control elements of the second sub-circuit 802 are in the second state, a two-way path is formed from the input port of the second sub-circuit 802 (which is connected to the first output port of the first sub-circuit 801) to the first output port (i.e., the first output port Port2 of the power divider circuit) and the second output port (i.e., the second output port Port3 of the power divider circuit) of the second sub-circuit 802; when the first to fourth control elements of the third sub-circuit 803 are in the first state, a one-way path is formed from the input port of the third sub-circuit 803 (which is connected to the second output port of the first sub-circuit 801) to the first output port (i.e., the third output port Port4 of the power divider circuit) of the third sub-circuit 803, thereby forming a three-way path from the input port Port1 of the power divider circuit to the first to third output ports Port2 to Port4 of the power divider circuit.

[0086] When the first to fourth control elements of the first sub-circuit 801 and the third sub-circuit 803 are in the second state, and the first to fourth control elements of the second sub-circuit 802 are in the first state, the power divider circuit operates in the fifth mode (i.e., three-way mode 2), forming a three-way path from the input port Port1 of the power divider circuit to the first output port Port2, the third output port Port4, and the fourth output port Port5 of the power divider circuit.

[0087] According to Figure 3In the illustrated embodiment, when the first to fourth control elements of the first sub-circuit 801 are in the second state, a bidirectional path is formed from the input port of the first sub-circuit 801 (i.e., the input port Port1 of the power splitter circuit) to the first output port and the second output port of the first sub-circuit 801. Therefore, in this case, signals enter the second sub-circuit 802 and the third sub-circuit 803. When the first to fourth control elements of the second sub-circuit 802 are in the first state, a unidirectional path is formed from the input port of the second sub-circuit 802 (which is connected to the first output port of the first sub-circuit 801) to the first output port of the second sub-circuit 802 (i.e., the first output port Port2 of the power splitter circuit); when the first to fourth control elements of the third sub-circuit 803 are in the second state, a bidirectional path is formed from the input port of the third sub-circuit 803 (which is connected to the second output port of the first sub-circuit 801) to the first output port (i.e., the third output port Port4 of the power splitter circuit) and the second output port (i.e., the fourth output port Port5 of the power splitter circuit) of the third sub-circuit 803, thereby forming a three-way path from the input port Port1 of the power splitter circuit to the first output port Port2, the third output port Port4, and the fourth output port Port5 of the power splitter circuit.

[0088] When the first to fourth control elements of each of the first sub-circuit 801 to the third sub-circuit 803 are in the second state, the power splitter circuit operates in the sixth mode (i.e., the four-way mode), forming a four-way path from the input port Port1 of the power splitter circuit to the first to fourth output ports Port2 to Port5 of the power splitter circuit.

[0089] According to Figure 3In the illustrated embodiment, when the first to fourth control elements of the first sub - circuit 801 are in the second state, a bidirectional path is formed from the input port of the first sub - circuit 801 (i.e., the input port Port1 of the power divider circuit) to the first output port and the second output port of the first sub - circuit 801. Therefore, in this case, signals enter the second sub - circuit 802 and the third sub - circuit 803. When the first to fourth control elements of the second sub - circuit 802 are in the second state, a bidirectional path is formed from the input port of the second sub - circuit 802 (which is connected to the first output port of the first sub - circuit 801) to the first output port of the second sub - circuit 802 (i.e., the first output port Port2 of the power divider circuit) and the second output port (i.e., the second output port Port3 of the power divider circuit); when the first to fourth control elements of the third sub - circuit 803 are in the second state, a bidirectional path is formed from the input port of the third sub - circuit 803 (which is connected to the second output port of the first sub - circuit 801) to the first output port of the third sub - circuit 803 (i.e., the third output port Port4 of the power divider circuit) and the second output port (i.e., the fourth output port Port5 of the power divider circuit), thereby forming a four - way path from the input port Port1 of the power divider circuit to the first to fourth output ports Port2 - Port5 of the power divider circuit.

[0090] Table 1 below more clearly shows the various operating modes of the mode - reconfigurable power divider circuit according to the embodiments of the present disclosure.

[0091] Table 1

[0092] The mode - reconfigurable power divider circuit according to the embodiments of the present disclosure uses a control element architecture to achieve broadband reconfigurable power dividing function, and only 12 control elements (e.g., PIN diodes) are used to achieve six operating modes, achieving a good balance in various aspects such as broadband, multiple operating modes, and low cost.

[0093] The embodiments of the present disclosure also provide a mode - reconfigurable power divider circuit, including a first - stage cascaded circuit to an N - th stage cascaded circuit connected in sequence, where N is a positive integer and N>1. The n - th stage cascaded circuit includes 2 n-1 sub - circuits, n is a positive integer, 1≤n≤N, and each sub - circuit of each cascaded circuit respectively includes a power divider circuit as Figure 3 shown.

[0094] The input port of the sub-circuit of the first-level cascade circuit is the input port of the power divider circuit; the first output port of the k-th sub-circuit of the m-th level cascade circuit is connected to the input port of the (2k - 1)-th sub-circuit of the (m + 1)-th level cascade circuit, and the second output port of the k-th sub-circuit of the m-th level cascade circuit is connected to the input port of the 2k-th sub-circuit of the (m + 1)-th level cascade circuit, where m is a positive integer, 1 ≤ m < N, k is a positive integer, and 1 ≤ k ≤ 2 m-1 ; the first output ports and the second output ports of the sub-circuits of the N-th level cascade circuit are respectively the first output port to the 2 N output ports of the power divider circuit.

[0095] For example, when N = 2, the power divider circuit is the Figure 8 shown power divider circuit. The first-level cascade circuit includes 1 (n = 1, 2 n-1 = 1) sub-circuit, the second-level cascade circuit includes 2 (n = 2, 2 n-1 = 2) sub-circuits, and each sub-circuit of each level cascade circuit respectively includes the Figure 3 shown power divider circuit. The input port of the sub-circuit of the first-level cascade circuit is the input port of the power divider circuit; the first output port of the 1st (k = 1) sub-circuit of the first (m = 1) level cascade circuit is connected to the input port of the 1st (2k - 1 = 1) sub-circuit of the second (m + 1 = 2) level cascade circuit, and the second output port of the 1st sub-circuit of the first-level cascade circuit is connected to the input port of the 2nd (2k = 2) sub-circuit of the second-level cascade circuit; the first output ports and the second output ports of the sub-circuits of the second (N = 2) level cascade circuit are respectively the first output port to the fourth (2 N = 4) output ports of the power divider circuit.

[0096] For another example, when N = 3, the first-level cascade circuit includes 1 (n = 1, 2 n-1 = 1) sub-circuit, the second-level cascade circuit includes 2 (n = 2, 2 n-1 = 2) sub-circuits, the third-level cascade circuit includes 4 (n = 3, 2 n-1 = 4) sub-circuits, and each sub-circuit of each level cascade circuit respectively includes the Figure 3The power divider circuit shown. The input port of the sub-circuit of the first-level cascaded circuit is the input port of the power divider circuit; the first output port of the first (m = 1) sub-circuit of the first-level cascaded circuit is connected to the input port of the first (2k - 1 = 1) sub-circuit of the second (m + 1 = 2) - level cascaded circuit, and the second output port of the first sub-circuit of the first-level cascaded circuit is connected to the input port of the second (2k = 2) sub-circuit of the second-level cascaded circuit; the first output port of the first (k = 1) sub-circuit of the second (m = 2) - level cascaded circuit is connected to the input port of the first (2k - 1 = 1) sub-circuit of the third (m + 1 = 3) - level cascaded circuit, and the second output port of the first sub-circuit of the second-level cascaded circuit is connected to the input port of the second (2k = 2) sub-circuit of the third-level cascaded circuit; the first output port of the second (k = 2) sub-circuit of the second (m = 2) - level cascaded circuit is connected to the input port of the third (2k - 1 = 3) sub-circuit of the third (m + 1 = 3) - level cascaded circuit, and the second output port of the second sub-circuit of the second-level cascaded circuit is connected to the input port of the fourth (2k = 4) sub-circuit of the third-level cascaded circuit; the first output port and the second output port of each sub-circuit of the third (N = 3) - level cascaded circuit are respectively the first output port to the eighth (2 N = 8) output ports of the power divider circuit.

[0097] The mode-reconfigurable power divider circuit according to an embodiment of the present disclosure uses a control element architecture to achieve broadband reconfigurable power division function, and realizes multiple working modes from 1 to 1 to 1 to 2 with only relatively few control elements (e.g., PIN diodes), and has the advantages of convenient and flexible use and low cost, and can be used in the design of array antenna feeding networks. N The mode-reconfigurable power divider according to an embodiment of the present disclosure also provides a mode-reconfigurable power divider, including a substrate and a power divider circuit printed on the substrate, wherein the power divider circuit includes the power divider circuit according to various embodiments of the present disclosure.

[0098] The present disclosure also provides an antenna feeding system including the power divider according to an embodiment of the present disclosure.

[0099] The present disclosure also provides an antenna feeding system including the power divider according to an embodiment of the present disclosure.

[0100] The embodiments of the present disclosure provide a broadband multi-mode reconfigurable power divider architecture, which can be applied to an antenna feeding network. On the one hand, based on the traditional power division technology, the function of reconfigurable power division ratio is added. The power divider can be used in a one-to-four power division network, and realizes the feeding modes of 1to1, 1to2 (two modes), 1to3 (two modes) and 1to4 during the switching process of six modes. It can be used for multiple purposes, meet the beam scanning requirements, realize the diversified utilization of resources, and improve the user experience. On the other hand, the power divider architecture can adopt the different parameters of PIN diodes under forward bias and reverse bias, and cooperate with open-circuit matching stubs, so that the reconfigurable matching network and the isolation impedance switching network have good matching performance and high isolation degree. It can also effectively improve the conduction bandwidth, improve the link efficiency, and achieve the purpose of energy conservation and consumption reduction, saving costs.

[0101] The present disclosure has disclosed exemplary embodiments, and although specific terms are used, they are only used and should only be construed as general illustrative meanings and not for the purpose of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly stated. Accordingly, those skilled in the art will understand that various forms and details may be changed without departing from the scope of the present disclosure as set forth by the appended claims.

Claims

1. A mode-reconfigurable power division circuit, characterized in that: The power division circuit comprises: A first input branch, one end of which is an input port; a second input branch, wherein two ends of the second input branch are connected to the first input branch via a first control element and a second control element respectively; a first output branch, one end of which is connected to the other end of the first input branch, and the other end of which is a first output port; a second output branch, one end of which is connected to the other end of the first input branch, and the other end of which is a second output port; a third control element, one end of which is connected to the first input branch; and a fourth control element, one end of which is connected to the second output branch, When the first control element to the fourth control element are in the first state, the power division circuit operates in the first mode to form a unidirectional path from the input port to the first output port. When the first control element to the fourth control element are in the second state, the power division circuit operates in the second mode to form a bidirectional path from the input port to the first output port and the second output port respectively.

2. The power dividing circuit according to claim 1, characterized in that: One end of the first control element is connected to the first input branch, and the other end of the first control element is connected to one end of the second input branch. One end of the second control element is connected to the first input branch, and the other end of the second control element is connected to the other end of the second input branch. A control signal is applied to the other end of the first control element and the other end of the second control element via the second input branch, and the control signal is also applied to the other end of the third control element and the other end of the fourth control element. The first control element to the fourth control element are controlled by the control signal to be in the first state or the second state.

3. The power dividing circuit according to claim 1, characterized in that: The first input branch has a "J"-shaped structure and includes a first straight portion, a first bent portion, a second bent portion and a second straight portion connected in sequence. The second input branch has a linear structure and is located on the same straight line as the first straight portion and the second straight portion of the first input branch.

4. The power dividing circuit according to claim 3, characterized in that: The first control element is connected to the intersection of the first straight line portion and the first bent portion of the first input branch. The second control element is connected to the intersection of the second bent portion and the second straight portion of the first input branch, The third control element is connected to a junction between the first bending portion and the second bending portion of the first input branch.

5. The power dividing circuit according to claim 1, characterized in that: The second output branch has an “L”-shaped structure, and the fourth control element is connected to a bending point of the “L”-shaped structure of the second output branch.

6. The power dividing circuit according to claim 1, characterized in that: The first output branch has an "L"-shaped structure, the power division circuit further includes an open-circuit branch, and the open-circuit branch is connected to a bending point of the "L"-shaped structure of the first output branch.

7. The power dividing circuit according to claim 1, characterized in that: The power division circuit further includes a first matching element, wherein: The first matching element is connected to the first input branch via the third control element.

8. The power division circuit according to claim 1, characterized in that: The power division circuit further includes a second matching element, wherein: The second matching element is connected to the second output branch via the fourth control element.

9. The power dividing circuit according to any one of claims 1 to 8, characterized in that: The first to fourth control elements include one of the following: RF relays, ferrite circulators, GaAs FETs, varactor diodes, and PIN diodes.

10. A mode-reconfigurable power division circuit, characterized in that: The power division circuit comprises a first sub-circuit, a second sub-circuit and a third sub-circuit, wherein each of the first sub-circuit to the third sub-circuit comprises a power division circuit according to any one of claims 1 to 9, The input port of the first sub-circuit is the input port of the power division circuit, The input port of the second sub-circuit is connected to the first output port of the first sub-circuit, and the first output port and the second output port of the second sub-circuit are respectively the first output port and the second output port of the power divider circuit. The input port of the third sub-circuit is connected to the second output port of the first sub-circuit, and the first output port and the second output port of the third sub-circuit are the third output port and the fourth output port of the power divider circuit respectively. When the first control element to the fourth control element of the first sub-circuit and the second sub-circuit are in the first state, the power division circuit operates in the first mode to form a unidirectional path from the input port of the power division circuit to the first output port of the power division circuit. When the first control element to the fourth control element of the first subcircuit are in a first state, and the first control element to the fourth control element of the second subcircuit are in a second state, the power division circuit operates in a second mode, forming a bidirectional path from the input port of the power division circuit to the first output port and the second output port of the power division circuit respectively, When the first control element to the fourth control element of the first subcircuit are in the second state, and the first control element to the fourth control element of the second subcircuit and the third subcircuit are in the first state, the power division circuit operates in the third mode, forming a bidirectional path from the input port of the power division circuit to the first output port and the third output port of the power division circuit respectively, When the first control element to the fourth control element of the first subcircuit and the second subcircuit are in the second state, and the first control element to the fourth control element of the third subcircuit are in the first state, the power division circuit operates in the fourth mode, forming a three-way path from the input port of the power division circuit to the first output port to the third output port of the power division circuit respectively, When the first control element to the fourth control element of each of the first sub-circuit and the third sub-circuit are in the second state, and the first control element to the fourth control element of the second sub-circuit are in the first state, the power division circuit operates in the fifth mode, forming a three-way path from the input port of the power division circuit to the first output port, the third output port and the fourth output port of the power division circuit respectively, When the first control element to the fourth control element of the first sub-circuit to the third sub-circuit are respectively in the second state, the power division circuit operates in the sixth mode, forming a four-way path from the input port of the power division circuit to the first output port to the fourth output port of the power division circuit respectively.

11. A mode-reconfigurable power division circuit, characterized in that: The power division circuit includes a first-layer cascade circuit to an N-th-layer cascade circuit that are sequentially cascaded, wherein N is a positive integer, N>1, Among them, the nth layer cascade circuit includes 2 n-1 sub-circuits, n is a positive integer, 1≤n≤N, each sub-circuit of each layer of the cascade circuit comprises a power division circuit according to any one of claims 1 to 9, The input port of the sub-circuit of the first-level cascade circuit is the input port of the power division circuit. The first output port of the kth subcircuit of the mth cascade circuit is connected to the input port of the (2k-1)th subcircuit of the m+1th cascade circuit, and the second output port of the kth subcircuit of the mth cascade circuit is connected to the input port of the 2kth subcircuit of the m+1th cascade circuit, where m is a positive integer, 1≤m<N, and k is a positive integer, 1≤k≤2 m-1 , The first output port and the second output port of each sub-circuit of the N-th layer cascade circuit are respectively the first output port to the second output port of the power divider circuit. N Output port.

12. A mode reconfigurable power divider, characterized in that: The power divider includes a substrate and a power divider circuit printed on the substrate, wherein the power divider circuit includes the power divider circuit according to any one of claims 1 to 11.

13. An antenna feeding system, characterized in that: The antenna feeding system comprises the power divider according to claim 12.

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