Universal high-bandwidth power platform

Abstract

A general high-bandwidth power platform takes a DSP (Digital Signal Processor) and an FPGA (Field Programmable Gate Array) as processors, and can cope with wide-range bandwidth and single-group or multi-group power electronic topology application scenes through different combined application modes; meanwhile, a single-sampling and single-updating software architecture and a double-sampling and double-updating software architecture are provided, so that the current inner loop bandwidth is effectively improved on the basis of improving the PWM switching frequency, and the response characteristic of the system is improved; the method is suitable for single-power electronic topology or multi-power electronic topology scenes such as a servo platform, a power supply platform and power electronic converter grid connection.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and particularly to a general high-bandwidth power platform. Background Art

[0002] Existing power electronic converters are mainly designed based on three digital processors: ARM, DSP, and FPGA. Among them, the operating speed of FPGA is faster than that of DSP and ARM, but the cost is high and the development difficulty is great. Therefore, according to different requirements, for low-bandwidth applications such as low-frequency current sources and inverters, DSP and ARM are mostly used for data processing, with low cost and small development difficulty; for high-bandwidth applications such as high-precision servo motors, FPGA is used for control.

[0003] Since power electronic converters have differences in bandwidth, topology, and control strategies according to different functions and application scenarios, the power circuit has poor generality and weak expandability in hardware design and software architecture, and needs to be designed according to specific requirements, with a long R & D cycle and high labor cost;

[0004] At the same time, current power electronic converters are mostly designed with digital processors as the core. The bandwidth of the current inner loop directly affects the response ability of the system, and the inherent delay of digital processors will reduce the system bandwidth. Summary of the Invention

[0005] The present disclosure provides a control system for a general high-bandwidth power platform, which is applicable to power electronic converters under different performances and can handle wide-range bandwidths and single-group or multi-group power electronic topology application scenarios.

[0006] The general high-bandwidth power platform provided by the present disclosure mainly includes: DSP and FPGA processors,

[0007] Wherein:

[0008] When used as a high-bandwidth servo controller platform:

[0009] FPGA is used for current sampling, current loop calculation, SVPWM modulation, PWM output, and system hardware protection;

[0010] DSP is used for position signal sampling, position loop calculation, speed loop calculation, and host computer communication; When used as a high-frequency current source platform:

[0011] FPGA is used for current sampling, current loop calculation, SPWM modulation, PWM output, and system hardware protection;

[0012] DSP communicates with the host computer;

[0013] When used as a low-bandwidth platform:

[0014] The DSP completes current sampling, current loop calculation, hardware protection, and communication functions.

[0015] Furthermore:

[0016] The DSP is of Harvard architecture, where the data bus and instruction bus of the microprocessor are separated, and when executing instructions, instruction fetching and data fetching can be performed simultaneously;

[0017] The FPGA performs parallel processing in a pure hardware manner, without being limited by the number of processor cores.

[0018] Furthermore, the platform is selected to trigger sampling at the carrier start point or midpoint.

[0019] Furthermore, the platform reduces the system delay T d by increasing the PWM frequency and reducing the time interval between current sampling and PWM update to increase the current loop bandwidth frequency.

[0020] Furthermore, when the system bandwidth requirement is high, the platform adopts a double-sampling and double-update control mode, specifically including:

[0021] Trigger sampling at the start point of carrier T(k - 1), immediately perform loop calculation, update the PWM duty cycle at the midpoint between the start points of carrier T(k - 1) and T(k), and trigger the next round of sampling;

[0022] The delay time T d is 0.5 PWM cycles, i.e., T d = 0.5T s .

[0023] Furthermore, when the system bandwidth requirement is not high, a single-sampling and single-update method is adopted for control, specifically including:

[0024] Trigger sampling at the midpoint between the start points of carrier T(k - 1) and T(k), trigger the loop calculation program at time T(k), and update the PWM duty cycle at time T(k + 1);

[0025] The delay time T d is 1.5 PWM cycles, i.e., T d = 1.5T s ;

[0026] Trigger the next round of sampling at the midpoint between the start points of carrier T(K) and T(k + 1).

[0027] Furthermore, the platform also includes a current loop feedforward control and a speed loop feedforward control module to improve the response speed.

[0028] Compared with the prior art, the beneficial effects of the present disclosure are as follows: (1) It can serve as a general-purpose power platform, which can be compatible with low bandwidth and high bandwidth in terms of performance, and the hardware components and software architecture can be flexibly configured; (2) By analyzing the mathematical relationship between bandwidth and the inherent delay of hardware, and improving the system bandwidth through software design and hardware components, the system performance is enhanced; (3) When the system bandwidth requirement is low, DSP is used for data processing to simplify the software development process; (4) It is applicable to single power electronic topology or multi-power electronic topology scenarios such as servo platforms, power platforms, and grid connection of power electronic converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] By describing the exemplary embodiments of the present disclosure in more detail in conjunction with the accompanying drawings, the above and other objects, features, and advantages of the present disclosure will become more apparent. Among them, in the exemplary embodiments of the present disclosure, the same reference numerals generally represent the same components.

[0030] Figure 1 It is a block diagram of the inner loop of a servo motor;

[0031] Figure 2 It is a timing diagram of single sampling and single update;

[0032] Figure 3 It is a timing diagram of double sampling and double update;

[0033] Figure 4 It is a schematic diagram of the principle structure of an exemplary general high-bandwidth power platform according to the present disclosure;

[0034] Figure 5 It is an application scenario of the general high-bandwidth power platform for servo control;

[0035] Figure 6 It is an application scenario of the general high-bandwidth power platform for power output control;

[0036] Figure 7 It is an application scenario of the general high-bandwidth power platform for grid connection control of power electronic converters. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0038] The present disclosure provides a general high-bandwidth power platform control system, which is applicable to power electronic converters under different performances, and is a hardware combination structure composed of a DSP and an FPGA to cope with wide-range bandwidth and single-group or multi-group power electronic topology application scenarios.

[0039] In an exemplary embodiment, the composition principle structure diagram of the platform is as shown in the appendix Figure 4 as follows.

[0040] 1. Main components

[0041] The platform is designed with a DSP and an FPGA as processors, where:

[0042] The DSP has a Harvard architecture, and the data bus and instruction bus of the microprocessor are separated. When executing instructions, the instruction fetch and data fetch can be performed simultaneously, and the instruction execution efficiency of the DSP is higher and the speed is faster than that of the same type of von Neumann architecture microprocessor. Moreover, the rich on-chip resources of the DSP make it particularly suitable for digital control systems such as motors;

[0043] The FPGA performs parallel processing in a pure hardware manner, is not limited by the number of processor cores, and has a significantly higher computing speed than the DSP and ARM. In the design of digital systems, it has become a suitable solution to improve the controller performance and system flexibility and narrow the real-time gap between digital control technology and analog control.

[0044] 2. Universality

[0045] This general high-bandwidth power platform is applicable to various types of power electronic conversion devices. Both the DSP and the FPGA have functions of acquisition, protection, and PWM output, and can be used in combination or separately, where:

[0046] 1) When the system bandwidth requirement is high or two-stage / multi-stage conversion devices are adopted, the DSP and the FPGA are combined to process data to improve the system response ability.

[0047] 2) When the system bandwidth requirement is low, the DSP is used to process data to simplify the software development process.

[0048] For example:

[0049] When used as a high-bandwidth servo controller platform, the FPGA performs current acquisition, current loop calculation, SVPWM modulation, PWM output, and system hardware protection, and the DSP performs position signal sampling, position loop calculation, speed loop calculation, and host computer communication;

[0050] When used as a high-frequency current source platform, the FPGA performs current acquisition, current loop calculation, SPWM modulation, PWM output, and system hardware protection, and the DSP performs host computer communication;

[0051] When acting as a low-bandwidth platform, the DSP performs sampling, loop calculation, hardware protection, and communication functions.

[0052] Figure 5 、 Figure 6 、 Figure 7 For general high-bandwidth power platform application scenarios, including single power electronics topology or multi-power electronics topology scenarios such as servo platforms, power platforms, and grid connection of power electronic converters.

[0053] 3. Optimized design to improve system performance

[0054] In the general high-bandwidth power platform of this embodiment, by analyzing the mathematical relationship between bandwidth and the inherent delay of the hardware, and through software design and hardware composition, the system bandwidth is increased and the system performance is improved.

[0055] Taking a servo motor as an example, the current inner-loop block diagram is as Figure 1 shown. Among them, is the current-loop PI controller, is the hardware delay, is the load.

[0056] Current inner-loop open-loop transfer function:

[0057]

[0058] Design the current regulator correction according to the typical type-II system:

[0059]

[0060] Let Get the type-II system

[0061]

[0062] The current-loop closed-loop transfer function is

[0063]

[0064] The undamped natural oscillation angular frequency ω of this second-order system transfer function n is:

[0065]

[0066] Damping ratio Take ξ = 0.707.

[0067] Then the bandwidth frequency ω b is

[0068]

[0069] It can be seen from Equation (6) that the bandwidth frequency of the current inner loop is inversely proportional to the delay time T d and in practical applications, the current loop bandwidth frequency can be increased by reducing T d . In a digital control system, the delay time T d includes sampling delay, calculation delay, and PWM output delay.

[0070] Taking the servo control platform as an example for analysis, according to the SVPWM modulation principle, at the starting point and midpoint of the carrier wave, the states of the switching tubes are both zero vectors. At this time, the switching tubes do not act, the sampled current is less affected by switching noise, and the currents at the starting point and midpoint of the carrier wave are the average currents within the switching period. Therefore, sampling is triggered at the starting point or midpoint of the carrier wave.

[0071] Preferably, in this embodiment, the single-sampling single-update and double-sampling double-update software architectures switched according to control requirements are as follows:

[0072] (1) Single-sampling single-update

[0073] When the system bandwidth requirement is not high, the single-sampling single-update method is used for control, and the timing diagram is as Figure 2 shown.

[0074] Sampling is triggered at the midpoint between carrier wave T(k - 1) and T(k), and the loop calculation program is triggered at T(k). Then, the PWM duty cycle is updated at T(k + 1), and the delay time T d is 1.5 PWM periods, that is, T d = 1.5T s . It can be seen that the delay T d can be reduced by increasing the PWM frequency (reducing T s ), and by reducing the sampling and PWM update time intervals.

[0075] (2) Double-sampling double-update

[0076] When the system bandwidth requirement is high, the double-sampling double-update control mode is adopted, and the timing diagram is as Figure 3 shown.

[0077] Sampling is triggered at carrier wave T(k - 1), and then the loop calculation is performed immediately. The PWM duty cycle is updated at the midpoint between carrier wave T(k - 1) and T(k), and the next round of sampling is triggered. In the double-sampling double-update mode, the delay time T d is 0.5 PWM period, that is, T d = 0.5T s . On the basis of increasing the PWM switching frequency, the bandwidth of the current inner loop can be effectively increased, and the system response characteristics can be improved. The double-sampling double-update mode has higher requirements for the processor, and FPGA is used for sampling and loop calculation.

[0078] Preferably, while increasing the bandwidth frequency ωb, current loop feedforward control and speed loop feedforward control can also be added when necessary to improve the response speed.

[0079] In this embodiment, a combination of DSP and FPGA is adopted to cope with the hardware combination structure for wide-range bandwidth and single-group or multi-group power electronic topology application scenarios; a single-sampling single-update and double-sampling double-update software architecture that can be switched according to control requirements.

[0080] The above technical solutions are only exemplary embodiments of the present invention. For those skilled in the art, based on the application methods and principles disclosed in the present invention, it is very easy to make various types of improvements or deformations, not limited to the methods described in the above specific embodiments of the present invention. Therefore, the methods described above are only preferred and do not have a restrictive meaning.

Claims

1. A general high-bandwidth power platform, characterized in that: Including DSP and FPGA processors, in: When used as a high-bandwidth servo controller platform: FPGA performs current sampling, current loop calculation, SVPWM modulation, PWM output and system hardware protection; DSP performs position signal sampling, position loop calculation, speed loop calculation, and host computer communication; When used as a high frequency current source platform: FPGA performs current sampling, current loop calculation, SPWM modulation, PWM output and system hardware protection; DSP communicates with the host computer; When used as a low-bandwidth platform: The DSP completes the current sampling, current loop calculation, hardware protection and communication functions.

2. The platform according to claim 1, characterized in that: The DSP is a Harvard structure, the data bus and instruction bus of the microprocessor are separated, and when executing instructions, instruction fetching and data fetching can be performed simultaneously; FPGA performs parallel processing in a pure hardware manner and is not limited by the number of processor cores.

3. The platform according to claim 1 or 2, characterized in that: The platform selects to trigger sampling at the start point or midpoint of the carrier.

4. The platform according to claim 3, characterized in that: The platform reduces the system delay T by increasing the PWM frequency and reducing the time interval between current sampling and PWM update. d , to increase the current loop bandwidth frequency.

5. The platform according to claim 4, characterized in that When the system bandwidth requirement is high, the platform adopts a double sampling and double updating control mode, which specifically includes: The sampling is triggered at the starting point of the carrier T(k-1), and then the loop calculation is performed. The PWM duty cycle is updated at the midpoint between the starting point of the carrier T(k-1) and the starting point of T(k), and the next round of sampling is triggered. Delay time T d is 0.5 PWM period, that is, T d =0.5T s .

6. The platform according to claim 4, characterized in that When the system bandwidth requirement is not high, a single sampling and single updating method is used for control, including: Trigger sampling at the midpoint between the carrier T(k-1) starting point and T(k) starting point, trigger the loop calculation program at time T(k), and update the PWM duty cycle at time T(k+1); Delay time T d is 1.5 PWM cycles, that is, T d =1.5T s ; The next round of sampling is triggered at the midpoint between the starting point of the carrier T(K) and the starting point of T(k+1).

7. The platform according to claim 1, characterized in that It also includes current loop feedforward control and speed loop feedforward control modules to improve response speed.

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