Driving circuit of high-power switching power supply

Abstract

The invention provides a driving circuit of a high-power switching power supply, and the driving circuit comprises a voltage generation circuit which is used for generating a first reference voltage V1; the first driving module is used for generating a first driving signal according to the first reference voltage V1 and the voltage of the first input signal S1; the second driving module is used for generating a second driving signal according to the first driving module and the first reference voltage V1; the control end of the first driving switch tube M1 is connected with the first driving module, and the first driving switch tube M1 can be switched on or switched off based on the first driving signal; the control end of the second driving switch tube M2 is connected with the second driving module, and the second driving switch tube M2 can be switched on or switched off based on the second driving signal; wherein only one of the first driving switch tube M1 and the second driving switch tube M2 is set to be conducted, the voltage difference between the control end of the first driving switch tube M1 and the current output end is smaller than the power supply voltage VIN, and the voltage difference between the control end of the second driving switch tube M2 and the current input end is smaller than the power supply voltage VIN.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a driving circuit for a high-power switching power supply. Background Art

[0002] The switching power supply control chips in the prior art usually include a driving circuit for generating a driving signal to drive an external power switching transistor. In a high-power switching power supply, the operating voltage of the external power switching transistor is relatively high, so its driving signal also needs to have a corresponding high voltage level. This requires that the driving switching transistor used in the driving circuit has a high gate-source breakdown voltage capability matching it, that is, it needs to withstand the power supply voltage VIN, resulting in a relatively large volume and high cost of the driving switching transistor used. Summary of the Invention

[0003] The purpose of the present invention is to solve the problem that in the existing switching power supply control chips, the driving circuit has to use a high-voltage withstand driving switching transistor due to the need to output a high-voltage driving signal, resulting in a large volume and high cost of the device.

[0004] According to a first aspect of the present invention, there is provided a driving circuit for a high-power switching power supply, including: A voltage generating circuit, with its input terminal connected to the power supply voltage VIN, for generating a first reference voltage V1, and the first reference voltage V1 is less than the power supply voltage VIN; A first driving module, with its first terminal connected to the first reference voltage V1, its second terminal grounded, and its third terminal connected to a first input signal S1, for generating a first driving signal according to the voltages of the first reference voltage V1 and the first input signal S1; A second driving module, with its first terminal connected to the power supply voltage VIN, its second and third terminals both connected to the first driving module, and its fourth terminal connected to the first reference voltage V1, for generating a second driving signal according to the first driving module and the first reference voltage V1; A first driving switching transistor M1, with its control terminal connected to the first driving module, its current output terminal grounded, and configured to be turned on or off based on the first driving signal; A second driving switching transistor M2, with its current input terminal connected to the power supply voltage VIN, its current output terminal connected to the current input terminal of the first driving switching transistor M1, and its control terminal connected to the second driving module, and configured to be turned on or off based on the second driving signal; Among them, the output terminal OUT of the driving circuit of the high-power switching power supply is arranged between the first driving switch tube M1 and the second driving switch tube M2; the first driving switch tube M1 and the second driving switch tube M2 are set to be only one conducting, and the voltage difference between the control terminal of the first driving switch tube M1 and the current output terminal is less than the power supply voltage VIN, and the voltage difference between the control terminal of the second driving switch tube M2 and the current input terminal is less than the power supply voltage VIN.

[0005] In a possible implementation manner, the first driving module includes: A first inverter A1, the input terminal is used as the third terminal of the first driving module, the first voltage reference terminal of the first inverter A1 is used as the first terminal of the first driving module, and the second voltage reference terminal of the first inverter A1 is grounded; A second inverter A2, the input terminal is connected to the output terminal of the first inverter A1, the first voltage reference terminal of the second inverter A2 is connected to the first voltage reference terminal of the first inverter A1, and the second voltage reference terminal of the second inverter A2 is grounded; A third inverter A3, the input terminal is connected to the output terminal of the second inverter A2, the first voltage reference terminal of the third inverter A3 is connected to the first voltage reference terminal of the first inverter A1, the second voltage reference terminal of the third inverter A3 is grounded, and the output terminal is connected to the control terminal of the first driving switch tube M1.

[0006] In a possible implementation manner, the first driving module further includes: A third switch tube M3, the current input terminal is connected to the second driving module, the current output terminal is grounded, and the control terminal is connected to the output terminal of the second inverter A2; A fourth switch tube M4, the current input terminal is connected to the second driving module, the current output terminal is grounded, and the control terminal is connected to the output terminal of the third inverter A3.

[0007] In a possible implementation manner, the second driving module includes: A logic control unit, the first terminal of the logic control unit is used as the first terminal of the second driving module, the second terminal of the logic control unit is used as the second terminal of the second driving module, the third terminal of the logic control unit is used as the third terminal of the second driving module, the fourth terminal of the logic control unit is used as the fourth terminal of the second driving module, the second terminal of the logic control unit is connected to the current input terminal of the third switch tube M3, and the third terminal of the logic control unit is connected to the current input terminal of the fourth switch tube M4; An output unit, wherein the first input terminal and the second input terminal of the output unit are both connected to the logic control unit, and the output terminal of the output unit is connected to the control terminal of the second driving switch transistor M2.

[0008] In a possible implementation manner, the output unit includes: A first NAND gate A4, and the first input terminal of the first NAND gate A4 serves as the first input terminal of the output unit; A second NAND gate A5, the first input terminal of the second NAND gate A5 serves as the second input terminal of the output unit, the second input terminal of the second NAND gate A5 is connected to the first output terminal of the first NAND gate A4, and the output terminal of the second NAND gate A5 is connected to the second input terminal of the first NAND gate A4; A fourth inverter A6, the input terminal of the fourth inverter A6 is connected to the output terminal of the second NAND gate A5, and the output terminal of the fourth inverter A6 serves as the output terminal of the output unit.

[0009] In a possible implementation manner, the logic control unit includes a fifth switch transistor M5, a sixth switch transistor M6, a seventh switch transistor M7, and a fifth inverter A7; In the logic control unit, the power supply voltage VIN is sequentially connected to the current input terminal of the third switch transistor M3 through the fifth switch transistor M5 and the sixth switch transistor M6; the control terminal of the seventh switch transistor M7 is connected to the control terminal of the fifth switch transistor M5, the current input terminal of the seventh switch transistor M7 is connected to the current output terminal of the fifth switch transistor M5, and the current output terminal of the seventh switch transistor M7 is connected to the control terminal of the sixth switch transistor M6 and serves as the fourth terminal of the second driving module; The input terminal of the fifth inverter A7 is connected to the current output terminal of the fifth switch transistor M5, and the output terminal is connected to the first input terminal of the first NAND gate A4.

[0010] In a possible implementation manner, the logic control unit further includes an eighth switch transistor M8, a ninth switch transistor M9, a tenth switch transistor M10, and a sixth inverter A8; In the logic control unit, the power supply voltage VIN is sequentially connected to the current input terminal of the fourth switch transistor M4 through the eighth switch transistor M8 and the ninth switch transistor M9; the control terminal of the tenth switch transistor M10 is connected to the control terminal of the eighth switch transistor M8, the current input terminal of the tenth switch transistor M10 is connected to the current output terminal of the eighth switch transistor M8, the current output terminal of the tenth switch transistor M10 is connected to the control terminal of the ninth switch transistor M9, and the current output terminal of the tenth switch transistor M10 is further connected to the control terminal of the sixth switch transistor M6; The input terminal of the sixth inverter A8 is connected to the current output terminal of the eighth switch M8, and the output terminal is connected to the first input terminal of the second NAND gate A5.

[0011] In a possible implementation, the logic control unit further includes: A seventh inverter A9, the input terminal of the seventh inverter A9 is connected to the output terminal of the fifth inverter A7, and the output terminal of the seventh inverter A9 is connected to the control terminal of the eighth switch M8; An eighth inverter A10, the input terminal of the eighth inverter A10 is connected to the output terminal of the sixth inverter A8, and the output terminal of the eighth inverter A10 is connected to the control terminal of the fifth switch M5.

[0012] In a possible implementation, the first NAND gate A4, the second NAND gate A5, the fourth inverter A6, the fifth inverter A7, the sixth inverter A8, the seventh inverter A9, and the eighth inverter A10 are all connected to the power supply voltage VIN and the first reference voltage V1.

[0013] In a possible implementation, the voltage generation circuit includes a first resistor R1 and a second resistor R2; in the voltage generation circuit, the power supply voltage VIN is grounded through the first resistor R1 and the second resistor R2 in sequence; the first node A between the first resistor R1 and the second resistor R2 is connected to the first voltage reference terminal of the first inverter A1, and the first node A is connected to the first end of the first driving module and the fourth end of the second driving module, for outputting the first reference voltage V1 to the first driving module and the second driving module.

[0014] In a possible implementation, the resistance values of the first resistor R1 and the second resistor R2 are both less than or equal to 1 KΩ.

[0015] In a possible implementation, when the first driving switch M1 is turned on and the second driving switch M2 is turned off, the voltage difference between the control terminal and the current output terminal of the first driving switch M1 is the first reference voltage V1, and the voltage difference between the control terminal and the current input terminal of the second driving switch M2 is 0; In a possible implementation, when the first driving switch M1 is turned off and the second driving switch M2 is turned on, the voltage difference between the control terminal and the current output terminal of the first driving switch M1 is 0, and the voltage difference between the current input terminal and the control terminal of the second driving switch M2 is the difference between the power supply voltage VIN and the first reference voltage V1.

[0016] According to a second aspect of the present invention, a high-power switching power supply is provided, which includes a control chip and an external power circuit. The control chip includes the driving circuit of the high-power switching power supply as described above, and the external power circuit includes an external high-power switching transistor.

[0017] According to the solution of the present invention, a first reference voltage V1 lower than the power supply voltage VIN is generated by setting a voltage generation circuit. On this basis, a first driving module and a second driving module are designed, such that the voltage difference between the control terminal and the current output terminal of the first driving switching transistor M1 is less than the power supply voltage VIN, and the voltage difference between the control terminal and the current input terminal of the second driving switching transistor M2 is also less than the power supply voltage VIN. The technical solution of the present invention significantly reduces the withstand voltage requirements for the first driving switching transistor M1 and the second driving switching transistor M2. Therefore, switching transistors with lower withstand voltage values can be selected, thereby reducing the volume and cost of the device.

[0018] Furthermore, by designing the resistance values of the first resistor R1 and the second resistor R2 to be less than or equal to 1 KΩ, it is ensured that during the operation of the circuit, the current values flowing through the first resistor R1 and the second resistor R2 are much larger than the operating current of the driving module, ensuring that the current flowing through the first resistor R1 and the second resistor R2 remains almost unchanged. This design effectively ensures that the first reference voltage V1 remains stable throughout the entire operation process, avoiding the influence of voltage fluctuations on the circuit performance.

[0019] The driving circuit of the high-power switching power supply of the present invention can input a first input signal S1 with a relatively low voltage and output a driving signal OUT with a relatively high voltage, enabling the driving signal to smoothly drive the external high-power switching transistor, improving the reliability of the high-voltage driving signal and the power conversion efficiency.

[0020] In addition, by setting a control chip including the above driving circuit in the high-power switching power supply, not only is the size of the driving circuit effectively reduced, but also the design of the entire power supply system is optimized, thereby significantly reducing the volume and cost of the high-power switching power supply.

[0021] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly and implement it according to the content of the specification, the following provides a detailed description of the preferred embodiments of the present invention as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 The block diagram of the driving circuit of the high-power switching power supply according to an embodiment of the present invention is shown; Figure 2 The topological structure diagram of the driving circuit of the high-power switching power supply according to another embodiment of the present invention is shown; Figure 3 Shown according to an embodiment of the present inventionFigure 2 Voltage waveform diagram of some signals in the drive circuit; Figure 4 Shows the topology structure diagram of the drive circuit of a high-power switching power supply according to another embodiment of the present invention; Figure 5 Shows the structure block diagram of a high-power switching power supply according to an embodiment of the present invention. Detailed implementation manners

[0023] To make the above objects, features and advantages of the present invention more obvious and understandable, the following will describe the detailed implementation manners of the present invention in conjunction with the accompanying drawings. It can be understood that the specific embodiments described herein are only used to explain the present invention, rather than limiting the present invention. Additionally, it should be noted that for the sake of description, only the parts related to the present invention are shown in the accompanying drawings rather than all the structures. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0024] The terms "comprising" and "having" and any variations thereof in the present invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products or devices.

[0025] Referring to "embodiment" in this context means that a particular feature, structure or characteristic described in conjunction with the embodiment can be included in at least one embodiment of the present invention. The phrase appears at various positions in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0026] Figure 1 Shows the structure block diagram of the drive circuit of a high-power switching power supply according to an embodiment of the present invention. As Figure 1As shown, the drive circuit of the high-power switching power supply includes a voltage generation circuit 100, a first drive module 200, a second drive module 300, a first drive switch M1, and a second drive switch M2. The input end of the voltage generation circuit 100 is connected to the power supply voltage VIN, and is used to generate a first reference voltage V1, which is less than the power supply voltage VIN. The voltage generation circuit 100 is also grounded. The first end of the first drive module 200 is connected to the voltage generation circuit 100, the second end of the first drive module 200 is grounded, the third end of the first drive module 200 is connected to the first input signal S1, and the first drive module 200 is used to generate a first drive signal according to the voltages of the first reference voltage V1 and the first input signal S1. The first end of the second drive module 300 is connected to the power supply voltage VIN, the second and third ends of the second drive module 300 are both connected to the first drive module, and the fourth end of the second drive module 300 is connected to the first reference voltage V1. The second drive module 300 is used to generate a second drive signal according to the first reference voltage V1 and the first drive module 200. The control end of the first drive switch M1 is connected to the first drive module 200, and the current output end is grounded. The first drive switch M1 is configured to be turned on or off based on the first drive signal. The current input end of the second drive switch M2 is connected to the power supply voltage VIN, the current output end is connected to the current input end of the first drive switch M1, and the control end is connected to the second drive module 300. The second drive switch M2 is configured to be turned on or off based on the second drive signal. Among them, the output end OUT of the drive circuit of the high-power switching power supply is provided between the first drive switch M1 and the second drive switch M2. The first drive switch M1 and the second drive switch M2 are configured such that only one of them is turned on at the same time, and the voltage difference between the control end and the current output end of the first drive switch M1 is less than the power supply voltage VIN, and the voltage difference between the control end and the current input end of the second drive switch M2 is also less than the power supply voltage VIN.

[0027] According to the solution of the embodiment of the present invention, by setting the voltage generation circuit to generate the first reference voltage V1 lower than the power supply voltage VIN, and on this basis, designing the first drive module and the second drive module, the voltage difference between the control end and the current output end of the first drive switch M1 is less than the power supply voltage VIN, and the voltage difference between the control end and the current input end of the second drive switch M2 is also less than the power supply voltage VIN. The technical solution of the present invention significantly reduces the withstand voltage requirements for the first drive switch M1 and the second drive switch M2. Therefore, switches with lower withstand voltage values can be selected, thereby reducing the volume and cost of the device.

[0028] It should be noted that in traditional high-power switching power supply drive circuits, since external power switching transistors need to withstand relatively high voltages, for a long time, those skilled in the art usually use drive switching transistors with higher breakdown voltages to ensure the output of high-reliability high-voltage drive signals. Against this background, a technical prejudice has gradually formed, that is, it is considered that drive switching transistors with high breakdown voltages must be used. However, the high-power switching power supply drive circuit proposed in this application generates a first reference voltage V1 lower than the power supply voltage VIN by setting a voltage generation circuit 100, and constructs a drive module based on this first reference voltage V1, enabling the first drive module 200 and the second drive module 300 to cooperate with each other with the participation of the first reference voltage V1, respectively controlling the on and off states of the first drive switching transistor M1 and the second drive switching transistor M2, so that the voltage difference between the control terminal and the current terminal of the first drive switching transistor M1 and the second drive switching transistor M2 is less than the power supply voltage VIN. Then, the drive module can select drive switching transistors with low breakdown voltages to work. Through the above collaborative working mechanism, while ensuring the output of high-reliability high-voltage drive signals, the drive circuit does not need to rely on high-breakdown-voltage drive switching devices, breaking the technical prejudice of the traditional design's dependence on high-breakdown-voltage drive devices, and achieving the optimization of the drive circuit structure and the reduction of system costs.

[0029] Figure 2 Fig. shows a topology structure diagram of a drive circuit of a high-power switching power supply according to another embodiment of the present invention. As Figure 2 shown, the first drive module 200 includes a first inverter A1, a second inverter A2, and a third inverter A3. The input terminal of the first inverter A1 serves as the third terminal of the first drive module 200, the first voltage reference terminal of the first inverter A1 serves as the first terminal of the first drive module 200, and the second voltage reference terminal of the first inverter A1 is grounded. The input terminal of the second inverter A2 is connected to the output terminal of the first inverter A1, the first voltage reference terminal of the second inverter A2 is connected to the first voltage reference terminal of the first inverter A1, and the second voltage reference terminal of the second inverter A2 is grounded. The input terminal of the third inverter A3 is connected to the output terminal of the second inverter A2, the first voltage reference terminal of the third inverter A3 is connected to the first voltage reference terminal of the first inverter A1, the second voltage reference terminal of the third inverter A3 is grounded, and the output terminal of the third inverter A3 is connected to the control terminal of the first drive switching transistor M1.

[0030] In this embodiment, the working principle of the first driving module 200 is as follows: After the circuit is powered on, the power supply voltage VIN is input to the voltage generating circuit 100, and the voltage generating circuit 100 outputs the first reference voltage V1. The first reference voltage V1 is input to the first driving module 200 and serves as the high reference voltage of the first inverter A1, the second inverter A2, and the third inverter A3 of the first driving module 200. In addition, the low reference voltage of the first inverter A1, the second inverter A2, and the third inverter A3 is the ground voltage. The input terminal of the first inverter A1 is connected to the third terminal of the first driving module 200 as the first input signal S1. When the voltage of the first input signal S1 is low, the first inverter A1 outputs a high level, so that the second inverter A2 outputs a low level and the third inverter A3 outputs a high level. At this time, the first driving switch M1 is turned on. When the voltage of the first input signal S1 is high, the first inverter A1 outputs a low level, so that the second inverter A2 outputs a high level and the third inverter A3 outputs a low level. At this time, the first driving switch M1 is turned off.

[0031] In one embodiment, when the voltage of the first input signal S1 is lower than it is a low level, preferably the ground voltage. When the voltage of the first input signal S1 is higher than it is a high level, preferably the first reference voltage V1.

[0032] In one embodiment, referring to Figure 2 the first driving module 200 further includes a third switch M3 and a fourth switch M4. The current input terminal of the third switch M3 is connected to the second driving module 300, the current output terminal is grounded, and the control terminal is connected to the output terminal of the second inverter A2. The current input terminal of the fourth switch M4 is connected to the second driving module 300, the current output terminal is grounded, and the control terminal is connected to the output terminal of the third inverter A3.

[0033] In this embodiment, according to the above embodiment, when the voltage of the first input signal S1 is low, the third inverter A3 outputs a high level. Therefore, the third switch M3 is turned off and the fourth switch M4 is turned on. When the voltage of the first input signal S1 is high, the third inverter A3 outputs a low level. Therefore, the third switch M3 is turned on and the fourth switch M4 is turned off.

[0034] In one embodiment, referring to Figure 2, the second driving module 300 includes a logic control unit 310 and an output unit 320. The first end of the logic control unit 310 serves as the first end of the second driving module 300, the second end of the logic control unit 310 serves as the second end of the second driving module 300, the third end of the logic control unit 310 serves as the third end of the second driving module 300, the fourth end of the logic control unit 310 serves as the fourth end of the second driving module 300. The second end of the logic control unit 310 is connected to the current input end of the third switching transistor M3, and the third end of the logic control unit 310 is connected to the current input end of the fourth switching transistor M4. The first input end and the second input end of the output unit 320 are both connected to the logic control unit 310, and the output end of the output unit 320 is connected to the control end of the second driving switching transistor M2.

[0035] In one embodiment, referring to Figure 2 , the output unit 320 includes a first NAND gate A4, a second NAND gate A5, and a fourth inverter A6. The first input end of the first NAND gate A4 serves as the first input end of the output unit 320. The first input end of the second NAND gate A5 serves as the second input end of the output unit 320. The second input end of the second NAND gate A5 is connected to the output end of the first NAND gate A4, and the output end of the second NAND gate A5 is connected to the second input end of the first NAND gate A4. The input end of the fourth inverter A6 is connected to the output end of the second NAND gate A5, and the output end of the fourth inverter A6 serves as the output end of the output unit 320.

[0036] In one embodiment, the logic control unit 310 includes a fifth switching transistor M5, a sixth switching transistor M6, a seventh switching transistor M7, and a fifth inverter A7. In the logic control unit 310, the power supply voltage VIN is sequentially connected to the current input end of the third switching transistor M3 through the fifth switching transistor M5 and the sixth switching transistor M6. The control end of the seventh switching transistor M7 is connected to the control end of the fifth switching transistor M5. The current input end of the seventh switching transistor M7 is connected to the current output end of the fifth switching transistor M5. The current output end of the seventh switching transistor M7 is connected to the control end of the sixth switching transistor M6 and serves as the fourth end of the second driving module 300. The input end of the fifth inverter A7 is connected to the current output end of the fifth switching transistor M5, and the output end is connected to the first input end of the first NAND gate A4.

[0037] In one embodiment, the logic control unit 310 further includes an eighth switching transistor M8, a ninth switching transistor M9, a tenth switching transistor M10, and a sixth inverter A8. In this logic control unit 310, the power supply voltage VIN is sequentially connected to the current input terminal of the fourth switching transistor M4 through the eighth switching transistor M8 and the ninth switching transistor M9. The control terminal of the tenth switching transistor M10 is connected to the control terminal of the eighth switching transistor M8. The current input terminal of the tenth switching transistor M10 is connected to the current output terminal of the eighth switching transistor M8. The current output terminal of the tenth switching transistor M10 is connected to the control terminal of the ninth switching transistor M9. The current output terminal of the tenth switching transistor M10 is also connected to the control terminal of the sixth switching transistor M6. The input terminal of the sixth inverter A8 is connected to the current output terminal of the eighth switching transistor M8, and the output terminal is connected to the first input terminal of the second NAND gate A5.

[0038] In one embodiment, the logic control unit 310 further includes a seventh inverter A9 and an eighth inverter A10. The input terminal of the seventh inverter A9 is connected to the output terminal of the fifth inverter A7, and the output terminal of the seventh inverter A9 is connected to the control terminal of the eighth switching transistor M8. The input terminal of the eighth inverter A10 is connected to the output terminal of the sixth inverter A8, and the output terminal of the eighth inverter A10 is connected to the control terminal of the fifth switching transistor M5.

[0039] In one embodiment, the first NAND gate A4, the second NAND gate A5, the fourth inverter A6, the fifth inverter A7, the sixth inverter A8, the seventh inverter A9, and the eighth inverter A10 are all connected to the power supply voltage VIN and the first reference voltage V1. The high reference voltage of the first NAND gate A4, the second NAND gate A5, the fourth inverter A6, the fifth inverter A7, the sixth inverter A8, the seventh inverter A9, and the eighth inverter A10 is the power supply voltage VIN, and the low reference voltage is the first reference voltage V1.

[0040] In one embodiment, the sixth switching transistor M6 and the ninth switching transistor M9 are preferably PMOS switching transistors.

[0041] In the above embodiments, the working principle of the drive circuit of the high-power switching power supply is as follows: The control terminals of the sixth switching transistor M6 and the ninth switching transistor M9 are connected to the first reference voltage V1. When the power supply voltage VIN is connected to the current input terminal, this first reference voltage V1 is the low reference voltage for the sixth switching transistor M6 and the ninth switching transistor M9. As analyzed from the above embodiments, when the voltage of the first input signal S1 is at a low level, the third switching transistor M3 is turned off and the fourth switching transistor M4 is turned on. At this time, the voltage at the current output terminal of the ninth switching transistor M9 is pulled down, and the ninth switching transistor M9 operates in the saturation region. A current flowing from the current input terminal to the current output terminal is generated in the sixth switching transistor M9. Therefore, the voltage at the current input terminal of the ninth switching transistor M9 is pulled down. Also, since the control terminal voltage of the ninth switching transistor M9 is the first reference voltage V1, the voltage at the current input terminal of the ninth switching transistor M9 is clamped at VGS9 + V1, where VGS9 is the voltage difference between the control terminal and the current input terminal of the ninth switching transistor M9. Since the third switching transistor M3 is in the off state, the sixth switching transistor M6 is also in the off state. Also, because the voltage difference VGS9 between the control terminal and the current input terminal of the ninth switching transistor M9 is less than the switching threshold voltage of the sixth inverter A8 (preferably ), for the sixth inverter A8, the voltage at the current input terminal of the ninth switching transistor M9 is at a low level. At this time, the sixth inverter A8 outputs a high level, then the eighth inverter A10 outputs a low level, causing the fifth switching transistor M5 to turn on and the seventh switching transistor M7 to turn off. At this time, the input terminal voltage of the fifth inverter A7 is pulled up through the fifth switching transistor M5. The fifth inverter A7 outputs a low level, then the seventh inverter A9 outputs a high level, causing the eighth switching transistor M8 to turn off and the tenth switching transistor M10 to turn on, ensuring that the input terminal voltage of the sixth inverter A8 is at a low level and the sixth inverter A8 outputs a high level. At this time, the first input terminal of the first NAND gate A4 is connected to the output terminal of the fifth inverter A7. Also, since the fifth inverter A7 outputs a low level, the first NAND gate A4 must output a high level to the second input terminal of the second NAND gate A5. Also, because the first input terminal of the second NAND gate A5 is connected to the output terminal of the sixth inverter A8, the voltage at the first input terminal of the second NAND gate A5 is at a high level. Therefore, both input terminals of the second NAND gate A5 are at high levels, and the second NAND gate A5 outputs a low level. The fourth inverter A6 outputs a high level, causing the second drive switching transistor M2 to turn off.

[0042] According to the above analysis, when the first input signal S1 is at a low level, the first driving switch transistor M1 is turned on and the second driving switch transistor M2 is turned off. Then, the driving voltage OUT output by the driving circuit of the high-power switching power supply is pulled to the ground voltage through the first driving switch transistor M1. At this time, since the high reference voltage of the third inverter A3 is the first reference voltage V1, when the first driving switch transistor M1 is turned on, the control terminal voltage is the first reference voltage V1. Then, the voltage difference between the control terminal and the current output terminal of the first driving switch transistor M1 is the first reference voltage V1. Also, since the high reference voltage of the fourth inverter A6 is the power supply voltage VIN, when the second driving switch transistor M2 is turned off, its control terminal voltage is the power supply voltage VIN. Then, the voltage difference between the control terminal and the current input terminal of the second driving switch transistor M2 is 0. To sum up, when the first input signal S1 is at a low level, the voltage differences between the control terminals and the current output terminals of the first driving switch transistor M1 and the second driving switch transistor M2 are both much smaller than the power supply voltage VIN, thereby effectively reducing the withstand voltage requirements of the first driving switch transistor M1 and the second driving switch transistor M2 and reducing their volume and cost.

[0043] When the voltage of the first input signal S1 is at a high level, the third switch transistor M3 is turned on and the fourth switch transistor M4 is turned off. At this time, the voltage at the current output terminal of the sixth switch transistor M6 is pulled down. And the sixth switch transistor M6 operates in the saturation region, and a current flowing from the current input terminal to the current output terminal is generated in the sixth switch transistor M6. Therefore, the voltage at the current input terminal of the sixth switch transistor M6 is pulled down. Also, since the control terminal voltage of the sixth switch transistor M6 is the first reference voltage V1, the voltage at the current input terminal of the sixth switch transistor M6 is clamped at VGS6 + V1, where VGS6 is the voltage difference between the control terminal and the current input terminal of the sixth switch transistor M6. Since the fourth switch transistor M4 is in the off state, the ninth switch transistor M9 is also in the off state. Also, because the voltage difference VGS6 between the control terminal and the current input terminal of the sixth switch transistor M6 is less than the switching threshold voltage of the fifth inverter A7 (preferably ), for the fifth inverter A7, the voltage at the current input terminal of the sixth switch transistor M6 is at a low level. At this time, the fifth inverter A7 outputs a high level, then the seventh inverter A9 outputs a low level, making the eighth switch transistor M8 turned on and the tenth switch transistor M10 turned off. At this time, the voltage at the input terminal of the sixth inverter A8 is pulled up through the eighth switch transistor M8, the sixth inverter A8 outputs a low level, then the voltage at the first input terminal of the second NAND gate A5 is at a low level, and the second NAND gate A5 must output a high level. Therefore, the fourth inverter A6 outputs a low level, making the second driving switch transistor M2 turned on; at the same time, the eighth inverter A10 outputs a high level, making the seventh switch transistor M7 turned on to ensure that the voltage at the input terminal of the fifth inverter A7 is at a low level.

[0044] According to the above analysis, when the first input signal S1 is at a high level, the first drive switch M1 is turned off and the second drive switch M2 is turned on. Then, the drive voltage OUT output by the drive circuit of the high-power switch power supply is pulled to the power supply voltage VIN through the second drive switch M2. At this time, since the low reference voltage of the fourth inverter A6 is the first reference voltage V1, when the second drive switch M2 is turned on, the control terminal voltage is the first reference voltage V1. Then, the voltage difference between the current input terminal and the control terminal of the second drive switch M2 is VIN - V1. Also, since the low reference voltage of the third inverter A3 is the ground voltage, when the first drive switch M1 is turned off, its control terminal voltage is the ground voltage. Then, the voltage difference between the control terminal and the current output terminal of the first drive switch M1 is 0. To sum up, when the first input signal S1 is at a high level, the voltage differences between the control terminal and the current output terminal of the first drive switch M1 and between the control terminal and the current input terminal of the second drive switch M2 are both much smaller than the power supply voltage VIN, effectively reducing the withstand voltage requirements of the first drive switch M1 and the second drive switch M2 and decreasing their volume and cost.

[0045] According to the above analysis, when the first input signal S1 is at a low level, the gate-source voltage difference of the first drive switch M1 is V1, and the gate-source voltage difference of the second drive switch M2 is 0; when the first input signal S1 is at a high level, the gate-source voltage difference of the first drive switch M1 is 0, and the gate-source voltage difference of the second drive switch M2 is VIN - V1. It should be noted that in actual circuit applications, due to factors such as device process differences, power supply ripple, and circuit parasitic parameters, the values of the gate-source voltage differences of the first drive switch M1 and the second drive switch M2 may deviate to a certain extent. Therefore, they should be understood as approximate values rather than strictly constant ideal values.

[0046] Figure 3 shows according to an embodiment of the present invention Figure 2 voltage waveform diagrams of some signals in the drive circuit of. As Figure 3 shown, the drive circuit of the high-power switch power supply of the present invention can input a relatively low-voltage first input signal S1 and output a relatively high-voltage drive signal OUT, enabling the drive signal OUT to successfully drive an external high-power switch tube and improving the reliability and power conversion efficiency of the high-voltage drive signal.

[0047] Figure 4 shows the topology structure diagram of the drive circuit of the high-power switch power supply according to another embodiment of the present invention. As Figure 4As shown, the voltage generation circuit 100 includes a first resistor R1 and a second resistor R2. In the voltage generation circuit 100, the power supply voltage VIN is grounded successively through the first resistor R1 and the second resistor R2. The first node A between the first resistor R1 and the second resistor R2 is connected to the first voltage reference terminal of the first inverter A1, the second inverter A2, and the third inverter A3. The first node A is also connected to the control terminal of the sixth switch tube M6 and the current output terminal of the seventh switch tube M7. The first node A is also connected to the control terminal of the ninth switch tube M9 and the current output terminal of the tenth switch tube M10. The first node A is also connected to the second voltage reference terminal of the first NAND gate A4, the second NAND gate A5, the fourth inverter A6, the fifth inverter A7, the sixth inverter A8, the seventh inverter A9, and the eighth inverter A10, for outputting a first reference voltage V1 to the first inverter A1, the second inverter A2, the third inverter A3, the fourth inverter A6, the fifth inverter A7, the sixth inverter A8, the seventh inverter A9, the eighth inverter A10, the first NAND gate A4, the second NAND gate A5, the sixth switch tube M6, the seventh switch tube M7, the ninth switch tube M9, and the tenth switch tube M10. In this embodiment, the power supply voltage VIN is divided by the first resistor R1 and the second resistor R2 to obtain the first reference voltage V1, where the voltage at the connection point of the first resistor R1 and the second resistor R2, i.e., point A, is the first reference voltage V1.

[0048] In one embodiment, the resistance values of the first resistor R1 and the second resistor R2 are both less than or equal to 1 KΩ. At this time, the voltage-dividing current formed by the series connection of the first resistor R1 and the second resistor R2 is at least while the static current and the current during steady-state operation of the first driving module 200 and the second driving module 300 are both much less than so that it can be ensured that whether the first driving module 200 and the second driving module 300 are operating or not, the current flowing through the first resistor R1 and the second resistor R2 is almost unchanged, thereby ensuring that the first reference voltage V1 is always a fixed value.

[0049] Figure 5 The structural block diagram of a high-power switching power supply according to an embodiment of the present invention is shown. Refer to Figure 5 This high-power switching power supply includes a control chip and an external power circuit. The control chip includes the driving circuit of the high-power switching power supply as described above. The external power circuit includes an external high-power switch tube. By providing a control chip including the above driving circuit in the high-power switching power supply, not only the size of the driving circuit is effectively reduced, but also the design of the entire power supply system is optimized, thereby significantly reducing the volume and cost of the high-power switching power supply.

[0050] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as falling within the scope described in this specification.

[0051] The above-described embodiments merely represent several implementation manners of the present invention. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the invention patent should be subject to the appended claims.

Claims

1. A driving circuit for a high-power switching power supply, characterized in that Comprising: A voltage generation circuit, with its input terminal connected to the power supply voltage VIN, for generating a first reference voltage V1, where the first reference voltage V1 is less than the power supply voltage VIN; A first driving module, with its first terminal connected to the first reference voltage V1, its second terminal grounded, and its third terminal connected to a first input signal S1, for generating a first driving signal according to the voltages of the first reference voltage V1 and the first input signal S1; A second driving module, with its first terminal connected to the power supply voltage VIN, its second and third terminals both connected to the first driving module, and its fourth terminal connected to the first reference voltage V1, for generating a second driving signal according to the first driving module and the first reference voltage V1; A first driving switch transistor M1, with its control terminal connected to the first driving module, its current output terminal grounded, and configured to be turned on or off based on the first driving signal; A second driving switch transistor M2, with its current input terminal connected to the power supply voltage VIN, its current output terminal connected to the current input terminal of the first driving switch transistor M1, and its control terminal connected to the second driving module, and configured to be turned on or off based on the second driving signal; Wherein, the output terminal OUT of the driving circuit of the high-power switching power supply is arranged between the first driving switch transistor M1 and the second driving switch transistor M2; the first driving switch transistor M1 and the second driving switch transistor M2 are configured such that only one of them is turned on, and the voltage difference between the control terminal and the current output terminal of the first driving switch transistor M1 is less than the power supply voltage VIN, and the voltage difference between the control terminal and the current input terminal of the second driving switch transistor M2 is less than the power supply voltage VIN.

2. The drive circuit according to claim 1, wherein The first driving module includes: A first inverter A1, with its input terminal serving as the third terminal of the first driving module, its first voltage reference terminal serving as the first terminal of the first driving module, and its second voltage reference terminal grounded; A second inverter A2, with its input terminal connected to the output terminal of the first inverter A1, its first voltage reference terminal connected to the first voltage reference terminal of the first inverter A1, and its second voltage reference terminal grounded; A third inverter A3, with its input terminal connected to the output terminal of the second inverter A2, its first voltage reference terminal connected to the first voltage reference terminal of the first inverter A1, its second voltage reference terminal grounded, and its output terminal connected to the control terminal of the first driving switch transistor M1.

3. The drive circuit according to claim 2, characterized in that The first driving module further includes: A third switch transistor M3, with its current input terminal connected to the second driving module, its current output terminal grounded, and its control terminal connected to the output terminal of the second inverter A2; A fourth switch transistor M4, with its current input terminal connected to the second driving module, its current output terminal grounded, and its control terminal connected to the output terminal of the third inverter A3.

4. The drive circuit according to claim 3, wherein The second driving module includes: A logic control unit, with the first end of the logic control unit serving as the first end of the second driving module, the second end of the logic control unit serving as the second end of the second driving module, the third end of the logic control unit serving as the third end of the second driving module, the fourth end of the logic control unit serving as the fourth end of the second driving module, the second end of the logic control unit being connected to the current input end of the third switching transistor M3, and the third end of the logic control unit being connected to the current input end of the fourth switching transistor M4; An output unit, with the first input end and the second input end of the output unit both connected to the logic control unit, and the output end of the output unit being connected to the control end of the second driving switching transistor M2.

5. The drive circuit according to claim 4, wherein The output unit includes: A first NAND gate A4, with the first input end of the first NAND gate A4 serving as the first input end of the output unit; A second NAND gate A5, with the first input end of the second NAND gate A5 serving as the second input end of the output unit, the second input end of the second NAND gate A5 being connected to the output end of the first NAND gate A4, and the output end of the second NAND gate A5 being connected to the second input end of the first NAND gate A4; A fourth inverter A6, with the input end of the fourth inverter A6 being connected to the output end of the second NAND gate A5, and the output end of the fourth inverter A6 serving as the output end of the output unit.

6. The drive circuit according to claim 5, characterized in that, The logic control unit includes a fifth switching transistor M5, a sixth switching transistor M6, a seventh switching transistor M7, and a fifth inverter A7; In the logic control unit, the power supply voltage VIN is sequentially connected to the current input end of the third switching transistor M3 through the fifth switching transistor M5 and the sixth switching transistor M6; the control end of the seventh switching transistor M7 is connected to the control end of the fifth switching transistor M5, the current input end of the seventh switching transistor M7 is connected to the current output end of the fifth switching transistor M5, and the current output end of the seventh switching transistor M7 is connected to the control end of the sixth switching transistor M6 and serves as the fourth end of the second driving module; The input end of the fifth inverter A7 is connected to the current output end of the fifth switching transistor M5, and the output end is connected to the first input end of the first NAND gate A4.

7. The drive circuit according to claim 6, characterized in that, The logic control unit further includes an eighth switching transistor M8, a ninth switching transistor M9, a tenth switching transistor M10, and a sixth inverter A8; In the logic control unit, the power supply voltage VIN is sequentially connected to the current input end of the fourth switching transistor M4 through the eighth switching transistor M8 and the ninth switching transistor M9; the control end of the tenth switching transistor M10 is connected to the control end of the eighth switching transistor M8, the current input end of the tenth switching transistor M10 is connected to the current output end of the eighth switching transistor M8, the current output end of the tenth switching transistor M10 is connected to the control end of the ninth switching transistor M9, and the current output end of the tenth switching transistor M10 is further connected to the control end of the sixth switching transistor M6; The input end of the sixth inverter A8 is connected to the current output end of the eighth switching transistor M8, and the output end is connected to the first input end of the second NAND gate A5.

8. The drive circuit according to claim 7, characterized in that, The logic control unit further includes: A seventh inverter A9, an input end of the seventh inverter A9 is connected to an output end of the fifth inverter A7, and an output end of the seventh inverter A9 is connected to a control end of the eighth switching transistor M8; An eighth inverter A10, an input end of the eighth inverter A10 is connected to an output end of the sixth inverter A8, and an output end of the eighth inverter A10 is connected to a control end of the fifth switching transistor M5.

9. The drive circuit according to claim 8, wherein A first voltage reference end and a second voltage reference end of the first NAND gate A4, the second NAND gate A5, the fourth inverter A6, the fifth inverter A7, the sixth inverter A8, the seventh inverter A9 and the eighth inverter A10 are respectively connected to the power supply voltage VIN and the first reference voltage V1.

10. The drive circuit according to claim 1, wherein The voltage generation circuit includes a first resistor R1 and a second resistor R2; in the voltage generation circuit, the power supply voltage VIN is grounded through the first resistor R1 and the second resistor R2 in sequence; a first node A between the first resistor R1 and the second resistor R2 is connected to a first end of the first driving module and a fourth end of the second driving module, and is configured to output the first reference voltage V1 to the first driving module and the second driving module.

11. The drive circuit according to claim 10, wherein Resistance values of the first resistor R1 and the second resistor R2 are both less than or equal to 1 KΩ.

12. The drive circuit according to any one of claims 1-11, characterized in that, When the first driving switching transistor M1 is turned on and the second driving switching transistor M2 is turned off, a voltage difference between a control end and a current output end of the first driving switching transistor M1 is the first reference voltage V1, and a voltage difference between a control end and a current input end of the second driving switching transistor M2 is 0.

13. The drive circuit according to any one of claims 1-11, characterized in that, When the first driving switching transistor M1 is turned off and the second driving switching transistor M2 is turned on, a voltage difference between a control end and a current output end of the first driving switching transistor M1 is 0, and a voltage difference between a current input end and a control end of the second driving switching transistor M2 is a difference between the power supply voltage VIN and the first reference voltage V1.

14. A high-power switching power supply, comprising a control chip and an external power circuit, the control chip includes a driving circuit of the high-power switching power supply according to any one of claims 1-13, and the external power circuit includes an external high-power switching transistor.

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