A multiple pulse signal generating circuit and implementation method
By designing a multi-pulse signal generation circuit, the problems of insufficient dynamic control and timing adjustment of pulse generation in the existing technology are solved, and the continuous adjustability of the memristor resistance state and efficient calculation are realized.
Patent Information
- Application Number
- CN202510303040.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-14
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2045-03-14
AI Technical Summary
Existing pulse generation technology cannot dynamically generate multiple pulses, has insufficient timing adjustment accuracy, and cannot monitor changes in input signals in real time, resulting in a lack of flexibility in updating the memristor resistance state and low computational efficiency.
A multi-pulse signal generation circuit was designed, including an input signal edge detection module, a pulse trigger judgment module, and a multi-pulse signal generation module. The dynamic generation and real-time monitoring of pulse signals are realized through a watchdog circuit and a delay circuit, and the continuous adjustable state of the memristor resistor is supported.
It achieves continuous adjustment of the memristor resistance state, improves computational efficiency and timing adjustment accuracy, reduces power consumption, and adapts to the needs of different neuromorphic devices.
Smart Images
Figure CN120223019B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit technology, and in particular to a multi-pulse signal generation circuit. Background Technology
[0002] Memristors, based on their continuously adjustable resistance under continuous pulse signals, can be used as neuromorphic devices to simulate the weight changes of biological synapses, making them a core component for realizing in-memory computing architectures. In existing technologies, pulse signal generation circuits used to provide continuous pulse signals to memristors are typically based on fixed periods or single pulse patterns, which have limitations in meeting the timing accuracy and dynamic control requirements of neuromorphic devices. The main drawbacks of existing pulse generation technologies include:
[0003] 1. Lack of dynamic control capability: Existing circuits cannot dynamically generate multiple pulses based on the input signal state, resulting in a lack of flexibility in updating the memristor resistance state, which limits the computing efficiency of in-memory computing.
[0004] 2. Insufficient timing adjustment precision: A single pulse signal is difficult to achieve fine adjustment of the state of multiple resistance levels, and the fixed period pulse interval cannot adapt to the dynamic needs of complex neuromorphic networks.
[0005] 3. Lack of real-time monitoring function: The existing circuit cannot adjust the pulse generation strategy according to the real-time changes of the input signal, resulting in increased energy consumption and calculation delay. Summary of the Invention
[0006] The purpose of this invention is to provide a multi-pulse signal generation circuit and implementation method, which controls the generation of multiple pulse signals to achieve continuous adjustment of the memristor resistance state.
[0007] To achieve the above objectives, the present invention provides the following solution:
[0008] A multi-pulse signal generation circuit includes: an input signal edge detection module, a pulse trigger judgment module, and a multi-pulse signal generation module;
[0009] The input signal edge detection module detects the falling edge of the external input signal and outputs a pulse signal D to the input terminal of the pulse trigger judgment module. The output terminal of the pulse trigger judgment module outputs a pulse signal C to the multiple pulse signal generation module. When the pulse signal C switches from high level to low level, the OUT_1 terminal of the multiple pulse signal generation module outputs a single pulse high-level signal, and the OUT_2 terminal outputs a continuous pulse high-level signal.
[0010] Optionally, the input signal edge detection module includes a first falling edge detection circuit, a second falling edge detection circuit, a first inverter, and a first OR gate;
[0011] The external input signal is input to the input terminal of the first falling edge detection circuit, and the output terminal of the first falling edge detection circuit is connected to the input terminal of the first OR gate.
[0012] The external input signal is input to the input terminal of the first inverter, the output terminal of the first inverter is connected to the input terminal of the second falling edge detection circuit, the output terminal of the first falling edge detection circuit is connected to the input terminal of the first OR gate, and the output terminal of the first OR gate outputs the pulse signal D.
[0013] Optionally, the pulse triggering judgment module includes a watchdog circuit, an SR latch, a first delay circuit, a NAND gate, a second inverter, a third inverter, and a fourth inverter;
[0014] The pulse signal D is input to the first input terminal of the watchdog circuit. The output terminal of the watchdog circuit is connected to the R port of the SR latch and the input terminal of the second inverter. The Q port of the SR latch and the output terminal of the second inverter are connected to the input terminal of the NAND gate. The output terminal of the NAND gate outputs the pulse signal C and is connected to the input terminal of the first delay circuit and the input terminal of the multiple pulse signal generation module. The output terminal of the first delay circuit is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the S port of the SR latch. The Q port of the SR latch is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the second input terminal of the watchdog circuit.
[0015] Optionally, the first delay circuit includes a first NMOS transistor, a first PMOS transistor, a first capacitor, a first current source, a second current source, and a first Schmitt trigger.
[0016] The input terminal of the first delay circuit is connected to the gates of the first NMOS transistor and the first PMOS transistor. The source of the first PMOS transistor is connected to the first current source. The source of the first NMOS transistor is connected to the second current source. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drains of the first PMOS transistor and the drain of the first NMOS transistor are both connected to one end of the first capacitor and the input terminal of the first Schmitt trigger. The first current source and the second current source are formed by connecting a bias voltage to the gate of the MOS transistor.
[0017] Optionally, the watchdog circuit includes a second PMOS transistor, a third PMOS transistor, a second capacitor, a third current source, and a second Schmitt trigger;
[0018] The first and second input terminals of the watchdog circuit are connected to the gates of the second and third PMOS transistors, respectively. The drain of the second PMOS transistor is connected to the drain of the third PMOS transistor, the third current source, and one end of the second capacitor. One end of the second capacitor is connected to the input terminal of the second Schmitt trigger. The sources of the second and third PMOS transistors and the other end of the second capacitor are all grounded. The third current source is formed by applying a bias voltage to the gate of the MOS transistor.
[0019] Optionally, the multiple pulse signal generation module includes: a second OR gate, a delay submodule, a third falling edge detection circuit, and a fourth falling edge detection circuit, wherein the delay submodule is composed of several delay circuits connected in series;
[0020] The output of the NAND gate is connected to the input of the delay submodule and the third falling edge detection circuit. The output of the third falling edge detection circuit is connected to the OUT_1 terminal and the input of the second OR gate. The output of the delay submodule is connected to the input of the fourth falling edge detection circuit. The output of the fourth falling edge detection circuit is connected to the input of the second OR gate. The output of the second OR gate is connected to the OUT_2 terminal.
[0021] The present invention also provides a method for implementing a multiple pulse signal generation circuit, comprising:
[0022] Acquire external input signals;
[0023] The external input signal is input to the input signal edge detection module, which outputs a pulse signal D. When the external input signal remains unchanged, the output pulse signal D is at a low level, and when the external input signal changes, the output pulse signal D is at a high level.
[0024] The pulse signal D is input to the pulse trigger judgment module, and the pulse trigger judgment module outputs the pulse signal C. If the pulse signal D remains low until the end of the timing, the output signal of the pulse trigger judgment module is low. After a delay, the output of the pulse trigger judgment module becomes high, resetting the timing. At the end of the next timing, the output of the pulse trigger judgment module becomes low again. If a high-level pulse appears in the pulse signal D before the end of the timing, the timing is immediately reset.
[0025] The pulse signal C is input to the multi-pulse signal generation module. When the pulse signal C switches from high level to low level, the multi-pulse signal generation module outputs a single pulse high-level signal and a continuous pulse high-level signal.
[0026] Optionally, the external input signal is input to the input signal edge detection module, and the output pulse signal D includes:
[0027] The external input signal is input to the first falling edge detection circuit. When the external input signal changes from high level to low level, the first falling edge detection circuit outputs a high-level pulse signal.
[0028] The external input signal is input to the second falling edge detection circuit through the first inverter. When the external input signal changes from low level to high level, the second falling edge detection circuit outputs a high level pulse signal.
[0029] The outputs of the first falling edge detection circuit and the second falling edge detection circuit are input to an OR gate to output the pulse signal D.
[0030] Optionally, the pulse signal C output by the pulse trigger determination module includes:
[0031] In the initial state, when the pulse signal D is a low-level input to the watchdog circuit, the R and S ports of the SR latch are both low, the Q port is high, and the Q' port is low. The pulse signal C = (R'Q')' = R + Q. At this time, the pulse signal C is high, the two input ports of the watchdog circuit are low, and the timing begins.
[0032] If the pulse signal D is input to the watchdog circuit at a high level, the watchdog circuit timer is reset, and the levels of each port of the SR latch and the pulse signal C remain unchanged;
[0033] If the pulse signal D remains low during the timing process, the S port of the SR latch will also remain low. When the timing ends, the output of the watchdog circuit will be high, resetting the SR latch so that the Q port is low and the Q' port is high. The pulse signal C will be high. The low-level signal Q port passes through the fourth inverter and is input to the second input port of the watchdog circuit in a high-level state. The output signal of the watchdog circuit will return to low. At this time, both the S port and the R port are low, the Q port remains low, and the Q' port remains high. The pulse signal C = R + Q simultaneously becomes low. The low-level pulse signal C passes through the first delay circuit and the third inverter to the S port. The S port changes from low to high, resetting the output of the SR latch so that the Q port is high and the Q' port is low. The pulse signal C returns to high, and the timing is reset.
[0034] Optionally, when the pulse signal C switches from high level to low level, the multiple pulse signals generate output single-pulse high-level signals and continuous pulse high-level signals, including:
[0035] When the pulse signal C switches from high level to low level, the pulse signal C is input to the third falling edge detection circuit to output a single pulse high level signal, and then the output remains at a low level. At the same time, the pulse signal C is sequentially input to several delay circuits, the pulse signal output by the fourth falling edge detection circuit and the signal output by the third falling edge detection circuit, and the continuous pulse high level signal is output by P-ORing.
[0036] The beneficial effects of this invention are: 1. Dynamic control capability: Multiple pulse signals can be generated by control, thereby realizing the continuous adjustment of the memristor resistance state and supporting intelligent information processing that integrates storage and computing;
[0037] 2. High-precision timing adjustment: The frequency of the pulse signal, the pulse width of the pulse, and the interval between adjacent pulses within multiple pulses can all be dynamically adjusted by the bias voltage to meet the needs of different neuromorphic devices.
[0038] 3. Energy efficiency optimization: The real-time input signal monitoring mechanism can reduce invalid pulse output, lower power consumption, and improve the control accuracy of neuromorphic devices.
[0039] 4. Compact structure: The watchdog circuit and delay module are integrated into a simple design, which helps to reduce the layout area and is suitable for large-scale integration. Attached Figure Description
[0040] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0041] Figure 1 This is an overall diagram of a multi-pulse signal generation circuit according to an embodiment of the present invention;
[0042] Figure 2 This is a schematic diagram of the falling edge detection circuit module structure according to an embodiment of the present invention;
[0043] Figure 3 This is a schematic diagram of the delay circuit module according to an embodiment of the present invention;
[0044] Figure 4 This is a schematic diagram of the watchdog circuit module according to an embodiment of the present invention. Detailed Implementation
[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0046] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0047] This invention is a dynamically adjustable multi-pulse signal generation circuit. Through real-time monitoring of input signals and an adjustable multi-pulse generation mechanism, it can provide high-precision, low-power pulse drive signals for neuromorphic devices and support the implementation of in-memory computing architecture.
[0048] This invention utilizes a watchdog circuit with a capacitor and a timing circuit design to generate pulse signals. The pulse signal is generated based on the state of the monitored input signal: when a normal change in the input signal is detected, the watchdog circuit capacitor discharges before the pulse signal is generated, and no pulse signal is generated; only when the monitored input signal remains unchanged for a long period does the pulse signal generate. A timing circuit including a delay circuit is designed, which can generate not only single pulse signals but also double or even multiple pulse signals, and the pulse interval and pulse width are adjustable. Furthermore, the charging speed of the capacitor can be controlled by adjusting the bias voltage of the watchdog circuit, thereby dynamically adjusting the pulse signal generation period.
[0049] The main objective of this invention is to generate multiple pulse signals based on the input signal state. If the input signal level changes within an adjustable time interval, the output remains at a low level. If the input signal remains at the same level within the time interval, the output is a continuous multiple pulse signal (or a single pulse can be output simultaneously). If the input signal remains unchanged, a pulse signal with a period of T is continuously output until the input signal level changes.
[0050] Example 1:
[0051] This embodiment provides a multi-pulse signal generation circuit, characterized in that it includes: an input signal edge detection module, a pulse trigger judgment module, and a multi-pulse signal generation module;
[0052] The input signal edge detection module detects the falling edge of the external input signal and outputs a pulse signal D to the input terminal of the pulse trigger judgment module. The output terminal of the pulse trigger judgment module outputs a pulse signal C to the multi-pulse signal generation module. When the pulse signal C switches from high level to low level, the OUT_1 terminal of the multi-pulse signal generation module outputs a single pulse high-level signal, and the OUT_2 terminal outputs a continuous pulse high-level signal.
[0053] Specifically, such as Figure 1 The diagram shows the circuit structure of this embodiment. The left side is the input signal edge detection module, the middle is the pulse trigger judgment module, and the right side is the multi-pulse signal generation module. The structures of the four falling edge detection circuit modules are all similar to... Figure 2 The structure given is completely identical; the structures of the three delay circuit modules are all the same. Figure 3 The structure given is completely identical, including the watchdog circuit module and... Figure 4 The structure is consistent with that given. The specific circuit connections of the falling edge detection circuit module, delay circuit module, and watchdog circuit module are described in [the document / document]. Figure 1 As shown in the diagram, the IN and OUT ports of each module are consistent with the schematic diagrams of the following three sub-modules. The function of the falling edge detection circuit module is: under normal circumstances, the output signal remains low; only when the input signal changes from high to low, it outputs a high-level pulse signal with a pulse width of tPHL. The function of the delay circuit module is: the output signal level is equal to the input signal level a certain period ago; the delay for the rising edge is tPLH, and the delay for the falling edge is tPHL, both of which are controllable. The function of the watchdog circuit module is: initially, the output is low; when both input signals are low, timing begins for a duration of t. If both input signals remain low until the timing ends, the output becomes high; whenever either input signal becomes high, the output becomes low, and the timing is reset when the high-level input signal ends.
[0054] Furthermore, the input signal edge detection module includes a first falling edge detection circuit, a second falling edge detection circuit, a first inverter, and a first OR gate;
[0055] An external input signal is input to the input terminal of the first falling edge detection circuit, and the output terminal of the first falling edge detection circuit is connected to the input terminal of the first OR gate;
[0056] An external input signal is input to the input terminal of the first inverter. The output terminal of the first inverter is connected to the input terminal of the second falling edge detection circuit. The output terminal of the first falling edge detection circuit is connected to the input terminal of the first OR gate. The output terminal of the first OR gate outputs a pulse signal D.
[0057] Specifically, such as Figure 2As shown, all falling edge detection circuits consist of a delay circuit module, an inverter, and an AND gate. The inverter output is high only during a short time tPHL after the input signal switches from high to low. Due to the delay effect, the output of the delay circuit remains high temporarily, so both inputs of the AND gate are high, and the output is high. In other cases, at least one input of the AND gate is always low, and the output is low. Therefore, the function of this module is: under normal circumstances, the output is low; only when the input switches from high to low does the output become high, and it returns to low at the end of the delay time. This results in a high-level pulse with a pulse width of tPHL.
[0058] Furthermore, the pulse triggering judgment module includes a watchdog circuit, an SR latch, a first delay circuit, a NAND gate, a second inverter, a third inverter, and a fourth inverter;
[0059] The pulse signal D is input to the first input terminal of the watchdog circuit. The output terminal of the watchdog circuit is connected to the R port of the SR latch and the input terminal of the second inverter. The Q port of the SR latch and the output terminal of the second inverter are connected to the input terminal of the NAND gate. The output terminal of the NAND gate outputs the pulse signal C and is connected to the input terminal of the first delay circuit and the input terminal of the multiple pulse signal generation module. The output terminal of the first delay circuit is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the S port of the SR latch. The Q port of the SR latch is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the second input terminal of the watchdog circuit.
[0060] Specifically, the pulse trigger judgment module receives the pulse signal D from the input signal edge detection module, and its output C = (R'Q')' = R + Q is provided to the multiple pulse signal generation module. The watchdog circuit receives signal D and the latch output signal Q, which are connected to IN2 and IN1 respectively. In fact, IN2 and IN1 can be interchanged. The watchdog circuit output is connected to the latch's R port and the second inverter. The first delay circuit receives signal C, and its output returns to the latch's S port via the third inverter.
[0061] Furthermore, the first delay circuit includes a first NMOS transistor, a first PMOS transistor, a first capacitor, a first current source, a second current source, and a first Schmitt trigger;
[0062] The input terminal of the first delay circuit is connected to the gates of the first NMOS transistor and the first PMOS transistor. The source of the first PMOS transistor is connected to the first current source. The source of the first NMOS transistor is connected to the second current source. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drains of the first PMOS transistor and the drain of the first NMOS transistor are both connected to one end of the first capacitor and the input terminal of the first Schmitt trigger. The second current source and the other end of the first capacitor are both grounded. The first current source and the second current source are formed by connecting a bias voltage to the gate of the MOS transistor.
[0063] Specifically, such as Figure 3 The input signal IN of the delay circuit module shown is connected to the gates of the first PMOS transistor M2 and the first NMOS transistor M3. M1 and M4 form the first current source and the second current source respectively by connecting the bias voltage to their gates. M5-M10 form a Schmitt trigger and output signal OUT.
[0064] If the input IN level remains unchanged, when IN is low, M1 and M2 are on, VC is high, and OUT is low; when IN is high, M3 and M4 are on, VC is low, and OUT is high. In summary, the output signal level is the same as the input signal.
[0065] If the input IN level changes, when IN changes from high to low, capacitor C is charged by M1 and M2, and VC gradually increases. After a period of time t1, VC rises to the Schmitt trigger switching voltage VT+, and the output OUT switches from high to low. The rise delay time tPLH can be adjusted by changing the bias voltage VB1.
[0066]
[0067] When IN changes from low to high, capacitors C are discharged through M3 and 4, and VC gradually decreases. After a period of time t2, VC drops to the Schmitt trigger switching voltage VT-, and the output OUT switches from low to high. The fall delay time tPHL can be adjusted by changing the bias voltage VB2.
[0068]
[0069] In summary, when the input signal IN changes, the output signal OUT will initially maintain the level before the IN change, and then flip to the level after a delay of t1 or t2. The delay time can be adjusted by changing the bias voltage. Therefore, the output level of the delay circuit module is always equal to the input level a certain period ago, thus achieving the signal delay function.
[0070] Furthermore, the watchdog circuit includes a second NMOS transistor, a third NMOS transistor, a second capacitor, a third current source, and a second Schmitt trigger;
[0071] The first and second input terminals of the watchdog circuit are connected to the gates of the second and third NMOS transistors, respectively. The drain of the second NMOS transistor is connected to the drain of the third NMOS transistor, the third current source, and one end of the second capacitor. One end of the second capacitor is connected to the input terminal of the second Schmitt trigger. The sources of the second and third NMOS transistors and the other end of the second capacitor are all grounded. The third current source is formed by connecting a bias voltage to the gate of the MOS transistor.
[0072] Specifically, such as Figure 4 The watchdog circuit module is similar to the delay circuit module. The input signals IN1 and IN2 are connected to the gates of the second NMOS transistor M2 and the third NMOS transistor M3, respectively. M1 forms a current source by connecting a bias voltage to its gate. M4-M9 form a Schmitt trigger, and the output signal is OUT. The aspect ratio of M1 should be relatively small, while the aspect ratios of M2 and M3 should be relatively large.
[0073] Initially, the capacitor has not accumulated charge, VC is low, and OUT is high. If M2 and M3 are low, timing begins. At this time, M2 and M3 are off, while M1 remains on, slowly charging capacitor C, causing VC to rise gradually. If IN1 or IN2 goes high during this period, the corresponding M2 or M3 immediately turns on, rapidly discharging the capacitor at a rate much greater than the charging rate of M1. VC is quickly pulled back to low. When IN1 and IN2 return from high to low, the watchdog circuit returns to its initial state, and the timing is reset. If IN1 and IN2 remain low, after time t, VC will rise to the Schmitt trigger VT+, at which point OUT goes low, and timing ends. Time t can be adjusted by changing the external bias voltage VB.
[0074]
[0075] Furthermore, the multiple pulse signal generation module includes: a second OR gate, a delay submodule, a third falling edge detection circuit, and a fourth falling edge detection circuit, wherein the delay submodule is composed of several series-connected delay circuits;
[0076] The output of the NAND gate is connected to the input of the delay submodule and the third falling edge detection circuit. The output of the third falling edge detection circuit is connected to the OUT_1 terminal and the input of the second OR gate. The output of the delay submodule is connected to the input of the fourth falling edge detection circuit. The output of the fourth falling edge detection circuit is connected to the input of the second OR gate. The output of the second OR gate is connected to the OUT_2 terminal.
[0077] Specifically, the input to the multi-pulse signal generation module is signal C from the pulse trigger judgment section. The outputs in the diagram are a single-pulse signal OUT_1 and a double-pulse signal OUT_2. Signal C is directly input to the third falling edge detection circuit below, which then outputs the single-pulse signal OUT_1. Simultaneously, signal C passes through two (or more) delay circuits before being input to the fourth falling edge detection circuit above. The output signal is then ORed with the single-pulse signal OUT_1 to output the double-pulse signal OUT_2. Similarly, if N-fold pulse signals are required, signal C can be passed through 2(N-1) delay circuits before being input to a falling edge detection circuit. The output signal of this falling edge detection circuit is then ORed with the N-1-fold pulse signal OUT_N-1.
[0078] Example 2:
[0079] This embodiment provides a method for implementing a multiple pulse signal generation circuit, based on a multiple pulse signal generation circuit of the embodiment, including:
[0080] Acquire external input signals;
[0081] The external input signal is input to the input signal edge detection module, which outputs a pulse signal D. When the external input signal remains unchanged, the output pulse signal D is at a low level, and when the external input signal changes, the output pulse signal D is at a high level.
[0082] The pulse signal D is input to the pulse trigger judgment module, and the pulse trigger judgment module outputs the pulse signal C. If the pulse signal D remains low until the end of the timing, the output signal of the pulse trigger judgment module is low. After a delay, the output of the pulse trigger judgment module becomes high, resetting the timing. At the end of the next timing, the output of the pulse trigger judgment module becomes low again. If a high-level pulse appears in the pulse signal D before the end of the timing, the timing is immediately reset.
[0083] The pulse signal C is input to the multi-pulse signal generation module. When the pulse signal C switches from high level to low level, the multi-pulse signal generation module outputs a single pulse high-level signal and a continuous pulse high-level signal.
[0084] Furthermore, the external input signal is input to the input signal edge detection module, and the output pulse signal D includes:
[0085] The external input signal is input to the first falling edge detection circuit. When the external input signal changes from high level to low level, the first falling edge detection circuit outputs a high level pulse signal.
[0086] The external input signal is input to the second falling edge detection circuit through the first inverter. When the external input signal changes from low level to high level, the second falling edge detection circuit outputs a high level pulse signal.
[0087] The outputs of the first falling edge detection circuit and the second falling edge detection circuit are input to an OR gate to output a pulse signal D.
[0088] Specifically, such as Figure 1 On the left is the input signal edge detection module, which consists of two falling edge detection circuits, an inverter, and an OR gate. The input comes from the external signal IN, and the output is denoted as D, which is provided to the pulse trigger judgment section.
[0089] When the input signal level remains constant, the outputs of both falling edge detection circuits (i.e., the first and second falling edge detection circuits) are low, and the overall output D is low. When the input signal changes from high to low, the upper first falling edge detection circuit outputs a pulse signal; when the input signal changes from low to high, the lower second falling edge detection circuit outputs a pulse signal. Therefore, the overall effect of the input signal edge detection section is: when the input signal remains constant, output D remains low; when the input signal level changes, output D is a high-level pulse signal.
[0090] The further pulse trigger judgment module outputs pulse signal C, which includes:
[0091] In the initial state, when the pulse signal D is low and the watchdog circuit is input, the R and S ports of the SR latch are both low, the Q port is high, and the Q' port is low. The pulse signal C = (R'Q')' = R + Q. At this time, the pulse signal C is high, the two input ports of the watchdog circuit are low, and the timing begins.
[0092] If the pulse signal D is a high-level input to the watchdog circuit, the watchdog circuit timer is reset, and the levels of each port of the SR latch and the pulse signal C remain unchanged.
[0093] If the pulse signal D remains low during the timing process, the S port of the SR latch will also remain low. When the timing ends, the watchdog circuit output will be high, resetting the SR latch so that the Q port is low and the Q' port is high. The pulse signal C will be high. The low-level signal Q port passes through a quad inverter and is input to the second input port of the watchdog circuit in a high-level state. The output signal of the watchdog circuit will return to low. At this time, both the S port and the R port are low, the Q port remains low, and the Q' port remains high. The pulse signal C = R + Q simultaneously becomes low. The low-level pulse signal C passes through the first delay circuit and the third inverter to the S port. The S port changes from low to high, resetting the output of the SR latch so that the Q port is high and the Q' port is low. The pulse signal C returns to high, and the timing is reset.
[0094] Specifically, such as Figure 1 As shown, the middle section is the pulse trigger judgment module, which consists of a watchdog circuit, an SR latch, a delay circuit, a NAND gate, and three inverters. The input to this part comes from D of the input signal edge detection section, and the output C = (R'Q')' = R + Q is provided to the multiple pulse signal generation section.
[0095] Initially, the input to this part is a low-level signal from the input signal edge detection module. Both the R and S terminals of the SR latch are low, Q = 1, Q' = 0, and the overall output C of this part is high. At this time, both inputs to the watchdog circuit are low, and timing begins.
[0096] If the external signal level changes during the timing process and a high-level pulse signal appears in the input signal D, the watchdog circuit will reset the timing. During this process, the levels of each port of the SR latch and the output signal C will not change.
[0097] If the external signal level remains unchanged during the timing process, the input signal D will always remain at a low level. During this process, the signal S will also always remain at a low level. When this timing ends, the output R of the watchdog circuit will become high, and then the SR latch will be reset to Q = 0 and Q' = 1. During this process, the output C = R + Q remains high. However, at this time, the low-level signal Q is input to the watchdog circuit in a high-level state through the fourth inverter, and the output signal R of the watchdog circuit will change back to low level, that is, the high-level time of the signal R is very short. At this time, both the signal S and the signal R are low level, Q remains low level, and Q' remains high level. Therefore, the output C = R + Q immediately becomes low level at the same time due to the change in the level of R. After a period of time, the low-level signal C at this time reaches the S port through the first delay circuit and the third inverter, and the signal S changes from low level to high level, resetting the output of the SR latch to Q = 1 and Q' = 0. In this way, the output C = R + Q of this part returns to high level, and the levels of each signal return to the state before the output R of the watchdog circuit changes, and the timing is reset.
[0098] Record the time from the start of timing to the end of timing of the watchdog circuit as t. Because the time when the output of the watchdog circuit remains high is very short, the time from the end of timing to the timing reset is mainly determined by the time of the signal C converted to low level passing through the delay circuit. Record the delay of the delay circuit for the falling signal as tPHL. The time period when the output signal C changes is T = t + tPHL. Generally, tPHL << t, so T ≈ t.
[0099] Generally speaking, the overall function of the pulse trigger judgment part is: the initial state output signal C is high, and the timing starts for a time t. Monitor the input signal D. If the signal D always remains low until the end of timing, then the output signal C will become low, the signal C will change back to high after tPHL, reset the timing, and become low again at the end of the next timing. If a high-level pulse of the signal D is detected during this process, the timing is immediately reset.
[0100] Furthermore, when the pulse signal C switches from high level to low level, the multi-pulse signal generates an output single-pulse high-level signal and a continuous pulse high-level signal, including:
[0101] When the pulse signal C switches from high level to low level, the pulse signal C is input to the third falling-edge detection circuit to output a single-pulse high-level signal, and then the output remains at a low level. At the same time, the pulse signal C is sequentially input to several delay circuits, and the pulse signal output by the fourth falling-edge detection circuit and the signal output by the third falling-edge detection circuit are ORed to output a continuous pulse high-level signal.
[0102] Specifically, such as Figure 1On the right is the multi-pulse signal generation module, which consists of two delay circuits, two falling edge detection circuits, and an OR gate. The input to this part is the signal C from the pulse trigger judgment part, and the outputs in the figure are the single pulse signal OUT_1 and the double pulse signal OUT_2.
[0103] Initially, signal C is high, and all outputs are low. When signal C changes from high to low, the lower third falling edge detection circuit outputs a high-level pulse signal with a pulse width of tPHL. At this time, the upper falling edge detection circuit remains low due to the delay circuit, so each output outputs a high-level pulse. After 2tPLH, the falling edge of signal C is input to the upper fourth falling edge detection circuit via two delay circuits. The fourth falling edge detection circuit outputs a high-level pulse signal with a pulse width of tPHL. Since the next timing cycle has not yet arrived, signal C input to the lower third falling edge detection circuit will remain high, and the output of the third falling edge detection circuit remains low. Therefore, the single-pulse signal output OUT_1 remains low, and the double-pulse signal output OUT_2 outputs another high-level pulse with a pulse width of tPHL. Thus, the overall effect of this part is: under normal circumstances, all outputs remain low. Only when signal C switches from high to low level will OUT_1 output a single-pulse high-level signal with a pulse width of tPHL, and OUT_2 output two consecutive high-level pulse signals, both with a pulse width of tPHL and an interval of 2tPLH. In practical applications, more branches can be added similarly based on the same principle, using N branches and N-input NOR gates to achieve N-fold pulse signal output OUT_N. Output ports can also be added or removed as needed.
[0104] Therefore, the overall principle of this invention is as follows: When the circuit starts working, the pulse trigger judgment section begins timing for a time t. The input signal edge detection section monitors the state of the input signal, or whenever the input signal undergoes a level state switch, the input signal edge detection section outputs a high-level pulse signal D to the pulse trigger judgment section, and the pulse trigger judgment section resets the timing. Each time timing t ends, after another time tPHL, the signal C provided by the pulse trigger judgment section to the multi-pulse signal generation section changes from high to low. The multi-pulse signal output will then appear as a continuous multi-pulse timing signal. The pulse trigger judgment section resets the timing, and signal C returns to the high-level state. The period of the signal output by this multi-pulse signal generation circuit is T = t + tPHL ≈ t, and the frequency of the signal is f = 1 / T ≈ 1 / t. This frequency can be adjusted in real time by changing the bias voltage of the watchdog circuit.
[0105] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.
Claims
1. A multi-pulse signal generation circuit, characterized in that, include: Input signal edge detection module, pulse trigger judgment module, and multiple pulse signal generation module; The input signal edge detection module detects the falling edge of the external input signal and outputs a pulse signal D to the input terminal of the pulse trigger judgment module. The output terminal of the pulse trigger judgment module outputs a pulse signal C to the multi-pulse signal generation module. When the pulse signal C switches from high level to low level, the OUT_1 terminal of the multi-pulse signal generation module outputs a single pulse high-level signal, and the OUT_2 terminal outputs a continuous pulse high-level signal. The pulse triggering judgment module includes a watchdog circuit, an SR latch, a first delay circuit, a NAND gate, a second inverter, a third inverter, and a fourth inverter. The pulse signal D is input to the first input terminal of the watchdog circuit. The output terminal of the watchdog circuit is connected to the R port of the SR latch and the input terminal of the second inverter. The Q port of the SR latch and the output terminal of the second inverter are connected to the input terminal of the NAND gate. The output terminal of the NAND gate outputs the pulse signal C and is connected to the input terminal of the first delay circuit and the input terminal of the multiple pulse signal generation module. The output terminal of the first delay circuit is connected to the input terminal of the third inverter. The output terminal of the third inverter is connected to the S port of the SR latch. The Q port of the SR latch is connected to the input terminal of the fourth inverter. The output terminal of the fourth inverter is connected to the second input terminal of the watchdog circuit. The multiple pulse signal generation module includes: a second OR gate, a delay submodule, a third falling edge detection circuit, and a fourth falling edge detection circuit, wherein the delay submodule is composed of several delay circuits connected in series; The output of the NAND gate is connected to the input of the delay submodule and the third falling edge detection circuit. The output of the third falling edge detection circuit is connected to the OUT_1 terminal and the input of the second OR gate. The output of the delay submodule is connected to the input of the fourth falling edge detection circuit. The output of the fourth falling edge detection circuit is connected to the input of the second OR gate. The output of the second OR gate is connected to the OUT_2 terminal.
2. The multi-pulse signal generation circuit according to claim 1, characterized in that, The input signal edge detection module includes a first falling edge detection circuit, a second falling edge detection circuit, a first inverter, and a first OR gate; The external input signal is input to the input terminal of the first falling edge detection circuit, and the output terminal of the first falling edge detection circuit is connected to the input terminal of the first OR gate. The external input signal is input to the input terminal of the first inverter, the output terminal of the first inverter is connected to the input terminal of the second falling edge detection circuit, the output terminal of the first falling edge detection circuit is connected to the input terminal of the first OR gate, and the output terminal of the first OR gate outputs the pulse signal D.
3. The multi-pulse signal generation circuit according to claim 1, characterized in that, The first delay circuit includes a first NMOS transistor, a first PMOS transistor, a first capacitor, a first current source, a second current source, and a first Schmitt trigger; The input terminal of the first delay circuit is connected to the gates of the first NMOS transistor and the first PMOS transistor. The source of the first PMOS transistor is connected to the first current source. The source of the first NMOS transistor is connected to the second current source. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drains of the first PMOS transistor and the drain of the first NMOS transistor are both connected to one end of the first capacitor and the input terminal of the first Schmitt trigger. The first current source and the second current source are formed by connecting a bias voltage to the gate of the MOS transistor.
4. The multi-pulse signal generation circuit according to claim 1, characterized in that, The watchdog circuit includes a second NMOS transistor, a third NMOS transistor, a second capacitor, a third current source, and a second Schmitt trigger; The first and second input terminals of the watchdog circuit are connected to the gates of the second and third NMOS transistors, respectively. The drain of the second NMOS transistor is connected to the drain of the third NMOS transistor, the third current source, and one end of the second capacitor. One end of the second capacitor is connected to the input terminal of the second Schmitt trigger. The sources of the second and third NMOS transistors and the other end of the second capacitor are all grounded. The third current source is formed by applying a bias voltage to the gate of the MOS transistor.
5. A method for implementing a multiple pulse signal generation circuit according to any one of claims 1-4, characterized in that, include: Acquire external input signals; The external input signal is input to the input signal edge detection module, which outputs a pulse signal D. When the external input signal remains unchanged, the output pulse signal D is at a low level, and when the external input signal changes, the output pulse signal D is at a high level. The pulse signal D is input to the pulse trigger judgment module, and the pulse trigger judgment module outputs the pulse signal C. If the pulse signal D remains low until the end of the timing, the output signal of the pulse trigger judgment module is low. After a delay, the output of the pulse trigger judgment module becomes high, resetting the timing. At the end of the next timing, the output of the pulse trigger judgment module becomes low again. If a high-level pulse appears in the pulse signal D before the end of the timing, the timing is immediately reset. The pulse signal C is input to the multi-pulse signal generation module. When the pulse signal C switches from high level to low level, the multi-pulse signal generation module outputs a single pulse high-level signal and a continuous pulse high-level signal.
6. The method for implementing the multiple pulse signal generation circuit according to claim 5, characterized in that, The external input signal is input to the input signal edge detection module, and the output pulse signal D includes: The external input signal is input to the first falling edge detection circuit. When the external input signal changes from high level to low level, the first falling edge detection circuit outputs a high-level pulse signal. The external input signal is input to the second falling edge detection circuit through the first inverter. When the external input signal changes from low level to high level, the second falling edge detection circuit outputs a high level pulse signal. The outputs of the first falling edge detection circuit and the second falling edge detection circuit are input to an OR gate to output the pulse signal D.
7. The method for implementing the multiple pulse signal generation circuit according to claim 5, characterized in that, The pulse signal C output by the pulse trigger determination module includes: In the initial state, when the pulse signal D is a low-level input to the watchdog circuit, the R and S ports of the SR latch are both low, the Q port is high, and the Q' port is low. The pulse signal C = (R'Q')' = R + Q. At this time, the pulse signal C is high, the two input ports of the watchdog circuit are low, and the timing begins. If the pulse signal D is input to the watchdog circuit at a high level, the watchdog circuit timer is reset, and the levels of each port of the SR latch and the pulse signal C remain unchanged; If the pulse signal D remains low during the timing process, the S port of the SR latch will also remain low. When the timing ends, the output of the watchdog circuit will be high, resetting the SR latch so that the Q port is low and the Q' port is high. The pulse signal C will be high. The low-level signal Q port will pass through the fourth inverter and be input to the second input port of the watchdog circuit in a high-level state. The output signal of the watchdog circuit will return to low. At this time, both the S port and the R port are low, the Q port remains low, and the Q' port remains high. The pulse signal C = R + Q will simultaneously become low. The low-level pulse signal C will pass through the first delay circuit and the third inverter to the S port. The S port will change from low to high, resetting the output of the SR latch so that the Q port is high and the Q' port is low. The pulse signal C will return to high, and the timing will be reset.
8. The method for implementing the multiple pulse signal generation circuit according to claim 5, characterized in that, When the pulse signal C switches from high level to low level, the multiple pulse signals generate output single pulse high-level signals and continuous pulse high-level signals, including: When the pulse signal C switches from high level to low level, the pulse signal C is input to the third falling edge detection circuit to output a single pulse high level signal, and then the output remains at a low level. At the same time, the pulse signal C is sequentially input to several delay circuits, the pulse signal output by the fourth falling edge detection circuit and the signal output by the third falling edge detection circuit, and the continuous pulse high level signal is output by P-ORing.
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