High-speed data transceiving circuit supporting multiple modulation modes

Abstract

The invention relates to a high-speed data transceiving circuit supporting multiple modulation modes. The high-speed data transceiving circuit comprises a multi-mode modulation unit, a multi-mode demodulation unit, a clock signal generation unit and a control unit, wherein the multi-mode modulation unit responds to a control signal generated by the control unit to determine a modulation type of a signal to be modulated, responds to a first clock signal CK1 sent by the clock signal generation unit to determine a corresponding modulation period so as to modulate the signal to be modulated to obtain a modulation signal, and responds to the first control signal to modulate the signal to be modulated to obtain the modulation signal. Transmitting the modulation signal; and the multi-mode demodulation unit obtains the modulation signal, selects a corresponding reference level signal in response to the control signal, compares the reference level signal with the modulation signal to obtain a comparison result, and determines a corresponding demodulation period in response to a second clock signal CK2 sent by the clock signal generation unit to demodulate the comparison result to obtain a required demodulation signal. The circuit can be integrated on a chip to support data transceiving of multiple modulation types.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuits, and particularly relates to a high-speed data transceiver circuit supporting multiple modulation modes. Background Art

[0002] A high-speed data transceiver is a core module applied in high-speed wired communication technology. Its main function is to convert parallel data into serial data for transmission and then restore the serial data to parallel data. Since the advent of the information age, the demand for data transmission has been increasing, and the requirement for data transmission rate has also been increasing.

[0003] However, traditional data transceiver devices have problems such as a single data transmission type, inability to be compatible with different data transmission protocols, and difficulty in meeting the data transmission requirements of multiple modulation modes. Therefore, there is a need to provide a high-speed data transceiver circuit that can be compatible with different data types. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a high-speed data transceiver circuit supporting multiple modulation modes. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0005] The present invention provides a high-speed data transceiver circuit supporting multiple modulation modes, including: a multi-mode modulation unit, a multi-mode demodulation unit, a clock signal generation unit, and a control unit; wherein, the multi-mode modulation unit is configured to determine the modulation type of the signal to be modulated in response to a control signal generated by the control unit, and determine a corresponding modulation period in response to a first clock signal CK1 sent by the clock signal generation unit, so as to modulate the signal to be modulated to obtain a modulated signal, and transmit the modulated signal in response to the first control signal; the multi-mode demodulation unit is configured to obtain the modulated signal, select a corresponding reference level signal in response to the control signal to compare with the modulated signal to obtain a comparison result, and determine a corresponding demodulation period in response to a second clock signal CK2 sent by the clock signal generation unit, so as to demodulate the comparison result to obtain a required demodulated signal.

[0006] Compared with the prior art, the beneficial effects of the present invention:

[0007] Aiming at the problem that existing data transceiver devices are difficult to meet the data transmission requirements of multiple modulation methods, the present invention provides a high-speed data transceiver circuit supporting multiple modulation methods. This high-speed data transceiver circuit can be integrated into a chip to support data transceiver of multiple modulation types. By dynamically adapting the multi-mode modulation and demodulation mechanism, it significantly improves the flexibility and environmental adaptability of data transmission, can automatically optimize the signal modulation type and demodulation reference level under complex channel conditions, and effectively overcomes the problem of imbalance between spectral efficiency and anti-interference ability caused by traditional single modulation methods. At the same time, based on the clock synchronization architecture of collaborative control, it realizes the precise matching of modulation and demodulation cycles, avoids signal distortion caused by timing misalignment, reduces the bit error rate while ensuring high-speed transmission. In addition, through modular integrated design, it simplifies the system structure, reduces the hardware overhead and power consumption of multi-mode switching, and provides a highly compatible and low-complexity solution for high-speed communication systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. is a structural block diagram of a high-speed data transceiver circuit supporting multiple modulation methods provided by an embodiment of the present invention;

[0009] Figure 2 FIG. is another structural block diagram of a high-speed data transceiver circuit supporting multiple modulation methods provided by an embodiment of the present invention;

[0010] Figure 3 FIG. is a schematic circuit connection diagram of a multi-mode modulation unit provided by an embodiment of the present invention;

[0011] Figure 4 FIG. is a timing relationship diagram of multiple modulation modes provided by an embodiment of the present invention;

[0012] Figure 5 FIG. is a schematic circuit connection diagram of a multi-mode demodulation unit provided by an embodiment of the present invention;

[0013] Figure 6 FIG. is an example diagram of the change of a PAM3 decoded signal provided by an embodiment of the present invention;

[0014] Figure 7 FIG. is the output eye diagram of the demodulated signal output in the NRZ working mode provided by an embodiment of the present invention;

[0015] Figure 8 FIG. is the output eye diagram of the demodulated signal output in the PAM3 working mode provided by an embodiment of the present invention;

[0016] Figure 9 FIG. is the output eye diagram of the demodulated signal output in the PAM4 working mode provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0018] In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0019] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0020] Before introducing the technical solutions of the embodiments of the present invention, relevant terms are explained.

[0021] Three-level pulse amplitude modulation: namely 3-Level PAM, abbreviated as PAM3 in English. PAM3 is a modulation technology widely used in digital communication. By mapping the input digital signal to three different amplitude levels (such as: -A, 0, +A), each symbol carries log2(3) ≈ 1.58 bits of information. While improving the data transmission efficiency, it takes into account the anti-noise performance and implementation complexity, and is applicable to high-speed wired communication (such as Ethernet, optical communication) and some wireless communication scenarios.

[0022] Four-level Pulse Amplitude Modulation: That is, 4-Level PAM, with the English abbreviation PAM4. PAM4 doubles the data rate at the same symbol rate by mapping every two consecutive input bits to a four-level symbol (such as the level values: -3A, -A, +A, +3A). For example, the input bit stream "00" is mapped to -3A, "01" is mapped to -A, "10" is mapped to +A, and "11" is mapped to +3A. Each symbol carries 2 bits of information, and the spectral efficiency is 2 bit / s / Hz, which is twice that of NRZ (1 bit / s / Hz). Compared with traditional binary modulation (such as NRZ, that is, 2-Level PAM), PAM-4 can carry 2 bits of information per symbol, significantly improving the spectral efficiency and transmission rate, and is especially suitable for high-speed short-distance communication scenarios (such as data center interconnection, optical modules, inter-chip communication, etc.).

[0023] Binary Modulation: That is, 2-Level PAM, with the English abbreviation NRZ. NRZ is the most basic modulation method in digital communication, which transmits by converting binary data (0 and 1) into an analog signal. Its core feature is that each symbol carries only 1 bit of information, and it has advantages such as simple implementation and strong anti-noise ability, and is widely used in low-rate, high-reliability or long-distance communication scenarios (such as satellite communication, wireless sensor networks, RFID, etc.).

[0024] Now, in combination with the accompanying drawings, a high-speed data transceiver circuit supporting multiple modulation methods provided by an embodiment of the present invention will be described in detail.

[0025] Figure 1 It is a structural block diagram of a high-speed data transceiver circuit supporting multiple modulation methods provided by an embodiment of the present invention. As Figure 1 shown, the high-speed data transceiver circuit includes: a multi-mode modulation unit, a multi-mode demodulation unit, a clock signal generation unit, and a control unit; among them, the multi-mode modulation unit is used to determine the modulation type of the signal to be modulated in response to the control signal generated by the control unit, and in response to the first clock signal CK1 sent by the clock signal generation unit, determine the corresponding modulation period to modulate the signal to be modulated to obtain a modulated signal, and in response to the first control signal, transmit the modulated signal; the multi-mode demodulation unit is used to obtain the modulated signal, select the corresponding reference level signal in response to the control signal to compare with the modulated signal to obtain a comparison result, and in response to the second clock signal CK2 sent by the clock signal generation unit, determine the corresponding demodulation period to demodulate the comparison result to obtain the required demodulated signal.

[0026] It should be noted that the signals generated by the control unit are used to determine the path of the input signal. Exemplarily, different control signals correspond to different modulation types for the signal to be modulated. The clock signal is only used to determine the modulation period or the demodulation period.

[0027] Now, Figure 1 the circuit connection relationships of the various structures in Figure 2 is another structural block diagram of a high-speed data transceiver circuit supporting multiple modulation methods provided by an embodiment of the present invention. It should be noted that Figure 2 the control unit and the clock signal generation unit are omitted in Figure 3 is a circuit connection schematic diagram of a multi-mode modulation unit provided by an embodiment of the present invention. As Figure 3 shown, the control signals include: a first control signal PAM3_EN and a second control signal PAM2_EN; both the first control signal PAM3_EN and the second control signal PAM2_EN include a set-to-0 enable signal and a set-to-1 enable signal; the multi-mode modulation unit includes: a modulation signal selection module, a PAM3 modulation module, a PAM4 / NRZ modulation module, and a selection driving module; wherein, the control ends of the modulation signal selection module and the selection driving module are both connected to the first control signal PAM3_EN, the first input ends of the PAM3 modulation module and the PAM4 / NRZ modulation module are both connected to the first clock signal, and the control end of the PAM4 / NRZ modulation module is connected to the second control signal PAM2_EN; the input end of the modulation signal selection module is connected to the signal to be modulated, the first output end is connected to the second input end of the PAM3 modulation module, the second output end is connected to the second input end of the PAM4 / NRZ modulation module, the output ends of the PAM3 modulation module and the PAM4 / NRZ modulation module are both connected to the input end of the selection driving module, and the output end of the selection driving module is connected to the input end of the multi-mode demodulation unit; the modulation signal selection module is configured to, in response to the set-to-0 enable signal of the first control signal PAM3_EN, transmit the signal to be modulated to the PAM4 / NRZ modulation module, or, in response to the set-to-1 enable signal of the first control signal PAM3_EN, transmit the signal to be modulated to the PAM3 modulation module; the PAM3 modulation module is configured to perform PAM3 modulation on the signal to be modulated to obtain a PAM3 signal; the PAM4 / NRZ modulation module is configured to, in response to the set-to-1 enable signal of the second control signal PAM2_EN, perform NRZ modulation on the signal to be modulated to obtain an NRZ signal, or, in response to the set-to-0 enable signal of the second control signal PAM2_EN, perform PAM4 modulation on the signal to be modulated to obtain a PAM4 signal; the selection driving module is configured to, in response to the set-to-0 enable signal or the set-to-1 enable signal of the first control signal PAM3_EN, drive the PAM3 signal, the PAM4 signal, or the NRZ signal to be transmitted to the multi-mode demodulation unit.

[0028] Specifically, the modulation signal selection module includes switches D0, D1, D2, and D3; the control terminals of switches D0, D1, D2, and D3 are all connected to the first control signal PAM3_EN; the input terminals of switches D0, D1, D2, and D3 are all connected to the signal to be modulated; the first output terminal of switch D0 is connected to the first input terminal of the PAM3 modulation module, the first output terminal of switch D1 is connected to the second input terminal of the PAM3 modulation module, and the first output terminal of switch D2 is connected to the third input terminal of the PAM3 modulation module; the second input terminal of switch D0 is connected to the first input terminal of the PAM4 / NRZ modulation module, the second output terminal of switch D1 is connected to the second input terminal of the PAM4 / NRZ modulation module, the second output terminal of switch D2 is connected to the third input terminal of the PAM4 / NRZ modulation module, and the output terminal of switch D3 is connected to the fourth input terminal of the PAM4 / NRZ module. The signals received by the four switches are all named with the corresponding switch names. For example, the signal received by switch D2 is named input signal D2.

[0029] It should be noted that the PAM3 modulation module is an existing modulation circuit, and for the sake of simplicity, it will not be elaborated here.

[0030] Please continue to refer to Figure 3 , the PAM4 / NRZ module includes: a first 2:1 serializer sub-module, a second 2:1 serializer sub-module, and a first selector; wherein, the control terminal of the first selector is connected to the second control signal PAM2_EN; the first input terminal of the first 2:1 serializer sub-module is connected to the second input terminal of switch D0, the second input terminal is connected to the second output terminal of switch D1, and the output terminal is connected to the first terminal of the first selector; the first input terminal of the second 2:1 serializer sub-module is connected to the second output terminal of switch D2, the second input terminal is connected to the output terminal of switch D3, and the output terminal is connected to the second terminal of the first selector. The output terminal of the first selector and the output terminal of the first 2:1 serializer sub-module are both connected to multiple input terminals of the selection driving module.

[0031] Please continue to refer to Figure 3, the selection driving module includes: a second selector, a third selector, a fourth selector, a fifth selector, a first driver, a second driver, a third driver, and a fourth driver; the control terminals of the second selector, the third selector, the fourth selector, and the fifth selector are connected to the first control signal PAM3_EN; the first to fourth output terminals of the PAM3 modulation module are respectively connected to the set-1 terminal of the second selector, the set-1 terminal of the third selector, the set-1 terminal of the fourth selector, and the set-1 terminal of the fifth selector; the output terminal of the first 2:1 serialization sub-module is respectively connected to the set-0 terminal of the second selector and the set-0 terminal of the fourth selector, and the output terminal of the second 2:1 serialization sub-module is respectively connected to the set-0 terminal of the third selector and the set-0 terminal of the fifth selector; the output terminal of the second selector is connected to the input terminal of the first driver, the output terminal of the third selector is connected to the input terminal of the second driver, the output terminal of the third selector is connected to the input terminal of the third driver, the output terminal of the fourth selector is connected to the input terminal of the fourth driver, and the output terminals of the first driver, the second driver, the third driver, and the fourth driver are all connected to the input terminal of the multi-mode demodulation unit.

[0032] It should be noted here that the types and models of the four drivers are the same, so they are all represented by "Driver" in the figure.

[0033] Figure 4 is the timing relationship diagram of multiple modulation modes provided by the embodiments of the present invention. Now, in combination with Figure 4 for Figure 3 the working principle of the multi-mode modulation unit in

[0034] (1) When the first control signal PAM3_EN is set to 0 and the second control signal PAM2_EN is set to 1, the signal to be modulated is subjected to NRZ modulation. Here, the first 2:1 serialization sub-module and the first selector form an NRZ modulation sub-module. Under the timing control of CK0, the first 2:1 serialization sub-module performs 2:1 serialization to obtain the S1 signal with twice the input data rate. At this time, the PAM2_EN set-“1” enable signal controls the first selector to select the S1 signal (i.e., the NRZ signal) as the S3 signal to enter the subsequent selection circuit.

[0035] (2) When the first control signal PAM3_EN is set to 0 and the second control signal PAM2_EN is set to 0, the signal to be modulated is subjected to PAM4 modulation. At this time, under the timing control of CK2, the first 2:1 serializer module and the second 2:1 serializer module respectively perform 2:1 serialization to obtain the S1 signal and the S2 signal with twice the input data rate. The PAM2_EN set to 0 enables the signal to control the first selector to select the S2 signal (i.e., the PAM4 signal) as the S3 signal to enter the subsequent selection circuit.

[0036] (3) When the first control signal PAM3_EN is set to 1, the signal to be modulated is subjected to PAM3 modulation. At this time, D0 to D2 are input as input signals into the PAM3 encoding circuit. The PAM3 encoding circuit encodes the input signals D0 to D2 according to the following combinational logic:

[0037]

[0038] DN O = D0D1;

[0039]

[0040] Among them, UP E and UP O are identification bit signals in the current cycle of CK0, used to compare with the S1 signal and the S3 signal in the next CK0 cycle; DN E signal, MD E signal, DN O signal, MD O signal are four-way demodulation signals (i.e., PAM3 signals), entering the subsequent selection circuit, is the inversion process.

[0041] In a possible implementation, a communication link is established between the multi-mode modulation unit and the multi-mode demodulation unit through a channel.

[0042] Furthermore, after obtaining the NRZ signal, since the first control signal PAM3_EN is set to 0, the NRZ signal is driven by the third driver and the fourth driver, and superimposed and input into the channel and output to the multi-mode demodulation unit.

[0043] After obtaining the PAM4 signal, the PAM4 signal is driven by the third driver to output a large swing signal, and, driven by the fourth driver to output a small swing signal, and the two are superimposed and input into the channel and output to the multi-mode demodulation unit.

[0044] After obtaining the PAM3 signal (DN E signal, MD E signal, DN O signal, MD OAfter the signal), since the first control signal PAM3_EN is set to 1, DN E signal and DN O The signal is driven by the first driver and output as a large swing signal, MD E signal and MD O The signal is driven by the second driver and output as a small swing signal, and the two are superimposed and input into the channel and output to the multi-mode demodulation unit.

[0045] Now, the specific composition of the multi-mode demodulation unit will be described.

[0046] Figure 5 FIG. is a schematic circuit connection diagram of the multi-mode demodulation unit provided by an embodiment of the present invention. It should be noted that Figure 5 "RX_DATA" in is used to refer to the input end for receiving the modulated signal output from the multi-modulation unit. "MUX" refers to a selector, and "NRZ_EN" is another representation of the second control signal. As Figure 5 shown, the multi-mode demodulation unit includes: a reference level selection module, a comparison module, and a multi-mode demodulation module; wherein, the control end of the reference level selection module is connected to the first control signal PAM3_EN, the control end of the comparison module is connected to the first control signal PAM3_EN and the second control signal PAM2_EN, and the first input end of the comparison module is connected to the second clock signal CK2; multiple input ends of the reference level selection module are connected to multiple reference voltages, the first output end and the second output end are respectively connected to the second input end and the third input end of the comparison module, the fourth input end of the comparison module is connected to the output end of the selection driving module, multiple output ends of the comparison module are connected to multiple input ends of the multi-mode demodulation module, and the output end of the multi-mode demodulation module is used to output a demodulated signal.

[0047] Among them, the reference level selection module includes: a sixth selector and a seventh selector; the control ends of the sixth selector and the seventh selector are both connected to the first control signal PAM3_EN; the first input end of the sixth selector is connected to the reference voltage V REF_PAM3_H and the second input end is connected to the reference voltage V REF_PAM4_H , and the output end is connected to the second input end of the comparison module; the first input end of the seventh selector is connected to the reference voltage V REF_PAM3_L and the second input end is connected to the reference voltage V REF_PAM4_L , and the output end is connected to the third input end of the comparison module.

[0048] Please continue to refer to Figure 5 , the comparison module includes: a first switch, a second switch, a third switch, a first comparator, a second comparator, and a third comparator; wherein, the output end of the sixth selector is connected to the negative pole of the first comparator, the output end of the seventh selector is connected to the negative pole of the third comparator, and the negative pole of the second comparator is connected to the reference voltage VREF_M ; The output ends of the selection driving module are respectively connected to the first ends of the first switch, the second switch, and the third switch. The second end of the first switch is connected to the positive pole of the first comparator. The second end of the second switch is connected to the positive pole of the second comparator. The second end of the third switch is connected to the positive pole of the third comparator. The output end of the first comparator is respectively connected to the first input end and the fourth input end of the multi-mode demodulation module. The output end of the second comparator is connected to the third input end of the multi-mode demodulation module. The output end of the third comparator is respectively connected to the second input end and the fifth input end of the multi-mode demodulation module. The output end of the second comparator can directly output the NRZ signal. The control ends of the first comparator, the second comparator, and the third comparator are all connected to the second clock signal CK2.

[0049] Please continue to refer to Figure 5 , the multi-mode demodulation module includes: a PAM4 decoding sub-module and a PAM3 decoding sub-module; the PAM4 decoding sub-module includes: an eighth selector; the PAM3 decoding sub-module includes: a ninth selector, a tenth selector, and a logic operation unit; wherein, the output end of the first comparator is respectively connected to the first input end of the eighth selector and the input end of the ninth selector; the output end of the third comparator is respectively connected to the second input end of the eighth selector and the input end of the tenth selector; the first output end of the eighth selector is used to output a first PAM4 decoding signal, and the second output end is used to output a second PAM4 decoding signal; the two output ends of the ninth selector are connected to the first and second input ends of the logic operation unit, the two output ends of the tenth selector are connected to the third and fourth input ends of the logic operation unit, and the logic operation unit is used to output a PAM3 decoding signal.

[0050] Exemplarily, the comparison result output by the comparison module is thermometer coding, which is represented by the symbols QH, QL, and QM. Now, examples corresponding to the above situations (1), (2), and (3) are described.

[0051] (1) When the first control signal PAM3_EN is set to 0 and the second control signal PAM2_EN is set to 1, the RX_DATA receives the NRZ signal, the reference level selection module does not output the reference voltage, and the NRZ signal is compared with the externally input reference voltage V REF_M . If the comparison result is a high level, QM is output as "1" as the NRZ_DATA (or the NRZ signal). If it is a low level, QM is output as "0" as the NRZ_DATA. Correspondingly, the multi-mode demodulation module directly outputs the NRZ_DATA.

[0052] (2) When the first control signal PAM3_EN is set to 0 and the second control signal PAM2_EN is set to 0, RX_DATA receives a PAM4 signal. At this time, the voltage value of the PAM4 signal is at the highest level. If the voltage value of the PAM4 signal is greater than the reference voltage V REF_PAM4_H , the output QH is "1"; if the voltage value is greater than the reference voltage V REF_M and less than the reference voltage V REF_PAM4_H , the output QM is "1"; if the voltage value is greater than the reference voltage V REF_PAM4_L and less than the reference voltage V REF_M , the output QL is "1". Correspondingly, the PAM4 decoding sub-module outputs PAM4_MSB (the second PAM4 decoding signal) as "1" and PAM4_LSB (the first PAM4 decoding signal) as "1", that is, the demodulated signal consists of the first PAM4 decoding signal and the second PAM4 decoding signal, represented as "11".

[0053] When the voltage value of the PAM4 signal is at the second highest level, the voltage value of the PAM4 signal is less than the reference voltage V REF_PAM4_H , the output QH is "0", and correspondingly, PAM4_LSB is "0"; the remaining QM is "1", and correspondingly, the output of PAM4_MSB is "1", and the demodulated signal is represented as "10".

[0054] When the voltage value of the PAM4 signal is at the second lowest level, QH is "0". If the voltage value is greater than the reference voltage V REF_M , the output QM is "1", and correspondingly, the output of PAM4_MSB is "1"; if the voltage value is greater than the reference voltage V REF_PAM4_L , the output QL is "1", and QL is selected as the output, PAM4_LSB is "1", and the demodulated signal is represented as "01".

[0055] When the voltage value of the PAM4 signal is at the low level, QH, QL, and QM are all "0", and QL and QM are selected as the output, and the demodulated signal is represented as "00".

[0056] (3) When the first control signal PAM3_EN is set to 1, RX_DATA needs to take two consecutive minimum data periods as the input of the comparator. After comparing with the reference voltages V REF_PAM3_H and V REF_PAM3_L respectively, the level value encoding of two consecutive minimum data periods is obtained, which is QH and QL; in any data period, when RX_DATA is at the PAM3 high level, the output QH is "1" and QL is "0"; when RX_DATA is at the PAM3 medium level, the output QH is "0" and QL is "1"; when RX_DATA is at the PAM3 low level, the output QH is "0" and QL is "0".

[0057] It should be noted that the PAM3 decoding sub-module is an existing PAM3 decoding circuit, which decodes the input signal according to the following logic:

[0058]

[0059] Among them, A, B, and C are the demodulation signals of the PAM3 decoding sub-module. and are the signals after inverting H1 and H2. H1 and H2 are the low-speed signals after deserializing QH obtained by comparing RX_DATA with V REF_PAM3_H . L1 and L2 are the low-speed signals after deserializing QL obtained by comparing RX_DATA with V REF_PAM3_L . and are the inverted signals of L1 and L2. is the exclusive OR operation.

[0060] Here, the PAM3 decoding signal output by the PAM3 decoding sub-module changes from binary code "000" to "111".

[0061] Figure 6 is an example diagram of the change of the PAM3 decoding signal provided by the embodiment of the present invention. As Figure 6 shown, D0~D2 are the signals to be modulated, A, B, and C are the demodulation signals of the PAM3 decoding sub-module. The waveforms of the demodulation signals and the signals to be modulated are the same, and the delay is about 3 ns. It should be noted that since there are eight level combination methods at the sending end, the situation where the previous UI is low level and the next UI is high level is ignored at the receiving end.

[0062] The above is the specific structure description of the high-speed data transceiver circuit supporting multiple modulation methods provided by the embodiment of the present invention. To verify the working characteristics of the high-speed data transceiver circuit, simulation software is used for simulation. Figure 7 is the output eye diagram of the demodulation signal output in the NRZ working mode provided by the embodiment of the present invention. Figure 8 is the output eye diagram of the demodulation signal output in the PAM3 working mode provided by the embodiment of the present invention. Figure 9 is the output eye diagram of the demodulation signal output in the PAM4 working mode provided by the embodiment of the present invention. Based on Figure 7 , Figure 8 and Figure 9 it can be seen that the sending end of the high-speed data transceiver circuit can select different modulation methods according to the control signal and output the corresponding signals, and the receiving end can restore and decode the signals according to the modulation method, effectively improving the flexibility and adaptability of data transmission and being able to be compatible with different standards and protocols.

[0063] Aiming at the problem that existing data transceiver devices are difficult to meet the data transmission requirements of multiple modulation methods, the present invention provides a high-speed data transceiver circuit supporting multiple modulation methods. This high-speed data transceiver circuit can be integrated into a chip and has the following technical effects:

[0064] First, by dynamically adapting the multi-mode modulation and demodulation mechanism, the environmental adaptability and spectral efficiency of the system are significantly improved. Based on the collaborative management of control signals and clock signals, this solution realizes the dynamic switching of modulation types (such as three-level, four-level, and binary modulation), can automatically optimize the signal modulation method under complex channel conditions, overcomes the limitations of traditional single modulation technologies that are difficult to balance high data rate and anti-noise performance. At the same time, through the flexible configuration of the reference level selection and comparison module, the accuracy of signal demodulation under different modulation modes is ensured.

[0065] Second, by adopting a modular circuit design and a clock synchronization architecture, the integrity and reliability of signal transmission are optimized. Through the collaborative work of discrete modulation modules (PAM3, PAM4 / NRZ) and demodulation modules (reference level selection, comparison, and decoding sub-modules), combined with the multi-path signal superposition mechanism of the drive circuit, signal distortion and inter-symbol interference are effectively suppressed; at the same time, based on the periodic synchronization control of the clock signal, the timing consistency of the modulation and demodulation processes is guaranteed, avoiding the increase in bit error rate caused by timing misalignment, and achieving the balance of high speed and low bit error.

[0066] Third, through hardware reuse and signal path optimization, the system complexity and power consumption are reduced. The modulation unit multiplexes key circuits (such as serialization sub-modules, drivers) through a switch network and a selector, reducing the hardware redundancy of multi-mode switching; the demodulation unit adopts a shared comparator and a dynamic reference level injection technology, avoiding the area and power consumption overhead brought by multiple sets of independent demodulation circuits. In addition, through the closed-loop control of the modulation signal and the demodulation logic, the system is ensured to be compatible with multiple communication standards, providing a high-integration, low-cost solution for high-speed wired / wireless communication.

[0067] The above content is a further detailed description of the present invention in combination with specific preferred implementation manners. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention belongs, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, which should all be regarded as belonging to the protection scope of the present invention.

Claims

1. A high-speed data transceiver circuit supporting multiple modulation modes, characterized in that: include: A multi-mode modulation unit, a multi-mode demodulation unit, a clock signal generation unit and a control unit; wherein, The multi-mode modulation unit is used to determine the modulation type of the signal to be modulated in response to the control signal generated by the control unit, and determine the corresponding modulation period in response to the first clock signal CK1 sent by the clock signal generation unit, so as to modulate the signal to be modulated to obtain a modulated signal, and transmit the modulated signal in response to the first control signal; The multi-mode demodulation unit is used to obtain the modulated signal, select a corresponding reference level signal in response to the control signal to compare with the modulated signal to obtain a comparison result, and determine a corresponding demodulation period in response to the second clock signal CK2 sent by the clock signal generating unit to demodulate the comparison result to obtain the desired demodulated signal.

2. The high-speed data transceiver circuit supporting multiple modulation modes according to claim 1, characterized in that: The control signal includes: a first control signal PAM3_EN and a second control signal PAM2_EN; the first control signal PAM3_EN and the second control signal PAM2_EN both include a set-0 enable signal and a set-1 enable signal; The multi-mode modulation unit includes: a modulation signal selection module, a PAM3 modulation module, a PAM4 / NRZ modulation module, and a selection drive module; Among them, the control end of the modulation signal selection module and the control end of the selection driving module are both connected to the first control signal PAM3_EN, the first input end of the PAM3 modulation module and the first input end of the PAM4 / NRZ modulation module are both connected to the first clock signal, and the control end of the PAM4 / NRZ modulation module is connected to the second control signal PAM2_EN; The input end of the modulation signal selection module is connected to the signal to be modulated, the first output end is connected to the second input end of the PAM3 modulation module, the second output end is connected to the second input end of the PAM4 / NRZ modulation module, the output end of the PAM3 modulation module and the output end of the PAM4 / NRZ modulation module are both connected to the input end of the selection driving module, and the output end of the selection driving module is connected to the input end of the multi-mode demodulation unit; The modulation signal selection module is used to transmit the signal to be modulated to the PAM4 / NRZ modulation module in response to the enable signal of the first control signal PAM3_EN being set to 0, or, in response to the enable signal of the first control signal PAM3_EN being set to 1, transmit the signal to be modulated to the PAM3 modulation module; The PAM3 modulation module is used to perform PAM3 modulation on the signal to be modulated to obtain a PAM3 signal; The PAM4 / NRZ modulation module is used to perform NRZ modulation on the signal to be modulated to obtain an NRZ signal in response to the enable signal of the second control signal PAM2_EN being set to 1, or to perform PAM4 modulation on the signal to be modulated to obtain a PAM4 signal in response to the enable signal of the second control signal PAM2_EN being set to 0; The selection driving module is used to drive the PAM3 signal, the PAM4 signal or the NRZ signal in response to the set-0 enable signal or the set-1 enable signal of the first control signal PAM3_EN, so as to transmit it to the multi-mode demodulation unit.

3. The high-speed data transceiver circuit supporting multiple modulation modes according to claim 2, characterized in that: The modulation signal selection module includes a switch D0, a switch D1, a switch D2 and a switch D3; The control ends of the switch D0, the switch D1, the switch D2 and the switch D3 are all connected to the first control signal PAM3_EN; The input ends of the switch D0, the switch D1, the switch D2 and the switch D3 are all connected to the signal to be modulated; The first output end of the switch D0 is connected to the first input end of the PAM3 modulation module, the first output end of the switch D1 is connected to the second input end of the PAM3 modulation module, and the first output end of the switch D2 is connected to the third input end of the PAM3 modulation module; The second input end of the switch D0 is connected to the first input end of the PAM4 / NRZ modulation module, the second output end of the switch D1 is connected to the second input end of the PAM4 / NRZ modulation module, the second output end of the switch D2 is connected to the third input end of the PAM4 / NRZ modulation module, and the output end of the switch D3 is connected to the fourth input end of the PAM4 / NRZ module.

4. The high-speed data transceiver circuit supporting multiple modulation modes according to claim 3, characterized in that: The PAM4 / NRZ module includes: a first 2:1 serialization submodule, a second 2:1 serialization submodule and a first selector; The control end of the first selector is connected to the second control signal PAM2_EN; the first input end of the first 2:1 serialization submodule is connected to the second input end of the switch D0, the second input end is connected to the second output end of the switch D1, and the output end is connected to the first end of the first selector; The first input end of the second 2:1 serialization submodule is connected to the second output end of the switch D2, the second input end is connected to the output end of the switch D3, the output end is connected to the second end of the first selector, and the output end of the first selector and the output end of the first 2:1 serialization submodule are both connected to multiple input ends of the selection driving module.

5. The high-speed data transceiver circuit supporting multiple modulation modes according to claim 4, characterized in that: The selection and driving module includes: a second selector, a third selector, a fourth selector, a fifth selector, a first driver, a second driver, a third driver and a fourth driver; Control ends of the second selector, the third selector, the fourth selector and the fifth selector are connected to the first control signal PAM3_EN; The first to fourth output ends of the PAM3 modulation module are respectively connected to the set-1 end of the second selector, the set-1 end of the third selector, the set-1 end of the fourth selector, and the set-1 end of the fifth selector; The output end of the first 2:1 serialization submodule is connected to the set-0 end of the second selector and the set-0 end of the fourth selector respectively, and the output end of the second 2:1 serialization submodule is connected to the set-0 end of the third selector and the set-0 end of the fifth selector respectively; The output end of the second selector is connected to the input end of the first driver, the output end of the third selector is connected to the input end of the second driver, the output end of the third selector is connected to the input end of the third driver, the output end of the fourth selector is connected to the input end of the fourth driver, and the output ends of the first driver, the second driver, the third driver and the fourth driver are all connected to the input end of the multi-mode demodulation unit.

6. The high-speed data transceiver circuit supporting multiple modulation modes according to claim 2, characterized in that: The multi-mode demodulation unit comprises: a reference level selection module, a comparison module and a multi-mode demodulation module; The control end of the reference level selection module is connected to the first control signal PAM3_EN, the control end of the comparison module is connected to the first control signal PAM3_EN and the second control signal PAM2_EN, and the first input end of the comparison module is connected to the second clock signal CK2; The multiple input terminals of the reference level selection module are connected to multiple reference voltages, the first output terminal and the second output terminal are respectively connected to the second input terminal and the third input terminal of the comparison module, the fourth input terminal of the comparison module is connected to the output terminal of the selection driving module, the multiple output terminals of the comparison module are connected to the multiple input terminals of the multi-mode demodulation module, and the output terminal of the multi-mode demodulation module is used to output the demodulated signal.

7. The high-speed data transceiver circuit supporting multiple modulation modes according to claim 6, characterized in that: The reference level selection module includes: a sixth selector and a seventh selector; The control end of the sixth selector and the control end of the seventh selector are both connected to the first control signal PAM3_EN; The first input terminal of the sixth selector is connected to the reference voltage V REF_PAM3_H , the second input terminal is connected to the reference voltage V REF_PAM4_H , an output end is connected to the second input end of the comparison module; The first input terminal of the seventh selector is connected to the reference voltage V REF_PAM3_L , the second input terminal is connected to the reference voltage V REF_PAM4_L , the output end is connected to the third input end of the comparison module.

8. The high-speed data transceiver circuit supporting multiple modulation modes according to claim 7, characterized in that: The comparison module includes: a first switch, a second switch, a third switch, a first comparator, a second comparator and a third comparator; The output end of the sixth selector is connected to the negative electrode of the first comparator, the output end of the seventh selector is connected to the negative electrode of the third comparator, and the negative electrode of the second comparator is connected to the reference voltage V REF_M ; The output end of the selection driving module is respectively connected to the first end of the first switch, the first end of the second switch and the first end of the third switch, the second end of the first switch is connected to the positive electrode of the first comparator, the second end of the second switch is connected to the positive electrode of the second comparator, and the second end of the third switch is connected to the positive electrode of the third comparator; The output end of the first comparator is connected to the first input end and the fourth input end of the multi-mode demodulation module respectively, the output end of the second comparator is connected to the third input end of the multi-mode demodulation module, and the output end of the third comparator is connected to the second input end and the fifth input end of the multi-mode demodulation module respectively; the output end of the second comparator can directly output the NRZ signal; Control terminals of the first comparator, the second comparator and the third comparator are all connected to the second clock signal CK2.

9. The high-speed data transceiver circuit supporting multiple modulation modes according to claim 8, characterized in that: The multi-mode demodulation module includes: a PAM4 decoding submodule and a PAM3 decoding submodule; the PAM4 decoding submodule includes: an eighth selector; the PAM3 decoding submodule includes: a ninth selector, a tenth selector and a logic operator; Wherein, the output terminal of the first comparator is connected to the first input terminal of the eighth selector and the input terminal of the ninth selector respectively; The output terminal of the third comparator is connected to the second input terminal of the eighth selector and the input terminal of the tenth selector respectively; The first output end of the eighth selector is used to output the first PAM4 decoded signal, and the second output end is used to output the second PAM4 decoded signal; The two output ends of the ninth selector are connected to the first and second input ends of the logic operator, and the two output ends of the tenth selector are connected to the third and fourth input ends of the logic operator, and the logic operator is used to output a PAM3 decoded signal.

10. The high-speed data transceiver circuit supporting multiple modulation modes according to claim 1, characterized in that: A communication link is established between the multi-mode modulation unit and the multi-mode demodulation unit via a channel.

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