Pixel circuit and low-light signal value reading method

Abstract

The invention provides a pixel circuit and a low-light signal value reading method, and the pixel circuit comprises a photodiode, a transmission transistor, a dual-conversion gain transistor, a reset transistor, and a voltage conversion unit. The voltage conversion unit is provided with a first voltage input end, a second voltage input end and a voltage output end, the first voltage input end is coupled to the first voltage line, the second voltage input end is coupled to the reset voltage line, and the voltage output end is coupled to the second end of the transverse overflow capacitor; in the high conversion gain reading stage of the pixel circuit, the voltage output end outputs the voltage of the first voltage line, and the output voltage of the first voltage line is higher than the output voltage of the reset voltage line; wherein the high-conversion gain reading stage is used for reading a low-light signal value. According to the pixel circuit, in a low-light environment, image charges can be prevented from flowing back to the photodiode due to insufficient capacitance of the first floating diffusion part, and the accuracy of a low-light signal value read by the pixel circuit in the low-light environment is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of pixel circuits, and more particularly, to a pixel circuit and a method for reading low-light signal values. Background Art

[0002] An image sensor is an electronic device that converts optical signals into electrical signals. It is an important part of modern optoelectronic technology and is widely used in devices such as cameras, webcams, smartphones, and drones. The core function of an image sensor is to capture light and generate corresponding image data, and its performance directly affects the imaging quality. An image sensor usually includes a plurality of pixel circuits, and each pixel circuit is responsible for sensing the light intensity at its corresponding position. Inside the pixel circuit, there are usually a photodiode (PD), multiple transistors, and related circuit structures for completing the acquisition, storage, reading, and transmission of optical signals.

[0003] According to related technologies, in low-light environments, pixel circuits usually read low-light signal values in a high conversion gain (HCG) mode. Specifically, the high conversion gain mode can increase the sensitivity of the sensor by increasing the voltage change caused by a unit charge (i.e., the CG value), making it easier to detect weak optical signals.

[0004] In the readout operation of the high conversion gain mode of the pixel circuit, a reasonably high floating diffusion voltage is crucial for smoothly transferring image charges from the photodiode to the floating diffusion through a high lateral electric field, which can prevent image charges from flowing back to the photodiode due to the too small capacitance of the floating diffusion. However, in related technologies, the floating diffusion voltage is insufficient, resulting in image charges flowing back to the photodiode, thereby affecting the accuracy of the low-light signal values read by the pixel circuit in low-light environments.

[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] In view of this, the present disclosure provides a pixel circuit and a method for reading low-light signal values to at least solve the problem that the low-light signal values read in the high conversion gain mode of existing pixel circuits are inaccurate.

[0007] In one aspect, embodiments of the present disclosure provide a pixel circuit for use in an image sensor, comprising: a photodiode configured to generate image charges in response to incident light; a first floating diffusion and a second floating diffusion, the first floating diffusion and the second floating diffusion being coupled to receive image charges from the photodiode; a transfer transistor coupled between the photodiode and the first floating diffusion, the transfer transistor being configured to transfer image charges from the photodiode to the first floating diffusion; a dual conversion gain transistor coupled between the first floating diffusion and the second floating diffusion; a reset transistor coupled between a reset voltage line and the second floating diffusion; a lateral overflow capacitor having a first end coupled to the second floating diffusion, the lateral overflow capacitor being configured to store image charges overflowing from the second floating diffusion; a voltage conversion unit having a first voltage input terminal, a second voltage input terminal, and a voltage output terminal, the first voltage input terminal being coupled to a first voltage line, the second voltage input terminal being coupled to the reset voltage line, and the voltage output terminal being coupled to a second end of the lateral overflow capacitor; in a high conversion gain readout phase of the pixel circuit, the voltage output terminal outputs the voltage of the first voltage line, and the output voltage of the first voltage line is higher than the output voltage of the reset voltage line; wherein, the high conversion gain readout phase is used to read low light signal values.

[0008] In some embodiments, the voltage conversion unit comprises:

[0009] a clock signal generation module for generating non-overlapping first and second clock signals under the action of a first control signal and a second control signal;

[0010] a first transistor having a first end coupled to the second voltage input terminal, a second end coupled to the voltage output terminal, and a gate receiving the second clock signal;

[0011] a second transistor having a first end coupled to a third voltage input terminal of the voltage conversion unit, a second end coupled to the voltage output terminal, and a gate receiving the first clock signal; wherein, the third voltage input terminal is coupled to a second voltage line, and the output voltage of the second voltage line is lower than the output voltage of the reset voltage line;

[0012] a third transistor having a first end coupled to the first voltage input terminal, a second end coupled to the voltage output terminal, and a gate receiving the second control signal through a first NOT gate.

[0013] In some embodiments, the pixel circuit further comprises:

[0014] a source follower having a first end coupled to the reset voltage line and a gate coupled to the first floating diffusion;

[0015] The row selection transistor, the first end of the row selection transistor is coupled to the second end of the source follower.

[0016] In some embodiments, the ratio of the lateral overflow capacitance value to the floating equivalent capacitance value is greater than or equal to 0.8; wherein, the lateral overflow capacitance value is the capacitance value of the lateral overflow capacitance, and the floating equivalent capacitance value is the sum of the equivalent capacitance values on the first floating diffusion part, the second floating diffusion part and the capacitance value of the lateral overflow capacitance.

[0017] On the other hand, an embodiment of the present disclosure further provides a method for reading a low light signal value, which is applied to the foregoing pixel circuit, and includes: a first shutter stage, clearing the image charges in the first floating diffusion part, the second floating diffusion part, the lateral overflow capacitance and the photodiode; an integration stage, the photodiode generates image charges in response to incident light, and the image charges are stored in at least one or a combination of at least one of the first floating diffusion part, the second floating diffusion part and the lateral overflow capacitance; a high conversion gain readout stage, connecting the first floating diffusion part, the second floating diffusion part and the lateral overflow capacitance and collecting the first voltage value of the first floating diffusion part, connecting the photodiode and the first floating diffusion part to enable the image charges in the photodiode to enter the first floating diffusion part, and collecting the second voltage value of the first floating diffusion part, calculating the difference between the second voltage value and the first voltage value as the low light signal value; wherein, in the high conversion gain readout stage, the voltage output terminal outputs the voltage of the first voltage line, and the output voltage of the first voltage line is higher than the output voltage of the reset voltage line; wherein, the high conversion gain readout stage is used to read the low light signal value.

[0018] In some embodiments, after the high conversion gain readout stage, the method for reading the low light signal value further includes:

[0019] A lateral overflow readout stage, connecting the photodiode and the first floating diffusion part to enable the image charges in the photodiode to enter the first floating diffusion part, then connecting the first floating diffusion part, the second floating diffusion part and the lateral overflow capacitance and collecting the third voltage value of the first floating diffusion part, clearing the image charges in the first floating diffusion part, the second floating diffusion part and the lateral overflow capacitance, connecting the first floating diffusion part, the second floating diffusion part and the lateral overflow capacitance and collecting the fourth voltage value of the first floating diffusion part, calculating the difference between the third voltage value and the fourth voltage value as the high light signal value;

[0020] A second shutter stage, clearing the image charges in the first floating diffusion part, the second floating diffusion part, the lateral overflow capacitance and the photodiode.

[0021] In some embodiments, in the first shutter stage and the second shutter stage, the voltage output terminal outputs the voltage of the reset voltage line;

[0022] Turn on the transfer transistor, the dual conversion gain transistor, and the reset transistor to clear the image charges in the first floating diffusion section, the second floating diffusion section, the horizontal overflow capacitor, and the photodiode.

[0023] In some embodiments, during the integration phase, the voltage output terminal outputs the voltage of the second voltage line;

[0024] The transfer transistor, the dual conversion gain transistor, and the reset transistor are all in the off state;

[0025] When there is an image charge overflow in the photodiode, the overflowed image charges are collected by at least one or a combination of the first floating diffusion section, the second floating diffusion section, and the horizontal overflow capacitor in sequence.

[0026] In some embodiments, during the high conversion gain readout phase, turn off the transfer transistor and the reset transistor, and turn on the dual conversion gain transistor to connect the first floating diffusion section, the second floating diffusion section, and the horizontal overflow capacitor;

[0027] Turn on the transfer transistor, turn off the dual conversion gain transistor and the reset transistor to connect the photodiode and the first floating diffusion section.

[0028] In some embodiments, during the horizontal overflow readout phase, the voltage output terminal outputs the voltage of the reset voltage line;

[0029] Turn on the transfer transistor and the dual conversion gain transistor, turn off the reset transistor to connect the photodiode, the first floating diffusion section, the second floating diffusion section, and the horizontal overflow capacitor;

[0030] Turn off the transfer transistor and the reset transistor, turn on the dual conversion gain transistor to connect the first floating diffusion section, the second floating diffusion section, and the horizontal overflow capacitor and collect the third voltage value of the first floating diffusion section;

[0031] Turn on the transfer transistor, the dual conversion gain transistor, and the reset transistor to clear the image charges in the photodiode, the first floating diffusion section, the second floating diffusion section, and the horizontal overflow capacitor;

[0032] Turn off the transfer transistor, turn on the dual conversion gain transistor and the reset transistor to connect the first floating diffusion section, the second floating diffusion section, and the horizontal overflow capacitor and collect the fourth voltage value of the first floating diffusion section;

[0033] Turn off the transfer transistor, turn on the dual conversion gain transistor and the reset transistor to connect the first floating diffusion section, the second floating diffusion section, and the horizontal overflow capacitor and collect the fourth voltage value of the first floating diffusion section.

[0034] Compared with the prior art, the present disclosure has at least the following technical effects:

[0035] The pixel circuit and the method for reading low-light signal values of the present disclosure increase a voltage conversion unit in the pixel circuit, and the voltage output terminal of the voltage conversion unit is coupled to the second terminal of the lateral overflow capacitor. During the high conversion gain readout stage of the pixel circuit, the voltage output terminal outputs the voltage of the first voltage line, and the output voltage of the first voltage line is higher than the output voltage of the reset voltage line. Thus, during the high conversion gain readout stage of the pixel circuit, the voltage change value at the second terminal of the lateral overflow capacitor can be increased compared with the prior art. Also, since the voltage change value at the second terminal of the lateral overflow capacitor is proportional to the voltage change value of the first floating diffusion part, the above setting can increase the voltage of the first floating diffusion part during the high conversion gain readout stage of the pixel circuit. Therefore, in a low-light environment, it can avoid the image charge from flowing back to the photodiode due to insufficient capacitance of the first floating diffusion part, and improve the accuracy of the low-light signal value read by the pixel circuit in a low-light environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0037] Figure 1 is a schematic structural diagram of a pixel circuit in the related art;

[0038] Figure 2 is a schematic structural diagram of another pixel circuit in the related art;

[0039] Figure 3 is a schematic structural diagram of a pixel circuit provided by an embodiment of the present disclosure;

[0040] Figure 4 is Figure 3 a schematic circuit diagram of the voltage conversion unit in

[0041] Figure 5 is Figure 3 a working waveform diagram of the pixel circuit in

[0042] Figure 6 is Figure 4 a working waveform diagram of the voltage conversion unit in

[0043] Figure 7 is Figure 4 another working waveform diagram of the voltage conversion unit in

[0044] Reference Signs:

[0045] PD, photodiode;

[0046] FD1, first floating diffusion region;

[0047] FD2, second floating diffusion region;

[0048] TX, transfer transistor;

[0049] DCG, dual conversion gain transistor;

[0050] RST, reset transistor;

[0051] CMIM, lateral overflow capacitor;

[0052] SC, voltage conversion unit;

[0053] CKG, clock signal generation module;

[0054] CS1, first control signal;

[0055] CS2, second control signal;

[0056] CKP, first clock signal;

[0057] CKN, second clock signal;

[0058] VCAP, voltage output terminal;

[0059] VDD, reset voltage line;

[0060] VQQ, first voltage line;

[0061] VCAP_Lo, second voltage line;

[0062] M1, first transistor;

[0063] M2, second transistor;

[0064] M3, third transistor;

[0065] SF, source follower;

[0066] SEL, row select transistor;

[0067] T1, first shutter phase;

[0068] T2, integration phase;

[0069] T3, high conversion gain readout phase;

[0070] T4, lateral overflow readout phase;

[0071] T5, second shutter phase. Detailed implementation manners

[0072] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their repetitive description will be omitted.

[0073] The terms "first", "second", and the like used in the specific description do not denote any order, quantity, or importance, but are merely used to distinguish different components. In addition, in the description of the present disclosure, the orientation or positional relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings, which is only for convenience of description and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present disclosure.

[0074] It should be noted that, without conflict, the features in the embodiments of the present disclosure and those in different embodiments can be combined with each other.

[0075] An image sensor is an electronic device that converts optical signals into electrical signals, which is an important part of modern optoelectronic technology and is widely used in devices such as cameras, webcams, smartphones, and drones. The core function of an image sensor is to capture light and generate corresponding image data, and its performance directly affects the imaging quality. An image sensor usually includes a plurality of pixel circuits, and each pixel circuit is responsible for sensing the light intensity at its corresponding position. Inside the pixel circuit, there are usually a photodiode, a plurality of transistors, and related circuit structures for completing the acquisition, storage, reading, and transmission of optical signals.

[0076] In a low-light environment, the pixel circuit usually reads the low-light signal value in a high conversion gain mode. Specifically, the high conversion gain mode can increase the sensitivity of the sensor by increasing the voltage change caused by a unit charge (i.e., the CG value), making it easier to detect weak optical signals.

[0077] In the readout operation of the high conversion gain mode of the pixel circuit, a reasonably high floating diffusion section voltage is crucial for smoothly transferring the image charge from the photodiode to the floating diffusion section through a high lateral electric field, and can prevent the image charge from flowing back to the photodiode due to the too small capacitance of the floating diffusion section. However, in the related art, the voltage of the floating diffusion section is insufficient, resulting in the image charge flowing back to the photodiode, thereby affecting the accuracy of the low-light signal value read by the pixel circuit in a low-light environment.

[0078] In the related art, there are the following two methods to increase the voltage of the floating diffusion section in the readout operation of the high conversion gain mode:

[0079] First, increase the output voltage of the reset voltage line. Specifically, in a pixel circuit structure as shown in Figure 1 a pixel circuit structure, it includes: a photodiode PD, a transfer transistor TX, a dual conversion gain transistor DCG, a reset transistor RST, a source follower SF, and a row selection transistor SEL. That is, increase the output voltage of the reset voltage line VDD in this pixel circuit, and then the voltage of the floating diffusion part can be increased in the high conversion gain readout stage. However, increasing the output voltage of the reset voltage line VDD will increase the power consumption of the pixel circuit. More importantly, since this pixel circuit shares the reset voltage line VDD with the analog circuit, increasing the output voltage of the reset voltage line VDD will affect the reliability of this pixel circuit and the analog circuit.

[0080] Second, in a pixel circuit structure as shown in Figure 2 a pixel circuit structure, by using the MoM (metal-metal capacitor) technology to increase the parasitic capacitance (i.e., the first capacitor C1) between the transfer transistor TX and the floating diffusion part FD, or the parasitic capacitance between the row selection transistor SEL and the floating diffusion part FD, so as to increase the coupling ratio between the transfer transistor TX and the floating diffusion part FD or the row selection transistor SEL and the floating diffusion part FD, and then the voltage of the floating diffusion part can be increased in the high conversion gain readout stage. Or, in a pixel circuit structure as shown in Figure 2 a pixel circuit structure, add an FDB signal line, and increase the coupling capacitance (i.e., the second capacitor C2) between the FDB signal line and the floating diffusion part FD by using the MoM (metal-metal capacitor) technology, and then the voltage of the floating diffusion part can be increased in the high conversion gain readout stage. However, increasing the voltage of the floating diffusion part FD in the above way has the following disadvantages: First, increasing the first capacitor C1 and the second capacitor C2 has limited effect on increasing the voltage of the floating diffusion part FD; second, the increased first capacitor C1 and second capacitor C2 will reduce the voltage change caused by a unit charge (i.e., the CG value), thus reducing the noise performance of the pixel circuit.

[0081] In view of this, on the one hand, as shown in Figure 3 a pixel circuit provided by an embodiment of the present disclosure is applied to an image sensor, and includes: a photodiode PD, a first floating diffusion part FD1, a second floating diffusion part FD2, a transfer transistor TX, a dual conversion gain transistor DCG, a reset transistor RST, a lateral overflow capacitor CMIM, and a voltage conversion unit SC.

[0082] Among them, the photodiode PD is configured to generate image charges in response to incident light. The first floating diffusion section FD1 and the second floating diffusion section FD2 are coupled to receive image charges from the photodiode PD. The transfer transistor TX is coupled between the photodiode PD and the first floating diffusion section FD1, and the transfer transistor TX is configured to transfer the image charges from the photodiode PD to the first floating diffusion section FD1. The dual conversion gain transistor DCG is coupled between the first floating diffusion section FD1 and the second floating diffusion section FD2. The reset transistor RST is coupled between the reset voltage line VDD and the second floating diffusion section FD2. The first end of the lateral overflow capacitor CMIM is coupled to the second floating diffusion section FD2, and the lateral overflow capacitor CMIM is configured to store the image charges overflowing from the second floating diffusion section FD2. The voltage conversion unit SC has a first voltage input terminal, a second voltage input terminal, and a voltage output terminal VCAP. The first voltage input terminal is coupled to the first voltage line VQQ, the second voltage input terminal is coupled to the reset voltage line VDD, and the voltage output terminal VCAP is coupled to the second end of the lateral overflow capacitor CMIM.

[0083] Specifically, the first end of the photodiode PD is coupled to the first end of the transfer transistor TX. The second end of the transfer transistor TX is coupled to the first floating diffusion section FD1. The first end of the dual conversion gain transistor DCG is coupled to the first floating diffusion section FD1, and the second end is coupled to the second floating diffusion section FD2. The first end of the reset transistor RST is coupled to the second floating diffusion section FD2, and the second end is coupled to the reset voltage line VDD. The first end of the lateral overflow capacitor CMIM is coupled to the second floating diffusion section FD2, and the second end is coupled to the voltage output terminal VCAP of the voltage conversion unit SC. The voltage conversion unit SC has a first voltage input terminal, a second voltage input terminal, and a voltage output terminal VCAP. The first voltage input terminal is coupled to the first voltage line VQQ, the second voltage input terminal is coupled to the reset voltage line VDD, and the voltage output terminal VCAP is coupled to the second end of the lateral overflow capacitor CMIM.

[0084] Further, in the high conversion gain readout stage T3 of the pixel circuit, the voltage output terminal VCAP outputs the voltage of the first voltage line VQQ, and the output voltage of the first voltage line VQQ is higher than the output voltage of the reset voltage line VDD; among them, the high conversion gain readout stage T3 is used to read the low light signal value. Specifically, the high conversion gain mode can increase the sensitivity of the sensor by increasing the voltage change caused by a unit charge (i.e., the CG value), making it easier to detect weak light signals and facilitating the reading of low light signal values. The low light signal value is also the voltage change value of the first floating diffusion section FD1 caused by the image circuit generated by the photodiode PD read out in the high conversion gain readout stage T3 of the pixel circuit in a low light environment.

[0085] In this embodiment, a voltage conversion unit SC is added to the pixel circuit, and the voltage output terminal VCAP of the voltage conversion unit SC is coupled to the second end of the lateral overflow capacitor CMIM. During the high conversion gain readout stage T3 of the pixel circuit, the voltage output terminal VCAP outputs the voltage of the first voltage line VQQ, and the output voltage of the first voltage line VQQ is higher than the output voltage of the reset voltage line VDD. Therefore, during the high conversion gain readout stage T3 of the pixel circuit, the voltage change value at the second end of the lateral overflow capacitor CMIM can be increased compared with the prior art. Also, since the voltage change value at the second end of the lateral overflow capacitor CMIM is proportional to the voltage change value of the first floating diffusion portion FD1, the above setting can increase the voltage of the first floating diffusion portion FD1 during the high conversion gain readout stage T3 of the pixel circuit. Thus, in a low light environment, it can avoid the image charge flowing back to the photodiode PD due to insufficient capacitance of the first floating diffusion portion FD1, and improve the accuracy of the low light signal value read by the pixel circuit in a low light environment. In addition, since this embodiment does not add or increase capacitance, this embodiment does not reduce the CG value (i.e., the voltage change caused by a unit charge), ensuring the accuracy of the low light signal value.

[0086] In some embodiments, such as Figure 4As shown, the voltage conversion unit SC includes: a clock signal generation module CKG, a first transistor M1, a second transistor M2, and a third transistor M3. Among them, the clock signal generation module CKG is used to generate non-overlapping first clock signal CKP and second clock signal CKN under the action of the first control signal CS1 and the second control signal CS2. The first end of the first transistor M1 is coupled to the second voltage input terminal, the second end is coupled to the voltage output terminal VCAP, and the gate inputs the second clock signal CKN. The first end of the second transistor M2 is coupled to the third voltage input terminal of the voltage conversion unit SC, the second end is coupled to the voltage output terminal VCAP, and the gate inputs the first clock signal CKP; wherein, the third voltage input terminal is coupled to the second voltage line VCAP_Lo, and the output voltage of the second voltage line VCAP_Lo is lower than the output voltage of the reset voltage line VDD. The first end of the third transistor M3 is coupled to the first voltage input terminal, the second end is coupled to the voltage output terminal VCAP, and the gate inputs the second control signal CS2 through the first NOT gate N1. Specifically, the voltage output terminal VCAP of the voltage conversion unit SC can output the voltages of the reset voltage line VDD, the first voltage line VQQ, and the second voltage line VCAP_Lo at different stages of the pixel circuit respectively. Through the above circuit in this embodiment, it can be realized that at the high conversion gain readout stage T3 of the pixel circuit, the voltage output terminal VCAP of the voltage conversion unit SC outputs the voltage of the first voltage line VQQ, that is, the voltage of the first end of the horizontal overflow capacitor CMIM at the high conversion gain readout stage T3 is the voltage of the first voltage line VQQ. Compared with the prior art, the voltage of the first end of the horizontal overflow capacitor CMIM at the high conversion gain readout stage T3 is the output voltage of the reset voltage line VDD, and the output voltage of the first voltage line VQQ is higher than the output voltage of the reset voltage line VDD. Therefore, the voltage change value of the second end of the horizontal overflow capacitor CMIM is proportional to the voltage change value of the first floating diffusion portion FD1, and the voltage of the first floating diffusion portion FD1 can be increased at the high conversion gain readout stage T3 of the pixel circuit.

[0087] In some embodiments, with continued reference to Figure 4 , the voltage conversion unit SC further includes: a sixth NOT gate N6. Its specific connection relationship is as Figure 4 shown.

[0088] In some embodiments, with continued reference to Figure 4 , the clock signal generation module CKG includes: a second NOT gate N2, a third NOT gate N3, a fourth NOT gate N4, a fifth NOT gate N5, a first NAND gate NA1, a second NAND gate NA2, a first NOR gate NOR1, a second NOR gate NOR2, a first buffer Buffer1, and a second buffer Buffer2. The connection relationship of the above components is as Figure 4As shown. Through the circuit design of the above-mentioned clock signal generation module CKG in this embodiment, non-overlapping first clock signal CKP and second clock signal CKN can be generated under the input control of the first control signal CS1 and the second control signal CS2. Furthermore, the voltage output terminal VCAP of the voltage conversion unit SC outputs the voltages of the reset voltage line VDD, the first voltage line VQQ, and the second voltage line VCAP_Lo at different stages of the pixel circuit respectively under the input control of the first control signal CS1 and the second control signal CS2.

[0089] In some embodiments, continuing to refer to Figure 3 , the pixel circuit further includes: a source follower SF and a row selection transistor SEL. Among them, the first end of the source follower SF is coupled to the reset voltage line VDD, and the gate is coupled to the first floating diffusion portion FD1. The first end of the row selection transistor SEL is coupled to the second end of the source follower SF. The source follower SF is used to read the voltage signal of the first floating diffusion portion FD1.

[0090] In some embodiments, the ratio of the value of the lateral overflow capacitor CMIM to the value of the floating equivalent capacitor is greater than or equal to 0.8. Wherein, the value of the lateral overflow capacitor CMIM is the capacitance value of the lateral overflow capacitor CMIM, and the value of the floating equivalent capacitor is the sum of the equivalent capacitance values on the first floating diffusion portion FD1, the second floating diffusion portion FD2, and the capacitance value of the lateral overflow capacitor CMIM. Specifically, the ratio of the value of the lateral overflow capacitor CMIM to the value of the floating equivalent capacitor can be any value among 0.8, 0.85, 0.9, 0.92, 0.95, 0.98, or 0.99, and the present disclosure does not limit this. Further, since the voltage change value (i.e., ΔVCAP) at the second end of the lateral overflow capacitor CMIM is proportional to the voltage change value (i.e., ΔFD1) of the first floating diffusion portion FD1, and the ratio of the value of the lateral overflow capacitor CMIM to the value of the floating equivalent capacitor is the proportionality coefficient of the proportionality between ΔVCAP and ΔFD1. Therefore, this embodiment can effectively utilize the large capacitance value of the lateral overflow capacitor CMIM to boost the voltage of the first floating diffusion portion FD1, and the voltage boosting efficiency of the first floating diffusion portion FD1 is much higher than that of the prior art.

[0091] On the other hand, as Figure 3 and Figure 5 shown, the embodiments of the present disclosure also provide a method for reading a low light signal value, which is applied to the aforementioned pixel circuit. The method for reading a low light signal value at least includes the following stages:

[0092] The first shutter stage T1, clearing the image charges in the first floating diffusion portion FD1, the second floating diffusion portion FD2, the lateral overflow capacitor CMIM, and the photodiode PD.

[0093] During the integration phase T2, the photodiode PD generates image charges in response to incident light, and the image charges are stored in at least one or a combination of more than one of the first floating diffusion portion FD1, the second floating diffusion portion FD2, and the lateral overflow capacitor CMIM.

[0094] During the high conversion gain readout phase T3, the first floating diffusion portion FD1, the second floating diffusion portion FD2, and the lateral overflow capacitor CMIM are connected, and the first voltage value of the first floating diffusion portion FD1 is acquired. The photodiode PD and the first floating diffusion portion FD1 are connected so that the image charges in the photodiode PD enter the first floating diffusion portion FD1, and the second voltage value of the first floating diffusion portion FD1 is acquired. The difference between the second voltage value and the first voltage value is calculated as the low light signal value.

[0095] Wherein, during the high conversion gain readout phase T3, the voltage output terminal VCAP outputs the voltage of the first voltage line VQQ, and the output voltage of the first voltage line VQQ is higher than the output voltage of the reset voltage line VDD; wherein, the high conversion gain readout phase T3 is used to read the low light signal value.

[0096] In this embodiment, by adding a voltage conversion unit SC in the pixel circuit and coupling the voltage output terminal VCAP of the voltage conversion unit SC to the second end of the lateral overflow capacitor CMIM, during the high conversion gain readout phase T3 of the pixel circuit, the voltage output terminal VCAP outputs the voltage of the first voltage line VQQ, and the output voltage of the first voltage line VQQ is higher than the output voltage of the reset voltage line VDD. Furthermore, it can be made that the voltage change value at the second end of the lateral overflow capacitor CMIM during the high conversion gain readout phase T3 of the pixel circuit is increased compared with the prior art. Also, since the voltage change value at the second end of the lateral overflow capacitor CMIM is proportional to the voltage change value of the first floating diffusion portion FD1, the above setting can increase the voltage of the first floating diffusion portion FD1 during the high conversion gain readout phase T3 of the pixel circuit. Thus, it can avoid the image charges flowing back to the photodiode PD due to the insufficient capacitance of the first floating diffusion portion FD1 in a low light environment, and improve the accuracy of the low light signal value read by the pixel circuit in a low light environment.

[0097] In some embodiments, with continued reference to Figure 3 and Figure 5 , for the method of reading the low light signal value, after the high conversion gain readout phase T3, it further includes:

[0098] During the horizontal overflow readout phase T4, the photodiode PD and the first floating diffusion section FD1 are connected to allow the image charges in the photodiode PD to enter the first floating diffusion section FD1. Then, the first floating diffusion section FD1, the second floating diffusion section FD2, and the horizontal overflow capacitor CMIM are connected, and the third voltage value of the first floating diffusion section FD1 is acquired. The image charges in the first floating diffusion section FD1, the second floating diffusion section FD2, and the horizontal overflow capacitor CMIM are cleared. The first floating diffusion section FD1, the second floating diffusion section FD2, and the horizontal overflow capacitor CMIM are connected, and the fourth voltage value of the first floating diffusion section FD1 is acquired. The difference between the third voltage value and the fourth voltage value is calculated as the high light signal value;

[0099] During the second shutter phase T5, the image charges in the first floating diffusion section FD1, the second floating diffusion section FD2, the horizontal overflow capacitor CMIM, and the photodiode PD are cleared.

[0100] It can be seen that the horizontal overflow readout phase T4 is used to read out the high light signal value. Further, the method for reading the low light signal value in this embodiment simultaneously includes the high conversion gain readout phase T3 for reading out the low light signal value and the horizontal overflow readout phase T4 for reading out the high light signal value. Among them, the high conversion gain readout phase T3 is used when the pixel circuit is in a low light environment, and the horizontal overflow readout phase T4 is used when the pixel circuit is in a high light environment. That is, in the aforementioned five phases of the method for reading the low light signal value, the pixel circuit will read out two data, namely the low light signal value and the high light signal value. Finally, according to whether the current illumination environment of the pixel circuit belongs to a low light environment or a high light environment, one of the low light signal value and the high light signal value is selected as the final light signal value of the pixel circuit for the current illumination environment.

[0101] In some embodiments, continue to refer to Figure 3 and Figure 5 , during the first shutter phase T1 and the second shutter phase T5, the voltage output terminal VCAP outputs the voltage of the reset voltage line VDD. The transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST are turned on to clear the image charges in the first floating diffusion section FD1, the second floating diffusion section FD2, the horizontal overflow capacitor CMIM, and the photodiode PD.

[0102] Specifically, in the first shutter phase T1 and the second shutter phase T5, high levels are input to the gates of the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST to turn on the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST. The voltage of the reset voltage line VDD is input to the second floating diffusion section FD2, the first floating diffusion section FD1, the first end of the photodiode PD, and the first end of the lateral overflow capacitor CMIM, thereby clearing the image charges in the first floating diffusion section FD1, the second floating diffusion section FD2, the lateral overflow capacitor CMIM, and the photodiode PD to prepare for reading a new light signal value by the pixel circuit at the next moment.

[0103] In some embodiments, continuing to refer to Figure 3 and Figure 5 , in the integration phase T2, the voltage output terminal VCAP outputs the voltage of the second voltage line VCAP_Lo. The transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST are all in the off state. When there is an image charge overflow in the photodiode PD, the overflowing image charges are collected by at least one or a combination of the first floating diffusion section FD1, the second floating diffusion section FD2, and the lateral overflow capacitor CMIM in sequence.

[0104] Specifically, in the integration phase T2, low levels are input to the gates of the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST to turn off the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST. In this phase, the photodiode PD is exposed to generate image charges by photogeneration. According to the intensity of the illumination environment where the photodiode PD is located, the photodiode PD may generate different amounts of image charges. When the amount of image charges generated by the photodiode PD is small, the image charges may all be stored in the photodiode PD. When the amount of generated image charges increases, the image charges will overflow to the first floating diffusion section FD1, the second floating diffusion section FD2, and the lateral overflow capacitor CMIM in sequence, and the overflowing image charges are collected by the first floating diffusion section FD1, the second floating diffusion section FD2, and the lateral overflow capacitor CMIM in sequence.

[0105] In some embodiments, continuing to refer to Figure 3 and Figure 5 , in the high conversion gain readout phase T3, the transfer transistor TX and the reset transistor RST are turned off, and the dual conversion gain transistor DCG is turned on to connect the first floating diffusion section FD1, the second floating diffusion section FD2, and the lateral overflow capacitor CMIM; the transfer transistor TX is turned on, and the dual conversion gain transistor DCG and the reset transistor RST are turned off to connect the photodiode PD and the first floating diffusion section FD1.

[0106] Specifically, the high conversion gain readout phase T3 includes the following steps: First, a low level is input to the gates of the transfer transistor TX and the reset transistor RST to turn off the transfer transistor TX and the reset transistor RST, and a high level is input to the gate of the dual conversion gain transistor DCG to turn on the dual conversion gain transistor DCG, thereby connecting the first floating diffusion section FD1, the second floating diffusion section FD2, and the lateral overflow capacitor CMIM. And the output voltage of the voltage output terminal VCAP jumps from the low voltage of the second voltage line VCAP_Lo to the high voltage of the first voltage line VQQ, increasing the voltage change value of the second end of the lateral overflow capacitor CMIM, and further increasing the voltage change value of the first floating diffusion section FD1 to boost the voltage of the first floating diffusion section FD1, so as to gather all the noise charges to the first floating diffusion section FD1 for readout.

[0107] Second, a low level is input to the gates of the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST to turn off the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST. At this time, SHR (Sample and Hold Reset) acquisition is performed to acquire the first voltage value of the first floating diffusion section FD1. In a low light environment, since the image charges generated by the photodiode PD during the integration phase T2 are few and are all stored in the photodiode PD, this first voltage value only includes all the noise charges in the current first floating diffusion section FD1, the second floating diffusion section FD2, and the lateral overflow capacitor CMIM, and does not include the image charges generated by the photodiode PD during the integration phase T2.

[0108] Then, a high level is input to the gate of the transfer transistor TX to turn on the transfer transistor TX, and low levels are input to the gates of the dual conversion gain transistor DCG and the reset transistor RST to turn off the dual conversion gain transistor DCG and the reset transistor RST. In a low light environment, the image charges stored in the photodiode PD enter the first floating diffusion section FD1 through the transfer transistor TX at this time. At this time, the first floating diffusion section FD1 includes image charges and noise charges.

[0109] Then, a low level is input to the gates of the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST to turn off the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST. At this time, SHS (Sample and Hold Signal) acquisition is performed to acquire the second voltage value of the first floating diffusion section FD1. In a low light environment, this second voltage value includes the aforementioned image charges and noise charges.

[0110] Finally, in a low-light environment, the difference between the second voltage value (including image charge and noise charge) and the first voltage value (including noise charge) is calculated as the low-light signal value.

[0111] In this embodiment, in a low-light environment, it is possible to avoid the image charge flowing back to the photodiode PD due to the insufficient capacitance of the first floating diffusion part FD1, and improve the accuracy of the low-light signal value read out by the pixel circuit in the low-light environment.

[0112] In some embodiments, continue to refer to Figure 3 and Figure 5 , in the horizontal overflow readout stage T4, the voltage output terminal VCAP outputs the voltage of the reset voltage line VDD;

[0113] Turn on the transfer transistor TX and the dual conversion gain transistor DCG, and turn off the reset transistor RST to connect the photodiode PD, the first floating diffusion part FD1, the second floating diffusion part FD2, and the horizontal overflow capacitor CMIM;

[0114] Turn off the transfer transistor TX and the reset transistor RST, and turn on the dual conversion gain transistor DCG to connect the first floating diffusion part FD1, the second floating diffusion part FD2, and the horizontal overflow capacitor CMIM and collect the third voltage value of the first floating diffusion part FD1;

[0115] Turn on the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST to clear the image charge in the photodiode PD, the first floating diffusion part FD1, the second floating diffusion part FD2, and the horizontal overflow capacitor CMIM;

[0116] Turn off the transfer transistor TX, and turn on the dual conversion gain transistor DCG and the reset transistor RST to connect the first floating diffusion part FD1, the second floating diffusion part FD2, and the horizontal overflow capacitor CMIM and collect the fourth voltage value of the first floating diffusion part FD1.

[0117] Among them, at the end of the high conversion gain readout stage T3 and at the beginning of the horizontal overflow readout stage T4, the output voltage of the voltage output terminal VCAP jumps from the high voltage of the first voltage line VQQ to the voltage of the reset voltage line VDD to avoid that the voltage of the reset voltage line VDD in the horizontal overflow readout stage T4 cannot clear the image charge in the horizontal overflow capacitor CMIM.

[0118] Specifically, the lateral overflow readout stage T4 includes the following steps: first, the gates of the transfer transistor TX and the dual conversion gain transistor DCG are input with a high level to turn on the transfer transistor TX and the dual conversion gain transistor DCG, and the gate of the reset transistor RST is input with a low level to turn off the reset transistor RST, thereby connecting the photodiode PD, the first floating diffusion FD1, the second floating diffusion FD2 and the lateral overflow capacitor CMIM to transfer the image charge generated by the exposure of the photodiode PD in the high conversion gain readout stage T3 to the first floating diffusion FD1, so as to increase the accuracy of the data read out by the pixel circuit.

[0119] Secondly, the gates of the transfer transistor TX and the reset transistor RST are both input with a low level to turn off the transfer transistor TX and the reset transistor RST, and the gate of the dual conversion gain transistor DCG is input with a high level to turn it on. At this time, SHS (Sample and Hold Signal) is performed to collect the dual conversion gain transistor DCG to collect the third voltage value of the first floating diffusion FD1. In a high-light environment, since the image charge generated by the photodiode PD in the integration stage T2 is large, it can be stored in the pass photodiode PD, the first floating diffusion FD1, the second floating diffusion FD2, and the lateral overflow capacitor CMIM. Therefore, the third voltage value may include all the image charges in the current first floating diffusion FD1, the second floating diffusion FD2, and the lateral overflow capacitor CMIM, as well as the noise charges in the first floating diffusion FD1, the second floating diffusion FD2, and the lateral overflow capacitor CMIM.

[0120] Then, the gates of the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST are all input with a high level to turn on the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST to clear the image charge in the photodiode PD, the first floating diffusion FD1, the second floating diffusion FD2, and the lateral overflow capacitor CMIM. In a high light environment, noise charge still remains in the first floating diffusion FD1, the second floating diffusion FD2, and the lateral overflow capacitor CMIM.

[0121] Then, the gate of the transfer transistor TX inputs a low level to turn off the transfer transistor TX, and the gates of the dual conversion gain transistor DCG and the reset transistor RST input a high level to turn on the dual conversion gain transistor DCG and the reset transistor RST. At this time, SHR (Sample and Hold Reset) acquisition is performed to acquire the fourth voltage value of the first floating diffusion FD1. In a high light environment, the fourth voltage value includes the aforementioned noise charge.

[0122] Finally, in a high light environment, the difference between the third voltage value (including image charge and noise charge) and the fourth voltage value (including noise charge) is calculated as the high light signal value.

[0123] In some embodiments, continuing to refer to Figure 4 and Figure 6 , in each working stage of the pixel circuit, the voltage output situation of the voltage output terminal VCAP can be as follows in sequence:

[0124] In the first shutter stage T1, the first control signal CS1 inputs a high level, the second control signal CS2 inputs a low level, the first clock signal CKP is at a high level, the second clock signal CKN is at a low level, and finally the voltage output terminal VCAP outputs the voltage of the reset voltage line VDD;

[0125] In the integration stage T2, the first control signal CS1 inputs a low level, the second control signal CS2 inputs a low level, the first clock signal CKP is at a low level, the second clock signal CKN is at a high level, and finally the voltage output terminal VCAP outputs the voltage of the second voltage line VCAP_Lo;

[0126] In the high conversion gain readout stage T3, the first control signal CS1 inputs a high level, the second control signal CS2 inputs a high level, the first clock signal CKP is at a high level, the second clock signal CKN is at a high level, and finally the voltage output terminal VCAP outputs the voltage of the first voltage line VQQ;

[0127] In the horizontal overflow readout stage T4, the first control signal CS1 inputs a high level, the second control signal CS2 inputs a low level, the first clock signal CKP is at a high level, the second clock signal CKN is at a low level, and finally the voltage output terminal VCAP outputs the voltage of the reset voltage line VDD;

[0128] In the second shutter stage T5, the first control signal CS1 inputs a high level, the second control signal CS2 inputs a low level, the first clock signal CKP is at a high level, the second clock signal CKN is at a low level, and finally the voltage output terminal VCAP outputs the voltage of the reset voltage line VDD.

[0129] In some embodiments, continuing to refer to Figure 4 and Figure 7 , in each working stage of the pixel circuit, the voltage output situation of the voltage output terminal VCAP can be as follows in sequence:

[0130] In the first shutter stage T1, the first control signal CS1 inputs a high level, the second control signal CS2 inputs a low level, the first clock signal CKP is at a high level, the second clock signal CKN is at a low level, and finally the voltage output terminal VCAP outputs the voltage of the reset voltage line VDD;

[0131] In the integration stage T2, the first control signal CS1 inputs a low level, the second control signal CS2 inputs a low level, the first clock signal CKP is at a low level, the second clock signal CKN is at a high level, and the final voltage output terminal VCAP outputs the voltage of the second voltage line VCAP_Lo;

[0132] In the high conversion gain readout stage T3, the first control signal CS1 inputs a low level, the second control signal CS2 inputs a high level, the first clock signal CKP is at a high level, the second clock signal CKN is at a high level, and the final voltage output terminal VCAP outputs the voltage of the first voltage line VQQ;

[0133] In the horizontal overflow readout stage T4, the first control signal CS1 inputs a high level, the second control signal CS2 inputs a low level, the first clock signal CKP is at a high level, the second clock signal CKN is at a low level, and the final voltage output terminal VCAP outputs the voltage of the reset voltage line VDD;

[0134] In the second shutter stage T5, the first control signal CS1 inputs a high level, the second control signal CS2 inputs a low level, the first clock signal CKP is at a high level, the second clock signal CKN is at a low level, and the final voltage output terminal VCAP outputs the voltage of the reset voltage line VDD.

[0135] The following takes an example to specifically illustrate the pixel circuit of the present disclosure and the method for reading low-light signal values:

[0136] In the first shutter stage T1, the transfer transistor TX, the dual conversion gain transistor DCG, and the reset transistor RST are all turned on, and the voltage of the first floating diffusion portion FD1 is the voltage of the reset voltage line VDD, for example: 3.0V.

[0137] In the integration stage T2, the voltage at the second end of the horizontal overflow capacitor CMIM drops from the voltage of the reset voltage line VDD to the voltage of the second voltage line VCAP_Lo (to improve the uniformity in low-light environments), for example 1.6V. At this time, the voltage change value ΔVCAP of the reset voltage line VDD is 1.4V. Correspondingly, the voltage VFD1 of the first floating diffusion portion FD1 = VDD + ΔVCAP * CMIM / Ctotal, where CMIM is the capacitance value of the horizontal overflow capacitor CMIM, and Ctotal is the floating equivalent capacitance value, that is, the sum of the equivalent capacitance values on the first floating diffusion portion FD1, the second floating diffusion portion FD2, and the capacitance value of the horizontal overflow capacitor CMIM. For example, if CMIM / Ctotal is taken as 0.8, then at this time the voltage VFD1 of the first floating diffusion portion FD1 = 3.0V - 1.4V * 0.8 = 1.88V.

[0138] In the prior art, during the high conversion gain readout stage T3, the voltage at the second end of the lateral overflow capacitor CMIM jumps from the voltage of the second voltage line VCAP_Lo to the voltage of the reset voltage line VDD. At this time, the voltage change value ΔVCAP of the reset voltage line VDD is 1.4V, and the voltage VFD1 of the first floating diffusion section FD1 is VDD + ΔVCAP * CMIM / Ctotal = 1.88V + 1.4V * 0.8 = 3.0V.

[0139] In the present disclosure: during the high conversion gain readout stage T3, the voltage at the second end of the lateral overflow capacitor CMIM jumps from the voltage of the second voltage line VCAP_Lo to the voltage of the first voltage line VQQ. Assuming the voltage of the first voltage line VQQ is 3.5V, at this time, the voltage change value ΔVCAP of the reset voltage line VDD is 1.9V, and the voltage VFD1 of the first floating diffusion section FD1 is VDD + ΔVCAP * CMIM / Ctotal = 1.88V + 1.9V * 0.8 = 3.4V. Therefore, the voltage of the first floating diffusion section FD1 is increased.

[0140] In summary, for the pixel circuit and the method for reading a low light signal value of the present disclosure, by adding a voltage conversion unit in the pixel circuit and coupling the voltage output terminal of the voltage conversion unit to the second end of the lateral overflow capacitor, during the high conversion gain readout stage of the pixel circuit, the voltage output terminal outputs the voltage of the first voltage line, and the output voltage of the first voltage line is higher than the output voltage of the reset voltage line. Furthermore, it can be made such that the voltage change value at the second end of the lateral overflow capacitor during the high conversion gain readout stage of the pixel circuit is increased compared with the prior art. Also, since the voltage change value at the second end of the lateral overflow capacitor is proportional to the voltage change value of the first floating diffusion section, the above setting can increase the voltage of the first floating diffusion section during the high conversion gain readout stage of the pixel circuit. Thus, it can be avoided that the image charge flows back to the photodiode due to insufficient capacitance of the first floating diffusion section in a low light environment, and the accuracy of the low light signal value read by the pixel circuit in a low light environment can be improved.

[0141] The above content is a further detailed description of the present disclosure in combination with specific optional embodiments. It cannot be determined that the specific implementation of the present disclosure is only limited to these descriptions. For those of ordinary skill in the technical field to which the present disclosure pertains, without departing from the concept of the present disclosure, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present disclosure.

Claims

1. A pixel circuit, applied to an image sensor, characterized in that: include: a photodiode configured to photogenerate image charge in response to incident light; a first floating diffusion and a second floating diffusion, the first floating diffusion and the second floating diffusion coupled to receive the image charge from the photodiode; a transfer transistor coupled between the photodiode and the first floating diffusion, the transfer transistor configured to transfer the image charge from the photodiode to the first floating diffusion; a dual conversion gain transistor coupled between the first floating diffusion and the second floating diffusion; a reset transistor coupled between a reset voltage line and the second floating diffusion; a lateral overflow capacitor, a first end of which is coupled to the second floating diffusion, and the lateral overflow capacitor is configured to store the image charge overflowed from the second floating diffusion; a voltage conversion unit, the voltage conversion unit having a first voltage input terminal, a second voltage input terminal and a voltage output terminal, the first voltage input terminal is coupled to the first voltage line, the second voltage input terminal is coupled to the reset voltage line, and the voltage output terminal is coupled to the second terminal of the lateral overflow capacitor; In the high conversion gain readout stage of the pixel circuit, the voltage output terminal outputs the voltage of the first voltage line, and the output voltage of the first voltage line is higher than the output voltage of the reset voltage line; wherein the high conversion gain readout stage is used to read out the low light signal value.

2. The pixel circuit according to claim 1, characterized in that: The voltage conversion unit comprises: A clock signal generating module, the clock signal generating module being used to generate a non-overlapping first clock signal and a second clock signal under the action of a first control signal and a second control signal; A first transistor, wherein a first terminal of the first transistor is coupled to the second voltage input terminal, a second terminal of the first transistor is coupled to the voltage output terminal, and a gate of the first transistor is input with the second clock signal; a second transistor, wherein a first terminal of the second transistor is coupled to a third voltage input terminal of the voltage conversion unit, a second terminal of the second transistor is coupled to the voltage output terminal, and a gate of the second transistor inputs the first clock signal; wherein the third voltage input terminal is coupled to a second voltage line, and an output voltage of the second voltage line is lower than an output voltage of the reset voltage line; A third transistor, wherein a first terminal of the third transistor is coupled to the first voltage input terminal, a second terminal of the third transistor is coupled to the voltage output terminal, and a gate of the third transistor is input with the second control signal through a first NOT gate.

3. The pixel circuit according to claim 1, characterized in that: Also includes: a source follower, wherein a first terminal of the source follower is coupled to the reset voltage line, and a gate is coupled to the first floating diffusion; A row selection transistor, a first terminal of the row selection transistor is coupled to the second terminal of the source follower.

4. The pixel circuit according to claim 1, characterized in that: The ratio of the lateral overflow capacitance value to the floating equivalent capacitance value is greater than or equal to 0.8; wherein the lateral overflow capacitance value is the capacitance value of the lateral overflow capacitance, and the floating equivalent capacitance value is the sum of the equivalent capacitance value on the first floating diffusion portion, the equivalent capacitance value on the second floating diffusion portion, and the capacitance value of the lateral overflow capacitance.

5. A method for reading a low light signal value, applied to a pixel circuit according to any one of claims 1 to 4, characterized in that: include: In a first shutter stage, the image charges in the first floating diffusion, the second floating diffusion, the lateral overflow capacitor and the photodiode are cleared; In an integration phase, the photodiode generates the image charge in response to incident light, and the image charge is stored in at least a combination of at least one or more of the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor; In a high conversion gain readout stage, the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor are connected to collect a first voltage value of the first floating diffusion, the photodiode and the first floating diffusion are connected to allow the image charge in the photodiode to enter the first floating diffusion, and a second voltage value of the first floating diffusion is collected, and a difference between the second voltage value and the first voltage value is calculated as a low light signal value; Wherein, in the high conversion gain readout stage, the voltage output terminal outputs the voltage of the first voltage line, and the output voltage of the first voltage line is higher than the output voltage of the reset voltage line; wherein, the high conversion gain readout stage is used to read out the low light signal value.

6. The method for reading a low light signal value according to claim 5, characterized in that: After the high conversion gain readout stage, it also includes: In a lateral overflow readout stage, the photodiode and the first floating diffusion are connected to allow the image charge in the photodiode to enter the first floating diffusion, the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor are connected to each other and a third voltage value of the first floating diffusion is collected, the image charge in the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor is cleared, the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor are connected to each other and a fourth voltage value of the first floating diffusion is collected, and a difference between the third voltage value and the fourth voltage value is calculated as a high illumination signal value; In a second shutter stage, the image charges in the first floating diffusion, the second floating diffusion, the lateral overflow capacitor, and the photodiode are cleared.

7. The method for reading a low light signal value according to claim 6, characterized in that: In the first shutter stage and the second shutter stage, the voltage output terminal outputs the voltage of the reset voltage line; The transfer transistor, the dual conversion gain transistor, and the reset transistor are turned on to flush the image charge in the first floating diffusion, the second floating diffusion, the lateral overflow capacitance, and the photodiode.

8. The method for reading a low light signal value according to claim 5, characterized in that: In the integration phase, the voltage output terminal outputs the voltage of the second voltage line; The transfer transistor, the dual conversion gain transistor and the reset transistor are all in an off state; When the image charge overflows from the photodiode, the overflowed image charge is sequentially collected by a combination of at least one or more of the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor.

9. The method for reading a low light signal value according to claim 5, characterized in that: In the high conversion gain readout phase, turning off the transfer transistor and the reset transistor, and turning on the dual conversion gain transistor to connect the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor; The transfer transistor is turned on, and the dual conversion gain transistor and the reset transistor are turned off to connect the photodiode and the first floating diffusion.

10. The method for reading a low light signal value according to claim 6, characterized in that: In the lateral overflow readout stage, the voltage output terminal outputs the voltage of the reset voltage line; Turning on the transfer transistor and the dual conversion gain transistor, and turning off the reset transistor, so as to connect the photodiode, the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor; Turning off the transfer transistor and the reset transistor, and turning on the dual conversion gain transistor to connect the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor and collect a third voltage value of the first floating diffusion; turning on the transfer transistor, the dual conversion gain transistor, and the reset transistor to clear the image charge in the photodiode, the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor; Turning off the transfer transistor, and turning on the dual conversion gain transistor and the reset transistor to connect the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor and collect a fourth voltage value of the first floating diffusion; The transfer transistor is turned off, and the dual conversion gain transistor and the reset transistor are turned on to connect the first floating diffusion, the second floating diffusion, and the lateral overflow capacitor and collect a fourth voltage value of the first floating diffusion.

Images