Pixel circuit and driving method thereof

Abstract

The invention discloses a pixel circuit and a driving method thereof. A capacitor and a control switch used for controlling gear switching are additionally arranged for each pixel unit. The newly-added capacitors of the plurality of pixel units are connected and commonly used as variable capacitors, on one hand, different numbers of newly-added capacitors are coupled to the floating diffusion region according to needs to adjust the capacitance of the conversion gain, so that the conversion gain of various gears is designed, and the conversion gain of a proper gear is selected according to different scenes; the signal-to-noise ratio loss during conversion gain gear switching is reduced, and the signal-to-noise ratio of the whole image is optimized; on the other hand, the control switch is used for selecting and controlling whether the variable capacitor is connected or not, reading of different rows can be achieved at the same time, and overlapping can be covered to improve the reading speed.

Description

Technical Field

[0001] The present invention relates to the field of image sensors, and particularly to a pixel circuit and a driving method thereof. Background Art

[0002] An image sensor uses the photoelectric conversion function of optoelectronic devices in a pixel array to convert the optical image on the photosensitive surface into an electrical signal corresponding to the optical image in a proportional relationship, and then through the processing, storage, etc. of the peripheral circuit, so as to record image information. The performance requirements of image sensors are increasing day by day, and the dynamic range has become a key performance parameter of CMOS image sensors. Currently, the most commonly used method is single exposure. By using the capacitors in the pixel unit to form different levels of conversion gains, high dynamic range (HDR) is achieved by switching different levels of conversion gains.

[0003] Figure 1 The following shows an example of an existing circuit suitable for this method. The circuit of each pixel unit includes: a photodiode PD, a transfer transistor TG, a reset transistor RST, a conversion gain control transistor DCG, and a source follower SF; a metal capacitor (not shown in the figure) can also be coupled to the node between the reset transistor RST and the conversion gain control transistor DCG. Among them, the photodiode PD is used to convert the sensed incident light into charge; the transfer transistor TG is coupled between the photodiode PD and the floating diffusion region FD, and is used to selectively transfer the charge accumulated by the photodiode PD to the floating diffusion region FD. The floating diffusion region FD is used to accumulate the received charge. The conversion gain control transistor DCG is used to selectively switch between two conversion gains. By connecting or disconnecting the metal capacitor to the floating diffusion region FD, the capacitance at the floating diffusion region FD is changed (when the metal capacitor is connected, the capacitance at the floating diffusion region FD increases, and the conversion gain of the pixel unit decreases; when the metal capacitor is not connected, the capacitance at the floating diffusion region FD decreases, and the conversion gain of the pixel unit increases); the reset transistor RST is coupled to the power supply voltage VDD and is used to selectively reset the charge accumulated at the floating diffusion region FD and the photodiode PD. The source follower SF is used to amplify the potential change of the floating diffusion region FD and output a PXD signal corresponding to the amplification result.

[0004] In the circuit design of the existing solution, the circuit working timing is as follows:

[0005] Clearing electrons: RST is turned on, DCG is turned on, TG is turned on, and the electrons in PD and FD are cleared;

[0006] Integration: TG is turned off, RST is turned on, DCG is turned on;

[0007] Readout process (LHHL mode):

[0008] Read LCG reference signal: TG off, RST off, DCG on, read LCG reference signal;

[0009] Read HCG reference signal: TG off, RST off, DCG off, read HCG reference signal;

[0010] Read HCG signal: TG on, RST off, DCG off, read HCG signal;

[0011] Read LCG signal: TG on, RST off, DCG on, read LCG signal.

[0012] For the above existing circuit, it can be read out in the high conversion gain (HCG) gear in low light, and can be read out in the low conversion gain (LCG) gear in bright light; however, on the one hand, the conversion gain can only be switched between two gears with fixed capacitance values. In the design of high dynamic range, in order to simultaneously take into account the dark field and high-brightness scenarios, the capacitance difference between the two gears is large. Therefore, when switching from the HCG gear to the LCG gear, the signal-to-noise ratio will jump; in this way, for points with different brightnesses in a scene, the darker points will lose part of the signal-to-noise ratio, reducing the image quality. On the other hand, in the existing image sensors, the readout timing of pixel units in different rows cannot cover and overlap, which limits the readout speed of the entire device. Summary of the Invention

[0013] To solve the problem of signal-to-noise ratio loss caused by fixed-gear conversion gain in the prior art, the present invention proposes a new pixel circuit and its driving method. On the one hand, the newly added first capacitors of multiple pixel units are connected in common as a variable capacitor to adjust the capacitance size of the conversion gain, obtaining multiple gears of conversion gain and improving the problem of signal-to-noise ratio loss; on the other hand, a control switch is also provided to select and control whether to connect the variable capacitor, and at the same time, the readout of different rows can cover and overlap to improve the readout speed.

[0014] The present invention provides a driving method for a pixel circuit, and the pixel circuit includes: pixel units, and one or more of the pixel units form a pixel array; each pixel unit includes:

[0015] One or more photodiodes;

[0016] One or more first transistors, correspondingly connected to the one or more photodiodes; the first transistor is coupled between the corresponding photodiode and a floating diffusion region of the pixel unit;

[0017] A second transistor, coupled to the power supply voltage;

[0018] A third transistor, coupled between the floating diffusion region and the second transistor;

[0019] Each of the pixel units further includes: a control switch and a first capacitor;

[0020] One end of the control switch is connected to the connection node of the second transistor and the third transistor, and the other end of the control switch is connected to the first capacitor;

[0021] Wherein, the first capacitors of m pixel units are connected in series, m>1 and m is an integer; the gain level is controlled by controlling the number of the first capacitors in series that are turned on.

[0022] Optionally, m pixel units include p pixel units in adjacent rows and / or adjacent columns, where 1<p≤m and p is an integer.

[0023] Optionally, m pixel units include at least one column of pixel units or at least one row of pixel units.

[0024] Optionally, m pixel units include q pixel units sharing the first capacitor, and every two of the q pixel units are separated by i rows and / or j columns, where 1<q≤m and q is an integer, i≥1 and i is an integer, j≥1 and j is an integer.

[0025] Optionally, among the q pixel units, every two pixel units are separated by 1 row; in at least one column of pixel units, the first capacitors are connected in series with each other across rows, forming a first series group and a second series group.

[0026] Optionally, at least two rows of pixel units share the first capacitor, and the driving method further includes: by setting the control switch, while reading a high conversion gain signal in the previous row, starting to read a low conversion gain reference signal in the next row.

[0027] Optionally, the circuit working timing of the pixel unit includes:

[0028] Electron clearing:

[0029] The second transistor is turned on, the third transistor is turned on, the first transistor is turned on, the control switch is turned off, the first capacitor is turned off, and the electrons in the photodiode and the floating diffusion region are cleared;

[0030] Integration:

[0031] The first transistor is turned off, the second transistor is turned on, the third transistor is turned on, the control switch is turned off, the first capacitor is turned off;

[0032] Readout process, the readout process includes:

[0033] Read low conversion gain reference signal: The first transistor is turned off, the second transistor is turned off, the third transistor is turned on, the control switch is turned on, and the first capacitor of the h-th row is turned on simultaneously to read the low conversion gain reference signal;

[0034] Read high conversion gain reference signal: The first transistor is turned off, the second transistor is turned off, the third transistor is turned on, the control switch is turned on, and the first capacitor of the k-th row is turned on simultaneously to read the high conversion gain reference signal;

[0035] Read high conversion gain signal: The first transistor is turned on, the second transistor is turned off, the third transistor is turned on, the control switch is turned on, and the first capacitor of the k-th row is turned on simultaneously to read the high conversion gain signal;

[0036] Read low conversion gain signal: The first transistor is turned on, the second transistor is turned off, the third transistor is turned on, the control switch is turned on, and the first capacitor of the h-th row is turned on simultaneously to read the low conversion gain signal.

[0037] m ≥ h > k, k ≥ 1, and h is an integer less than or equal to the maximum number of rows of the pixel array, and k is an integer less than the maximum number of rows of the pixel array.

[0038] Optionally, the control switch and the first capacitor are fabricated within or outside the area of the pixel unit.

[0039] Optionally, the control switch includes a fourth transistor, the first capacitor includes a fifth transistor, and the driving method includes controlling the number of turned-on fifth transistors connected in series to control different gain levels.

[0040] Optionally, each pixel unit includes four, or eight, or nine, or sixteen of the photodiodes.

[0041] Optionally, each pixel unit further includes a second capacitor, and the second capacitor is coupled to the connection node of the second transistor and the third transistor.

[0042] Optionally, each pixel unit further includes:

[0043] A sixth transistor, the control terminal of which is connected to the floating diffusion region;

[0044] A seventh transistor, coupled between the sixth transistor and the signal output line, for selecting an output.

[0045] Optionally, the first transistor includes a transfer transistor;

[0046] The second transistor includes a reset transistor;

[0047] The third transistor includes a gain conversion transistor;

[0048] The sixth transistor includes a source follower transistor;

[0049] The seventh transistor includes a selection output transistor.

[0050] Optionally, the fourth transistor and / or the fifth transistor are fabricated synchronously with at least one of the first, second, third, sixth, and seventh transistors.

[0051] The present invention also provides a pixel circuit applied to the driving method described in any one of the above.

[0052] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In this solution, a capacitor and a control switch for controlling gear switching are newly added to each pixel unit, and the newly added capacitors of multiple pixel units are connected in common as a variable capacitor. On the one hand, different numbers of newly added capacitors are coupled to the floating diffusion region as needed to adjust the capacitance size of the conversion gain, thereby designing conversion gains of multiple gears, so as to select an appropriate conversion gain gear according to different scenarios, reduce the signal-to-noise ratio loss during the conversion gain gear switching, and optimize the signal-to-noise ratio of the entire image; on the other hand, a control switch is also provided to select and control whether to connect the variable capacitor and simultaneously enable the readout of different rows to overlap to improve the readout speed.

[0053] In an example of this solution, two transistors are newly added on the basis of the existing design of each pixel unit. The first newly added transistor is used as a control switch for controlling gear switching; the second newly added transistors of multiple pixel units are connected in series and shared as a variable capacitor. By controlling the number of the second newly added transistors turned on, the capacitance size of the conversion gain is adjusted, thereby designing conversion gains of multiple gears, selecting an appropriate low conversion gain gear according to different brightnesses, and selecting an appropriate high conversion gain gear according to the proportion of different brightness points in the same scenario, so that the signal-to-noise ratio of the entire image is optimal and the signal-to-noise ratio loss is reduced.

[0054] In an example of this solution, for multiple pixel units with shareable capacitors, by setting a control switch (such as the first newly added transistor), it is possible to control whether to enable the mode of overlapping signal readout timings; if this mode is enabled, the control switch of one pixel unit is disconnected each time to control it to enter the high conversion gain mode. In this way, while reading the high conversion gain signal of this pixel unit, the readout of the low conversion gain reference signal of the next pixel unit can be started, and so on, to accelerate the readout speed of the entire device. Description of the Drawings

[0055] The drawings of the present invention form a part of this specification and are used to further understand the present invention. The drawings show embodiments of the present invention and are used together with the specification to illustrate the principles of the present invention.

[0056] Figure 1 It is a circuit schematic diagram of each pixel unit in the pixel circuit of the prior art.

[0057] Figure 2 In the example of the present invention, it is a circuit schematic diagram of adding a control switch and a shared capacitor to each pixel unit.

[0058] Figure 3 In the example of the present invention, it is a circuit schematic diagram of adding two transistors to each pixel unit.

[0059] Figure 4 In the example of the present invention, it is a histogram reflecting the relationship between the number of pixels and the corresponding number of electrons at different brightness levels.

[0060] Figure 5a In the example of the present invention, it is a schematic diagram of the relationship between the number of electrons and the signal-to-noise ratio when selecting a low conversion gain gear.

[0061] Figure 5b In the example of the present invention, it is a schematic diagram of the relationship between the number of electrons and the signal-to-noise ratio when selecting a high conversion gain gear.

[0062] Figure 6 It is a schematic diagram for comparing the signal-to-noise ratio loss when switching the conversion gain gear according to the prior art and the example of the present invention.

[0063] Figure 7 In the example of the present invention, it is a circuit operation timing diagram when the readout processes of two rows of pixel units with a shared capacitor overlap.

[0064] Figure 8 It is a schematic diagram of the timing overlap of three rows of pixel units;

[0065] Figure 9 In the example of the present invention having a medium conversion gain mode, it is a circuit operation timing diagram when reading two rows of pixel units with a shared capacitor separately;

[0066] Figure 10 In the example of the present invention, it is a circuit schematic diagram of setting a second capacitor for the pixel unit. Detailed implementation manners

[0067] The following detailed descriptions are all illustrative and are intended to provide further explanations of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present invention belongs.

[0068] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present invention.

[0069] The present invention proposes a new pixel circuit design. Figure 2 As shown, on the basis of the design of the existing circuit, each pixel unit includes a photodiode PD, a transfer transistor TG, a reset transistor RST, a conversion gain control tube DCG, and a source follower tube SF. The present invention adds a first capacitor C and a control switch K to each pixel unit, one end of the control switch K is connected to the node between the reset transistor RST and the conversion gain control tube DCG, and the other end is connected to the first capacitor C; the first capacitor C can be selectively connected or disconnected with the node between the reset transistor RST and the conversion gain control tube DCG through the control switch K; the newly added first capacitors C of multiple pixel units are connected in series as variable capacitors of low conversion gain gears, and the capacitance size of the conversion gain is adjusted by connecting different numbers of first capacitors C, so as to select the conversion gain suitable for the current scene, reduce the signal-to-noise loss when switching the conversion gain, and optimize the signal-to-noise ratio of the entire pixel array.

[0070] Figure 2 The first capacitors C1 to C1 of m pixel units are shown. m In the case where m>1 and m is an integer, in different examples, for example, m pixel units include p pixel units, where 1 <p≤m且p为整数;这p个像素单元位于相邻的行和 / 或相邻的列,各自的第一电容C可以串联并共用。又例如,m个像素单元包括至少一列或至少一行像素单元,可以将它们的第一电容C串联并共用。又例如,m个像素单元包括q个像素单元,其中的每两个像素单元之间间隔i行和 / 或间隔j列,1<q≤m且q为整数,i≥1且i为整数,j≥1且j为整数;即,隔开若干行和 / 或若干列的像素单元可以把各自的第一电容C串联在一起共用。

[0071] Figure 3 FIG. 1 is an example of a pixel circuit according to the present invention. Figure 3 The description is made by taking pixel units in the same column but different rows as an example, showing pixel units in the nth row, n+1th row, and n+2th row in the same column (the same-named devices of each pixel unit are distinguished by different subscripts).

[0072] Each pixel unit of the present invention is provided with a photodiode PD, a transfer transistor TG, a reset transistor RST, a conversion gain control transistor DCG, and a source follower SF. Additionally, two transistors T1 and T2 are newly added to each pixel unit. Transistor T1 serves as a control switch for controlling gear shifting. The transistors T2 of the pixel units are connected in series and act as variable capacitors in the low conversion gain gear. By controlling the on and off of transistor T2, the capacitance size of the conversion gain can be adjusted. In this way, different numbers of rows of transistors T2 can be turned on as needed to select a conversion gain suitable for the current scene. By setting the control switch T1 transistor, it is also possible to control whether, while connecting the variable capacitor, the readout processes of different row pixel units overlap to improve the readout speed.

[0073] The photodiode PD can convert the incident light it senses into electrons and accumulate the charges generated by the electrons. The transfer transistor TG is coupled between the photodiode PD and the floating diffusion region FD. When the transfer transistor TG responds to the first control signal issued by the external control circuit and is placed in the conducting state, the electrons of the photodiode PD can be transferred to the floating diffusion region FD. The floating diffusion region FD receives the electrons and accumulates the charges generated by the electrons.

[0074] Each pixel unit in this example is provided with a photodiode PD and its corresponding transfer transistor TG. In other examples, each pixel unit can also include multiple photodiodes PD, such as 4, 8, 9, 16, etc., and a corresponding transfer transistor TG is provided for each photodiode PD. These transfer transistors TG are commonly coupled to the floating diffusion region FD of the pixel unit. The multiple photodiodes PD share other components in the circuit of the pixel unit except for the transfer transistor TG.

[0075] Transistor T1 is coupled between the first node 1 and the second node 2. The first node 1 is the connection point between the reset transistor RST and the conversion gain control transistor DCG, and the second node 2 is the connection point between the transistor T2 of this row and the transistor T2 of the next row. At the two transistors T2 of the first row and the last row in this column, the ends that are not connected to other adjacent transistors T2 can be grounded.

[0076] The conversion gain control transistor DCG is coupled between the reset transistor RST and the floating diffusion region FD. The reset transistor RST is also coupled to the power supply voltage VDD. The conversion gain control transistor DCG can selectively switch the conversion gain. When it is placed in the on or off state in response to a third control signal issued by an external control circuit, it connects or disconnects the capacitor connected to the first node from the floating diffusion region FD respectively, so as to change the capacitance at the floating diffusion region FD and enter different conversion gain modes. When the conversion gain control transistor DCG is on, when the reset transistor RST is placed in the on state in response to a second control signal issued by an external control circuit, the charges accumulated in the floating diffusion region FD and the photodiode PD can be released for resetting.

[0077] The control terminal (gate) of the source follower transistor SF is connected to the floating diffusion region FD, can receive the charges accumulated in the floating diffusion region FD, amplify the potential change at the floating diffusion region FD, and output a corresponding PXD signal according to the amplification result. In some examples, the source follower transistor SF is coupled between the power supply voltage VDD and a selection output transistor SEL, and can transmit the PXD signal to the selection output transistor SEL; the selection output transistor SEL is used to selectively output the PXD signal amplified corresponding to the charge amount in the floating diffusion region FD. When it is placed in the on state in response to a fourth control signal issued by an external control circuit, it can transmit the received PXD signal to the signal output line to which the selection output transistor SEL is connected.

[0078] In the solution of this example, the capacitance sizes corresponding to different conversion gains are adjusted by controlling the number of conducting transistors T2, so as to achieve multiple gears of conversion gain, in order to select a suitable conversion gain for different scenarios. Figure 4 The histogram shows an example of the relationship between the number of read electrons and the number of pixels at different brightness levels in a scenario. Max corresponds to the brightest pixel point and the case with the largest number of electrons; Peak corresponds to the pixel point with the largest brightness proportion, that is, the case with the largest proportion of electrons in the pixels. Figure 5a 、 Figure 5b They are respectively examples showing the relationship between the number of electrons and the signal-to-noise ratio when selecting the low conversion gain gear and the high conversion gain gear; Figure 5a 、 Figure 5b The horizontal axis of represents the number of read electrons, and the vertical axis represents the signal-to-noise ratio (SNR). The maximum value of SNR is the signal-to-noise ratio corresponding to the maximum quantifiable number of electrons of the PXD signal. A horizontal line B is drawn in the figure according to the maximum value of SNR; a horizontal double-headed arrow is also used to represent the dynamic range (Range) of the CMOS image sensor. Figure 5b In peak1 to peak3 and Figure 5aPD1 to PD3 correspond one by one; for example, under the same histogram reflecting the relationship between the number of electrons and the number of pixels, PD2 and peak2 respectively correspond to the number of electrons at the Max and Peak positions in this histogram.

[0079] Combined with Figure 4 and Figure 5a , during image preview, first, under different scenarios, according to the number of electrons corresponding to the brightest point (represented by Max in Figure 4 ) in the actual scenario, select an appropriate low conversion gain gear (LCG) to ensure that all electrons can be read out; then, combined with Figure 4 and Figure 5b , under the same scenario, according to the proportion of different brightness points, based on the number of electrons when the proportion of electrons in the entire pixel is the largest (represented by Peak in Figure 4 ), select an appropriate high conversion gain gear (HCG) to optimize the signal-to-noise ratio of the entire image.

[0080] Figure 5a In Figure 5a a plurality of different gears LCG1, LCG2... LCGn of low conversion gain are designed, which are shown as dotted lines with different slopes; different gears LCG1, LCG2... LCGn correspond to the situation where the floating diffusion region FD is connected to different numbers of transistors T2, so that the capacitors corresponding to the conversion gains of these gears are different.

[0081] Taking PD2 as an example, illustrate the situation when selecting the LCG gear: The straight line A2C2 drawn from PD2 intersects the oblique lines representing different gears LCG1, LCG2... LCGn, and intersects the horizontal line B corresponding to the maximum SNR value at point A2; among the intersections of these oblique lines and A2C2, the gear where the intersection with a larger SNR value and less than the maximum SNR value is located is used as the most suitable low conversion gain gear for the current brightness (PD2). Taking the example of Figure 5a , the selected low conversion gain gear for PD2 is LCG2 (in Figure 5a , the part converted from the HCG gear at the selected gear LCG2 is shown as a solid line, which is different from other unselected LCG gears).

[0082] Among the other LCG levels that are not selected, for example, the intersection of LCG1 and A2C2 will be higher than the horizontal line B (not marked in the figure), and the SNR value represented by this intersection will exceed the SNR maximum value; while the SNR values corresponding to the intersections of LCG3 to LCGn with A2C2 respectively are all smaller than the SNR value corresponding to the intersection of LCG2 and A2C2. Therefore, the LCG2 level is selected for PD2. Similarly, when selecting the LCG level for PD1, the intersection of LCG1 and A1C1 will be the point closest to but not exceeding the SNR maximum value. Therefore, it is suitable to select LCG1 as the low conversion gain level corresponding to the brightness of PD1. When selecting the LCG level for PD3, the intersections of LCG1 and LCG2 with A3C3 will both be higher than the SNR maximum value, and the SNR value corresponding to the intersection of LCG3 and A3C3 is larger than the SNR values corresponding to the remaining intersections. Therefore, it is suitable to select LCG3 as the low conversion gain level corresponding to the brightness of PD3.

[0083] In Figure 5b , peak1, peak2, and peak3 are the numbers of electrons corresponding to the pixels with the largest brightness ratios in three different scenarios. In the figure, straight lines D1E1, D2E2, and D3E3 are drawn based on peak1, peak2, and peak3, respectively, so that they intersect the horizontal line B representing the SNR maximum value at points D1, D2, and D3; in Figure 5b , different levels HCG1, HCG2... HCGn are designed for the high conversion gain, which are represented by multiple dotted lines with different slopes; different levels HCG1, HCG2... HCGn correspond to the situation where the floating diffusion region FD is connected to different numbers of transistors T2, so that the capacitances of the conversion gains corresponding to these levels are different. Figure 5b The LCG maximum level corresponding to the LCG maximum value is also shown in Figure 5b . The LCG maximum value is not greater than the HCG minimum value. Therefore,

[0084] Taking peak2 as an example, the situation when selecting the HCG level is described: the straight line D2E2 drawn from peak2 intersects the oblique lines representing different levels HCG1, HCG2... HCGn and intersects the horizontal line B representing the SNR maximum value at point D2; among the intersections of these oblique lines and D2E2, the level where the intersection has a larger SNR value and is smaller than the SNR maximum value is used as the most suitable high conversion gain level in the current scenario; in this example, the HCG2 level is selected for peak2 (marked as a solid line in the figure to distinguish it from other unselected HCG levels). The situation is similar when determining the HCG level for other peak value corresponding scenarios and will not be elaborated one by one.

[0085] Figure 6 is a circuit of the prior art (see Figure 1 ) and the circuit of the example of the present invention (seeFigure 3 ) Schematic diagram for comparing the SNR loss when switching the conversion gain gear. The horizontal axis represents the number of electrons read out, and the vertical axis refers to the SNR on the left side. Figure 6 Also inserted in it are the histogram and its normal distribution graph showing the relationship between the number of pixels and the corresponding number of electrons in the example scenario of the present invention with PD2 as the maximum number of electrons. The horizontal axis represents the number of electrons read out, and the vertical axis refers to the number of pixels on the right side.

[0086] In the circuit of the prior art (see Figure 1 example), the relationship between the SNR and the number of electrons read out is as Figure 6 shown by the solid line in. During the readout process, there are only two fixed gear switches. When switching from the HCG gear to the LCG gear, the SNR jumps. Therefore, when just switching to the LCG gear, there will be SNR loss, reducing the image quality.

[0087] In the pixel circuit of this solution (see Figure 3 example), the relationship between the SNR and the number of electrons read out is as Figure 6 shown by the dashed line in. It can be seen from the figure that in this solution, first, a suitable low conversion gain gear (such as LCG2) is selected according to the brightest point (such as PD2) in the actual scenario, and then a high conversion gain gear (such as HCG2) is selected according to the point with the largest brightness ratio (the vertex of the normal distribution). Comparing Figure 6 the curve change from the HCG gear to the LCG gear in the existing design with the curve change from the HCG2 gear to the LCG2 gear in the example of this solution, it can be seen that this solution reduces the SNR loss when switching the conversion gain gear, can optimize the SNR of the entire pixel, and obtain higher-quality images.

[0088] For the circuit design of the present invention (see Figure 3 example), the circuit working timing is as follows:

[0089] Electron clearing: RST is turned on, DCG is turned on, TG is turned on, T1 is turned off, T2 is turned off, and the electrons in PD and FD are cleared;

[0090] Integration: TG is turned off, RST is turned on, DCG is turned on, T1 is turned off, T2 is turned off;

[0091] Readout process (LHHL mode):

[0092] Reading the LCG reference signal: TG is turned off, RST is turned off, DCG is turned on, T1 is turned on, and T2 is turned on simultaneously in the h row to read the LCG reference signal;

[0093] Reading the HCG reference signal: TG is turned off, RST is turned off, DCG is turned on, T1 is turned on, and T2 is turned on simultaneously in the k row to read the HCG reference signal;

[0094] Read HCG signal: TG is turned on, RST is turned off, DCG is turned on, T1 is turned on, T2s of k rows are turned on simultaneously, and read the HCG signal;

[0095] Read LCG signal: TG is turned on, RST is turned off, DCG is turned on, T1 is turned on, T2s of h rows are turned on simultaneously, and read the LCG signal.

[0096] Where k is an integer less than the maximum number of rows of the pixel array and k≥1, and h is an integer less than or equal to the maximum number of rows of the pixel array and h>k; different LCG gears have their corresponding h values, and different HCG gears also have their corresponding k values. When selecting the LCG gear and HCG gear according to the current scenario, the corresponding number of h rows and k rows of transistors T2 can be turned on respectively during the actual reading process as the conversion gain capacitors of the corresponding gears.

[0097] When multiple (such as h or k rows) transistors T2 are turned on and their capacitances are used for sharing, it is possible to further determine whether to connect the currently shared capacitance to a single pixel unit by turning on or off the T1 transistor of each pixel unit.

[0098] Based on further settings of the control switch (T1 transistor), the readout timing of every two rows of pixel units can also be made into an Overlap (overlapping) mode, that is, while reading the HCG signal of the previous row, the next row can start reading the LCG reference signal, with a separation of two steps, to improve the readout speed of the entire device. Different from the above example where the T1 transistor is in the on state when reading the HCG reference signal and the HCG signal, in this Overlap mode, the T1 transistors of the pixel units in the row where the HCG reference signal and the HCG signal are read are turned off, which is different from the on state of the T1 transistors of other rows.

[0099] As Figure 7 shown, in the example of the Overlap mode, in the circuit sharing the h and k row capacitances, it includes the pixel units of the nth row and the (n + 1)th row (n + 1 < k), Figure 7 showing the readout timing of the nth row and the (n + 1)th row. Among them, TG, RST, DCG, T1, and T2 correspond to each transistor, n and n + 1 are used to distinguish these two rows of pixel units, and "on" and "off" indicate the on or off state of the transistor.

[0100] As Figure 7 shown, when reading the nth row, it includes the following timing:

[0101] Read LCG reference signal: TGn off, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n on, T1(n + 1) off, T2n on, T2(n + 1) on;

[0102] Read HCG reference signal: TGn off, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n off, T1(n + 1) off, T2n on, T2(n + 1) on;

[0103] Read HCG signal: TGn on, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n off, T1(n + 1) off, T2n on, T2(n + 1) on;

[0104] Read LCG signal: TGn on, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n on, T1(n + 1) off, T2n on, T2(n + 1) on.

[0105] When reading the HCG signal in the nth row, the (n + 1)th row starts to read the LCG reference signal, including the following timing:

[0106] Read LCG reference signal: TGn off, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n off, T1(n + 1) on, T2n on, T2(n + 1) on;

[0107] Read HCG reference signal: TGn off, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n off, T1(n + 1) on, T2n on, T2(n + 1) on;

[0108] Read HCG signal: TGn off, TG(n + 1) on, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n off, T1(n + 1) on, T2n on, T2(n + 1) on;

[0109] Read LCG signal: TGn off, TG(n + 1) on, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n off, T1(n + 1) on, T2n on, T2(n + 1) on.

[0110] Combine Figures 7 - 8It can be seen that during the readout process of each row of pixel units, in the order of "LCG reference signal", "HCG reference signal", "HCG signal", and "LCG signal", it shows the form of LHHL (low-high-high-low). Through the cooperation of the T1 transistors of each row control switch, when reading the "HCG signal" in the nth row, the (n + 1)th row starts to read the "LCG reference signal"; when reading the "HCG signal" in the (n + 1)th row, the (n + 2)th row starts to read the "LCG reference signal", and so on, to achieve the Overlap mode where the readout timings of the upper and lower two rows of signals can overlap and cover, effectively improving the readout speed.

[0111] In the Overlap mode, only the switch states of the T1 transistors of one row are different from those of the T1 transistors of other rows at a time: for the row that is currently reading the "HCG reference signal" and "HCG signal" (such as Figure 7 the first half of the nth row and the second half of the (n + 1)th row), it is necessary to control the T1 transistors of this row to turn off (such as Figure 7 the T1n transistor in the first half and the T1(n + 1) transistor in the second half), and at the same time control the T1 transistors of other rows to turn on; similarly, for the row that is currently reading the "LCG signal" and "LCG reference signal" (such as Figure 7 the first half of the nth row and the second half of the (n + 1)th row), it is necessary to control the T1 transistors of this row to turn on (such as Figure 7 the T1n transistor in the first half and the T1(n + 1) transistor in the second half), and at the same time control the T1 transistors of other rows to turn off.

[0112] Therefore, according to the switch states of the T1 transistors of each pixel unit's control switch, it is also possible to control whether to enable the Overlap mode. For example, if only one pixel unit is controlled to be in the high conversion gain mode each time (turning off the T1 transistor of this unit and turning on the T1 transistors of other units), then the readout timing of the Overlap mode can be enabled between the upper and lower two pixel units with shared capacitors. Or, if multiple pixel units can be made to be in the high conversion gain mode each time (that is, the T1 transistors of these units are all turned off), then the Overlap mode is not applicable, but in this case, different gear selections of the high conversion gain capacitor can be achieved. In addition, the low conversion gain mode of each pixel unit in the present invention is not affected by whether the Overlap mode is enabled or not, and multiple gear selections of variable capacitors can be achieved in the low conversion gain mode.

[0113] Except for the nth and (n + 1)th rows, the following description does not involve the control states of the transistors and the capacitor sharing situations in other rows for the time being. Refer to Figure 3 the circuit of Figure 7In the timing sequence, the T2n transistor and the T2(n + 1) transistor are fully turned on and in series as capacitors; the DCGn transistor and the DCG(n + 1) transistor are fully turned on. The switching states of the T1n transistor and the T1(n + 1) transistor are opposite, enabling the pixels in the n-th row and the (n + 1)-th row to share the capacitors corresponding to the T2n transistor and the T2(n + 1) transistor and the capacitors on the connection line from the n-th row to the (n + 1)-th row.

[0114] Taking the timing sequence of the n-th row as an example, in the low conversion gain mode of the n-th row, when reading the "LCG reference signal (LCG_ref)" and the "LCG signal (LCG_sig)" of the n-th row, the T1n transistor is turned on and the T1(n + 1) transistor is turned off. Then, the capacitors of the T2n transistor and the T2(n + 1) transistor can be connected to the floating diffusion region FDn of the n-th row through the T1n transistor and the DCGn transistor. In the high conversion gain mode of the n-th row, when reading the "HCG reference signal (HCG_ref)" and the "HCG signal (HCG_sig)" of the n-th row, the T1n transistor is turned off and no additional capacitor is connected to the floating diffusion region FDn of the n-th row. It can be seen that the capacitors in the two conversion gain modes are different, realizing the gear switching.

[0115] While the T1n transistor is turned off, the T1(n + 1) transistor is turned on. The capacitors of the T2n transistor and the T2(n + 1) transistor can be connected to the floating diffusion region FD(n + 1) of the (n + 1)-th row through the T1(n + 1) transistor and the DCG(n + 1) transistor, realizing the capacitance adjustment of the (n + 1)-th row in its low conversion gain mode. Similarly, when the (n + 1)-th row is in the high conversion gain mode, the T1(n + 1) transistor is turned off, and the shared capacitors of the T2n transistor and the T2(n + 1) transistor can be connected to the floating diffusion region FDn of the n-th row through the turned-on T1n transistor and the DCGn transistor, switching the n-th row to the low conversion gain mode.

[0116] Assume that in another example, the switching states of the T1 transistors of one or more rows of pixels are the same as those of the T1n transistor in the n-th row. These pixels and the pixels in the n-th row are called the first group of pixels. Then, when the T1 transistors of the first group of pixels are turned on together, the capacitors of all the currently series-connected T2 transistors in the pixel region are shared by the first group of pixels, and the shared capacitors are distributed in the floating diffusion region FD of the first group of pixels. All the first group of pixels are in the low conversion gain mode. When the T1 transistors of the first group of pixels are turned off, no shared capacitor is connected to the floating diffusion region FD of the first group of pixels (the shared capacitor is connected to other pixels with the T1 transistors turned on at this time). All the first group of pixels are in the high conversion gain mode.

[0117] Similarly, assume that the switching states of the T1 transistors of one or more rows of pixels are the same as those of the T1n transistor in the (n + 1)-th row. These pixels and the pixels in the (n + 1)-th row are called the second group of pixels. When the T1 transistors of the second group of pixels are turned on together, the capacitances of all the currently series-connected T2 transistors in the pixel region are shared by the second group of pixels. The shared capacitance is distributed in the floating diffusion regions FD of the second group of pixels, and all the second group of pixels are in the low conversion gain mode. When the T1 transistors of the second group of pixels are turned off, no shared capacitance is connected to the floating diffusion regions FD of the second group of pixels (the shared capacitance is connected to other pixels with the T1 transistors turned on at this time), and all the second group of pixels are in the high conversion gain mode.

[0118] It can be understood that the above is only an example. One or more rows of pixels can also adjust the states of their T1 transistors according to application requirements, and distribute the shared capacitance by following the first group of pixels or the second group of pixels at different stages. For example, the T2 transistors of a certain row of pixels are turned on and connected to the series-connected capacitances; the T1 transistors of this row of pixels, when the T1 transistors of the first group of pixels are turned on, are turned on together with the first group of pixels to distribute the currently shared capacitance. However, the T1 transistors of this row of pixels may not be turned off when the T1 transistors of the first group of pixels are turned off, but may also be turned on when the T1 transistors of the second group of pixels are turned on, and distribute the currently shared capacitance together with the second group of pixels.

[0119] In the above example, the T2n transistor and the T2(n + 1) transistor are conducting throughout as series-connected capacitances, and the DCGn transistor and the DCG(n + 1) transistor are also conducting throughout. In another example provided below, the T2n transistor and the T2(n + 1) transistor are selectively conducting, so that different values of shared capacitance can be combined for distribution; in addition, the DCGn transistor and the DCG(n + 1) transistor are selectively conducting to adjust the shared capacitance for the floating diffusion region FD, thereby providing different gear selections for the conversion gain. Among them, except for the two rows of n and n + 1, the following description does not involve the state control of transistors and capacitance sharing in other rows for the time being.

[0120] In the example where the state of the DCG transistor can be switched according to needs, when controlling the n-th row and the (n + 1)-th row of the shared capacitance, Figure 9 The timing for reading the n-th row is shown as:

[0121] Clearing electrons: TGn on, TG(n + 1) on, RSTn on, RST(n + 1) on, DCGn on, DCG(n + 1) on, clearing the electrons in PD and FD;

[0122] Integration: TGn off, TG(n + 1) off;

[0123] Reading the LCG reference signal: TGn off, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n on, T1(n + 1) on, T2n on, T2(n + 1) on;

[0124] Read MCG reference signal: TGn off, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n on, T1(n + 1) off, T2n on, T2(n + 1) on;

[0125] Read HCG reference signal: TGn off, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn off, DCG(n + 1) on, T1n off, T1(n + 1) off, T2n off, T2(n + 1) off;

[0126] Read HCG signal: TGn on, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn off, DCG(n + 1) on, T1n off, T1(n + 1) off, T2n off, T2(n + 1) off;

[0127] Read MCG signal: TGn on, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n on, T1(n + 1) off, T2n on, T2(n + 1) on;

[0128] Read LCG signal: TGn on, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n on, T1(n + 1) on, T2n on, T2(n + 1) on.

[0129] The timing when reading the (n + 1)-th row is the same as that of reading the n-th row:

[0130] Read LCG reference signal: TGn off, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n on, T1(n + 1) on, T2n on, T2(n + 1) on;

[0131] Read MCG reference signal: TGn off, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) on, T1n off, T1(n + 1) on, T2n on, T2(n + 1) on;

[0132] Read HCG reference signal: TGn off, TG(n + 1) off, RSTn off, RST(n + 1) off, DCGn on, DCG(n + 1) off, T1n off, T1(n + 1) off, T2n off, T2(n + 1) off;

[0133] Read the HCG signal: TGn is on, TG(n + 1) is off, RSTn is off, RST(n + 1) is off, DCGn is on, DCG(n + 1) is off, T1n is off, T1(n + 1) is off, T2n is off, T2(n + 1) is off;

[0134] Read the MCG signal: TGn is on, TG(n + 1) is off, RSTn is off, RST(n + 1) is off, DCGn is on, DCG(n + 1) is on, T1n is off, T1(n + 1) is on, T2n is on, T2(n + 1) is on;

[0135] Read the LCG signal: TGn is on, TG(n + 1) is off, RSTn is off, RST(n + 1) is off, DCGn is on, DCG(n + 1) is on, T1n is on, T1(n + 1) is on, T2n is on, T2(n + 1) is on.

[0136] It can be seen that according to the on or off state of the DCGn transistor, a middle conversion gain mode (MCG) is added to each row. Specifically, taking the pixel unit in the nth row as an example, in the low conversion gain mode, the DCGn transistor, T1n transistor, T1(n + 1) transistor, and DCG(n + 1) transistor are all on; the capacitances obtained by the on states of the T2n transistor and T2(n + 1) transistor can be respectively connected to the floating diffusion regions FDn and FD(n + 1) of these two rows, realizing the capacitance adjustment in the low conversion gain mode of the nth row and the (n + 1)th row respectively. At this time, the connection line between the floating diffusion region FDn of the nth row and the floating diffusion region FD(n + 1) of the (n + 1)th row is on. For the nth row pixel being read currently, it is equivalent to the capacitance that can accumulate charges being expanded to the sum of the capacitances of these two floating diffusion regions FDn + FD(n + 1).

[0137] Compared with the transistor control situation in the low conversion gain mode, in the middle conversion gain mode, the states of other transistors remain unchanged, and the T1(n + 1) transistor turns to the off state. Then, the series capacitances of the T2n transistor and T2(n + 1) transistor are jointly connected to the floating diffusion region FDn of the nth row, adjusting the capacitance of the conversion gain of the nth row pixel; at this time, due to the off state of the T1(n + 1) transistor, the connection line between the floating diffusion region FDn of the nth row and the floating diffusion region FD(n + 1) of the (n + 1)th row is not on, and the capacitance that the nth row pixel can accumulate charges is the capacitance of the floating diffusion region FDn.

[0138] Compared with the transistor control situation in the middle conversion gain mode, in the high conversion gain mode, in addition to the T1(n + 1) transistor remaining off, the DCGn transistor and T1n transistor at the connection line turn to the off state. Therefore, no additional capacitance is connected to the floating diffusion region FDn of the nth row. At this time, the capacitance of the conversion gain of the nth row pixel is different from that in the other two modes, realizing the switching of three gears.

[0139] It can be seen that when the n-th row in this example is in the high conversion gain mode, even if the DCG(n + 1) transistor in the (n + 1)-th row is turned on, since the T1(n + 1) transistor and the T2n transistor and T2(n + 1) transistor acting as capacitors are all in the off state, the (n + 1)-th row cannot obtain an additional capacitor at this time. It can be understood that in other examples, when the n-th row is in the high conversion gain mode, if only the DCGn transistor and the T1n transistor are turned off to prevent an additional capacitor from being connected to the floating diffusion region FDn of the n-th row, and at the same time the DCG(n + 1) transistor, the T1(n + 1) transistor, the T2n transistor, and the T2(n + 1) transistor are all kept in the on state, then the series capacitors corresponding to the T2n transistor and the T2(n + 1) transistor can be shared by the (n + 1)-th row and connected to the floating diffusion region FD(n + 1) of the (n + 1)-th row to adjust the capacitor for the conversion gain of the (n + 1)-th row and switch a gear for the (n + 1)-th row.

[0140] The above embodiments are described by taking pixels in different rows of the same column as examples. It can be understood that in different embodiments, the number of rows of pixels in which the T2 transistors are connected in series in each column can be less than or equal to the total number of rows in this column. Or, the multiple pixels in which the T2 transistors are connected in series are pixels in the same row but different columns, and the number of columns of pixels in which the T2 transistors are connected in series in each row can be less than or equal to the total number of columns in this row. Or, the multiple pixels in which the T2 transistors are connected in series can be located in adjacent rows and / or adjacent columns; or in non-adjacent rows and / or non-adjacent columns, and the number of rows and / or columns separated between every two pixels connected by the T2 transistors can be the same or different. Or, all the pixels in the pixel region are divided into at least two groups, and the T2 transistors of each group of pixels are respectively connected to form at least two groups of series capacitors; for example, in at least one column of pixels, the T2 transistors of the pixels in every other row are connected in series with each other.

[0141] In some other embodiments, each pixel may further be provided with at least one second capacitor, and the second capacitor may have a fixed capacitance value. As Figure 10 shown, the second capacitor C 01 can be coupled to the first node of the RST transistor and the DCG transistor. Then, regardless of the switching states of the T1 transistor and the T2 transistor, when the DCG transistor is turned on, at least the capacitance value of the second capacitor C 01 can be connected to the floating diffusion region FD.

[0142] In summary, in the solution of the present invention, a transistor T1 and a transistor T2 are additionally provided for each pixel. The transistor T1 is used to control the gear switching; the transistors T2 of multiple pixels are connected and shared as a variable capacitor, and the size of the capacitor for adjusting the conversion gain is adjusted by controlling the number of turned-on transistors T2, so as to design multiple gears of conversion gain, select a suitable conversion gain gear according to the current scene, make the signal-to-noise ratio of the entire image optimal, and reduce the signal-to-noise ratio loss.

[0143] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation to the present invention. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to the present invention. Such modifications, improvements, and corrections are proposed in the present invention, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of the present invention.

[0144] It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, by way of example and not limitation, alternative configurations of the embodiments of the present invention may be regarded as consistent with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.

Claims

1. A driving method for a pixel circuit, the pixel circuit comprising: Pixel units, one or more of which form a pixel array; Each of the pixel units includes: One or more photodiodes; One or more first transistors, correspondingly connected to the one or more photodiodes; the first transistor is coupled between the corresponding photodiode and a floating diffusion region of the pixel unit; A second transistor, coupled to a power supply voltage; A third transistor, coupled between the floating diffusion region and the second transistor; Characterized in that each of the pixel units further includes: a control switch and a first capacitor; One end of the control switch is connected to a connection node of the second transistor and the third transistor, and the other end of the control switch is connected to the first capacitor; Wherein, the first capacitors of m pixel units are connected in series, m>1 and m is an integer; the gain level is controlled by controlling the number of the first capacitors in series that are turned on.

2. The driving method of the pixel circuit according to claim 1, wherein The m pixel units include p pixel units in adjacent rows and / or adjacent columns, where 1<p≤m and p is an integer.

3. The driving method of the pixel circuit according to claim 2, wherein The m pixel units include at least one column of pixel units or at least one row of pixel units.

4. The driving method of the pixel circuit according to claim 1, wherein The m pixel units include q pixel units sharing the first capacitor, and every two of the q pixel units are spaced apart by i rows and / or j columns, where 1<q≤m and q is an integer, i≥1 and i is an integer, j≥1 and j is an integer.

5. The driving method of the pixel circuit according to claim 4, wherein Among the q pixel units, every two pixel units are spaced apart by 1 row; in at least one column of pixel units, the first capacitors are connected in series with each other across rows, forming a first series group and a second series group.

6. The driving method of the pixel circuit according to claim 1, wherein There is at least a sharing of the first capacitors of two rows of pixel units, and the driving method further includes: by setting the control switch, while reading a high conversion gain signal in the upper row, the lower row starts to read a low conversion gain reference signal.

7. The driving method of the pixel circuit according to claim 1, characterized in that, The circuit working timing of the pixel unit includes: Electron clearing: The second transistor is turned on, the third transistor is turned on, the first transistor is turned on, the control switch is turned off, the first capacitor is turned off, and the electrons in the photodiode and the floating diffusion region are cleared; Integration: The first transistor is turned off, the second transistor is turned on, the third transistor is turned on, the control switch is turned off, the first capacitor is turned off; Readout process, the readout process includes: Reading a low conversion gain reference signal: the first transistor is turned off, the second transistor is turned off, the third transistor is turned on, the control switch is turned on, the first capacitors of h rows are turned on simultaneously, and the low conversion gain reference signal is read; Reading a high conversion gain reference signal: the first transistor is turned off, the second transistor is turned off, the third transistor is turned on, the control switch is turned on, the first capacitors of k rows are turned on simultaneously, and the high conversion gain reference signal is read; Reading a high conversion gain signal: the first transistor is turned on, the second transistor is turned off, the third transistor is turned on, the control switch is turned on, the first capacitors of k rows are turned on simultaneously, and the high conversion gain signal is read; Reading a low conversion gain signal: the first transistor is turned on, the second transistor is turned off, the third transistor is turned on, the control switch is turned on, the first capacitors of h rows are turned on simultaneously, and the low conversion gain signal is read; Wherein, m≥h>k, k≥1, and h is an integer less than or equal to the maximum number of rows of the pixel array, and k is an integer less than the maximum number of rows of the pixel array.

8. The driving method of the pixel circuit according to claim 1, wherein The control switch and the first capacitor are fabricated within or outside the region of the pixel unit.

9. The driving method of the pixel circuit according to any one of claims 1 to 8, characterized in that The control switch includes a fourth transistor, the first capacitor includes a fifth transistor, and the driving method includes controlling the number of the fifth transistors connected in series that are turned on to control different gain levels.

10. The driving method of the pixel circuit according to claim 1, wherein, Each of the pixel units includes four, or eight, or nine, or sixteen of the photodiodes.

11. The driving method of the pixel circuit according to claim 1, characterized in that, Each of the pixel units further includes a second capacitor, and the second capacitor is coupled to the connection node of the second transistor and the third transistor.

12. The driving method of the pixel circuit according to claim 9, wherein Each of the pixel units further includes: a sixth transistor, a control terminal of the sixth transistor being connected to the floating diffusion region; a seventh transistor, coupled between the sixth transistor and the signal output line, for selecting an output.

13. The driving method of the pixel circuit according to claim 12, wherein the first transistor includes a transfer transistor; the second transistor includes a reset transistor; the third transistor includes a gain conversion transistor; the sixth transistor includes a source follower transistor; the seventh transistor includes a selection output transistor.

14. The driving method of the pixel circuit according to claim 13, wherein the fourth transistor and / or the fifth transistor is fabricated synchronously with at least one of the first, second, third, sixth, and seventh transistors.

15. A pixel circuit, applied to the driving method according to any one of claims 1 to 14.

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