Semiconductor structure and manufacturing method thereof, memory and memory system

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, a memory and a memory system. The method for manufacturing the semiconductor structure comprises the following steps: forming a plurality of preset layers which extend along a first direction and are arranged along a second direction in a semiconductor layer; forming a plurality of semiconductor columns in array distribution along the first direction and the second direction in the semiconductor layer, wherein the side walls of the semiconductor columns are in contact with the preset layer; and gate structures which are distributed adjacent to the preset layer in the third direction and extend in the first direction are formed on the side walls of the semiconductor columns, and every two of the first direction, the second direction and the third direction intersect.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly, to semiconductor structures, methods of manufacturing semiconductor structures, memories, and storage systems. Background Art

[0002] With the rise and development of fields such as artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the requirements for the storage density of semiconductor structures such as three-dimensional semiconductor memory devices are also getting higher and higher. However, as the storage density of semiconductor structures increases, the number of their storage units is increasing, the size is getting smaller, and the spatial density is getting larger. This makes the heights of multiple storage units vary greatly, which has a great impact on the performance of semiconductor structures. Summary of the Invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies mentioned in the above background art part or other deficiencies in the prior art.

[0004] This application provides a method of manufacturing a semiconductor structure. The method includes: forming a plurality of preset layers extending in a first direction and arranged in a second direction in a semiconductor layer; forming a plurality of semiconductor pillars distributed in an array in the first direction and the second direction in the semiconductor layer, wherein the side walls of the semiconductor pillars are in contact with the preset layers; and forming a gate structure on the side walls of the semiconductor pillars adjacent to the preset layers in a third direction and extending in the first direction, wherein the first direction, the second direction, and the third direction intersect pairwise.

[0005] In one embodiment, forming a plurality of preset layers extending in a first direction and arranged in a second direction in a semiconductor layer includes: forming a plurality of grooves extending in the first direction and arranged in the second direction in the semiconductor layer; and filling the grooves with an insulating material to form the preset layers.

[0006] In one embodiment, the method further includes: forming a dielectric layer at a preset depth of an initial semiconductor layer, wherein the dielectric layer divides the initial semiconductor layer into the semiconductor layer and a remaining layer, and the preset layers extend in the semiconductor layer from a first surface of the semiconductor layer away from the dielectric layer in the third direction.

[0007] In one embodiment, the method further includes: removing the remaining layer and the dielectric layer to expose a second surface of the semiconductor layer opposite to the first surface, wherein the top surface of the semiconductor pillar is coplanar with the second surface, and the gate structure extends from the second surface in the third direction to the preset layers.

[0008] In one embodiment, forming a plurality of semiconductor pillars arrayed along the first direction and the second direction in the semiconductor layer includes: forming a plurality of isolation portions extending along the second direction and the third direction in the semiconductor layer, where the plurality of isolation portions divide the semiconductor layer into a plurality of initial semiconductor pillars, and the initial semiconductor pillars and the isolation portions are alternately arranged along the first direction; and forming a plurality of trenches that penetrate the initial semiconductor pillars, extend along the first direction, and are arranged along the second direction, where the plurality of trenches expose the surface of the preset layer, and the trenches and the preset layer divide the semiconductor layer into a plurality of semiconductor pillars extending along the third direction, and the gate structure is located in the trenches.

[0009] In one embodiment, the plurality of trenches include a first trench and a second trench arranged adjacent to each other. The first trench exposes the first sidewall of the semiconductor pillar, and the second trench exposes the second sidewall of the semiconductor pillar that is opposite to the first sidewall along the second direction. The method includes: forming the gate structure on the first sidewall of the semiconductor pillar; and forming an isolation structure that is adjacent to the preset layer along the third direction and extends along the first direction on the second sidewall of the semiconductor pillar.

[0010] In one embodiment, the gate structure includes a gate dielectric layer and a gate layer. Wherein, forming a gate structure that is adjacent to the preset layer along the third direction and extends along the first direction on the sidewall of the semiconductor pillar includes: forming the gate dielectric layer that is adjacent to the preset layer along the third direction and extends along the first direction on the sidewall of the semiconductor pillar; and forming the gate layer on a side of the gate dielectric layer away from the semiconductor pillar.

[0011] In one embodiment, forming a dielectric layer at a preset depth in the initial semiconductor layer includes: implanting ions at the preset depth in the initial semiconductor layer by means of ion implantation to form the dielectric layer.

[0012] In one embodiment, the method further includes: bonding a carrier wafer to the first surface of the semiconductor layer; and removing the remaining layer and the dielectric layer to expose the second surface of the semiconductor layer.

[0013] In one embodiment, the semiconductor pillar includes a first end and a second end that are oppositely arranged along the third direction, where the second end is closer to the preset layer than the first end. The method further includes: forming a capacitor connected to the first end.

[0014] In one embodiment, the receiving carrier is removed to expose the second end of the conductor pillar; and a bit line connected to the second end and extending along the second direction is formed.

[0015] In one embodiment, a gate lead-out structure and a bit line lead-out structure respectively connected to the gate structure and the bit line are formed from a side close to the second end.

[0016] On the other hand, the present application provides a semiconductor structure. The semiconductor structure includes: semiconductor pillars arrayed along a first direction and a second direction; gate structures located on at least one side of the semiconductor pillars along the second direction; and a preset layer located on one side of the gate structures along a third direction, wherein the first direction, the second direction, and the third direction intersect pairwise.

[0017] In one embodiment, the preset layer includes a single-layer structure, and its material includes an insulating material.

[0018] In one embodiment, the semiconductor pillar includes a first end and a second end oppositely arranged along the third direction, wherein the first end is coplanar with the surface of the gate structure away from the preset layer, and the second end is coplanar with the surface of the preset layer away from the gate structure.

[0019] In one embodiment, the gate structure is located at a first sidewall of the semiconductor pillar and extends along the first direction. The semiconductor structure further includes: an isolation structure located on a second sidewall of the semiconductor pillar opposite to the first sidewall, adjacent to the preset layer along the third direction and extending along the first direction.

[0020] In one embodiment, the gate structure includes: a gate dielectric layer located on the sidewall of the semiconductor pillar, adjacent to the preset layer along the third direction and extending along the first direction; and a gate layer located on a side of the gate dielectric layer away from the semiconductor pillar.

[0021] In one embodiment, the semiconductor structure further includes: a capacitor connected to the first end; and a bit line connected to the second end and extending along the second direction.

[0022] In one embodiment, the semiconductor structure further includes: a gate lead-out structure and a bit line lead-out structure located on a side close to the preset layer and respectively connected to the gate structure and the bit line.

[0023] In one embodiment, the isolation structure includes a first isolation surface and a second isolation surface that are oppositely disposed along the third direction, wherein the first isolation surface is closer to the preset layer than the second isolation surface; the preset layer includes a first preset surface and a second preset surface that are oppositely disposed along the third direction, wherein the first preset surface is closer to the isolation structure than the second preset surface; wherein, the width of the first isolation surface is smaller than the width of the second isolation surface, and the width of the first preset surface is smaller than the width of the second preset surface.

[0024] On the other hand, the present application provides a memory, which includes: a memory cell array including the semiconductor structure as described above; and a peripheral circuit coupled to the memory cell array.

[0025] On the other hand, the present application provides a storage system, which includes at least one memory; and a controller coupled to the memory for controlling the memory to store data. Description of the Drawings

[0026] In conjunction with the drawings, through the following detailed description of non-limiting embodiments, other features, objects, and advantages of the present application will become more apparent. In the drawings:

[0027] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0028] Figure 2 is a partial structural schematic diagram of an initial semiconductor layer formed on a plane in a first direction and a second direction according to an exemplary embodiment of the present application;

[0029] Figure 3 is a structural schematic diagram of forming a dielectric layer according to an exemplary embodiment of the present application, wherein, Figure 3 is Figure 2 a partial cross-sectional schematic diagram along the A-A direction;

[0030] Figure 4 and Figure 5 are respectively structural schematic diagrams of forming a preset layer according to an exemplary embodiment of the present application, wherein, Figure 5 is Figure 4 a partial cross-sectional schematic diagram along the A-A direction;

[0031] Figure 6 is a structural schematic diagram of forming a first bonding layer according to an exemplary embodiment of the present application;

[0032] Figure 7 is a structural schematic diagram of forming a second bonding layer according to an exemplary embodiment of the present application;

[0033] Figure 8 is a partial structural schematic diagram of a bonding structure formed after bonding a first bonding layer and a second bonding layer according to an exemplary embodiment of the present application;

[0034] Figure 9 For Figure 8 is a structural schematic diagram of thinning after flipping the structure by 180°;

[0035] Figure 10 and Figure 11 are structural schematic diagrams of forming an initial semiconductor pillar and an isolation part according to an exemplary embodiment of the present application, where Figure 11 is Figure 10 a partial cross-sectional schematic diagram along the B-B direction;

[0036] Figure 12 and Figure 13 are structural schematic diagrams of forming a semiconductor pillar and a trench according to an exemplary embodiment of the present application, where Figure 13 is Figure 12 a partial cross-sectional schematic diagram along the A-A direction;

[0037] Figure 14 and Figure 15 are structural schematic diagrams of forming a gate structure and an isolation structure according to an exemplary embodiment of the present application, where Figure 15 is Figure 14 a partial cross-sectional schematic diagram along the A-A direction;

[0038] Figure 16 is an enlarged structural schematic diagram of an isolation structure and a second preset layer according to an exemplary embodiment of the present application;

[0039] Figure 17 is a structural schematic diagram of forming a capacitor according to an exemplary embodiment of the present application;

[0040] Figure 18 For Figure 17 is a structural schematic diagram of thinning after flipping the structure by 180°;

[0041] Figure 19 are structural schematic diagrams of forming a bit line, a gate lead structure, and a bit line lead structure according to an exemplary embodiment of the present application;

[0042] Figure 20 is a schematic block diagram of a memory according to an exemplary embodiment of the present application;

[0043] Figure 21 is a partial schematic structural diagram of a memory according to an exemplary embodiment of the present application; and

[0044] Figure 22 FIG. Figure 22 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0045] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way.

[0046] It should be noted that in this specification, the expressions of first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the feature, especially do not represent any order. Therefore, without departing from the teachings of the present application, the first surface discussed in the present application may also be referred to as the second surface, and the first direction may also be referred to as the second direction, the third direction, and vice versa.

[0047] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to strict scale. As used herein, the terms "substantially", "about", and similar terms are used as terms indicating approximation, rather than terms indicating degree, and are intended to illustrate the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.

[0048] In addition, herein, when describing that a part is located "on" another part, for example, the meanings of "on", "above", and "over" should be interpreted in the broadest way, so that "on" not only means "directly on something", but also includes "on something" with intermediate features or layers therebetween, and "above" or "over" does not absolutely mean located above with reference to the direction of gravity, nor only means "above something" or "over something", but may also include "above something" or "over something" without intermediate features or layers therebetween (i.e., directly on something).

[0049] It should also be understood that expressions such as "comprising", "including", "having", "containing", and / or "including having" in this specification are open rather than closed expressions, which mean the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than only modifying a single element in the list. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0050] This description is made with reference to the schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and dimensions shown, but include various equivalent structures capable of achieving the same functions and shape and dimension deviations caused, for example, during manufacturing. The positions shown in the drawings are essentially schematic and are not intended to limit the positions of the components.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0052] As used herein, the term "layer" refers to a portion of a material that includes a region having a height. A layer can be a region of a uniform or non-uniform continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above, and / or below it. A layer can include multiple layers.

[0053] In addition, in this application, when using "connected" or "coupled", it can indicate direct or indirect contact between the corresponding components, unless there are clear other limitations or can be deduced from the context.

[0054] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments can be combined with each other. Additionally, unless expressly limited or contradictory to the context, the specific steps included in the methods described in this application do not have to be limited to the recited order and can be executed in any order or executed in parallel. The following will detail this application with reference to the drawings and in combination with the embodiments.

[0055] Figure 1 is a flowchart of a method 1000 for manufacturing a semiconductor structure according to an exemplary embodiment of the present application.

[0056] As Figure 1As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, forming a plurality of preset layers extending in a first direction and arranged in a second direction in a semiconductor layer; S1200, forming a plurality of semiconductor pillars arranged in an array in the first direction and the second direction in the semiconductor layer, wherein the sidewalls of the semiconductor pillars are in contact with the preset layers; and S1300, forming a gate structure adjacent to the preset layers in a third direction and extending in the first direction on the sidewalls of the semiconductor pillars. Steps S1100 to S1300 will be described in detail below.

[0057] In an exemplary embodiment of the present application, as Figure 4 and Figure 5 shown, the first direction Y, the second direction X, and the third direction Z may intersect pairwise, and a plurality of preset layers 1200 extending in the first direction Y and arranged in the second direction X may be formed in the semiconductor layer 1100.

[0058] Figure 2 FIG. is a partial structural schematic diagram of the initial semiconductor layer 100 provided according to an exemplary embodiment of the present application on a plane formed in the first direction Y and the second direction X. Figure 3 FIG. is a structural schematic diagram of a formed dielectric layer 200 provided according to an exemplary embodiment of the present application, wherein, Figure 3 is Figure 2 a partial cross-sectional schematic diagram along the A-A direction.

[0059] The material of the initial semiconductor layer 100 may include at least one of single-crystal silicon, polycrystalline silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0060] In an exemplary embodiment of the present application, as Figure 3 shown, a dielectric layer 200 may be formed at a preset depth of the initial semiconductor layer 100. The dielectric layer 200 may divide the initial semiconductor layer 100 into a semiconductor layer 1100 and a remaining layer 300. Exemplarily, a part of the initial semiconductor layer 100 on one side of the dielectric layer 200 may be the semiconductor layer 1100, and a part of the initial semiconductor layer 100 on the other side of the dielectric layer 200 may be the remaining layer 300. Since the semiconductor layer 1100 is a part of the initial semiconductor layer 100, the semiconductor layer 1100 may have the same material as the initial semiconductor layer 100, such as single-crystal silicon, etc.

[0061] Exemplarily, ions may be implanted at a preset depth of the initial semiconductor layer 100 by ion implantation to form the dielectric layer 200. For example, the initial semiconductor layer 100 may be subjected to hydrogen ion implantation to form a hydrogen ion-rich dielectric layer 200 at a preset depth of the initial semiconductor layer 100.

[0062] In this application, the semiconductor layer 1100 is formed by setting the dielectric layer 200, which is beneficial to improving the uniformity of the thickness of the semiconductor layer 1100. For example, it is beneficial to improve the consistency of the height of the semiconductor layer 1100 in the third direction Z. In other words, by setting the dielectric layer 200 to form the semiconductor layer 1100 in this application, it is beneficial to make the surface of the semiconductor layer 1100 in contact with the dielectric layer 200 (such as Figure 9 shown as the second surface 1120) extend along the second direction X.

[0063] Figure 4 and Figure 5 are respectively schematic structural diagrams of forming the preset layer 1200 according to the exemplary embodiments of this application. Among them, Figure 5 is Figure 4 a partial cross-sectional view along the A-A direction. Exemplarily, as Figure 5 shown, forming a plurality of preset layers 1200 extending along the first direction Y and arranged in the second direction X in the semiconductor layer 1100 may include: forming a plurality of grooves (not shown) extending along the first direction Y and arranged in the second direction X in the semiconductor layer 1100; and filling the grooves with an insulating material to form the preset layer 1200.

[0064] Exemplarily, as Figure 4 and Figure 5 shown, the preset layer 1200 may include a first preset layer 1210 and a second preset layer 1220 that are spaced apart. The first preset layer 1210 and the second preset layer 1220 may have different widths along the second direction X, so as to facilitate the subsequent formation of a gate structure 1400 adjacent to the first preset layer 1210 along the third direction Z and an isolation structure 1500 adjacent to the second preset layer 1220 along the third direction Z ( Figure 15 ). It should be understood that the plurality of preset layers 1200 may also have substantially the same width. In actual processes, the widths of the plurality of preset layers 1200 can be reasonably set according to actual requirements.

[0065] Exemplarily, as Figure 5 shown, a plurality of grooves can be formed starting from the first surface 1110 of the semiconductor layer 1100 that is far from the dielectric layer 200, so that the formed preset layer 1200 can extend in the semiconductor layer 1100 along the third direction Z starting from the first surface 1110. Exemplarily, the distances that the plurality of preset layers 1200 extend in the semiconductor layer 1100 along the third direction Z may be substantially the same. In other words, the positions where the plurality of preset layers 1200 extend into the semiconductor layer 1100 are substantially flush along the second direction X.

[0066] Exemplarily, an insulating material such as silicon nitride can be deposited in the groove by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form a preset layer 1200. It should be understood that during the process of filling the insulating material, it is inevitable that the insulating material will also be formed on the first surface 1110 of the semiconductor layer 1100. Therefore, a planarization process such as a mechanical grinding process can also be performed to remove the insulating material on the first surface 1110 and make the first surface 1110 extendable along the second direction X.

[0067] Exemplarily, as Figure 8 shown, a carrier wafer 500 can be formed on the first surface 1110. Exemplarily, the carrier wafer 500 can be bonded to the first surface 1110 by a bonding process. For example, a first bonding layer 410 ( Figure 6 ) can be formed on the first surface 1110; a second bonding layer 420 ( Figure 7 ) can be formed on the carrier wafer 500; and by bonding the first bonding layer 410 and the second bonding layer 420, the carrier wafer 500 can be bonded to the first surface 1110 ( Figure 8 ).

[0068] Exemplarily, the first bonding layer 410 and the second bonding layer 420 can have a similar structure. For example, both the first bonding layer 410 and the second bonding layer 420 can include a plurality of bonding contacts (not shown) and a dielectric for isolating the bonding contacts. The bonding contacts can include a conductive material, such as copper (Cu). The remaining regions of the first bonding layer 410 and the second bonding layer 420 can be formed of a dielectric material (for example, silicon oxide or silicon nitride). The bonding contacts and the surrounding dielectrics in the first bonding layer 410 and the second bonding layer 420 can be used for hybrid bonding. Exemplarily, the dielectric materials in the first bonding layer 410 and the second bonding layer 420 can be the same, such as both being silicon oxide or both being silicon nitride, etc., to achieve bonding between the same materials, such as silicon oxide-silicon oxide bonding or silicon nitride-silicon nitride bonding, reduce the bonding interface, and improve the bonding strength of the first bonding layer 410 and the second bonding layer 420.

[0069] Exemplarily, the first bonding layer 410 and the second bonding layer 420 can be bonded by any suitable bonding process (for example, anodic bonding, fusion bonding, transfer bonding, adhesive bonding, and eutectic bonding, etc.). In this application, subsequent processes can be performed after flipping the Figure 8 shown structure by 180°.

[0070] Figure 9 Schematic diagram of the structure after flipping the structure of Figure 8 by 180° and then thinning. In an exemplary embodiment of the present application, as shown in Figure 9 , the remaining layer 300 and the dielectric layer 200 can be removed to expose the second surface 1120 of the semiconductor layer 1100 opposite to the first surface 1110, where the second surface 1120 can extend along the second direction X.

[0071] Exemplarily, a planarization process (e.g., CMP) and / or an etching process can be used to remove the remaining layer 300 and the dielectric layer 200 to expose the second surface 1120 of the semiconductor layer 1100. Exemplarily, a grinding operation can be performed to roughly remove part of the remaining layer 300 to expose part of the dielectric layer 200; then, a wet etching operation can be performed to remove the remaining remaining layer 300 on the dielectric layer 200. Exemplarily, a CMP operation can be performed to remove the dielectric layer 200 to expose the semiconductor layer 1100. It should be understood that the thinning operation and the removal stage can be performed in various ways, and the above processes are illustrative rather than restrictive, and those skilled in the art can adopt other suitable removal processes as needed, all of which are within the scope of the present application. For example, the rough removal operation of the remaining layer 300 can be performed by using grinding, wet etching, dry etching or CMP operation, or the remaining remaining layer 300 can be removed by wet etching, dry etching or CMP operation.

[0072] Figure 10 and Figure 11 are schematic diagrams of the structure for forming the initial semiconductor pillar 1130 and the isolation part 1300 according to an exemplary embodiment of the present application, where Figure 11 is Figure 10 a partial cross-sectional view along the B-B direction. Figure 12 and Figure 13 are schematic diagrams of the structure for forming the semiconductor pillar 1140 and the trench 600 according to an exemplary embodiment of the present application, where Figure 13 is Figure 12 a partial cross-sectional view along the A-A direction.

[0073] In an exemplary embodiment of the present application, as shown in Figure 12 and Figure 13 , a plurality of semiconductor pillars 1140 arranged in an array along the first direction Y and the second direction X can be formed in the semiconductor layer 1100, where the side walls of the semiconductor pillars 1140 can be in contact with the preset layer 1200.

[0074] Exemplarily, forming a plurality of semiconductor pillars 1140 distributed in an array along a first direction Y and a second direction X in the semiconductor layer 1100 may include: forming a plurality of isolation portions 1300 extending along the second direction X and a third direction Z in the semiconductor layer 1100, wherein the plurality of isolation portions 1300 divide the semiconductor layer 1100 into a plurality of initial semiconductor pillars 1130, and the initial semiconductor pillars 1130 and the isolation portions 1300 are alternately arranged along the first direction Y( Figure 10 and Figure 11 ); and forming a plurality of trenches 600 that penetrate the initial semiconductor pillars 1130 and extend along the first direction Y and are arranged along the second direction X, wherein the plurality of trenches 600 expose the surface of the preset layer 1200, and the trenches 600 and the preset layer 1200 divide the semiconductor layer 1100 into a plurality of semiconductor pillars 1140 extending along the third direction Z( Figure 12 and Figure 13 ).

[0075] Exemplarily, Figure 10 and Figure 11 As shown, a plurality of isolation portions 1300 extending along the second direction X and the third direction Z may be formed in the semiconductor layer 1100, wherein the plurality of isolation portions 1300 may divide a part of the semiconductor layer 1100 into a plurality of initial semiconductor pillars 1130. The initial semiconductor pillars 1130 and the isolation portions 1300 may be alternately arranged along the first direction Y. For example, a plurality of grooves (not shown) extending along the second direction X and the third direction Z may be formed in the semiconductor layer 1100; and isolation portions 1300 may be formed in the grooves, wherein the semiconductor layer 1100 that is not removed forms the initial semiconductor pillars 1130.

[0076] Exemplarily, an etching process may be used to etch the semiconductor layer 1100 to form grooves and initial semiconductor pillars 1130. For example, the semiconductor layer 1100 may be etched by one or more dry etching and / or wet etching processes using a patterned mask as a mask to etch grooves in the semiconductor layer 1100, wherein the semiconductor layer 1100 that is not removed may form the initial semiconductor pillars 1130.

[0077] Exemplarily, the material of the isolation portion 1300 may include but is not limited to insulating materials such as oxides. Exemplarily, an insulating material may be deposited in the grooves by a thin film deposition process to form the isolation portion 1300, so that adjacent initial semiconductor pillars 1130 are isolated by the isolation portion 1300. In addition, a planarization process such as a mechanical grinding process may be performed to remove the insulating material on the second surface 1120.

[0078] Exemplarily, as Figure 12 and Figure 13As shown, a plurality of trenches 600 can be formed through the initial semiconductor pillar 1130 and extending along the first direction Y and arranged along the second direction X, wherein the plurality of trenches 600 can expose the surface of the preset layer 1200. As Figure 13 shown, the plurality of trenches 600 can include a first trench 610 and a second trench 620 arranged adjacent to each other. The first trench 610, the second trench 620, and the preset layer 1200 together divide the semiconductor layer 1100 into a plurality of semiconductor pillars 1140 extending along the third direction Z. Exemplarily, one or more dry etching and / or wet etching processes can be used to etch and form the first trench 610 and the second trench 620.

[0079] In this application, the semiconductor pillar 1140 is formed by etching the semiconductor layer 1100. Therefore, the semiconductor pillar 1140 can have the same material as the semiconductor layer 1100. In addition, as Figure 13 shown, since the first trench 610, the second trench 620, and the preset layer 1200 together divide the initial semiconductor pillar 1130 into a plurality of semiconductor pillars 1140, the first trench 610 can expose the first sidewall 1141 of the semiconductor pillar 1140, the second trench 620 can expose the first sidewall 1142 of the semiconductor pillar 1140 opposite to the first sidewall 1141 along the second direction X, and the preset layer 1200 can be located on the sidewall of the semiconductor pillar 1140. In other words, a part of the sidewall of the semiconductor pillar 1140 along the third direction Z can be exposed by the first trench 610 and the second trench 620, and another part of the sidewall of the semiconductor pillar 1140 along the third direction Z can be in contact with the preset layer 1200.

[0080] Exemplarily, as Figure 13 shown, the first trench 610 and the second trench 620 can be formed starting from the second surface 1120 of the semiconductor layer 1100, so that the top surface of the formed semiconductor pillar 1140 can be coplanar with the second surface 1120.

[0081] Exemplarily, the plurality of semiconductor pillars 1140 are spaced apart from each other to expose one or more sidewalls of the semiconductor pillar 1140. For example, the semiconductor pillar 1140 can have a cubic shape to expose its four sidewalls. It should be understood that the semiconductor pillar 1140 can have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillar 1140 in a plan view (e.g., in the X-Y plane) can have a square shape, a rectangular shape (or a trapezoidal shape), a circular (or an elliptical shape), or any other suitable shape.

[0082] As Figure 14 and Figure 15As shown, the figure is a process step diagram for forming a gate structure 1400 provided by the present application. It should be understood that the process for forming the gate structure 1400 provided by the present application is only an example and is not specifically limited. In actual processes, the process for forming the gate structure 1400 can be reasonably set according to actual needs. In addition, although the present application describes that the isolation structure 1500 is formed simultaneously in the process of forming the gate structure 1400, it should be understood that the formation process sequence of the isolation structure 1500 and the gate structure 1400 is not specifically limited, and the two can be formed sequentially. Of course, the isolation structure 1500 may not be formed, and the present application does not make specific requirements for this, which can be designed according to actual processes.

[0083] Figure 14 and Figure 15 are schematic structural diagrams of forming the gate structure 1400 and the isolation structure 1500 provided according to an exemplary embodiment of the present application. Among them, Figure 15 is Figure 14 a partial cross-sectional view along the A-A direction.

[0084] In an exemplary embodiment of the present application, as Figure 14 and Figure 15 shown, a gate structure 1400 adjacent to the preset layer 1200 along the third direction Z and extending along the first direction Y can be formed on the sidewall of the semiconductor column 1140. Exemplarily, the gate structure 1400 can be formed on the first sidewall 1141 of the semiconductor column 1140 via the first trench 610. The gate structure 1400 can extend from the second surface 1120 along the third direction Z to the first preset layer 1210.

[0085] In the present application, as described above, by using, for example, a planarization process to remove the remaining layer 300 and the dielectric layer 200, the second surface 1120 ( Figure 9 ) is exposed, and the second surface 1120 can be extended along the second direction X. On this basis, setting the gate structure 1400 to extend from the second surface 1120 is beneficial to realizing that the surfaces of multiple gate structures 1400 located on the second surface can extend along the second direction X. In other words, the surfaces of multiple gate structures 1400 located on the second surface can be substantially flush. In addition, in the present application, by setting the preset layer 1200, it can be realized that the positions where multiple preset layers 1200 extend into the semiconductor layer 1100 are substantially flush along the second direction X. On this basis, setting the gate structure 1400 to extend along the third direction Z to the first preset layer 1210 is beneficial to realizing that the surfaces of multiple gate structures 1400 in contact with the first preset layer 1210 can be substantially flush. It can be seen that the heights of the multiple gate structures 1400 provided by the present application along the third direction Z are highly consistent, which is beneficial to reducing the process difficulty of forming the semiconductor structure and improving the performance of the semiconductor structure.

[0086] The gate structure 1400 may include a gate dielectric layer 1410 and a gate layer 1420. Exemplarily, forming the gate structure 1400 may include: forming a gate dielectric layer 1410 on a first sidewall 1141 of the semiconductor pillar 1140, which is adjacent to the first preset layer 1210 along the third direction Z and extends along the first direction Y; and forming a gate layer 1420 on a side of the gate dielectric layer 1410 away from the semiconductor pillar 1140. Exemplarily, a dielectric layer 1430 may also be formed on a side of the gate layer 1420 away from the gate dielectric layer 1410, and an air gap 1440 may exist in the dielectric layer 1430. The dielectric layer 1430 may separate two gate structures 1400 within the first trench 610.

[0087] Exemplarily, the gate dielectric layer 1410 and the gate layer 1420 may be sequentially deposited and formed through one or more thin film deposition processes including but not limited to CVD, PVD, ALD, or any combination thereof. The gate dielectric layer 1410 may include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 1410 may include silicon oxide. The gate layer 1420 may include one or more conductive materials such as metals and / or metal compounds such as tungsten W and / or titanium nitride TiN. Exemplarily, a planarization process such as a chemical mechanical polishing process may be performed to remove excess conductive material and dielectric material on the surface of the semiconductor pillar 1140.

[0088] Exemplarily, etching processes such as downward drilling etching, dry etching, and / or wet etching may be employed to form two spaced-apart gate structures 1400 in the first trench 610. Exemplarily, a bottom-down drilling etching process may be used to disconnect the gate structure 1400 at the bottom of the first trench 610 until the first preset layer 1210 is exposed.

[0089] Exemplarily, an etch-back process may be used to remove a portion of the gate layer 1420 along the third direction Z such that the upper end of the gate layer 1420 is below the top surface of the semiconductor pillar 1140. In addition, since the gate dielectric layer 1410 is not etched back, the upper end of the gate layer 1420 is below the upper end of the gate dielectric layer 1410. In this way, the etched-back gate layer 1420 may extend along the first direction Y, and the portion corresponding to the semiconductor pillar 1140 may serve as a gate electrode. The gate structure 1400 may be connected to the peripheral circuit to enable the transmission of electrical signals between the gate electrode and the peripheral circuit.

[0090] Exemplarily, one or more thin film deposition processes may be used to form the dielectric layer 1430. The material of the dielectric layer 1430 includes but is not limited to, for example, silicon oxide. In addition, a planarization treatment process such as a mechanical polishing process may also be performed to remove the dielectric layer 1430 on the surface of the semiconductor pillar 1140.

[0091] Exemplarily, the semiconductor pillar 1140 and the gate structure 1400 can be jointly used to form a vertical transistor, where the semiconductor pillar 1140 can be used to form the active regions of multiple channels in the vertical transistor. Exemplarily, the gate structure 1400 can be located on at least one sidewall of the semiconductor pillar 1140, that is, the semiconductor pillar 1140 can be at least partially surrounded by the gate structure 1400. For example, the semiconductor pillar 1140, the gate dielectric layer 1410, and the gate layer 1420 can be radially arranged in this order from the center of the vertical transistor. Exemplarily, the gate dielectric layer 1410 can surround and contact the semiconductor pillar 1140. The gate layer 1420 can surround and contact the gate dielectric layer 1410.

[0092] It should be understood that Figure 15 the case where the gate structure 1400 shown in is located on one sidewall of the semiconductor pillar 1140 is only an example and not a specific limitation.

[0093] In an embodiment of the present application, the gate structure 1400 can be located on multiple sidewalls of the semiconductor pillar 1140. At this time, the semiconductor pillar 1140 and the gate structure 1400 can be jointly used to form a multi-gate transistor (for example, a gate-all-around (GAA) transistor, a triple-gate transistor, or a double-gate transistor). The multi-gate transistor can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the cut-off state, since the channel is completely depleted, the leakage current of the multi-gate transistor can also be significantly reduced. Therefore, using a multi-gate transistor can achieve better speed (saturation drain current) / leakage current performance.

[0094] In another embodiment of the present application, the gate structure 1400 can be located on one sidewall of the semiconductor pillar 1140. At this time, the semiconductor pillar 1140 and the gate structure 1400 can be jointly used to form a single-gate transistor. Exemplarily, the single-gate transistors adjacent along the second direction X can be symmetrically arranged. By setting the single-gate transistors in the present application, the density of the semiconductor pillars 1140 in the second direction X can be significantly increased, and the manufacturing process difficulty can be reduced. In addition, the symmetric single-gate transistors can have a larger process window, which is beneficial to reducing the pitch between, for example, the subsequently formed bit lines, word lines, and transistors.

[0095] Exemplarily, as Figure 14As shown, a separation structure 700 can be formed to penetrate the gate dielectric layer 1410 and the gate layer 1420 along the third direction Z, so as to separate the annular gate structure 1400 in the first trench 610 into at least two parts. For example, two separation structures 700 with a certain interval can be formed in each annular gate structure 1400 to separate the annular gate structure 1400 into two parts. In other words, the two separation structures 700 separate the annular gate dielectric layer 1410 into two parts and the gate layer 1420 into two parts.

[0096] It should be understood that the present application does not specifically limit the size and / or position of the separation structure 700, and the size and / or position of the separation structure 700 can be arbitrarily set according to the actual process to separate the gate structure 1400 in the sacrificial gap 400 into two parts.

[0097] Exemplarily, as Figure 14 and Figure 15 shown, an isolation structure 1500 adjacent to the second preset layer 1220 along the third direction Z and extending along the first direction Y can be formed on the second sidewall 1142 of the semiconductor column 1140 via the second trench 620.

[0098] Exemplarily, one or more thin film deposition processes can be used to form the isolation structure 1500 in the second trench 620. Exemplarily, the isolation structure 1500 can include a conductive layer and / or an air gap layer. Specifically, an air gap layer (such as an air gap) and / or a conductive layer (such as a metal material layer) can be formed in the second trench 620 according to the pitch of the semiconductor columns 1140, such as the size of the second trench 620 along the second direction X.

[0099] Exemplarily, if the isolation structure 1500 includes a conductive layer, an isolation lead-out structure (not shown) connected to the isolation structure 1500 can also be formed. In the present application, the isolation lead-out structure can be set to be grounded or a certain fixed potential can be applied to the isolation lead-out structure, so that the isolation structure 1500 can electrically insulate between adjacent semiconductor columns 1140 and reduce the coupling phenomenon between adjacent semiconductor columns 1140.

[0100] Exemplarily, as Figure 16 shown, a schematic enlarged structure diagram of the isolation structure 1500 and the second preset layer 1220. The isolation structure 1500 can include a first isolation surface 1510 and a second isolation surface 1520 oppositely arranged along the third direction Z, wherein the first isolation surface 1510 is closer to the second preset layer 1220 than the second isolation surface 1520. The preset layer 1200 includes a first preset surface 1221 and a second preset surface 1222 oppositely arranged along the third direction Z, wherein the first preset surface 1221 is closer to the isolation structure 1500 than the second preset surface 1222.

[0101] In the present application, as Figure 5 and Figure 16 shown, the second preset layer 1220 may extend in the semiconductor layer 1100 along the third direction Z starting from the first surface 1110 of the semiconductor layer 1100, that is, the second preset surface 1222 is closer to the first surface 1110 of the semiconductor layer 1100 than the first preset surface 1221. Limited by the actual etching process, the width of the second preset surface 1222 along the second direction X may be greater than the width of the first preset surface 1221 along the second direction X. In other words, the width of the first preset surface 1221 along the second direction X may be less than the width of the second preset surface 1222 along the second direction X.

[0102] Similarly, as Figure 15 and Figure 16 shown, the isolation structure 1500 may extend in the second trench 620 along the third direction Z starting from the second surface 1120 opposite to the first surface 1110 until it contacts the second preset layer 1220, that is, the second isolation surface 1520 is closer to the second surface 1120 than the first isolation surface 1510, and the first isolation surface 1510 may contact the first preset surface 1221. Limited by the actual etching process, the width of the second isolation surface 1520 along the second direction X may be greater than the width of the first isolation surface 1510 along the second direction X. In other words, the width of the first isolation surface 1510 along the second direction X may be less than the width of the second isolation surface 1520 along the second direction X.

[0103] It should be understood that the width relationship between two surfaces of the gate structure 1400 oppositely arranged along the third direction Z may have a similar relationship to the width relationship between the first isolation surface 1510 and the second isolation surface 1520 in the isolation structure 1500. The width relationship between two surfaces of the first preset layer 1210 oppositely arranged along the third direction Z may have a similar relationship to the width relationship between the first preset surface 1221 and the second preset surface 1222 in the second preset layer 1220. To avoid redundancy, the present application will not elaborate in detail herein.

[0104] In an exemplary embodiment of the present application, as Figure 17 shown, the semiconductor pillar 1140 may include a first end 1143 and a second end 1144 oppositely arranged along the third direction Z, where the second end 1144 is closer to the preset layer 1200 than the first end 1143. In other words, the first end 1143 may be located on the second surface 1120, and the second end 1144 may be located on the first surface 1110.

[0105] Exemplarily, a capacitor 1610 may be formed and connected to the first end 1143. For example, a capacitor layer 1600 may be formed on the second surface 1120, where the capacitor layer 1600 may include a plurality of capacitors 1610. The capacitor 1610 may include a first electrode (not shown) connected to the first end 1143 of the semiconductor pillar 1140, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1610 may include, but is not limited to, a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor, etc. Exemplarily, the capacitor 1610 may be a vertical capacitor, where the first electrode, the capacitor dielectric, and the second electrode are stacked along the third direction Z, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0106] Figure 18 To Figure 17 is a schematic structural diagram of the structure after flipping the structure by 180° and then thinning. In an exemplary embodiment of the present application, as Figure 18 shown, the carrier wafer 500 may be removed to expose the second end 1144 of the conductor pillar 1140.

[0107] Exemplarily, the carrier wafer 500, the second bonding layer 420, and the first bonding layer 410 may be removed to expose the second end 1144 of the conductor pillar 1140. For example, the carrier wafer 500, the second bonding layer 420, and the first bonding layer 410 may be removed by at least one of the removal processes such as grinding, wet etching, dry etching, and planarization processing.

[0108] In an exemplary embodiment of the present application, as Figure 19 shown, a bit line 1700 may be formed and connected to the second end 1144 of the semiconductor pillar 1140 and extending along the second direction X. The bit line 1700 may be adjacent to the gate structure 1400 along the third direction Z. Exemplarily, a gate lead-out structure 1810 and a bit line lead-out structure 1820 may be formed from the side close to the second end 1144 and connected to the gate structure 1400 and the bit line 1700 respectively. The gate lead-out structure 1810 and the bit line lead-out structure 1820 may be used to realize the connection between the gate structure 1400 and the bit line 1700 and an external circuit respectively.

[0109] Figure 19 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application.

[0110] The semiconductor structure may include a semiconductor pillar 1140, a gate structure 1400, and a preset layer 1200.

[0111] The semiconductor columns 1140 can be arrayed along a first direction Y and a second direction X. The semiconductor columns 1140 can extend along a third direction Z, where the first direction Y, the second direction X, and the third direction Z can intersect pairwise. The gate structure 1400 can be located on at least one side of the semiconductor columns 1140 along the second direction X. The preset layer 1200 can be located on one side of the gate structure 1400 along the third direction Z. The gate structure 1400 and the preset layer 1200 can extend along the first direction Y and be arranged along the second direction X.

[0112] The plurality of semiconductor columns 1140 are spaced apart from each other. For example, the semiconductor columns 1140 can have a cubic shape to expose their four side walls. It should be understood that the semiconductor columns 1140 can have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor columns 1140 in a planar view (e.g., in the X-Y plane) can have a square shape, a rectangular shape (or a trapezoidal shape), a circular (or an elliptical shape), or any other suitable shape.

[0113] The material of the semiconductor columns 1140 can include at least one of single-crystalline silicon, polycrystalline silicon, single-crystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0114] Exemplarily, the semiconductor column 1140 can include a first side wall 1141 and a first side wall 1142 that are oppositely arranged along the second direction X. The preset layer 1200 can include a first preset layer 1210 and a second preset layer 1220 that are spaced apart. The first preset layer 1210 can be located on the first side wall 1141, and the second preset layer 1220 can be located on the first side wall 1142. The gate structure 1400 can be located on the first side wall 1141 and can be in contact with the preset layer 1200 along the third direction Z.

[0115] Exemplarily, the semiconductor structure can further include an isolation structure 1500 located on the second side wall 1142 of the semiconductor column 1140. The isolation structure 1500 can be adjacent to the second preset layer 1220 along the third direction Z and extend along the first direction Y.

[0116] The preset layer 1200 can include a single-layer structure, and its material can include an insulating material such as silicon nitride. The first preset layer 1210 and the second preset layer 1220 can have different widths along the second direction X so as to facilitate the gate structure 1400 being adjacent to the first preset layer 1210 along the third direction Z and the isolation structure 1500 being adjacent to the second preset layer 1220 along the third direction Z. It should be understood that the plurality of preset layers 1200 can also have substantially the same width. In actual processes, the widths of the plurality of preset layers 1200 can be reasonably set according to actual requirements. The plurality of preset layers 1200 have substantially the same height along the third direction Z.

[0117] The gate structure 1400 may include a gate dielectric layer 1410 and a gate layer 1420. The gate dielectric layer 1410 may be located on the first sidewall 1141 of the semiconductor pillar 1140, adjacent to the preset layer 1200 along the third direction Z and extending along the first direction Y. The gate layer 1420 may be located on the side of the gate dielectric layer 1410 away from the semiconductor pillar 1140.

[0118] Exemplarily, the semiconductor structure may further include a dielectric layer 1430 on the side of the gate layer 1420 away from the gate dielectric layer 1410, and an air gap 1440 may exist in the dielectric layer 1430. The dielectric layer 1430 may separate two gate structures 1400 from each other.

[0119] The gate dielectric layer 1410 and / or the dielectric layer 1430 may include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. For example, the gate dielectric layer 1410 and / or the dielectric layer 1430 may include silicon oxide. The gate layer 1420 may include one or more conductive materials such as metals and / or metal compounds such as tungsten W and / or titanium nitride TiN. The gate structure 1400 may be connected to the peripheral circuit to realize the transmission of electrical signals between the gate electrode and the peripheral circuit.

[0120] In an exemplary embodiment of the present application, the semiconductor pillar 1140 may include a first end 1143 and a second end 1144 that are oppositely arranged along the third direction Z, where the second end 1144 is closer to the preset layer 1200 than the first end 1143. The first end 1143 may be coplanar with the surface of the gate structure 1400 away from the preset layer 1200, and the second end 1144 may be coplanar with the surface of the preset layer 1200 away from the gate structure 1400.

[0121] In the present application, as described above, the first ends 1143 of the plurality of semiconductor pillars 1140 may be located on the second surface 1120, where the second surface 1120 may extend along the second direction X. On this basis, the surface of the gate structure 1400 away from the preset layer 1200 is coplanar with the first end 1143, which is beneficial to realizing that the surfaces of the plurality of gate structures 1400 away from the preset layer 1200 can extend along the second direction X. In other words, the surfaces of the plurality of gate structures 1400 away from the preset layer 1200 may be substantially flush.

[0122] In addition, by providing the preset layer 1200 in the present application, it is possible to make the positions where multiple preset layers 1200 extend into the semiconductor layer 1100 substantially flush along the second direction X. On this basis, setting the surface of the preset layer 1200 away from the gate structure 1400 to be coplanar with the second end 1144 and the gate structure 1400 extending along the third direction Z to the first preset layer 1210 is conducive to making the surfaces of multiple gate structures 1400 in contact with the first preset layer 1210 substantially flush. It can be seen that the heights of the multiple gate structures 1400 provided in the present application along the third direction Z are highly consistent, which is conducive to reducing the process difficulty of forming the semiconductor structure and improving the performance of the semiconductor structure.

[0123] Exemplarily, the semiconductor pillar 1140 and the gate structure 1400 can be jointly used to form a vertical transistor, where the semiconductor pillar 1140 can be used to form the active regions of multiple channels in the vertical transistor. Exemplarily, the gate structure 1400 can be located on at least one sidewall of the semiconductor pillar 1140, that is, the semiconductor pillar 1140 can be at least partially surrounded by the gate structure 1400. For example, the semiconductor pillar 1140, the gate dielectric layer 1410, and the gate layer 1420 can be radially arranged in this order from the center of the vertical transistor. Exemplarily, the gate dielectric layer 1410 can surround and contact the semiconductor pillar 1140. The gate layer 1420 can surround and contact the gate dielectric layer 1410.

[0124] It should be understood that Figure 19 the case where the gate structure 1400 shown in

[0125] is located on one sidewall of the semiconductor pillar 1140 is only an example and not a specific limitation. In an embodiment of the present application, the gate structure 1400 can be located on multiple sidewalls of the semiconductor pillar 1140. At this time, the semiconductor pillar 1140 and the gate structure 1400 can be jointly used to form a multi-gate transistor (for example, a gate-all-around (GAA) transistor, a triple-gate transistor, or a double-gate transistor). The multi-gate transistor can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the cut-off state, since the channel is completely depleted, the leakage current of the multi-gate transistor can also be significantly reduced. Therefore, using a multi-gate transistor can achieve better speed (saturated drain current) / leakage current performance.

[0126] In another embodiment of the present application, the gate structure 1400 may be located on a sidewall of the semiconductor pillar 1140. At this time, the semiconductor pillar 1140 and the gate structure 1400 can be jointly used to form a single-gate transistor. Exemplarily, the single-gate transistors adjacent along the second direction X may be symmetrically arranged. By providing the single-gate transistors in the present application, the density of the semiconductor pillars 1140 in the second direction X can be significantly increased, and the manufacturing process difficulty can be reduced. In addition, the symmetric single-gate transistors may have a larger process window, which is beneficial to reducing the pitch between, for example, the bit lines, word lines, and transistors formed subsequently.

[0127] Exemplarily, as Figure 14 shown, the semiconductor structure may further include a partitioning structure 700 that penetrates through the gate dielectric layer 1410 and the gate layer 1420 along the third direction Z to partition the annular gate structure 1400 into at least two parts. In other words, the two partitioning structures 700 partition the annular gate dielectric layer 1410 into two parts and partition the gate layer 1420 into two parts.

[0128] It should be understood that the present application does not specifically limit the size and / or position of the partitioning structure 700, and the size and / or position of the partitioning structure 700 can be arbitrarily set according to the actual process to partition the gate structure 1400 in the sacrificial gap 400 into two parts.

[0129] Exemplarily, the isolation structure 1500 may include a conductive layer and / or an air gap layer. Specifically, the size of the isolation structure 1500 along the second direction X can be set according to the pitch between adjacent semiconductor pillars 1140.

[0130] Exemplarily, if the isolation structure 1500 includes a conductive layer, an isolation lead-out structure (not shown) connected to the isolation structure 1500 may also be formed. In the present application, the isolation lead-out structure can be set to be grounded or a certain fixed potential can be applied to the isolation lead-out structure, so that the isolation structure 1500 can electrically insulate between adjacent semiconductor pillars 1140 and reduce the coupling phenomenon between adjacent semiconductor pillars 1140.

[0131] Exemplarily, as Figure 16 shown, a schematic enlarged view of the isolation structure 1500 and the second preset layer 1220. The isolation structure 1500 may include a first isolation surface 1510 and a second isolation surface 1520 that are oppositely arranged along the third direction Z, where the first isolation surface 1510 is closer to the second preset layer 1220 than the second isolation surface 1520. The preset layer 1200 includes a first preset surface 1221 and a second preset surface 1222 that are oppositely arranged along the third direction Z, where the first preset surface 1221 is closer to the isolation structure 1500 than the second preset surface 1222.

[0132] In the present application, as Figure 5and Figure 16 As shown, the second preset layer 1220 may extend in the semiconductor layer 1100 along the third direction Z starting from the first surface 1110 of the semiconductor layer 1100. That is, the second preset surface 1222 is closer to the first surface 1110 of the semiconductor layer 1100 than the first preset surface 1221. Limited by the actual etching process, the width of the second preset surface 1222 along the second direction X may be greater than the width of the first preset surface 1221 along the second direction X. In other words, the width of the first preset surface 1221 along the second direction X may be less than the width of the second preset surface 1222 along the second direction X.

[0133] Similarly, as Figure 15 and Figure 16 shown, the isolation structure 1500 may extend in the second trench 620 along the third direction Z starting from the second surface 1120 opposite to the first surface 1110 until it contacts the second preset layer 1220. That is, the second isolation surface 1520 is closer to the second surface 1120 than the first isolation surface 1510, and the first isolation surface 1510 may contact the first preset surface 1221. Limited by the actual etching process, the width of the second isolation surface 1520 along the second direction X may be greater than the width of the first isolation surface 1510 along the second direction X. In other words, the width of the first isolation surface 1510 along the second direction X may be less than the width of the second isolation surface 1520 along the second direction X.

[0134] It should be understood that the width relationship between the two surfaces of the gate structure 1400 oppositely arranged along the third direction Z may have a similar relationship to the width relationship between the first isolation surface 1510 and the second isolation surface 1520 in the isolation structure 1500. The width relationship between the two surfaces of the first preset layer 1210 oppositely arranged along the third direction Z may have a similar relationship to the width relationship between the first preset surface 1221 and the second preset surface 1222 in the second preset layer 1220. To avoid redundancy, this application will not elaborate in detail here.

[0135] In an exemplary embodiment of the present application, as Figure 19As shown, the semiconductor structure may further include a capacitor 1610 connected to the first end 1143. For example, a capacitor layer 1600 may be located on the first end 1143, where the capacitor layer 1600 may include a plurality of capacitors 1610. The capacitor 1610 may include a first electrode (not shown) connected to the first end 1143 of the semiconductor pillar 1140, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1610 may include, but is not limited to, a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor, etc. Exemplarily, the capacitor 1610 may be a vertical capacitor, where the first electrode, the capacitor dielectric, and the second electrode are stacked along the third direction Z, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0136] In an exemplary embodiment of the present application, as Figure 19 shown, the semiconductor structure may further include a bit line 1700 connected to the second end 1144 of the semiconductor pillar 1140 and extending along the second direction X. The bit line 1700 may be adjacent to the gate structure 1400 along the third direction Z.

[0137] Exemplarily, the semiconductor structure may further include a gate lead-out structure 1810 and a bit line lead-out structure 1820 located on one side close to the preset layer 1200 and connected to the gate structure 1400 and the bit line 1700 respectively. The gate lead-out structure 1810 and the bit line lead-out structure 1820 may be respectively used to realize the connection between the gate structure 1400 and the bit line 1700 and an external circuit.

[0138] Since the content and structure involved in describing the method 1000 for manufacturing the semiconductor structure above may be fully or partially applicable to the semiconductor structure described here, the related or similar content will not be repeated here.

[0139] Although an exemplary structure and preparation method of the semiconductor structure are described herein, it can be understood that one or more features may be omitted, substituted, or added from the preparation method of the semiconductor structure. Additionally, the exemplified layers and their materials are merely exemplary.

[0140] Figure 20 is a schematic block diagram of a memory 2000 according to an exemplary embodiment of the present application. Figure 21 is a partial schematic structural diagram of a memory 2000 according to an exemplary embodiment of the present application. The memory 2000 may include a memory cell array 2100 and a peripheral circuit 2200.

[0141] The memory cell array 2100 and the peripheral circuit 2200 may be separately formed on different substrates and then bonded to form the memory 2000.

[0142] The peripheral circuit 2200 may be coupled to the memory cell array 2100. The peripheral circuit 2200 (also referred to as the control and sensing circuit) may include any suitable digital, analog, and / or mixed-signal circuits for facilitating the operation of the memory cell array 2100. For example, the peripheral circuit 2200 may include a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion of the above functional circuits (e.g., a sub-circuit), or any active or passive component of a circuit (e.g., a transistor, a diode, a resistor, or a capacitor), one or more of them.

[0143] The memory cell array 2100 may include an array of memory cells (such as the semiconductor structure 1000 described above) using transistors as switches and selection devices. In some embodiments, the memory cell array 2100 includes a DRAM cell array. For ease of description, the DRAM cell array may be used as an example for describing the memory cell array 2100 in the present application. However, it should be understood that the memory cell array 2100 is not limited to the DRAM cell array, and may include any other suitable type of memory cell array that can use transistors as switches and selection devices, such as a PCM cell array, a static random-access memory (SRAM) cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, just to name a few examples, or any combination thereof.

[0144] The memory cell array 2100 may be a DRAM device, where the memory cells are provided in the form of a DRAM cell array. In some embodiments, each DRAM cell includes a capacitor for storing a data bit as a positive charge or a negative charge and one or more transistors (also referred to as transfer transistors) for controlling (e.g., switching and selecting) access to the DRAM cell. In some embodiments, each DRAM cell is a one-transistor-one-capacitor (1T1C) cell. The DRAM cells may be refreshed, for example, by the peripheral circuit 2200 to maintain data.

[0145] Figure 22 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0146] System 10 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (which has a storage system 12 located therein). As Figure 22 shown, system 10 may include a host 18 and a storage system 12, and the storage system 12 has one or more memories 2000 (such as may include a three-dimensional memory 14) and a controller 16. The host 18 can be a processor of the electronic device, such as a central processing unit (CPU), or can be a system-on-chip (SoC), such as an application processor (AP). The host 18 can be configured to send or receive data to and from the three-dimensional memory 14.

[0147] The three-dimensional memory 14 can include the semiconductor structures described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage the data stored in the three-dimensional memory 14 and communicate with the host 18. For example, the controller 16 can communicate with an external device (such as the host 18) according to a specific communication protocol.

[0148] The above description is only the preferred embodiment of the present application and the explanation of the applied technical principles. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present application.

Claims

1. A method of manufacturing a semiconductor structure, characterized in that, The method includes: Forming a plurality of preset layers extending in a first direction and arranged in a second direction in a semiconductor layer; Forming a plurality of semiconductor pillars distributed in an array in the first direction and the second direction in the semiconductor layer, wherein sidewalls of the semiconductor pillars are in contact with the preset layers; and Forming a gate structure on sidewalls of the semiconductor pillars, adjacent to the preset layers in a third direction and extending in the first direction, wherein the first direction, the second direction, and the third direction intersect pairwise.

2. The method according to claim 1, characterized in that, Forming a plurality of preset layers extending in a first direction and arranged in a second direction in a semiconductor layer includes: Forming a plurality of grooves extending in the first direction and arranged in the second direction in the semiconductor layer; and Filling insulating materials in the grooves to form the preset layers.

3. The method according to claim 1, characterized in that, The method further includes: Forming a dielectric layer at a preset depth of an initial semiconductor layer, wherein the dielectric layer divides the initial semiconductor layer into the semiconductor layer and a remaining layer, and the preset layers extend in the semiconductor layer in the third direction starting from a first surface of the semiconductor layer away from the dielectric layer.

4. The method according to claim 3, wherein The method further includes: Removing the remaining layer and the dielectric layer to expose a second surface of the semiconductor layer opposite to the first surface, wherein a top surface of the semiconductor pillar is coplanar with the second surface, and the gate structure extends from the second surface in the third direction to the preset layers.

5. The method according to claim 1, characterized in that, Forming a plurality of semiconductor pillars distributed in an array in the first direction and the second direction in the semiconductor layer includes: Forming a plurality of isolation portions extending in the second direction and the third direction in the semiconductor layer, wherein the plurality of isolation portions divide the semiconductor layer into a plurality of initial semiconductor pillars, and the initial semiconductor pillars and the isolation portions are alternately arranged in the first direction; and Forming a plurality of trenches extending through the initial semiconductor pillars, extending in the first direction, and arranged in the second direction, wherein surfaces of the preset layers are exposed by the plurality of trenches, and the trenches and the preset layers divide the semiconductor layer into a plurality of semiconductor pillars extending in the third direction, and the gate structure is located in the trenches.

6. The method according to claim 5, characterized in that, The plurality of trenches include a first trench and a second trench arranged adjacent to each other. The first trench exposes a first sidewall of the semiconductor pillar, and the second trench exposes a second sidewall of the semiconductor pillar opposite to the first sidewall in the second direction. The method includes: Forming the gate structure on the first sidewall of the semiconductor pillar; and Forming an isolation structure on the second sidewall of the semiconductor pillar, adjacent to the preset layers in the third direction and extending in the first direction.

7. The method according to claim 1, wherein The gate structure includes a gate dielectric layer and a gate layer, wherein forming a gate structure on sidewalls of the semiconductor pillars, adjacent to the preset layers in the third direction and extending in the first direction, includes: Forming the gate dielectric layer on sidewalls of the semiconductor pillars, adjacent to the preset layers in the third direction and extending in the first direction; and The gate layer is formed on a side of the gate dielectric layer away from the semiconductor pillar.

8. The method according to claim 3, characterized in that, Forming a dielectric layer at a preset depth of the initial semiconductor layer, including: Injecting ions at the preset depth of the initial semiconductor layer by ion implantation to form the dielectric layer.

9. The method according to claim 4, wherein The method further includes: Bonding a carrier wafer to a first surface of the semiconductor layer; and Removing the remaining layer and the dielectric layer to expose a second surface of the semiconductor layer.

10. The method according to claim 9, wherein The semiconductor pillar includes a first end and a second end oppositely arranged along the third direction, wherein the second end is closer to the preset layer than the first end, and the method further includes: Forming a capacitor connected to the first end.

11. The method according to claim 10, wherein, Removing the carrier wafer to expose the second end of the conductor pillar; and Forming a bit line connected to the second end and extending along the second direction.

12. The method according to claim 11, wherein, Forming a gate lead-out structure and a bit line lead-out structure respectively connected to the gate structure and the bit line from a side close to the second end.

13. A semiconductor structure, characterized in that, Including: Semiconductor pillars, arrayed and distributed along a first direction and a second direction; Gate structures, located on at least one side of the semiconductor pillars along the second direction; And A preset layer, located on a side of the gate structures along a third direction, wherein the first direction, the second direction and the third direction intersect pairwise.

14. The semiconductor structure according to claim 13, wherein, The preset layer includes a single-layer structure, and its material includes an insulating material.

15. The semiconductor structure according to claim 13, wherein, The semiconductor pillar includes a first end and a second end oppositely arranged along the third direction, wherein the first end is coplanar with a surface of the gate structure away from the preset layer, and the second end is coplanar with a surface of the preset layer away from the gate structure.

16. The semiconductor structure according to claim 13, wherein The gate structure is located at a first side wall of the semiconductor pillar and extends along the first direction, and the semiconductor structure further includes: An isolation structure, located on a second side wall of the semiconductor pillar opposite to the first side wall, adjacent to the preset layer along the third direction and extending along the first direction.

17. The semiconductor structure according to claim 13, wherein, The gate structure includes: A gate dielectric layer, located on a side wall of the semiconductor pillar, adjacent to the preset layer along the third direction and extending along the first direction; and A gate layer, located on a side of the gate dielectric layer away from the semiconductor pillar.

18. The semiconductor structure according to claim 15, wherein, The semiconductor structure further includes: A capacitor, connected to the first end; and A bit line, connected to the second end and extending along the second direction.

19. The semiconductor structure according to claim 18, wherein The semiconductor structure further includes: a gate lead-out structure and a bit line lead-out structure located on a side close to the preset layer and respectively connected to the gate structure and the bit line.

20. The semiconductor structure according to claim 16, wherein, The isolation structure includes a first isolation surface and a second isolation surface oppositely arranged along the third direction, wherein the first isolation surface is closer to the preset layer than the second isolation surface; The preset layer includes a first preset surface and a second preset surface oppositely arranged along the third direction, wherein the first preset surface is closer to the isolation structure than the second preset surface; Wherein, the width of the first isolation surface is smaller than the width of the second isolation surface, and the width of the first preset surface is smaller than the width of the second preset surface.

21. A memory, characterized in that, Comprising: A memory cell array including the semiconductor structure according to any one of claims 13 to 20; And Peripheral circuits coupled to the memory cell array.

22. A storage system, characterized in that, Comprising: At least one memory according to claim 21; And A controller coupled to the memory for controlling the memory to store data.

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