Semiconductor structure, preparation method thereof and storage system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method thereof and a storage system, and aims to reduce electric leakage between two adjacent vertical transistors. The semiconductor structure provided by the embodiment of the invention comprises a plurality of semiconductor columns which are arranged at intervals along a second direction, and gate structures and isolation structures are alternately arranged between two adjacent semiconductor columns at intervals; the gate structures and the adjacent semiconductor columns form vertical transistors, and the conductive blocks in the isolation structures are located between two adjacent vertical transistors; in the process that the vertical transistors are conducted, the conductive blocks between the vertical transistors can enable electrons in the conducted vertical transistors not to easily penetrate through the conductive blocks to move towards the adjacent vertical transistors, the coupling effect between the adjacent vertical transistors is improved, and then electric leakage between the adjacent vertical transistors is reduced.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of semiconductor chips, and particularly to a semiconductor structure, a preparation method thereof, and a storage system. Background Art

[0002] A semiconductor structure includes a plurality of vertical transistors and a plurality of storage capacitors. The vertical transistors are connected to the storage capacitors, and the storage capacitors are connected to the source electrodes of the vertical transistors. The conduction or cutoff of the vertical transistors determines whether the information stored in the storage capacitors can be read and rewritten. The storage capacitors represent logical 1 and 0 by the amount of charge stored therein, or rather, the high and low voltage differences across the capacitors. However, there is a problem of leakage between adjacent transistors. Summary of the Invention

[0003] Embodiments of the present application adopt the following technical solutions:

[0004] On the one hand, embodiments of the present application provide a semiconductor structure, including a plurality of semiconductor pillars, gate structures, and isolation structures. The semiconductor pillars extend along a first direction, and the plurality of semiconductor pillars are spaced apart along a second direction, where the second direction is perpendicular to the first direction. The gate structures and the isolation structures are alternately spaced apart along the second direction. The gate structures are located between two adjacent semiconductor pillars, and the isolation structures are also located between two adjacent semiconductor pillars. The isolation structure includes: a first insulating block, a conductive block, and a second insulating block. Along the first direction, the conductive block is located between the first insulating block and the second insulating block. The first insulating block includes a first insulating layer and a second insulating layer. The first insulating layer is located on the side of the conductive block away from the second insulating block. The first insulating layer wraps the second insulating layer, so that part of the first insulating layer is located between the second insulating layer and the conductive block, and part of the first insulating layer is located between the second insulating layer and the semiconductor pillar.

[0005] In some embodiments, the first insulating layer includes a first hollow cylinder that extends along a third direction perpendicular to the first direction and the second direction. The outer sidewall of the first hollow cylinder is in contact with the conductive block and the semiconductor pillar. The second insulating layer includes a second hollow cylinder that extends along the third direction. The outer sidewall of the second hollow cylinder is in contact with the inner sidewall of the first hollow cylinder.

[0006] In some embodiments, the material of the first insulating layer includes silicon nitride, and the material of the second insulating layer includes an insulating oxide material.

[0007] In some embodiments, the lengths of the plurality of conductive blocks in the first direction are equal, and the ends of the conductive blocks away from the second insulating block are aligned in the second direction.

[0008] In some embodiments, the isolation structure further includes an isolation layer located between the conductive block and the semiconductor pillar.

[0009] In some embodiments, the isolation layer includes a first isolation layer and a second isolation layer stacked along a second direction. The first isolation layer is located between the second isolation layer and the semiconductor pillar, and the second isolation layer is located between the first isolation layer and the conductive block.

[0010] In some embodiments, one side of the first isolation layer close to the semiconductor pillar is in contact with the semiconductor pillar, one side of the first isolation layer away from the semiconductor pillar is in contact with the second isolation layer, and one side of the second isolation layer away from the first isolation layer is in contact with the conductive block.

[0011] In some embodiments, the isolation structure further includes a first conductive pillar, and the first conductive pillar passes through a part of the first insulating layer and a part of the second insulating layer to contact the conductive block.

[0012] On the other hand, an embodiment of the present application further provides a method for manufacturing a semiconductor structure, including:

[0013] Forming a plurality of semiconductor pillars, the semiconductor pillars extending along a first direction, the plurality of semiconductor pillars being spaced along a second direction, and forming gate trenches and isolation trenches alternately spaced along the second direction, where the second direction is perpendicular to the first direction;

[0014] Forming a gate structure in the gate trenches and forming an isolation structure in the isolation trenches, so that the gate structure and the isolation structure are alternately spaced along the second direction;

[0015] Forming the isolation structure includes: forming a first insulating block, a conductive block, and a second insulating block along the first direction, so that the conductive block is located between the first insulating block and the second insulating block;

[0016] Forming the first insulating block includes: forming a first insulating layer and a second insulating layer, so that the first insulating layer is located on a side of the conductive block away from the second insulating block, the first insulating layer wraps the second insulating layer, so that a part of the first insulating layer is located between the second insulating layer and the conductive block, and a part of the first insulating layer is located between the second insulating layer and the semiconductor pillar.

[0017] In some embodiments, before forming the isolation structure, it further includes:

[0018] Forming an initial isolation layer in the isolation trench, the initial isolation layer covering the sidewall of the isolation trench extending along the first direction and covering the bottom wall of the isolation trench;

[0019] Sequentially forming a third insulating block, a conductive block, and a second insulating block in the isolation trench, so that the conductive block is located between the third insulating block and the second insulating block;

[0020] Forming the third insulating block includes: forming an initial third insulating block above the initial isolation layer, and removing a part of the initial third insulating block to form the third insulating block, such that the perpendicular distance from one end of each third insulating block away from the bottom wall of the isolation groove to the bottom wall of the isolation groove is the same.

[0021] In some embodiments, forming the first insulating block includes:

[0022] Removing a part of the initial isolation layer adjacent to the third insulating block, and the remaining part of the initial isolation layer forms the isolation layer;

[0023] Removing the third insulating block, and forming the first insulating block at the position where the third insulating block is removed and at the position where the removed part of the initial isolation layer is located.

[0024] In some embodiments, forming the conductive block includes:

[0025] After forming the third insulating block, forming an initial conductive block, and removing a part of the initial conductive block to form the conductive block, such that the third insulating block and the conductive block are in contact along the second direction; and the initial isolation layer is located between the conductive block and the semiconductor pillar.

[0026] In some embodiments, forming the initial isolation layer includes: forming an initial first isolation layer, and forming an initial second isolation layer;

[0027] The remaining initial isolation layer forms the isolation layer including: after removing a part of the initial isolation layer adjacent to the third insulating block, the remaining initial first isolation layer forms the first isolation layer, the remaining initial second isolation layer forms the second isolation layer, and the first isolation layer and the second isolation layer form the isolation layer.

[0028] In some embodiments, after forming the first insulating block, further including:

[0029] Removing a part of the first insulating layer and the second insulating layer to form a first conductive hole extending along the first direction, and one end of the first conductive hole is located on a side of the conductive block away from the second insulating block;

[0030] Forming a first conductive pillar in the first conductive hole, such that the first conductive pillar is connected to the conductive block to form an isolation structure.

[0031] In another aspect, an embodiment of the present application further provides a storage system, including a 3D memory and a controller. The 3D memory may include the semiconductor structure as described above; the controller is coupled to the 3D memory to control the 3D memory to store data.

[0032] In another aspect, an embodiment of the present application further provides an electronic device, including a host and the storage system as above, and the host and the storage system are coupled. Description of the Drawings

[0033] To more clearly illustrate the technical solutions in this application, the following will briefly introduce the drawings required for use in some embodiments of this application. Obviously, the drawings in the following description are only the drawings of some embodiments of this application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and are not limitations on the actual dimensions of the products involved in the embodiments of this application, the actual processes of the methods, the actual timings of the signals, etc.

[0034] Figure 1 A three-dimensional structure diagram of a semiconductor structure according to some embodiments;

[0035] Figure 2 A cross-sectional view of a semiconductor structure according to some embodiments;

[0036] Figure 3 For Figure 1 A structure diagram of a storage cell in

[0037] Figure 4 For Figure 3 An equivalent circuit diagram of the storage cell shown;

[0038] Figure 5 A structural schematic diagram of a semiconductor structure in some embodiments of this application;

[0039] Figure 6 Another structural schematic diagram of a semiconductor structure in some embodiments of this application;

[0040] Figure 7 A flowchart of a manufacturing method of a semiconductor structure in some embodiments of this application;

[0041] Figure 8 A structural schematic diagram of a semiconductor layer provided in some embodiments of this application;

[0042] Figure 9 A structural schematic diagram before forming a gate trench and an isolation trench in some embodiments of this application;

[0043] Figure 10 A structural schematic diagram after forming a gate trench and an isolation trench in some embodiments of this application;

[0044] Figure 11 A structural schematic diagram before filling a sacrificial material into the gate trench and the isolation trench in some embodiments of this application;

[0045] Figure 12 A structural schematic diagram after filling a sacrificial material into the gate trench and the isolation trench in some embodiments of this application;

[0046] Figure 13Schematic diagram of the structure in the third direction after filling the sacrificial material in some embodiments of the present application;

[0047] Figure 14 Schematic diagram of the structure after removing the sacrificial material in the isolation groove in some embodiments of the present application;

[0048] Figure 15 Schematic diagram of the structure after forming the initial isolation layer in some embodiments of the present application;

[0049] Figure 16 Schematic diagram of the structure after forming the initial third insulating block in some embodiments of the present application;

[0050] Figure 17 Schematic diagram of the structure after forming the third insulating block in some embodiments of the present application;

[0051] Figure 18 Schematic diagram of the structure after forming the initial conductive block in some embodiments of the present application;

[0052] Figure 19 Schematic diagram of the structure after forming the conductive block in some embodiments of the present application;

[0053] Figure 20 Schematic diagram of the structure after forming the initial second insulating block in some embodiments of the present application;

[0054] Figure 21 Schematic diagram of the structure after forming the second insulating block in some embodiments of the present application;

[0055] Figure 22 Schematic diagram of the structure after forming the initial first isolation layer and the initial second isolation layer in some embodiments of the present application;

[0056] Figure 23 Another schematic diagram of the structure after forming the initial third insulating block in some embodiments of the present application;

[0057] Figure 24 Another schematic diagram of the structure after forming the third insulating block in some embodiments of the present application;

[0058] Figure 25 Another schematic diagram of the structure after forming the initial conductive block in some embodiments of the present application;

[0059] Figure 26 Another schematic diagram of the structure after forming the conductive block in some embodiments of the present application;

[0060] Figure 27 Another schematic diagram of the structure after forming the initial second insulating block in some embodiments of the present application;

[0061] Figure 28Another schematic structural diagram after forming the second insulating block in some embodiments of the present application;

[0062] Figure 29 Another schematic structural diagram after forming the isolation groove in some embodiments of the present application;

[0063] Figure 30 Another schematic structural diagram after forming the initial second isolation layer in some embodiments of the present application;

[0064] Figure 31 Schematic structural diagram after forming the initial first gate layer in some embodiments of the present application;

[0065] Figure 32 Schematic structural diagram after forming the initial second gate layer in some embodiments of the present application;

[0066] Figure 33 Schematic structural diagram after forming the filling layer in some embodiments of the present application;

[0067] Figure 34 Schematic structural diagram after removing a part of the initial isolation layer in some embodiments of the present application;

[0068] Figure 35 Schematic structural diagram after forming the gate layer in some embodiments of the present application;

[0069] Figure 36 Schematic structural diagram after removing a part of the initial first isolation layer and a part of the initial second isolation layer in some embodiments of the present application;

[0070] Figure 37 Schematic structural diagram after removing the third insulating block in some embodiments of the present application;

[0071] Figure 38 Schematic structural diagram after forming the first insulating layer in some embodiments of the present application;

[0072] Figure 39 Schematic structural diagram after forming the second insulating layer in some embodiments of the present application;

[0073] Figure 40 Schematic structural diagram after forming the first conductive hole in some embodiments of the present application;

[0074] Figure 41 Schematic structural diagram after forming the first conductive pillar in some embodiments of the present application;

[0075] Figure 42 Schematic structural diagram in the first direction after forming the first conductive pillar and the second conductive pillar in some embodiments of the present application;

[0076] Figure 43Schematic diagram of the structure after forming the second conductive hole in some embodiments of the present application;

[0077] Figure 44 Schematic diagram of the structure after forming the second conductive pillar in some embodiments of the present application;

[0078] Figure 45 Frame of the storage system in some embodiments of the present application Figure One ;

[0079] Figure 46 Frame of the storage system in some embodiments of the present application Figure Two 。

[0080] Description of reference numerals: 1, semiconductor structure; 2, memory cell array layer; 3, device layer; 4, vertical transistor; 5, semiconductor pillar; 6, gate structure; 7, gate dielectric layer; 8, storage capacitor; 9, bit line; 10, wiring layer; 11, peripheral circuit layer; 12, first connection portion; 13, second connection portion; 14, semiconductor pillar group; 15, gate layer; 16, isolation structure; 17, first insulating block; 18, conductive block; 19, second insulating block; 20, first insulating layer; 21, second insulating layer; 22, first hollow cylinder; 23, second hollow cylinder; 24, first conductive pillar; 25, isolation layer; 26, first isolation layer; 27, second isolation layer; 28, semiconductor layer; 29, mask plate; 30, insulating groove; 31, dielectric material; 32, gate groove; 33, isolation groove; 34, sacrificial material; 35, initial isolation layer; 36, third insulating block; 37, initial third insulating block; 38, initial conductive block; 39, initial second insulating block; 40, initial first isolation layer; 41, initial second isolation layer; 42, initial first gate layer; 43, initial second gate layer; 44, filling layer; 45, initial filling layer; 46, first conductive hole; 47, second conductive hole; 48, first gate notch; 49, second gate notch; 50, second conductive pillar; 51, controller; 52, 3D memory; 1000, storage system. Detailed implementation manners

[0081] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0082] In the description of the present application, it should be understood that the orientation or positional relationships indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present application.

[0083] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0084] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0085] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. Another example is that when describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical contact or electrical contact. However, the term "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments invented herein are not necessarily limited to the content herein.

[0086] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0087] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0088] As used herein, "about", "substantially" or "approximately" includes the stated value and an average within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by a person of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0089] In the context of this application, the meanings of "on", "above", and "over" should be construed in the broadest manner such that "on" not only means "directly on something", but also includes "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over something", but also includes "above" or "over something" with no intermediate features or layers therebetween (i.e., directly on something).

[0090] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0091] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0092] Figure 1 is a three-dimensional structural diagram of a semiconductor structure according to some embodiments, Figure 2 is a cross-sectional view of a semiconductor structure according to some embodiments, Figure 3 is Figure 1 a structural diagram of one of the memory cells in Figure 4 is Figure 3 an equivalent circuit diagram of the memory cell shown.

[0093] It should be noted that in Figure 1 and Figure 2In this case, a semiconductor structure 1 provided by an embodiment of the present application is in a three-dimensional coordinate system of X - Y - Z. The semiconductor structure 1 extends in the Y - Z plane. The second direction Y and the third direction Z are, for example, two orthogonal directions in the plane where the semiconductor structure 1 is located (for example, the plane where the source layer SL is located). The second direction Y is, for example, the extending direction of the bit line (BL), and the third direction Z is, for example, the extending direction of the word line (WL). The first direction X is perpendicular to the plane where the semiconductor structure 1 is located, that is, perpendicular to the Y - Z plane.

[0094] See Figure 1 and Figure 2 , a semiconductor structure 1 provided by some embodiments of the present application may include a memory cell array layer, a source layer SL, and a device layer 3 coupled to the memory cell array layer 2. The device layer 3 may be disposed on a side of the memory cell array layer 2 away from the source layer SL in the first direction X.

[0095] As used in the present application, whether a component (such as a layer, a structure, or a device) is "on", "above", or "below" another component (such as a layer, a structure, or a device) of a semiconductor device (such as a 3D memory) is determined with respect to the device layer 3 of the semiconductor device in the first direction X when the device layer 3 is in the lowest plane of the semiconductor device in the first direction X. Throughout the content of the present application, the same concept is applied to describe the spatial relationship.

[0096] See Figure 2 and Figure 3 , the source layer SL may be connected to a first reference voltage, and the first reference voltage may be a ground voltage or other voltage. The source layer SL may include a semiconductor material, such as single - crystal silicon, single - crystal germanium, III - V group compound semiconductor materials, II - VI group compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region doped with a p - type dopant. The source layer SL may also include an undoped region.

[0097] See Figure 1 and Figure 2 , the memory cell array layer 2 includes a plurality of memory cells arranged in an array along the second direction Y and the third direction Z. Among them, as Figure 3 and Figure 4As shown, the memory cell includes a vertical transistor 4 and a storage capacitor 8. The vertical transistor 4 can be formed by a channel structure formed by a semiconductor pillar 5 and a gate structure 6 adjacent to the channel structure. Among them, a gate dielectric layer 7 is further provided between the channel structure and the corresponding gate structure 6. The channel structure has a source electrode and a drain electrode, and the source electrode and the drain electrode are respectively located at both ends of the channel structure. The drain electrode of the vertical transistor 4 is connected to the bit line 9, the source electrode of the vertical transistor 4 is connected to one plate of the storage capacitor 8, and the other plate of the storage capacitor 8 can be connected to the source layer SL. The storage capacitor 8 represents logic 1 and 0 by the amount of charge stored therein, or rather, the high and low voltage differences across the capacitor. The gate structure 6 of the vertical transistor 4 is connected to the word line WL. A voltage is applied through the word line WL to control the conduction or cutoff of the vertical transistor 4, and when the vertical transistor 4 is conducting, the bit line 9 performs a read or write operation on the vertical transistor 4.

[0098] In some embodiments, referring to Figure 1 and Figure 2 , the semiconductor structure 1 may further include a word line WL and a bit line 9. The word line WL can be coupled to the gate structure 6 of at least one vertical transistor 4. The bit line 9 can be coupled to the drain electrode of at least one vertical transistor 4. Among them, the drain electrodes of a plurality of vertical transistors 4 spaced apart along the second direction Y are coupled to the same bit line 9.

[0099] Continuing to refer to Figure 2 , in some embodiments, the memory cell array layer 2 may further include a wiring layer 10. The wiring layer 10 is located on the side of the bit line 9 away from the vertical transistor 4. The wiring layer 10 can be coupled to the vertical transistor 4, and the wiring layer 10 can be connected to the drain electrode of the channel structure in each vertical transistor 4 through the bit line 9.

[0100] In the above embodiments, the device layer 3 coupled to the memory cell array layer 2 may include a substrate and a peripheral circuit layer 11 disposed on the substrate. The material of the substrate may be single crystal silicon or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film. The peripheral circuit layer 11 may be configured to control and sense the array devices. The peripheral circuit layer 11 may be any suitable digital, analog, and / or mixed signal control and sensing circuit for supporting the operation (or work) of the array devices, including but not limited to page buffers, decoders (such as row decoders and column decoders), sense amplifiers, drivers (such as word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (such as transistors, diodes, resistors, or capacitors). The peripheral circuit may also include any other circuits compatible with advanced logic processes, including logic circuits (such as processors and programmable logic devices (PLDs)) or storage circuits (such as static random access memories (SRAMs)).

[0101] The peripheral circuit layer 11 may be coupled to the wiring layer 10 such that the memory cell array layer 2 and the device layer 3 can be coupled. Specifically, since the peripheral circuit layer 11 is coupled to the wiring layer 10, the peripheral circuit in the device layer 3 can be coupled to the vertical transistor 4 in the memory cell array layer 2 to achieve the transmission of electrical signals between the peripheral circuit and the vertical transistor 4. In some possible implementation manners, a bonding interface may be provided between the peripheral circuit layer 11 and the wiring layer 10, through which the peripheral circuit layer 11 and the wiring layer 10 can be bonded and coupled to each other.

[0102] In the above embodiments, a first connection portion 12 located on the wiring layer 10 may be provided on one side of the memory cell array layer 2 close to the peripheral circuit layer 11. The first connection portion 12 is used to connect to the vertical transistor 4 inside the memory cell array layer 2. The peripheral circuit layer 11 may include a second connection portion 13 and a transistor disposed on the substrate. The second connection portion 13 is connected to the transistor and is located on the side of the transistor close to the memory cell array layer 2, where the transistor may include complementary metal oxide semiconductor (CMOS). In the above embodiments, the first connection portion 12 and the second connection portion 13 are bonded together, and the connection between the vertical transistor 4 and the transistor is achieved through the bonding between the first connection portion 12 and the second connection portion 13, thereby realizing the connection between the memory cell array layer 2 and the peripheral circuit layer 11.

[0103] Please refer to Figure 5 , in the above embodiments, the memory cell array layer 2 (such asFigure 2 The vertical transistor 4 in the figure (not shown) may include an MSG (mirror single gate) vertical transistor. An embodiment of the present application provides a semiconductor structure 1, including a plurality of semiconductor column groups 14 arranged in an array along a second direction Y and a third direction Z. Each semiconductor column group 14 includes two semiconductor columns 5 (that is, the semiconductor structure 1 includes a plurality of semiconductor columns 5). Each semiconductor column 5 extends along a first direction X. The two semiconductor columns 5 belonging to the same semiconductor column group 14 are spaced apart in the second direction Y. The semiconductor structure 1 further includes the above-mentioned gate structure 6. The gate structure 6 is located between two adjacent semiconductor columns 5 belonging to the same semiconductor column group 14. The gate structure 6 includes two gate layers 15. The two gate layers 15 are spaced apart in the second direction Y and the gate layer 15 extends along the first direction X. One of the gate layers 15 is close to one semiconductor column 5 in the semiconductor column group 14, and the other gate layer 15 is close to the other semiconductor column 5 belonging to the same semiconductor column group 14. The gate layer 15 and the adjacent semiconductor column 5 form a vertical transistor 4. In a semiconductor column group 14, the two gate layers 15 are mirror-symmetrically distributed, that is, the formed vertical transistor 4 is an MSG vertical transistor. In other embodiments, the vertical transistor 4 in the memory cell array layer 2 may also include a single-gate vertical transistor, a double-gate vertical transistor, a tri-gate vertical transistor, and a GAA (gate all around) vertical transistor, etc.

[0104] Continuing to refer to Figure 5 , in some embodiments, the semiconductor structure 1 provided by the embodiment of the present application further includes an isolation structure 16. The isolation structure 16 is located between two semiconductor column groups 14 that are spaced apart and adjacent in the second direction Y. The semiconductor column group 14 includes two semiconductor columns 5 that are spaced apart in the second direction Y (that is, the isolation structure 16 is located between two adjacent semiconductor columns 5). Combining the above embodiments where the gate structure 6 is located between two adjacent semiconductor columns 5 belonging to the same semiconductor column group 14, the gate structure 6 and the isolation structure 16 are alternately spaced apart along the second direction. The isolation structure 16 includes a first insulating block 17, a conductive block 18, and a second insulating block 19. Along the first direction, the conductive block 18 is located between the first insulating block 17 and the second insulating block 19. Combining Figure 2 , in the implementation manner where the above memory cell array layer 2 includes a storage capacitor 8 and a bit line 9, in the first direction X, the isolation structure 16 is located between the storage capacitor 8 and the bit line 9. The second insulating block 19 in the isolation structure 16 is closer to the storage capacitor 8 than the first insulating block 17, and the first insulating block 17 in the isolation structure 16 is closer to the bit line 9 than the second insulating block 19.

[0105] In the above implementation, the conductive block 18 is configured with a preset potential. Exemplarily, the conductive block 18 can be grounded or connected to a negative voltage. The conductive block 18 can be made of a conductive material. Exemplarily, the conductive block 18 can be made of at least one of tungsten metal, cobalt metal, and titanium nitride (TiN). The second insulating block 19 can be made of an insulating material. The second insulating block 19 is used to insulate the end of the conductive block 18 away from the first insulating block 17. Exemplarily, the second insulating block 19 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide.

[0106] Continuing to refer to Figure 5 , in the semiconductor structure 1 provided by the embodiment of the present application, it includes a plurality of semiconductor columns 5 arranged at intervals along the second direction. The gate structures 6 and the isolation structures 16 are alternately arranged at intervals between two adjacent semiconductor columns 5. The gate structure 6 and the adjacent semiconductor column 5 form a vertical transistor 4. The conductive block 18 in the isolation structure 16 is located between two adjacent vertical transistors 4. During the conduction process of the vertical transistor 4, the conductive block 18 between the vertical transistors 4 can prevent the electrons in the turned-on vertical transistor 4 from easily passing through the conductive block 18 and moving to the adjacent vertical transistor 4, reducing the coupling effect between the adjacent vertical transistors 4, and further reducing the leakage between the adjacent vertical transistors 4.

[0107] Continuing to refer to Figure 5 , in some embodiments, the first insulating block 17 includes a first insulating layer 20 and a second insulating layer 21. Both the first insulating layer 20 and the second insulating layer 21 can be made of an insulating material. Exemplarily, the first insulating layer 20 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The second insulating layer 21 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The first insulating layer 20 and the second insulating layer 21 together are used to insulate the end of the conductive block 18 away from the second insulating block 19.

[0108] In the above embodiment, the first insulating layer 20 is located on the side of the conductive block 18 away from the second insulating block 19. A part of the first insulating layer 20 covers the end of the conductive block 18 away from the second insulating block 19 to insulate the end of the conductive block 18 away from the second insulating block 19. At the same time, another part of the first insulating layer 20 covers the semiconductor column 5 on the side of the conductive block 18 away from the second insulating block 19 to support the conductive block 18 and maintain the height of the conductive block 18 in the isolation structure 16.

[0109] In the above embodiments, the first insulating layer 20 encloses a through hole (not shown), and the through hole extends along the third direction Z. The second insulating layer 21 is located in the through hole. Even if the first insulating layer 20 wraps the second insulating layer 21, part of the first insulating layer 20 is located between the second insulating layer 21 and the conductive block 18, and part of the first insulating layer 20 is located between the second insulating layer 21 and the semiconductor column 5, further realizing the support for the conductive block 18 and maintaining the height of the conductive block 18 in the isolation structure 16. The second insulating layer 21 may be a solid structure to better support the conductive block 18; the second insulating layer 21 may also enclose another through hole.

[0110] Continuing to refer to Figure 5 , by way of example, the first insulating layer 20 includes a first hollow column 22. The first hollow column 22 may include a hollow square column, a hollow cylindrical column, a hollow semi-cylindrical column, etc. The first hollow column 22 extends along the third direction Z. Part of the outer sidewall of the first hollow column 22 is attached to the conductive block 18 to insulate the end of the conductive block 18 away from the second insulating block 19; another part of the outer sidewall of the first hollow column 22 is attached to the semiconductor column 5 to support the conductive block 18 and maintain the height of the conductive block 18 in the isolation structure 16; the second insulating layer 21 includes a second hollow column 23. The second hollow column 23 may also include a hollow square column, a hollow cylindrical column, a hollow semi-cylindrical column, etc. The second hollow column 23 extends along the third direction. The outer sidewall of the second hollow column 23 is attached to the inner sidewall of the first hollow column 22, which can further support the conductive block 18 and maintain the height of the conductive block 18 in the isolation structure 16.

[0111] Continuing to refer to Figure 5 , in the embodiments of the present application, the isolation structure 16 further includes a first conductive column 24. The first conductive column 24 passes through part of the first insulating layer 20 and part of the second insulating layer 21 and contacts the conductive block 18. The first conductive column 24 is used to lead out the conductive block 18 to realize the grounding or connection of negative pressure of the conductive block 18, so that electrons in the turned-on vertical transistor 4 are not easily transmitted through the conductive block 18 to adjacent vertical transistors 4, reducing the coupling effect between adjacent vertical transistors 4 and reducing the leakage between adjacent vertical transistors 4.

[0112] In the above embodiments, the material of the first insulating layer 20 includes silicon nitride, and the material of the second insulating layer 21 includes an insulating oxide material. Through the above arrangement, in the process of forming the first conductive pillar 24 to pass through a part of the first insulating layer 20 and a part of the second insulating layer 21, since the materials of the second insulating layer 21 and the first insulating layer 20 are different, there is an etching selectivity between the first insulating layer 20 and the second insulating layer 21, and the second insulating layer 21 can prevent the first insulating layer 20 in contact with the semiconductor pillar 5 in the second direction Y from being completely removed, thereby avoiding the direct connection between the formed first conductive pillar 24 and the semiconductor pillar 5 and generating leakage.

[0113] In the above implementation manner where the conductive block 18 is located between the first insulating block 17 and the second insulating block 19 in the first direction X, the first insulating block 17 and the second insulating block 19 can limit both ends of the conductive block 18 in the first direction X from exceeding both ends of the gate layer 15 in the first direction X. Combining Figure 2 That is to say, in the implementation manner where the memory cell array layer 2 includes the storage capacitor 8 and the bit line 9 in the above, the end of the gate layer 15 close to the storage capacitor 8 is closer to the storage capacitor 8 than the end of the conductive block 18 close to the storage capacitor 8, and the end of the gate layer 15 close to the bit line 9 is closer to the bit line 9 than the end of the conductive block 18 close to the bit line 9. So that while the conductive block 18 can reduce the coupling effect between adjacent vertical transistors 4, it can prevent one end of the conductive block 18 in the first direction X from exceeding one end of the adjacent gate layer 15 in the first direction, thereby avoiding the electrons in the conductive block 18 from being reversely coupled to the adjacent gate layer 15 when the conductive block 18 is energized through the first conductive pillar 24, and further affecting the operation of the adjacent vertical transistors 4.

[0114] Continuing to refer to Figure 5 In the embodiments of the present application, the lengths of the plurality of conductive blocks 18 in the first direction X are equal, and one end of each conductive block 18 away from the second insulating block 19 is aligned in the second direction Y, and at the same time, one end of each conductive block 18 close to the second insulating block 19 is aligned in the second direction Y; that is to say, the plurality of conductive blocks 18 spaced in the second direction are located at the same height. Through the above arrangement, the influence of each conductive block 18 on the coupling effect between the adjacent vertical transistors 4 is the same, improving the stability of the semiconductor structure 1.

[0115] Continuing to refer to Figure 5, in the embodiments of the present application, the isolation structure 16 further includes an isolation layer 25, and the isolation layer 25 is located between the conductive block 18 and the semiconductor pillar 5 in the second direction Y. Wherein the isolation layer 25 is a single-layer structure, and the isolation layer 25 can be made of an insulating material. Exemplarily, the isolation layer 25 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. Through the above arrangement, the isolation layer 25 can achieve insulation between the conductive block 18 and the semiconductor pillar 5 in the second direction Y.

[0116] In an implementation manner where the semiconductor structure 1 includes the second insulating block 19, the isolation layer 25 can also be located between the second insulating block 19 and the semiconductor pillar 5 adjacent to the second insulating block 19 in the second direction Y.

[0117] Please refer to Figure 6 , in the above embodiments, the isolation layer 25 can also include a first isolation layer 26 and a second isolation layer 27, and the first isolation layer 26 and the second isolation layer 27 are stacked along the second direction Y. The first isolation layer 26 is located between the second isolation layer 27 and the semiconductor pillar 5, and the second isolation layer 27 is located between the first isolation layer 26 and the conductive block 18. Wherein both the first isolation layer 26 and the second isolation layer 27 can be made of an insulating material. Exemplarily, the first isolation layer 26 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The second isolation layer 27 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The first isolation layer 26 and the second isolation layer 27 can be made of the same material or different materials; for example, the material of the first isolation layer 26 includes insulating oxide material, and the material of the second isolation layer 27 includes silicon nitride. Through the above arrangement, the first isolation layer 26 and the second isolation layer 27 can jointly achieve insulation between the conductive block 18 and the semiconductor pillar 5 in the second direction Y.

[0118] In the above embodiments, one side of the first isolation layer 26 close to the semiconductor pillar 5 is in contact with the semiconductor pillar 5, one side of the first isolation layer 26 far from the semiconductor pillar 5 is in contact with the second isolation layer 27, and one side of the second isolation layer 27 far from the first isolation layer 26 is in contact with the conductive block 18.

[0119] In an embodiment where the isolation layer 25 is a single-layer structure, the isolation layer 25 includes insulating oxide. Compared with the isolation layer 25 including the first isolation layer 26 formed of insulating oxide material and the second isolation layer 27 formed of silicon nitride. The isolation layer is only formed of insulating oxide, which reduces the equivalent oxide thickness (EOT) and can increase the process window for continuing to reduce the vertical transistor size according to the requirements of Moore's law.

[0120] Meanwhile, during the formation of the isolation layer 25, only one layer of insulating oxide is deposited. Subsequently, during the formation of the conductive block 18, the width of the conductive block 18 in the second direction Y can be increased to further reduce the coupling effect between adjacent vertical transistors 4, thereby reducing the leakage between adjacent vertical transistors 4.

[0121] An embodiment of the present application also provides a method for manufacturing a semiconductor structure 1, which can be used to fabricate the semiconductor structure 1 in the above embodiment. Please refer to Figure 7 , the manufacturing method may include steps S100 - S400:

[0122] S100: Form a plurality of semiconductor pillars. The semiconductor pillars extend along a first direction, and the plurality of semiconductor pillars are spaced along a second direction, forming gate trenches and isolation trenches that are alternately spaced along the second direction, where the second direction is perpendicular to the first direction.

[0123] Please refer to Figure 8 , in step S100, before forming the plurality of semiconductor pillars 5, a semiconductor layer 28 is provided. The semiconductor layer 28 may include single - crystal silicon, poly - silicon, etc. Then, a mask plate 29 is formed above the semiconductor layer 28. The material of the mask plate 29 includes SiN. In the implementation where the mask plate 29 includes SiN, an oxide layer is deposited on the semiconductor layer 28 before forming the mask plate 29, and then the mask plate 29 is formed on the oxide layer to avoid stress problems caused by direct contact between the mask plate 29 formed of SiN and the Si of the semiconductor layer 28.

[0124] Please refer to Figure 9 , through the mask plate 29, a plurality of insulating trenches 30 spaced along a third direction Z are formed on the semiconductor layer 28, and the insulating trenches 30 extend into the semiconductor layer 28 along the first direction X. The distance between adjacent two insulating trenches 30 in the third direction is equal. In the implementation where the semiconductor structure 1 includes bit lines 9, the extending direction of the insulating trenches 30 in the third direction Z is the same as the extending direction of the bit lines 9.

[0125] After forming the insulating trenches 30, under high - temperature conditions, an epitaxial growth layer of oxide is formed on the inner wall of the insulating trenches 30 (i.e., the single - crystal silicon on the inner wall of the insulating trenches 30 is oxidized into silicon dioxide) to repair the surface of the exposed semiconductor layer 28.

[0126] After forming the oxide layer in the insulating trenches 30, a dielectric material 31 is filled in the insulating layer, and chemical - mechanical polishing (CMP) is performed on the upper surface of the semiconductor layer 28. The dielectric material 31 may include at least one of silicon oxide and nitride.

[0127] Please refer to Figure 10, in step S100, it further includes forming gate trenches 32 and isolation trenches 33 which are alternately and spaced along the second direction Y on the semiconductor layer 28 through a mask plate 29, wherein the gate trenches 32 extend into the semiconductor layer 28 along the first direction X and extend in the third direction Z; the isolation trenches 33 extend into the semiconductor layer 28 along the first direction X and extend in the third direction Z.

[0128] Please refer to Figure 11 , after forming the gate trenches 32, an epitaxial oxide layer is formed on the inner walls of the gate trenches 32 under high temperature conditions (i.e., oxidizing the single-crystalline silicon on the inner walls of the gate trenches 32 into silicon dioxide) to repair the surface of the exposed semiconductor layer 28.

[0129] Similarly, continue to refer to Figure 11 , after forming the isolation trenches 33, an epitaxial oxide layer is formed on the inner walls of the isolation trenches 33 under high temperature conditions (i.e., oxidizing the single-crystalline silicon on the inner walls of the isolation trenches 33 into silicon dioxide) to repair the surface of the exposed semiconductor layer 28.

[0130] The formation of the oxide layer on the inner walls of the gate trenches 32 and the formation of the oxide layer on the inner walls of the isolation trenches 33 can be formed simultaneously in the same step.

[0131] Please refer to Figure 12 , after forming the oxide layer on the inner walls of the gate trenches 32 and the inner walls of the isolation trenches 33, a sacrificial material 34 is filled in the gate trenches 32 and the isolation trenches 33. The sacrificial material 34 can include spin-on carbon (SOC), carbon, etc.

[0132] So far, please refer to Figure 13 , a plurality of semiconductor pillars 5 surrounded by the dielectric material 31 and the sacrificial material 34 are formed on the remaining semiconductor layer 28. The semiconductor pillars 5 extend along the first direction, and the plurality of semiconductor pillars 5 are spaced along the second direction. In the second direction Y, there is the sacrificial material 34 between adjacent semiconductor pillars 5, and in the third direction Z, there is the dielectric material 31 between adjacent semiconductor pillars 5.

[0133] S200: Form a gate structure in the gate trench and form an isolation structure in the isolation trench, so that the gate structure and the isolation structure are alternately and spaced along the second direction.

[0134] In step S200, the gate structure 6 can be formed before forming the isolation structure 16, or the gate structure 6 can be formed after forming the isolation structure 16, or the gate structure 6 can be formed during the formation of the isolation structure 16.

[0135] S300: Forming the isolation structure includes: forming a first insulating block, a conductive block, and a second insulating block along the first direction, with the conductive block located between the first insulating block and the second insulating block.

[0136] Please refer to Figure 14 and compare with Figure 12 , before forming the isolation structure 16 in step S300, the preparation method provided by the embodiments of the present application further includes removing all the sacrificial materials 34 located in the isolation groove 33. In the implementation manner where the sacrificial material 34 includes carbon, the process of removing all the sacrificial materials 34 in the isolation groove 33 may include ashing to remove all the sacrificial materials 34 in the isolation groove 33.

[0137] During the process of removing all the sacrificial materials 34 in the isolation groove 33, a part of the oxide layer on the inner wall of the isolation groove 33 will be removed simultaneously. Therefore, before forming the isolation structure 16, please refer to Figure 15 , the preparation method provided by the embodiments of the present application further includes: forming an initial isolation layer 35 in the isolation groove 33, and the initial isolation layer 35 covers the side wall of the isolation groove 33 extending in the first direction and covers the bottom wall of the isolation groove 33.

[0138] In some embodiments, the initial isolation layer 35 is a single-layer structure, and the initial isolation layer 35 can be made of an insulating material. Exemplarily, the initial isolation layer 35 may include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. In this embodiment, the initial isolation layer 35 includes an insulating oxide. Then, forming the initial isolation layer 35 includes depositing an oxide layer in the isolation groove 33, and this oxide layer and the remaining part of the oxide layer on the inner wall of the isolation groove 33 together form the initial isolation layer 35.

[0139] In the above embodiments, please refer to Figures 16 to 21 , forming the isolation structure 16 in step S300 further includes sequentially forming a third insulating block 36, a conductive block 18, and a second insulating block 19 in the isolation groove 33, so that the conductive block 18 is located between the third insulating block 36 and the second insulating block 19.

[0140] Please refer to Figure 16 and Figure 17 , in the implementation manner where the initial isolation layer 35 includes an insulating oxide, forming the third insulating block 36 includes forming an initial third insulating block 37 above the initial isolation layer 35 and removing a part of the initial third insulating block 37 to form the third insulating block 36, so that the vertical distance from one end of each third insulating block 36 away from the bottom wall of the isolation groove 33 to the bottom wall of the isolation groove 33 is the same.

[0141] In the above implementation manner, the initial third insulating block 37 may include silicon nitride (SiN). Forming the initial third insulating block 37 above the initial isolation layer 35 may include depositing SiN in the isolation groove 33 to form the initial third insulating block 37. In the subsequent formation of the conductive block 18 (such as Figure 19During the process shown, the third insulating block 36 can make the conductive block 18 have a certain height.

[0142] In one implementation, the thickness of the deposited SiN is greater than 1 / 2 of the width of the isolation trench 33 in the second direction Y, so that the formed initial third insulating block 37 almost fills the isolation trench 33, and there are no gap defects on the third insulating block 36 formed after removing part of the initial third insulating block 37 subsequently. In the above implementation, the same height of part of the initial third insulating block 37 is removed from each isolation trench 33, and the remaining part of the initial third insulating block 37 forms the third insulating block 36, so that the vertical distance from one end of each third insulating block 36 away from the bottom wall of the isolation trench 33 to the bottom wall of the isolation trench 33 is the same, thereby achieving the alignment of one end of each conductive block 18 away from the second insulating block 19 in the second direction Y.

[0143] In another implementation, the thickness of the deposited SiN is not limited. In the case where the thickness of the SiN is insufficient, there will be gap defects extending along the first direction X in the initial third insulating block 37. During the process of removing part of the initial third insulating block 37, part of the initial third insulating block 37 is removed by using phosphoric acid (H3PO4) solution. The silicon nitride (SI3N4) forming the initial third insulating block 37 can first react with water in the phosphoric acid solution to generate silicon dioxide (SIO2) and ammonia (NH3). Subsequently, the generated SIO2 can react with H3PO4 to generate silicic acid (H2SiO3) and phosphorus pentoxide (P2O5). Then, during the process of removing part of the initial third insulating block 37, the precipitate generated by the reaction of silicon nitride and the phosphoric acid solution can adhere to the gap defects, so that the side of the formed third insulating block 36 away from the bottom wall of the isolation trench 33 is a flat surface.

[0144] In the above implementation, the chemical reaction formula of silicon nitride and the phosphoric acid solution is SI3N4 + 6H2O → 3SIO2↓ + 4NH3↑, Similarly, in the above implementation, the same height of part of the initial third insulating block 37 is removed from each isolation trench 33, and the remaining part of the initial third insulating block 37 forms the third insulating block 36, so that the vertical distance from one end of each third insulating block 36 away from the bottom wall of the isolation trench 33 to the bottom wall of the isolation trench 33 is the same, thereby achieving the alignment of one end of each conductive block 18 away from the second insulating block 19 in the second direction Y.

[0145] Please refer to Figure 18 and Figure 19, in the above embodiments, forming the conductive block 18 in the preparation method provided by the embodiments of the present application may include: after forming the third insulating block 36, forming an initial conductive block 38, and removing a part of the initial conductive block 38 to form the conductive block 18, so that the third insulating block 36 and the conductive block 18 are in contact with each other along the second direction; and making the initial isolation layer 35 be located between the conductive block 18 and the semiconductor column 5.

[0146] In the above implementation manner, the initial conductive block 38 may include titanium nitride (TiN). Forming the initial conductive block 38 above the third insulating block 36 may include depositing TiN in the isolation groove 33 to form the initial conductive block 38. The initial conductive block 38 fills the isolation groove 33. In the subsequent step of removing a part of the initial conductive block 38, the same height of the part of the initial conductive block 38 in each isolation groove 33 is removed, and the remaining part of the initial conductive block 38 forms the conductive block 18, so that the third insulating block 36 and the conductive block 18 are in contact with each other along the second direction. The lengths of the plurality of conductive blocks 18 formed in each isolation groove 33 are the same, and in the above embodiments, the plurality of conductive blocks 18 are aligned in the second direction Y; the influence of each conductive block 18 on the coupling effect between the adjacent vertical transistors 4 is the same, improving the stability of the semiconductor structure 1. And making the initial isolation layer 35 be located between the conductive block 18 and the semiconductor column 5. The initial isolation layer 35 can realize insulation between the conductive block 18 and the semiconductor column 5 in the second direction Y.

[0147] Please refer to Figure 20 and Figure 21 , in the above embodiments, forming the second insulating block 19 in the preparation method provided by the embodiments of the present application may include: after forming the conductive block 18, forming an initial second insulating block 39, and removing a part of the initial second insulating block 39 to form the second insulating block 19, so that the conductive block 18 is located between the first insulating block 17 and the second insulating block 19.

[0148] In the above implementation, the initial second insulating block 39 may include silicon nitride (SiN). Forming the initial second insulating block 39 above the conductive block 18 may include depositing SiN in the isolation groove 33 to form the initial second insulating block 39. The initial second insulating block 39 fills the isolation groove 33 and covers the mask plate 29. In the subsequent step of removing a part of the initial second insulating block 39, a part of the initial second insulating block 39 may be removed by CMP so that the remaining part of the initial second insulating block 39 forms the second insulating block 19, and the second insulating block 19 is used to insulate the end of the conductive block 18 away from the first insulating block 17. One end of the second insulating block 19 away from the isolation groove 33 is aligned with the mask plate 29, and the formed third insulating block 36, conductive block 18, and second insulating block 19 fill the isolation groove 33. The initial isolation layer 35 may also be located between the second insulating block 19 and the semiconductor pillar 5 adjacent to the second insulating block 19 in the second direction.

[0149] Please refer to Figure 22 , in some other embodiments, the initial isolation layer 35 is divided into a two-layer structure. Forming the initial isolation layer 35 includes forming the initial first isolation layer 40 and forming the initial second isolation layer 41. In the preparation method provided by the embodiments of the present application, after the initial first isolation layer 40 is formed, the initial first isolation layer 40 covers the side wall of the isolation groove 33 extending along the first direction X and covers the bottom wall of the isolation groove 33. Then, the initial second isolation layer 41 is formed on the initial first isolation layer 40, and the initial second isolation layer 41 covers the side of the initial first isolation layer 40 facing away from the side wall of the isolation groove 33 and covers the side of the initial first isolation layer 40 facing away from the bottom wall of the isolation groove 33. Among them, both the initial first isolation layer 40 and the initial second isolation layer 41 may be made of insulating materials. Exemplarily, the initial first isolation layer 40 may include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The initial second isolation layer 41 may include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide.

[0150] In the implementation where the initial isolation layer 35 includes the initial first isolation layer 40 and the initial second isolation layer 41, if the material of the initial first insulating layer 20 includes an insulating oxide material, forming the initial first isolation layer 40 includes depositing an oxide layer in the isolation groove 33, and the oxide and the remaining part of the oxide layer located on the inner wall of the isolation groove 33 together form the initial first isolation layer 40. The material of the initial second isolation layer 41 includes silicon nitride.

[0151] Please refer to Figure 23 and Figure 24, in combination with the above embodiments, forming the third insulating block 36 in the manufacturing method provided by the embodiments of the present application includes forming an initial third insulating block 37 above the initial second isolation layer 41, and removing a part of the initial third insulating block 37 to form the third insulating block 36, so that the vertical distance from one end of each third insulating block 36 away from the bottom wall of the isolation groove 33 to the bottom wall of the isolation groove 33 is the same.

[0152] In the above implementation, the initial third insulating block 37 may include an insulating oxide. Forming the initial third insulating block 37 above the initial isolation layer 35 may include depositing an insulating oxide in the isolation groove 33 to form the initial third insulating block 37.

[0153] In the above implementation, the formed initial third insulating block 37 almost fills the isolation groove 33. The same height of a part of the initial third insulating block 37 is removed from each isolation groove 33, and the remaining part of the initial third insulating block 37 forms the third insulating block 36, so that the vertical distance from one end of each third insulating block 36 away from the bottom wall of the isolation groove 33 to the bottom wall of the isolation groove 33 is the same.

[0154] Among them, the initial second isolation layer 41 is located between the initial first isolation layer 40 and the initial third insulating block 37. Since both the initial first isolation layer 40 and the initial third insulating block 37 include insulating oxides, during the process of removing a part of the initial third insulating block 37, the initial second isolation layer 41 including SiN can protect the initial first isolation layer 40, preventing the initial first isolation layer 40 and the part of the initial third insulating block 37 to be removed from being removed simultaneously, and thus losing the function of insulating the conductive block 18 from the semiconductor column 5 in the second direction Y after the conductive block 18 is formed subsequently.

[0155] Please refer to Figure 25 and Figure 26 , in combination with the above embodiments, forming the conductive block 18 in the manufacturing method provided by the embodiments of the present application may include: after forming the third insulating block 36, forming an initial conductive block 38, and removing a part of the initial conductive block 38 to form the conductive block 18, so that the third insulating block 36 and the conductive block 18 are in contact with each other along the second direction; and making the initial first isolation layer 40 and the initial second isolation layer 41 be located between the conductive block 18 and the semiconductor column 5, wherein the first isolation layer 26 and the second isolation layer 27 are stacked along the second direction, the first isolation layer 26 is located between the second isolation layer 27 and the semiconductor column 5, and the second isolation layer 27 is located between the first isolation layer 26 and the conductive block 18.

[0156] In the above implementation, the initial conductive block 38 may include titanium nitride (TiN). Forming the initial conductive block 38 above the third insulating block 36 may include depositing TiN in the isolation groove 33 to form the initial conductive block 38. The initial conductive block 38 fills the isolation groove 33. In the subsequent step of removing a part of the initial conductive block 38, the same height of the part of the initial conductive block 38 in each isolation groove 33 is removed, and the remaining part of the initial conductive block 38 forms the conductive block 18, so that the third insulating block 36 and the conductive block 18 are in contact with each other along the second direction. The lengths of the plurality of conductive blocks 18 formed in each isolation groove 33 are the same, and the plurality of conductive blocks 18 are aligned in the second direction Y; the influence of each conductive block 18 on the coupling effect between the adjacent vertical transistors 4 is the same, improving the stability of the semiconductor structure 1. And the initial isolation layer 35 is located between the conductive block 18 and the semiconductor column 5. The first isolation layer 26 and the second isolation layer 27 can jointly achieve insulation between the conductive block 18 and the semiconductor column 5 in the second direction Y.

[0157] Please refer to Figure 27 and Figure 28 In combination with the above embodiments, in the manufacturing method provided by the embodiments of the present application, forming the second insulating block 19 may include: after forming the conductive block 18, forming an initial second insulating block 39, and removing a part of the initial second insulating block 39 to form the second insulating block 19, so that the conductive block 18 is located between the first insulating block 17 and the second insulating block 19. After forming the second insulating block 19, the initial first isolation layer 40 and the initial second isolation layer 41 may also be located between the second insulating block 19 and the semiconductor column 5. The first isolation layer 26 and the second isolation layer 27 are stacked along the second direction, the first isolation layer 26 is located between the second isolation layer 27 and the semiconductor column 5, and the second isolation layer 27 is located between the first isolation layer 26 and the second insulating block 19.

[0158] In the above implementation, the initial second insulating block 39 may include silicon nitride (SiN). Forming the initial second insulating block 39 above the conductive block 18 may include depositing SiN in the isolation groove 33 to form the initial second insulating block 39. The initial second insulating block 39 fills the isolation groove 33 and covers the mask plate 29; in the subsequent step of removing a part of the initial second insulating block 39, a part of the initial second insulating block 39 may be removed by CMP, so that the remaining part of the initial second insulating block 39 forms the second insulating block 19, and the second insulating block 19 is used to achieve insulation of the end of the conductive block 18 far from the first insulating block 17. One end of the second insulating block 19 far from the isolation groove 33 is aligned with the mask plate 29, and the formed third insulating block 36, conductive block 18 and second insulating block 19 fill the isolation groove 33.

[0159] Please refer to Figure 29, before forming the isolation structure 16 in step S300, the manufacturing method provided by the embodiments of the present application may further include removing a part of the sacrificial material 34 located in the isolation groove 33. The remaining part of the sacrificial material 34 in the isolation groove 33 has a certain height in the first direction X. During the subsequent formation of the conductive block 18, the remaining part of the sacrificial material 34 in the isolation groove 33 can make the conductive block 18 have a certain height. In the implementation manner where the sacrificial material 34 includes carbon, the process of removing a part of the sacrificial material 34 in the isolation groove 33 may include ashing to remove a part of the sacrificial material 34 in the isolation groove 33.

[0160] Please refer to Figure 30 , during the process of forming the isolation structure 16, it also includes forming an initial isolation layer 35, and the initial isolation layer 35 includes an initial first isolation layer 40 and an initial second isolation layer 41. During the process of removing a part of the sacrificial material 34 in the isolation groove 33, a part of the oxide layer on the inner wall of the isolation groove 33 will be removed simultaneously, and the remaining part of the oxide layer serves as the initial first isolation layer 40.

[0161] In the above embodiments, after removing a part of the sacrificial material 34 in the isolation groove 33, an initial second isolation layer 41 is formed. The initial second isolation layer 41 covers the side of the initial first isolation layer 40 facing away from the side wall of the isolation groove 33, and covers the side of the remaining sacrificial layer facing away from the bottom wall of the isolation groove 33. Among them, the initial second isolation layer 41 may be made of an insulating material. Exemplarily, the initial second isolation layer 41 may include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. In the embodiments of the present application, the initial second isolation layer 41 may include silicon nitride (SiN).

[0162] In the above embodiments, the remaining sacrificial material 34 in the isolation groove 33 can make the conductive block 18 have a certain height. Therefore, after forming the initial second isolation layer 41, it is not necessary to form a third insulating block 36 in the isolation groove 33, and the conductive block 18 can be directly formed in the isolation groove 33. Similarly, the implementation manner of forming the conductive block 18 may include: forming an initial conductive block 38, and removing a part of the initial conductive block 38 to form the conductive block 18, and making the initial first isolation layer 40 and the initial second isolation layer 41 located between the conductive block 18 and the semiconductor column 5, where the first isolation layer 26 and the second isolation layer 27 are stacked along the second direction, the first isolation layer 26 is located between the second isolation layer 27 and the semiconductor column 5, and the second isolation layer 27 is located between the first isolation layer 26 and the conductive block 18.

[0163] In the above embodiments, the subsequent steps of forming the conductive block 18 and the second insulating block 19 are the same as those described above, and will not be elaborated here.

[0164] Please refer to Figures 31 to 33 , and compare and refer toFigure 21 After forming the third insulating block 36, the conductive block 18, and the second insulating block 19 in step S300, the embodiment of the present application further includes forming the gate structure 6.

[0165] Before forming the gate structure 6, the manufacturing method provided by the embodiment of the present application further includes removing all the sacrificial material 34 located in the gate trench 32. Similarly, in the implementation where the sacrificial material 34 includes carbon, the process of removing all the sacrificial material 34 may include ashing to remove the sacrificial material 34. During the process of removing all the sacrificial material 34 in the gate trench 32, a part of the oxide layer on the sidewall of the gate trench 32 will be removed simultaneously, and the remaining part of the oxide layer forms the above-mentioned gate dielectric layer 7. The formed gate dielectric layer 7 includes a part on the sidewall of the gate trench 32 and a part on the bottom wall of the gate trench 32.

[0166] Please refer to Figure 31 Forming the gate structure 6 includes forming an initial first gate layer 42 in the gate trench 32. The initial first gate layer 42 covers the sidewall of the gate trench 32 extending along the first direction X and covers the bottom wall of the gate trench 32. The initial first gate layer 42 may include at least one of titanium nitride (TiN) and tungsten (W). In the embodiment of the present application, the initial first gate layer 42 includes tungsten.

[0167] Please refer to Figure 32 Forming the gate structure 6 further includes removing a part of the initial first gate layer 42 to form an initial second gate layer 43. The initial second gate layer 43 covers the sidewall of the gate trench 32 extending along the first direction X and covers the bottom wall of the gate trench 32. In the cross-section of the semiconductor structure 1X-Y, the initial second gate layer 43 forms a structure similar to a "U" shape. One end of the initial second gate layer 43 away from the bottom wall of the gate trench 32 extends upward in the first direction X beyond one end of the conductive block 18 away from the bottom wall of the isolation trench 33, that is, the vertical distance from one end of the initial second gate layer 43 away from the bottom wall of the gate trench 32 to the bottom wall of the gate trench 32 is greater than the vertical distance from one end of the conductive block 18 away from the bottom wall of the isolation trench 33 to the bottom wall of the isolation trench 33.

[0168] Please refer to Figure 33 Forming the gate structure 6 further includes forming a filling layer 44. After forming the initial second gate layer 43, an initial filling layer 45 is formed, and a part of the initial filling layer 45 is removed to form the filling layer 44, so that the filling layer 44 is located between the parts of the initial second gate layer 43 covering the sidewall of the gate trench 32 and completely fills the gate trench 32. Exemplarily, the filling layer 44 may include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. In the above embodiment, the filling layer 44 includes an insulating oxide layer.

[0169] Combined with Figure 2, in some embodiments, after forming the filling layer 44, the preparation method provided by the embodiments of the present application may further include forming a storage capacitor 8, where the formed storage capacitor 8 is located on a side of the semiconductor pillar 5 away from the bottom wall of the gate trench 32 or the bottom wall of the isolation trench 33, and the storage capacitor 8 is correspondingly connected to an end of the semiconductor pillar 5 away from the bottom wall of the gate trench 32 or the bottom wall of the isolation trench 33.

[0170] S400: Forming the first insulating block includes: forming a first insulating layer and a second insulating layer, making the first insulating layer located on a side of the conductive block away from the second insulating block, the first insulating layer wrapping the second insulating layer, such that a part of the first insulating layer is located between the second insulating layer and the conductive block, and a part of the first insulating layer is located between the second insulating layer and the semiconductor pillar.

[0171] Please refer to Figure 34 , in step S400, forming the first insulating block 17 includes: removing a part of the initial isolation layer 35 adjacent to the third insulating block 36; the part of the initial isolation layer 35 adjacent to the third insulating block 36 includes the part of the initial isolation layer 35 located between the third insulating block 36 and the semiconductor pillar 5 in the second direction Y, and the part of the initial isolation layer 35 located between the third insulating block 36 and the bottom wall of the isolation trench 33. The remaining part of the initial isolation layer 35 forms the final isolation layer 25, and the isolation layer 25 is located between the conductive block 18 and the semiconductor pillar 5 in the second direction Y; meanwhile, the isolation layer 25 is also located between the second insulating block 19 and the semiconductor pillar 5 adjacent to the second insulating block 19 in the second direction Y; to achieve insulation between the conductive block 18 and the semiconductor pillar 5 in the second direction Y.

[0172] Continue to refer to Figure 34 , in the implementation manner of removing the part of the initial isolation layer 35 adjacent to the third insulating block 36, the part of the oxide layer located on the bottom wall of the gate trench 32 and the part of the oxide layer located on the side wall of the gate trench 32 in the gate trench 32 will be removed simultaneously, where the height of the part of the oxide layer located on the side wall of the gate trench 32 removed is the same as the height of the part of the initial isolation layer 35 located between the third insulating block 36 and the semiconductor pillar 5 removed in the second direction Y, so as to expose one end of the part of the initial second gate layer 43 close to the bottom wall of the gate trench 32.

[0173] Please refer to Figure 35 , and compare and refer to Figure 34, in the above implementation, it is also exposed that after a part of the initial second gate layer 43, a part of the initial second gate layer 43 is removed to form two gate layers 15 spaced apart along the second direction Y. The gate layer 15 and the adjacent semiconductor pillar 5 form a vertical transistor 4. In a semiconductor pillar group 14, the two gate layers 15 are mirror-symmetrically distributed, that is, the formed vertical transistor 4 is an MSG vertical transistor 4. Combining with the conductive block 18 in the isolation structure 16, the conductive block 18 in the isolation structure 16 is located between two adjacent vertical transistors 4; during the conduction process of the vertical transistor 4, the conductive block 18 between the vertical transistors 4 can prevent the electrons in the turned-on vertical transistor 4 from easily passing through the conductive block 18 and moving to the adjacent vertical transistor 4, reducing the coupling effect between adjacent vertical transistors 4, and thus reducing the leakage between adjacent vertical transistors 4.

[0174] In the above implementation, one end of the gate layer 15 close to the bottom wall of the gate groove 32 extends downward in the first direction X beyond one end of the conductive block 18 close to the bottom wall of the isolation groove 33, that is, the vertical distance from one end of the gate layer 15 close to the bottom wall of the gate groove 32 to the bottom wall of the gate groove 32 is less than the vertical distance from one end of the conductive block 18 close to the bottom wall of the isolation groove 33 to the bottom wall of the isolation groove 33. While the conductive block 18 can reduce the coupling effect between adjacent vertical transistors 4, it can prevent one end of the conductive block 18 from exceeding one end of the adjacent gate layer 15 in the first direction, and further prevent the electrons in the conductive block 18 from being reversely coupled to the gate layer 15 adjacent to the conductive block 18 when the conductive block 18 is energized, thereby affecting the operation of the adjacent vertical transistor 4.

[0175] Please refer to Figure 36 , and compare and refer to Figure 27 , in the above embodiment, in combination with the implementation in which the initial isolation layer 35 includes an initial first isolation layer 40 and an initial second isolation layer 41, removing a part of the initial isolation layer 35 adjacent to the third insulating block 36 includes removing a part of the initial second isolation layer 41 adjacent to the third insulating block 36 and a corresponding part of the initial first isolation layer 40. The remaining initial first isolation layer 40 forms the first isolation layer 26, and the remaining initial second isolation layer 41 forms the second isolation layer 27. The first isolation layer 26 and the second isolation layer 27 are stacked along the second direction Y. The first isolation layer 26 is located between the second isolation layer 27 and the semiconductor pillar 5, and the second isolation layer 27 is located between the first isolation layer 26 and the conductive block 18. The first isolation layer 26 and the second isolation layer 27 jointly form the isolation layer 25. At the same time, the isolation layer 25 jointly formed by the first isolation layer 26 and the second isolation layer 27 is also located between the second insulating block 19 and the semiconductor pillar 5 adjacent to the second insulating block 19 in the second direction Y; the first isolation layer 26 and the second isolation layer 27 can jointly achieve insulation between the conductive block 18 and the semiconductor pillar 5 in the second direction Y.

[0176] Please refer to Figures 37 to 39 , in the above embodiments, for comparison and reference Figure 35 , forming the first insulating block 17 further includes removing the third insulating block 36. After removing the third insulating block 36, the bottom wall of the isolation groove 33, one end of the conductive block 18 close to the bottom wall of the isolation groove 33, and the side wall of a part of the semiconductor column 5 located on the side of the conductive block 18 close to the bottom wall of the isolation groove 33 are exposed. Forming the first insulating block 17 further includes forming the first insulating block 17 at the position of the removed third insulating block 36 and at the position of the removed part of the initial isolation layer 35.

[0177] Please refer to Figure 38 and Figure 39 , in some embodiments of step S400, forming the first insulating block 17 further includes: forming a first insulating layer 20 and a second insulating layer 21. The first insulating layer 20 is located on the side of the conductive block 18 away from the second insulating block 19. The first insulating layer 20 covers the bottom wall of the isolation groove 33, one end of the conductive block 18 close to the bottom wall of the isolation groove 33, and the side wall of a part of the semiconductor column 5 located on the side of the conductive block 18 close to the bottom wall of the isolation groove 33. Among them, a part of the first insulating layer 20 covering one end of the conductive block 18 away from the second insulating block 19 is used to insulate one end of the conductive block 18 away from the second insulating block 19; a part of the first insulating layer 20 covering the bottom wall of the isolation groove 33 and the side wall of a part of the semiconductor column 5 located on the side of the conductive block 18 close to the bottom wall of the isolation groove 33 is used to support the conductive block 18 to maintain the height of the conductive block 18 in the isolation structure 16.

[0178] Continue to refer to Figure 38 and Figure 39 , in the above embodiments, the first insulating layer 20 encloses to form a through hole, and the through hole extends along the third direction Z. The above-mentioned second insulating layer 21 is located in the through hole, that is, the first insulating layer 20 wraps the second insulating layer 21, so that a part of the first insulating layer 20 is located between the second insulating layer 21 and the conductive block 18, and a part of the first insulating layer 20 is located between the second insulating layer 21 and the semiconductor column 5, further realizing the support of the conductive block 18 and maintaining the height of the conductive block 18 in the isolation structure 16. Among them, the second insulating layer 21 can be a solid structure to better support the conductive block 18; the second insulating layer 21 can also enclose to form another through hole. Among them, the material of the first insulating layer 20 includes silicon nitride, and the material of the second insulating layer 21 includes an insulating oxide material.

[0179] Continue to refer to Figure 38 and Figure 39, in the above embodiments, during the process of forming the first insulating layer 20, silicon nitride can simultaneously cover one end of the gate layer 15 exposed in the gate trench 32. Exemplarily, silicon nitride can fill the gate trench 32 to achieve insulation between the gate layer 15 and the semiconductor pillar 5.

[0180] Referring to Figure 2 , in some embodiments, after forming the first insulating block 17, forming a plurality of bit lines 9 is further included. Among them, in the implementation manner where the semiconductor structure 1 includes a storage capacitor 8, forming a plurality of bit lines 9 includes forming a plurality of bit lines 9 on a side of the semiconductor layer 28 facing away from the storage capacitor 8. The bit lines 9 extend along the second direction Y, and the plurality of bit lines 9 are spaced apart in the third direction Z. A plurality of semiconductor pillars 5 spaced apart in the second direction Y are connected to the same bit line 9, and a plurality of semiconductor pillars 5 spaced apart in the third direction Z are respectively connected to different bit lines 9. After forming the bit lines 9, a wiring layer 10 is formed on a side of the bit lines 9 facing away from the semiconductor layer 28, and the wiring layer 10 is used to connect to the peripheral circuit layer 11.

[0181] Please refer to Figure 40 , in step S400, after forming the first insulating block 17, removing a part of the first insulating layer 20, the second insulating layer 21, and a part of the semiconductor layer 28 is further included to form a first conductive hole 46 extending along the first direction X.

[0182] Continuing to refer to Figure 40 , after forming the conductive block 18, the conductive block 18 extends in the third direction Z, and a plurality of conductive blocks 18 are spaced apart in the second direction Y, while a plurality of bit lines 9 are spaced apart in the third direction Z. The formed first conductive hole 46 is located between two adjacent bit lines 9 in the third direction Z, and one end of the first conductive hole 46 extends into the semiconductor layer 28 to a side of the conductive block 18 away from the second insulating block 19.

[0183] In the above implementation manner, the material of the first insulating layer 20 includes silicon nitride, and the material of the second insulating layer 21 includes an insulating oxide material. Then, during the process of removing a part of the first insulating layer 20 and the second insulating layer 21 to form the first conductive hole 46, due to the different materials of the second insulating layer 21 and the first insulating layer 20, there is an etching selectivity between the first insulating layer 20 and the second insulating layer 21. The second insulating layer 21 can prevent the first insulating layer 20 in contact with the semiconductor pillar 5 in the second direction Y from being completely removed, so that the semiconductor pillar 5 is exposed in the formed first conductive hole 46, thereby avoiding direct contact between the first conductive pillar 24 (as shown in Figure 41 ) formed in the first conductive hole 46 and the semiconductor pillar 5 to generate leakage.

[0184] Please refer to Figure 40 and Figure 41, after forming the first conductive via 46, a first conductive pillar 24 is formed within the first conductive via 46 to connect the first conductive pillar 24 to the conductive block 18, thereby forming the isolation structure 16. The connection between the first conductive pillar 24 and the conductive block 18 is used to lead out the conductive block 18 to achieve grounding of the conductive block 18 or connection to a negative voltage. As a result, electrons in the vertically-conductive transistor 4 that are being conducted are less likely to pass through the conductive block 18 and move towards an adjacent vertically-conductive transistor 4, reducing the coupling effect between adjacent vertically-conductive transistors 4 and minimizing leakage between adjacent vertically-conductive transistors 4. Among them, the formed first conductive pillar 24 is located between two adjacent bit lines 9 in the third direction Z, and one end of the first conductive pillar 24 extends into the semiconductor layer 28 to the conductive block 18 and contacts the conductive block 18. In the above implementation, a plurality of conductive blocks 18 are arranged at intervals in the second direction Y, and each conductive block 18 is correspondingly connected to a first conductive pillar 24. The first conductive pillar 24 is located at the edge of the semiconductor layer 28 to facilitate wiring in the semiconductor structure 1.

[0185] In the implementation of step S400, after forming the first insulating block 17, it further includes forming a second conductive via 47 extending along the first direction X.

[0186] Please refer to Figure 42 , after forming the gate layer 15, the gate layer 15 extends in the third direction Z, and two gate layers 15 belonging to the same gate structure 6 are connected at the edge of the semiconductor layer 28. Before forming the second conductive via 47 in the above implementation, the embodiment of the present application may further include forming a first gate notch 48 at one end of the gate layer 15 close to the edge of the semiconductor layer 28, and forming a second gate notch 49 at the other end of the gate layer 15 close to the edge of the semiconductor layer 28, so that the two gate layers 15 belonging to the same gate structure 6 are not connected to each other. Among them, the first gate notch 48 and the second gate notch 49 are respectively located on the gate layers 15 on both sides in the gate structure 6. For example, if the first gate notch 48 is located on the first gate layer 15 along the second direction Y, then the second gate notch 49 is located on the second gate layer 15 in the second direction Y, and vice versa.

[0187] Please refer to Figure 42 and Figure 43 , in the above implementation, forming the second conductive via 47 includes forming a second conductive via 47 at one end of the gate layer 15 located at the edge of the semiconductor layer 28, and forming another second conductive via 47 at the other end of the gate layer 15 located at the edge of the semiconductor layer 28. The second conductive via 47 is located between two adjacent bit lines 9 in the third direction Z, and one end of the second conductive via 47 extends into the semiconductor layer 28 to the side of the gate layer 15 away from the second insulating block 19.

[0188] Please refer to Figure 43 and Figure 44, after forming the second conductive via 47, a second conductive pillar 50 is formed in the second conductive via 47 to connect the second conductive pillar 50 to the gate layer 15. The gate layer 15 is led out for leading out the word line. Wherein, the formed second conductive pillar 50 is arranged at an interval from the bit line 9 in the third direction Z, and one end of the second conductive pillar 50 extends into the semiconductor layer 28 to the gate layer 15 and contacts the gate layer 15. In the above implementation manner, the two second conductive pillars 50 for connecting the same gate structure 6 are respectively located at both ends of the gate structure 6 in the third direction Z. Combining with the implementation manner in which the above gate structure 6 includes the first gate notch 48 and the second gate notch 49, since the first gate notch 48 and the second gate notch 49 are respectively located at both ends of the gate layer 15 close to the edge of the semiconductor layer 28, the space for connecting the end of the gate layer 15 in the third direction Z to the second conductive pillar 50 is increased, and the process window is improved; at the same time, since the first gate notch 48 and the second gate notch 49 are respectively located on the gate layers 15 on both sides of the gate structure 6, the problem that two gate layers 15 belonging to the same gate structure 6 are connected to the same second conductive pillar 50 is avoided.

[0189] Please refer to Figure 45 and Figure 46 , some embodiments of the present application further provide a storage system 1000. The storage system 1000 includes a controller 51 and a three-dimensional memory 52. The three-dimensional memory 52 may include the semiconductor structure 1 as described above. The controller 51 is coupled to the three-dimensional memory 52 to control the three-dimensional memory 52 to store data. The term "three-dimensional memory 52" refers to a semiconductor device formed by transistors (referred to as "vertical transistors 4" herein, such as DRAM vertical transistors 4) arranged in an array on the main surface of a substrate and extending perpendicular to the substrate or a direction. As used herein, the term "vertical / vertically" means nominally perpendicular to the substrate (i.e., the lateral surface).

[0190] Wherein, the storage system 1000 can be integrated into various types of storage devices. For example, it is included in the same package (for example, Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is to say, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (such as cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic devices with a memory.

[0191] In some embodiments, referring to Figure 45 , the storage system 1000 includes a controller 51 and a three-dimensional memory 52, and the storage system 1000 can be integrated into a memory card.

[0192] Wherein, the memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, and a UFS.

[0193] In other embodiments, referring to Figure 46 , the storage system 1000 includes a controller 51 and a plurality of three-dimensional memories 52, and the storage system 1000 is integrated into a Solid State Drive (SSD).

[0194] In the storage system 1000, in some embodiments, the controller 51 is configured to operate in a low-duty-cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0195] In other embodiments, the controller 51 is configured to operate in a high-duty-cycle environment of an SSD or an eMMC, and the SSD or eMMC is used for data storage in mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0196] In some embodiments, the controller 51 can be configured to manage data stored in the three-dimensional memory 52 and communicate with external devices (such as a host). In some embodiments, the controller 51 can also be configured to control the operations of the three-dimensional memory 52, such as read, erase, and program operations. In some embodiments, the controller 51 can also be configured to manage various functions regarding data stored in or to be stored in the three-dimensional memory 52, including at least one of bad block management, garbage collection, logical-to-physical address conversion, and wear leveling. In some embodiments, the controller 51, 20 is also configured to process error correction codes for data read from or written to the three-dimensional memory 52.

[0197] Of course, the controller 51 can also perform any other suitable functions, such as formatting the three-dimensional memory 52; for example, the controller 51 can communicate with an external device (such as a host) through at least one of various interface protocols.

[0198] It should be noted that the interface protocols include at least one of USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol.

[0199] Some embodiments of the present application also provide an electronic device. The electronic device can be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0200] The electronic device may include a host and the storage system 1000 described above, and the coupling between the host and the storage system 1000 may further include at least one of a Central Processing Unit (CPU) and a cache.

[0201] The above are only the specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A plurality of semiconductor columns, the semiconductor columns extending along a first direction, and the plurality of semiconductor columns being spaced apart along a second direction, wherein the second direction is perpendicular to the first direction; A gate structure and an isolation structure, the gate structure and the isolation structure being alternately spaced apart along the second direction, the gate structure being located between two adjacent semiconductor columns, and the isolation structure also being located between two adjacent semiconductor columns; The isolation structure includes: a first insulating block, a conductive block, and a second insulating block. Along the first direction, the conductive block is located between the first insulating block and the second insulating block. The first insulating block includes a first insulating layer and a second insulating layer. The first insulating layer is located on a side of the conductive block away from the second insulating block. The first insulating layer wraps the second insulating layer, such that a part of the first insulating layer is located between the second insulating layer and the conductive block, and a part of the first insulating layer is located between the second insulating layer and the semiconductor column.

2. The semiconductor structure according to claim 1, wherein The first insulating layer includes a first hollow cylinder, the first hollow cylinder extending along a third direction, the third direction being perpendicular to the first direction and the second direction, and an outer sidewall of the first hollow cylinder being in contact with the conductive block and the semiconductor column; The second insulating layer includes a second hollow cylinder, the second hollow cylinder extending along the third direction, and an outer sidewall of the second hollow cylinder being in contact with an inner sidewall of the first hollow cylinder.

3. The semiconductor structure according to claim 2, wherein The material of the first insulating layer includes silicon nitride, and the material of the second insulating layer includes an insulating oxide material.

4. The semiconductor structure according to claim 1, wherein The lengths of the plurality of conductive blocks in the first direction are equal, and one end of each conductive block away from the second insulating block is aligned in the second direction.

5. The semiconductor structure according to claim 1, wherein The isolation structure further includes an isolation layer, the isolation layer being located between the conductive block and the semiconductor column.

6. The semiconductor structure according to claim 5, wherein, The isolation layer includes a first isolation layer and a second isolation layer stacked along the second direction, the first isolation layer being located between the second isolation layer and the semiconductor column, and the second isolation layer being located between the first isolation layer and the conductive block.

7. The semiconductor structure according to claim 6, wherein A side of the first isolation layer close to the semiconductor column is in contact with the semiconductor column, a side of the first isolation layer away from the semiconductor column is in contact with the second isolation layer, and a side of the second isolation layer away from the first isolation layer is in contact with the conductive block.

8. The semiconductor structure according to claim 1, characterized in that, The isolation structure further includes a first conductive column, the first conductive column passing through a part of the first insulating layer and a part of the second insulating layer to contact the conductive block.

9. A method for preparing a semiconductor structure, characterized in that, Comprising: Forming a plurality of semiconductor columns, the semiconductor columns extending along a first direction, and the plurality of semiconductor columns being spaced apart along a second direction to form gate grooves and isolation grooves alternately spaced apart along the second direction, wherein the second direction is perpendicular to the first direction; Forming a gate structure in the gate grooves and forming an isolation structure in the isolation grooves, such that the gate structure and the isolation structure are alternately spaced apart along the second direction; Forming the isolation structure includes: forming a first insulating block, a conductive block, and a second insulating block along the first direction, such that the conductive block is located between the first insulating block and the second insulating block; Forming the first insulating block includes: forming a first insulating layer and a second insulating layer, with the first insulating layer located on a side of the conductive block away from the second insulating block, the first insulating layer wrapping the second insulating layer, such that a part of the first insulating layer is located between the second insulating layer and the conductive block, and a part of the first insulating layer is located between the second insulating layer and the semiconductor pillar.

10. The method for preparing a semiconductor structure according to claim 9, wherein, Before forming the isolation structure, it further includes: Forming an initial isolation layer in the isolation groove, the initial isolation layer covering sidewalls of the isolation groove extending in a first direction and covering a bottom wall of the isolation groove; Sequentially forming a third insulating block, a conductive block, and a second insulating block in the isolation groove, with the conductive block located between the third insulating block and the second insulating block; Forming the third insulating block includes: forming an initial third insulating block above the initial isolation layer and removing a part of the initial third insulating block to form the third insulating block, such that a perpendicular distance from an end of each third insulating block away from the bottom wall of the isolation groove to the bottom wall of the isolation groove is the same.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein, Forming the first insulating block includes: Removing a part of the initial isolation layer adjacent to the third insulating block, and the remaining part of the initial isolation layer forms the isolation layer; Removing the third insulating block, and forming the first insulating block at a position where the third insulating block is removed and at a position where the removed part of the initial isolation layer is located.

12. The method for manufacturing a semiconductor structure according to claim 10, wherein, Forming the conductive block includes: After forming the third insulating block, forming an initial conductive block and removing a part of the initial conductive block to form the conductive block, such that the third insulating block and the conductive block are in contact along a second direction; and the initial isolation layer is located between the conductive block and the semiconductor pillar.

13. The method for preparing a semiconductor structure according to claim 10, wherein, Forming the initial isolation layer includes: forming an initial first isolation layer and forming an initial second isolation layer; The remaining initial isolation layer forms the isolation layer includes: after removing a part of the initial isolation layer adjacent to the third insulating block, the remaining initial first isolation layer forms a first isolation layer, and the remaining initial second isolation layer forms a second isolation layer, and the first isolation layer and the second isolation layer form the isolation layer.

14. The method for manufacturing a semiconductor structure according to claim 10, wherein After forming the first insulating block, it further includes: Removing a part of the first insulating layer and the second insulating layer to form a first conductive hole extending along the first direction, with one end of the first conductive hole located on a side of the conductive block away from the second insulating block; Forming a first conductive pillar in the first conductive hole, such that the first conductive pillar is connected to the conductive block to form the isolation structure.

15. A storage system, characterized in that, Includes: A three-dimensional memory, the three-dimensional memory being a semiconductor structure as described in any one of claims 1 - 8; A controller, the controller being coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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