Semiconductor structure, preparation method thereof and storage system

Abstract

The embodiment of the invention provides a semiconductor structure, a preparation method thereof and a storage system, and aims to reduce electric leakage between two adjacent vertical transistors. The semiconductor structure provided by the embodiment of the invention comprises a plurality of semiconductor columns which are arranged at intervals along a second direction, and gate structures and isolation structures are alternately arranged between two adjacent semiconductor columns at intervals; the gate structures and the adjacent semiconductor columns form vertical transistors, and the conductive blocks in the isolation structures are located between two adjacent vertical transistors; in the process that the vertical transistors are conducted, the conductive blocks between the vertical transistors can enable electrons in the conducted vertical transistors not to easily penetrate through the conductive blocks to move towards the adjacent vertical transistors, the coupling effect between the adjacent vertical transistors is improved, and then electric leakage between the adjacent vertical transistors is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of semiconductor chips, and particularly to a semiconductor structure, a preparation method thereof, and a storage system. Background Art

[0002] A semiconductor structure includes a plurality of vertical transistors and a plurality of storage capacitors. The vertical transistors are connected to the storage capacitors, and the storage capacitors are connected to the source electrodes of the vertical transistors. The conduction or cutoff of the vertical transistors determines whether the information stored in the storage capacitors can be read and rewritten. The storage capacitors represent logical 1 and 0 by the amount of charge stored therein, or equivalently, by the magnitude of the voltage difference across the capacitors. However, there is a problem of leakage between adjacent transistors. Summary of the Invention

[0003] The embodiments of the present application adopt the following technical solutions:

[0004] On the one hand, the embodiments of the present application provide a semiconductor structure, including a plurality of semiconductor pillars, a gate structure, and an isolation structure. The semiconductor pillars extend along a first direction, and the plurality of semiconductor pillars are spaced apart along a second direction, where the second direction is perpendicular to the first direction. The gate structure and the isolation structure are alternately spaced along the second direction. The gate structure is located between two adjacent semiconductor pillars, and the isolation structure is also located between two adjacent semiconductor pillars. The isolation structure includes: a first insulating block, a conductive block, and a second insulating block. Along the first direction, the conductive block is located between the first insulating block and the second insulating block. The first insulating block includes a first insulating layer and a second insulating layer. The first insulating layer is located on the side of the conductive block away from the second insulating block, and in the first direction, the first insulating layer is in contact with the conductive block. In the second direction, the second insulating layer is located between the first insulating layer and the semiconductor pillar.

[0005] In some embodiments, the material of the first insulating layer includes silicon nitride or an insulating oxide material, and the material of the second insulating layer includes silicon nitride or an insulating oxide material.

[0006] In some embodiments, the second insulating layer includes a third insulating layer and a fourth insulating layer. The third insulating layer is located on the side of the first insulating layer away from the second insulating block and on both sides of the first insulating layer along the second direction. The fourth insulating layer is located on the side of the third insulating layer away from the second insulating block and on both sides of the third insulating layer along the second direction.

[0007] In some embodiments, the lengths of the plurality of conductive blocks in the first direction are equal, and the ends of the conductive blocks away from the second insulating block are aligned in the second direction.

[0008] In some embodiments, the isolation structure further includes an isolation layer, and the isolation layer is also located between the conductive block and the semiconductor pillar.

[0009] In some embodiments, the isolation layer includes a first isolation layer and a second isolation layer stacked along a second direction. The first isolation layer is located between the second isolation layer and the semiconductor pillar, and the second isolation layer is located between the first isolation layer and the conductive block.

[0010] In some embodiments, one side of the first isolation layer close to the semiconductor pillar is in contact with the semiconductor pillar, one side of the first isolation layer far from the semiconductor pillar is in contact with the second isolation layer, and one side of the second isolation layer far from the first isolation layer is in contact with the conductive block.

[0011] In some embodiments, the isolation structure further includes a first conductive pillar, and the first conductive pillar passes through a part of the second insulating block and contacts the conductive block.

[0012] On the other hand, an embodiment of the present application further provides a method for manufacturing a semiconductor structure, including:

[0013] Forming a plurality of semiconductor pillars, the semiconductor pillars extending along a first direction, the plurality of semiconductor pillars being spaced along a second direction, forming gate trenches and isolation trenches alternately spaced along the second direction, where the second direction is perpendicular to the first direction;

[0014] Forming a gate structure in the gate trenches and forming an isolation structure in the isolation trenches, so that the gate structure and the isolation structure are alternately spaced along the second direction;

[0015] Forming the isolation structure includes: forming a first insulating block, a conductive block, and a second insulating block along the first direction, so that the conductive block is located between the first insulating block and the second insulating block;

[0016] Among them, forming the first insulating block includes: forming a first insulating layer and a second insulating layer, so that the first insulating layer is located on a side of the conductive block far from the second insulating block and is in contact with the conductive block in the first direction; and the second insulating layer is located between the first insulating layer and the semiconductor pillar in the second direction.

[0017] In some embodiments, before forming the isolation structure, it further includes:

[0018] Forming an initial isolation layer in the isolation trench, the initial isolation layer covering the side wall of the isolation trench extending along the first direction and covering the bottom wall of the isolation trench;

[0019] Sequentially forming a first insulating layer, a conductive block, and a second insulating block in the isolation trench, so that the conductive block is located between the first insulating layer and the second insulating block;

[0020] Forming the first insulating layer includes: forming an initial first insulating layer above the initial isolation layer and removing a part of the initial first insulating layer to form the first insulating layer, so that the vertical distance from one end of each first insulating layer far from the bottom wall of the isolation trench to the bottom wall of the isolation trench is the same.

[0021] In some embodiments, forming the first insulating layer includes:

[0022] Removing a portion of the initial isolation layer adjacent to the first insulating layer, and the remaining initial isolation layer forms an isolation layer;

[0023] Forming a second insulating layer at the position of the removed portion of the initial isolation layer.

[0024] In some embodiments, forming the conductive block includes:

[0025] After forming the first insulating layer, forming an initial conductive block and removing a portion of the initial conductive block to form a conductive block, such that the first insulating layer and the conductive block are in contact along a second direction; and the initial isolation layer is located between the conductive block and the semiconductor pillar.

[0026] In some embodiments, forming the initial isolation layer includes: forming an initial first isolation layer and forming an initial second isolation layer;

[0027] The remaining initial isolation layer forming an isolation layer includes: after removing the portion of the initial isolation layer adjacent to the first insulating layer, the remaining initial first isolation layer forms a first isolation layer, the remaining initial second isolation layer forms a second isolation layer, and the first isolation layer and the second isolation layer form an isolation layer.

[0028] In some embodiments, after forming the second insulating block, it further includes:

[0029] Removing a portion of the second insulating block to form a first conductive hole extending along a first direction, with one end of the first conductive hole located on a side of the conductive block away from the first insulating layer;

[0030] Forming a first conductive pillar in the first conductive hole, connecting the first conductive pillar to the conductive block to form an isolation structure.

[0031] In another aspect, an embodiment of the present application further provides a storage system, including a 3D memory and a controller. The 3D memory may include the semiconductor structure as described above; the controller is coupled to the 3D memory to control the 3D memory to store data.

[0032] In another aspect, an embodiment of the present application further provides an electronic device, including a host and the storage system as above, and the host and the storage system are coupled. Description of the Drawings

[0033] To more clearly illustrate the technical solutions in the present application, the following briefly introduces the drawings required for use in some embodiments of the present application. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and are not limitations on the actual dimensions of the products involved in the embodiments of the present application, the actual processes of the methods, the actual timings of the signals, etc.

[0034] Figure 1 Is a three-dimensional structure diagram of a semiconductor structure according to some embodiments;

[0035] Figure 2 Is a cross-sectional view of a semiconductor structure according to some embodiments;

[0036] Figure 3 Is Figure 1 A structure diagram of a storage unit in

[0037] Figure 4 Is Figure 3 An equivalent circuit diagram of the storage unit shown;

[0038] Figure 5 Is a schematic structural diagram of a semiconductor structure in some embodiments of the present application;

[0039] Figure 6 Is another schematic structural diagram of a semiconductor structure in some embodiments of the present application;

[0040] Figure 7 Is a flowchart of a method for manufacturing a semiconductor structure in some embodiments of the present application;

[0041] Figure 8 Is a schematic structural diagram of a semiconductor layer provided in some embodiments of the present application;

[0042] Figure 9 Is a schematic structural diagram before forming a gate trench and an isolation trench in some embodiments of the present application;

[0043] Figure 10 Is a schematic structural diagram after forming a gate trench and an isolation trench in some embodiments of the present application;

[0044] Figure 11 Is a schematic structural diagram before filling a sacrificial material into the gate trench and the isolation trench in some embodiments of the present application;

[0045] Figure 12 Is a schematic structural diagram after filling a sacrificial material into the gate trench and the isolation trench in some embodiments of the present application;

[0046] Figure 13Schematic diagram of the structure in the third direction after filling the sacrificial material in some embodiments of the present application;

[0047] Figure 14 Schematic diagram of the structure after removing the sacrificial material in the isolation groove in some embodiments of the present application;

[0048] Figure 15 Schematic diagram of the structure after forming the initial isolation layer in some embodiments of the present application;

[0049] Figure 16 Schematic diagram of the structure after forming the initial first insulating layer in some embodiments of the present application;

[0050] Figure 17 Schematic diagram of the structure after forming the first insulating layer in some embodiments of the present application;

[0051] Figure 18 Schematic diagram of the structure after forming the initial conductive block in some embodiments of the present application;

[0052] Figure 19 Schematic diagram of the structure after forming the conductive block in some embodiments of the present application;

[0053] Figure 20 Schematic diagram of the structure after forming the initial second insulating block in some embodiments of the present application;

[0054] Figure 21 Schematic diagram of the structure after forming the second insulating block in some embodiments of the present application;

[0055] Figure 22 Schematic diagram of the structure after forming the initial first isolation layer and the initial second isolation layer in some embodiments of the present application;

[0056] Figure 23 Another schematic diagram of the structure after forming the initial first insulating layer in some embodiments of the present application;

[0057] Figure 24 Another schematic diagram of the structure after forming the first insulating layer in some embodiments of the present application;

[0058] Figure 25 Another schematic diagram of the structure after forming the initial conductive block in some embodiments of the present application;

[0059] Figure 26 Another schematic diagram of the structure after forming the conductive block in some embodiments of the present application;

[0060] Figure 27 Another schematic diagram of the structure after forming the initial second insulating block in some embodiments of the present application;

[0061] Figure 28Another structural schematic diagram after forming the second insulating block in some embodiments of the present application;

[0062] Figure 29 Structural schematic diagram after forming the initial first gate layer in some embodiments of the present application;

[0063] Figure 30 Structural schematic diagram after forming the initial second gate layer in some embodiments of the present application;

[0064] Figure 31 Structural schematic diagram after forming the filling layer in some embodiments of the present application;

[0065] Figure 32 Structural schematic diagram after removing part of the initial isolation layer in some embodiments of the present application;

[0066] Figure 33 Structural schematic diagram after forming the gate layer in some embodiments of the present application;

[0067] Figure 34 Structural schematic diagram after removing part of the initial first isolation layer in some embodiments of the present application;

[0068] Figure 35 Structural schematic diagram after forming the gate layer in some embodiments of the present application;

[0069] Figure 36 Structural schematic diagram after forming the second insulating layer in some embodiments of the present application;

[0070] Figure 37 Another structural schematic diagram after forming the fourth insulating layer in some embodiments of the present application;

[0071] Figure 38 Structural schematic diagram after forming the first conductive hole in some embodiments of the present application;

[0072] Figure 39 Structural schematic diagram after forming the first conductive pillar in some embodiments of the present application;

[0073] Figure 40 Structural schematic diagram in the first direction after forming the first conductive pillar and the second conductive pillar in some embodiments of the present application;

[0074] Figure 41 Structural schematic diagram after forming the second conductive hole in some embodiments of the present application;

[0075] Figure 42 Structural schematic diagram after forming the second conductive pillar in some embodiments of the present application;

[0076] Figure 43 Frame of the storage system in some embodiments of the present applicationFigure 1 ;

[0077] Figure 44 For the block diagram of the storage system in some embodiments of the present application Figure 2 。

[0078] Description of reference numerals: 1. Semiconductor structure; 2. Memory cell array layer; 3. Device layer; 4. Vertical transistor; 5. Semiconductor pillar; 6. Gate structure; 7. Gate dielectric layer; 8. Storage capacitor; 9. Bit line; 10. Wiring layer; 11. Peripheral circuit layer; 12. First connection part; 13. Second connection part; 14. Semiconductor pillar group; 15. Gate layer; 16. Isolation structure; 17. First insulating block; 18. Conductive block; 19. Second insulating block; 20. First insulating layer; 21. Second insulating layer; 22. First conductive pillar; 23. Isolation layer; 24. First isolation layer; 25. Second isolation layer; 26. Third insulating layer; 27. Fourth insulating layer; 28. Semiconductor layer; 29. Mask plate; 30. Insulating groove; 31. Dielectric material; 32. Gate groove; 33. Isolation groove; 34. Sacrificial material; 35. Initial isolation layer; 36. Initial first insulating layer; 37. Initial conductive block; 38. Initial second insulating block; 39. Initial first isolation layer; 40. Initial second isolation layer; 41. Initial first gate layer; 42. Initial second gate layer; 43. Filling layer; 44. Initial filling layer; 45. First conductive hole; 46. Second conductive hole; 47. First gate notch; 48. Second gate notch; 49. Second conductive pillar; 50. Controller; 51. 3D memory; 1000. Storage system. Detailed implementation manners

[0079] Next, the technical solutions in some embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present application.

[0080] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present application.

[0081] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described above may be included in any one or more embodiments or examples in any appropriate manner.

[0082] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0083] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. Also, for example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical contact or electrical contact. However, the term "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments invented herein are not necessarily limited to the content herein.

[0084] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0085] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0086] As used herein, "about", "substantially" or "approximately" includes the stated value and the average value within an acceptable deviation range of the specific value, where the acceptable deviation range is determined by those of ordinary skill in the art considering the measurement being discussed and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system).

[0087] In the context of the present application, the meanings of "on", "above", and "over" should be construed in the broadest possible manner such that "on" not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over something", but also includes the meaning of "above" or "over something" without intermediate features or layers therebetween (i.e., directly on something).

[0088] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0089] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Additionally, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0090] Figure 1 Is a three-dimensional structural diagram of a semiconductor structure according to some embodiments, Figure 2 Is a cross-sectional view of a semiconductor structure according to some embodiments, Figure 3 Is Figure 1 A structural diagram of one of the storage cells in Figure 4 Is Figure 3 The equivalent circuit diagram of the storage cell shown in

[0091] It should be noted that in Figure 1 And Figure 2 A semiconductor structure 1 provided by an embodiment of the present application is in a three-dimensional coordinate system of X - Y - Z. The semiconductor structure 1 extends in the Y - Z plane. The second direction Y and the third direction Z are, for example, two orthogonal directions in the plane where the semiconductor structure 1 is located (for example, the plane where the source layer SL is located): The second direction Y is, for example, the extending direction of the bit line (BL), and the third direction Z is, for example, the extending direction of the word line (WL). The first direction X is perpendicular to the plane where the semiconductor structure 1 is located, that is, perpendicular to the Y - Z plane.

[0092] SeeFigure 1 and Figure 2 Some embodiments of the present application provide a semiconductor structure 1 that may include a memory cell array layer, a source layer SL, and a device layer 3 coupled to the memory cell array layer 2. The device layer 3 may be disposed on a side of the memory cell array layer 2 away from the source layer SL in a first direction X.

[0093] As used in this application, whether a component (e.g., layer, structure, or device) is "on," "over," or "under" another component (e.g., layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to a device layer 3 of the semiconductor device in a first direction X when the device layer 3 is located in the lowest plane of the semiconductor device in the first direction X. The same concept is applied to describe spatial relationships throughout the content of this application.

[0094] See also Figure 2 and Figure 3 The source layer SL may be connected to a first reference voltage, which may be a ground voltage or other voltages. The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, which is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0095] See also Figure 1 and Figure 2 The memory cell array layer 2 includes a plurality of memory cells arranged in an array along the second direction Y and the third direction Z. Figure 3 and Figure 4 As shown, the memory cell includes a vertical transistor 4 and a storage capacitor 8. The vertical transistor 4 can be formed by a channel structure formed by a semiconductor column 5 and a gate structure 6 adjacent to the channel structure. Among them, a gate dielectric layer 7 is also provided between the channel structure and the corresponding gate structure 6. The channel structure has a source and a drain, and the source and the drain are respectively located at the two ends of the channel structure. The drain of the vertical transistor 4 is connected to the bit line 9, the source of the vertical transistor 4 is connected to one plate of the storage capacitor 8, and the other plate of the storage capacitor 8 can be connected to the source layer SL. The storage capacitor 8 represents logical 1 and 0 by the amount of charge stored therein, or the high and low voltage difference across the capacitor. The gate structure 6 of the vertical transistor 4 is connected to the word line WL. The vertical transistor 4 is turned on or off by applying a voltage through the word line WL, and when the vertical transistor 4 is turned on, the bit line 9 performs a read or write operation on the vertical transistor 4.

[0096] In some embodiments, seeFigure 1 and Figure 2 Further, the semiconductor structure 1 may further include a word line WL and a bit line 9. The word line WL may be coupled to the gate structure 6 of at least one vertical transistor 4. The bit line 9 may be coupled to the drain of at least one vertical transistor 4. The drains of a plurality of vertical transistors 4 spaced apart along the second direction Y are coupled to the same bit line 9.

[0097] Continuing to refer to Figure 2 In some embodiments, the memory cell array layer 2 may further include a wiring layer 10. The wiring layer 10 is located on a side of the bit line 9 away from the vertical transistor 4. The wiring layer 10 may be coupled to the vertical transistor 4, wherein the wiring layer 10 may be connected to the drain of the channel structure in each vertical transistor 4 through the bit line 9.

[0098] In the above embodiments, the device layer 3 coupled to the memory cell array layer 2 may include a substrate and a peripheral circuit layer 11 disposed on the substrate. Wherein, the material of the substrate may be single crystal silicon, or other suitable materials, such as silicon germanium, germanium or silicon-on-insulator thin film. The peripheral circuit layer 11 may be configured to control and sense array devices. The peripheral circuit layer 11 may be any suitable digital, analog, and / or mixed signal control and sensing circuit for supporting the operation (or work) of the array devices, including but not limited to page buffers, decoders (such as row decoders and column decoders), sense amplifiers, drivers (such as word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (such as transistors, diodes, resistors or capacitors). The peripheral circuit may further include any other circuits compatible with advanced logic processes, including logic circuits (such as processors and programmable logic devices (PLD)) or storage circuits (such as static random access memory (SRAM)).

[0099] The peripheral circuit layer 11 may be coupled to the wiring layer 10 such that the memory cell array layer 2 and the device layer 3 may be coupled. Specifically, since the peripheral circuit layer 11 is coupled to the wiring layer 10, the peripheral circuit in the device layer 3 may be coupled to the vertical transistor 4 in the memory cell array layer 2 to implement the transmission of electrical signals between the peripheral circuit and the vertical transistor 4. In some possible implementation manners, a bonding interface may be provided between the peripheral circuit layer 11 and the wiring layer 10, through which the peripheral circuit layer 11 and the wiring layer 10 may be bonded and coupled to each other.

[0100] In the above embodiments, on the side of the memory cell array layer 2 close to the peripheral circuit layer 11, a first connection part 12 located in the wiring layer 10 may be provided. The first connection part 12 is used to connect to the vertical transistor 4 inside the memory cell array layer 2. The peripheral circuit layer 11 may include a second connection part 13 and a transistor provided on the substrate. The second connection part 13 is connected to the transistor and is located on the side of the transistor close to the memory cell array layer 2, where the transistor may include a Complementary Metal Oxide Semiconductor (CMOS). In the above embodiments, the first connection part 12 and the second connection part 13 are bonded and connected, and the connection between the vertical transistor 4 and the transistor is realized through the bonding between the first connection part 12 and the second connection part 13, thereby realizing the connection between the memory cell array layer 2 and the peripheral circuit layer 11.

[0101] Please refer to Figure 5 , in the above embodiments, the vertical transistor 4 in the memory cell array layer 2 (as Figure 2 shown) may include an MSG (mirror single gate) vertical transistor. An embodiment of the present application provides a semiconductor structure 1, including a plurality of semiconductor pillar groups 14 arranged in an array along the second direction Y and the third direction Z. Each semiconductor pillar group 14 includes two semiconductor pillars 5 (that is, the semiconductor structure 1 includes a plurality of semiconductor pillars 5). Each semiconductor pillar 5 extends along the first direction X, and the two semiconductor pillars 5 belonging to the same semiconductor pillar group 14 are spaced apart in the second direction Y. The semiconductor structure 1 further includes the above-mentioned gate structure 6. The gate structure 6 is located between two adjacent semiconductor pillars 5 belonging to the same semiconductor pillar group 14. The gate structure 6 includes two gate layers 15. The two gate layers 15 are spaced apart along the second direction Y and extend along the first direction X. One of the gate layers 15 is close to one semiconductor pillar 5 in the semiconductor pillar group 14, and the other gate layer 15 is close to the other semiconductor pillar 5 belonging to the same semiconductor pillar group 14. The gate layer 15 and the adjacent semiconductor pillar 5 form a vertical transistor 4. In one semiconductor pillar group 14, the two gate layers 15 are mirror-symmetrically distributed, that is, the formed vertical transistor 4 is an MSG vertical transistor. In other embodiments, the vertical transistor 4 in the memory cell array layer 2 may also include a single-gate vertical transistor, a double-gate vertical transistor, a tri-gate vertical transistor, and a GAA (gate all around) vertical transistor, etc.

[0102] Continue to refer to Figure 5, in some embodiments, the semiconductor structure 1 provided by the embodiments of the present application further includes an isolation structure 16, and the isolation structure 16 is located between two semiconductor pillar groups 14 that are spaced apart and adjacent to each other in the second direction Y. The semiconductor pillar group 14 includes two semiconductor pillars 5 that are spaced apart in the second direction Y (that is, the isolation structure 16 is located between two adjacent semiconductor pillars 5). Combining the above embodiments where the gate structure 6 is located between two adjacent semiconductor pillars 5 belonging to the same semiconductor pillar group 14, the gate structure 6 and the isolation structure 16 are alternately spaced apart in the second direction. The isolation structure 16 includes a first insulating block 17, a conductive block 18, and a second insulating block 19. Along the first direction, the conductive block 18 is located between the first insulating block 17 and the second insulating block 19. Combining Figure 2 , in the implementation manner where the memory cell array layer 2 includes the storage capacitor 8 and the bit line 9 as described above, in the first direction X, the isolation structure 16 is located between the storage capacitor 8 and the bit line 9. The second insulating block 19 in the isolation structure 16 is closer to the storage capacitor 8 than the first insulating block 17, and the first insulating block 17 in the isolation structure 16 is closer to the bit line 9 than the second insulating block 19.

[0103] In the above implementation manner, the conductive block 18 is configured with a preset potential. Exemplarily, the conductive block 18 can be grounded or connected to a negative voltage. The conductive block 18 can be made of a conductive material. Exemplarily, the conductive block 18 can be made of at least one of tungsten, cobalt, and titanium nitride (TiN).

[0104] Continue to refer to Figure 5 , in the semiconductor structure 1 provided by the embodiments of the present application, it includes a plurality of semiconductor pillars 5 that are spaced apart in the second direction. The gate structure 6 and the isolation structure 16 are alternately spaced apart between two adjacent semiconductor pillars 5. The gate structure 6 and the adjacent semiconductor pillar 5 form a vertical transistor 4. The conductive block 18 in the isolation structure 16 is located between two adjacent vertical transistors 4. During the conduction process of the vertical transistor 4, the conductive block 18 between the vertical transistors 4 can prevent electrons in the turned-on vertical transistor 4 from easily passing through the conductive block 18 and moving to the adjacent vertical transistor 4, reducing the coupling effect between adjacent vertical transistors 4, and further reducing the leakage between adjacent vertical transistors 4.

[0105] Continue to refer to Figure 5, in some embodiments, the first insulating block 17 includes a first insulating layer 20 and a second insulating layer 21, where both the first insulating layer 20 and the second insulating layer 21 can be made of insulating materials. Exemplarily, the first insulating layer 20 may include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The second insulating layer 21 may include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. Exemplarily, the material of the first insulating layer 20 is silicon nitride, and the material of the second insulating layer 21 is also silicon nitride. The first insulating layer 20 and the second insulating layer 21 are jointly used to insulate the end of the conductive block 18 away from the second insulating block 19.

[0106] In the above embodiments, the first insulating layer 20 is located on the side of the conductive block 18 away from the second insulating block 19. In the first direction X, one end of the first insulating layer 20 contacts the conductive block 18 and completely covers the surface of the conductive block 18 on the side close to the first insulating layer 20; in the second direction Y, the second insulating layer 21 is located between the first insulating layer 20 and the semiconductor pillar 5, and the second insulating layer 21 is spaced from the conductive block 18 (that is, the second insulating block 19 does not contact the conductive block 18).

[0107] Continue to refer to Figure 5 , in the embodiments of the present application, the isolation structure 16 further includes a first conductive pillar 22, and the first conductive pillar 22 passes through part of the second insulating block 19 and contacts the conductive block 18. The first conductive pillar 22 is used to lead out the conductive block 18 to achieve grounding or connecting a negative voltage of the conductive block 18, so that electrons in the conductive vertical transistor 4 are not easily transferred through the conductive block 18 to adjacent vertical transistors 4, reducing the coupling effect between adjacent vertical transistors 4 and reducing the leakage between adjacent vertical transistors 4.

[0108] The second insulating block 19 can be made of insulating materials. The second insulating block 19 is used to insulate the end of the conductive block 18 away from the first insulating block 17. Exemplarily, the second insulating block 19 may include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide.

[0109] Through the above settings, during the formation of the first conductive pillar 22 and making the first conductive pillar 22 pass through part of the second insulating block, after the formation of the first conductive pillar 22, in the second direction Y, there is still a remaining part of the second insulating block 19 between the first conductive pillar 22 and the semiconductor pillar 5. Since the second insulating block 19 is made of insulating materials, the second insulating block 19 can prevent the formed first conductive pillar 22 from being directly connected to the semiconductor pillar 5, resulting in leakage.

[0110] In the above embodiments, since the first conductive pillar 22 penetrates through a part of the second insulating block 19, during the process of connecting the conductive block 18 through the first conductive pillar 22 to lead out the conductive block 18, the process of forming the first conductive pillar 22 does not need to consider the relationship with the bit line 9 (that is, the first conductive pillar 22 can be completed in the front end of line (FEOL), avoiding forming the first conductive pillar 22 in the back end of line (BEOL) to lead out the conductive block 18), thereby reducing the process difficulty of forming the semiconductor structure 1.

[0111] In the above implementation manner where the conductive block 18 is located between the first insulating block 17 and the second insulating block 19 in the first direction X, the first insulating block 17 and the second insulating block 19 can limit both ends of the conductive block 18 in the first direction from exceeding the two ends of the gate layer 15 in the first direction X. Combining Figure 2 That is to say, in the implementation manner where the memory cell array layer 2 includes the storage capacitor 8 and the bit line 9 in the above, the end of the gate layer 15 close to the storage capacitor 8 is closer to the storage capacitor 8 than the end of the conductive block 18 close to the storage capacitor 8, and the end of the gate layer 15 close to the bit line 9 is closer to the bit line 9 than the end of the conductive block 18 close to the bit line 9. So that while the conductive block 18 can reduce the coupling effect between adjacent vertical transistors 4, it can avoid one end of the conductive block 18 in the first direction X from exceeding one end of the adjacent gate layer 15 in the first direction, thereby avoiding the electrons in the conductive block 18 from being reversely coupled to the gate layer 15 adjacent to the conductive block 18 when the conductive block 18 is energized through the first conductive pillar 22, and further affecting the operation of the adjacent vertical transistors 4.

[0112] Continue to refer to Figure 5 In the embodiments of the present application, the lengths of the plurality of conductive blocks 18 in the first direction X are equal, and one end of each conductive block 18 far from the second insulating block 19 is aligned in the second direction Y, and at the same time, one end of each conductive block 18 close to the second insulating block 19 is aligned in the second direction Y; that is to say, the plurality of conductive blocks 18 arranged at intervals in the second direction Y are located at the same height. Through the above settings, the influence of each conductive block 18 on the coupling effect between the adjacent vertical transistors 4 is the same, improving the stability of the semiconductor structure 1.

[0113] Continue to refer to Figure 5, in the embodiments of the present application, the isolation structure 16 further includes an isolation layer 23, and the isolation layer 23 is located between the conductive block 18 and the semiconductor pillar 5 in the second direction Y. The isolation layer 23 is a single-layer structure, and the isolation layer 23 can be made of an insulating material. Exemplarily, the isolation layer 23 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. Through the above arrangement, the isolation layer 23 can achieve insulation between the conductive block 18 and the semiconductor pillar 5 in the second direction Y.

[0114] In an implementation manner where the semiconductor structure 1 includes the second insulating block 19, the isolation layer 23 can also be located between the second insulating block 19 and the semiconductor pillar 5 adjacent to the second insulating block 19 in the second direction Y.

[0115] Please refer to Figure 6 , in the above embodiments, the isolation layer 23 can also include a first isolation layer 24 and a second isolation layer 25. The first isolation layer 24 and the second isolation layer 25 are stacked along the second direction Y. The first isolation layer 24 is located between the second isolation layer 25 and the semiconductor pillar 5, and the second isolation layer 25 is located between the first isolation layer 24 and the conductive block 18. Both the first isolation layer 24 and the second isolation layer 25 can be made of an insulating material. Exemplarily, the first isolation layer 24 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The second isolation layer 25 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The first isolation layer 24 and the second isolation layer 25 can be made of the same material or different materials; for example, the material of the first isolation layer 24 is an insulating oxide material, and the material of the second isolation layer 25 is silicon nitride. Through the above arrangement, the first isolation layer 24 and the second isolation layer 25 can jointly achieve insulation between the conductive block 18 and the semiconductor pillar 5 in the second direction Y.

[0116] In the above embodiments, one side of the first isolation layer 24 close to the semiconductor pillar 5 is in contact with the semiconductor pillar 5, one side of the first isolation layer 24 far from the semiconductor pillar 5 is in contact with the second isolation layer 25, and one side of the second isolation layer 25 far from the first isolation layer 24 is in contact with the conductive block 18.

[0117] In the implementation where the isolation layer 23 includes a first isolation layer 24 and a second isolation layer 25, the second insulating layer 21 includes a third insulating layer 26 and a fourth insulating layer 27. The third insulating layer 26 and the fourth insulating layer 27 are stacked along the second direction Y. The third insulating layer 26 is located on the side of the first insulating layer 20 away from the second insulating block 19 and on both sides of the first insulating layer 20 along the second direction Y (that is, the third insulating layer 26 is located between the first insulating layer 20 and the semiconductor pillar 5, and the third insulating layer 26 covers the surface of the first insulating layer 20); the fourth insulating layer 27 is located on the side of the third insulating layer 26 away from the second insulating block 19 and on both sides of the third insulating layer 26 along the second direction Y (that is, the fourth insulating layer 27 is located between the third insulating layer 26 and the semiconductor pillar 5, and the fourth insulating layer 27 covers the surface of the first insulating layer 20). Both the third insulating layer 26 and the fourth insulating layer 27 can be made of insulating materials. Exemplarily, the third insulating layer 26 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The fourth insulating layer 27 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The third insulating layer 26 and the fourth insulating layer 27 can be made of the same material or different materials. In the implementation where the material of the first isolation layer 24 is an insulating oxide material and the material of the second isolation layer 25 is silicon nitride, the material of the third insulating layer 26 can be silicon nitride, and the fourth insulating layer can also be silicon nitride, and the third insulating layer 26 and the second isolation layer 25 can be an integral structure, that is, the third insulating layer 26 and the second isolation layer 25 are formed simultaneously in the same step.

[0118] In an embodiment where the isolation layer 23 is a single-layer structure, the isolation layer 23 includes an insulating oxide. Compared with the isolation layer 23 including a first isolation layer 24 formed of an insulating oxide material and a second isolation layer 25 formed of silicon nitride. The isolation layer is only formed of an insulating oxide, reducing the Equivalent Oxide Thickness (EOT), and can increase the process window for continuing to reduce the size of vertical transistors according to Moore's law requirements.

[0119] At the same time, during the formation of the isolation layer 23, only one layer of insulating oxide is deposited. Then, during the formation of the conductive block 18, the width of the conductive block 18 in the second direction Y can be increased to further reduce the coupling effect between adjacent vertical transistors 4, thereby reducing the leakage between adjacent vertical transistors 4.

[0120] An embodiment of the present application also provides a method for manufacturing a semiconductor structure 1, which can be used to fabricate the semiconductor structure 1 in the above embodiments. Please refer to Figure 7 , the manufacturing method may include steps S100 - S400:

[0121] S100: Form multiple semiconductor pillars. The semiconductor pillars extend along a first direction, and the multiple semiconductor pillars are arranged at intervals along a second direction, forming gate trenches and isolation trenches that are alternately arranged at intervals along the second direction, where the second direction is perpendicular to the first direction.

[0122] Please refer to Figure 8 , in step S100, before forming the multiple semiconductor pillars 5, a semiconductor layer 28 will be provided. The semiconductor layer 28 may include single-crystalline silicon, polycrystalline silicon, etc. Then, a mask plate 29 is formed above the semiconductor layer 28, and the material of the mask plate 29 includes SiN. In the implementation where the mask plate 29 includes SiN, before forming the mask plate 29, an oxide layer is deposited on the semiconductor layer 28, and then the mask plate 29 is formed on the oxide layer to avoid stress problems caused by direct contact between the mask plate 29 formed by SiN and the Si of the semiconductor layer 28.

[0123] Please refer to Figure 9 , through the mask plate 29, multiple insulating trenches 30 are formed on the semiconductor layer 28 and are arranged at intervals along a third direction Z, and the insulating trenches 30 extend into the semiconductor layer 28 along the first direction X. The distance between two adjacent insulating trenches 30 in the third direction is equal. In the implementation where the semiconductor structure 1 includes bit lines 9, the extending direction of the insulating trenches 30 in the third direction Z is the same as the extending direction of the bit lines 9.

[0124] After forming the insulating trenches 30, under high-temperature conditions, an epitaxial growth oxide layer is formed on the inner wall of the insulating trenches 30 (i.e., the single-crystalline silicon on the inner wall of the insulating trenches 30 is oxidized into silicon dioxide) to repair the surface of the exposed semiconductor layer 28.

[0125] After forming the oxide layer in the insulating trenches 30, a dielectric material 31 is filled in the insulating layer, and chemical mechanical polishing (CMP) is performed on the upper surface of the semiconductor layer 28. The dielectric material 31 may include at least one of silicon dioxide and nitride.

[0126] Please refer to Figure 10 , step S100 further includes forming gate trenches 32 and isolation trenches 33 that are alternately arranged at intervals along the second direction Y on the semiconductor layer 28 through the mask plate 29, where the gate trenches 32 extend into the semiconductor layer 28 along the first direction X and extend in the third direction Z; the isolation trenches 33 extend into the semiconductor layer 28 along the first direction X and extend in the third direction Z.

[0127] Please refer to Figure 11 , after forming the gate trenches 32, similarly, under high-temperature conditions, an epitaxial growth oxide layer is formed on the inner wall of the gate trenches 32 (i.e., the single-crystalline silicon on the inner wall of the gate trenches 32 is oxidized into silicon dioxide) to repair the surface of the exposed semiconductor layer 28.

[0128] Similarly, continuing to refer to Figure 11 , after forming the isolation trench 33, the inner wall of the isolation trench 33 is also epitaxially grown with an oxide layer under high temperature conditions (i.e., the single crystal silicon on the inner wall of the isolation trench 33 is oxidized into silicon dioxide) to repair the surface of the exposed semiconductor layer 28.

[0129] The formation of the oxide layer on the inner wall of the gate trench 32 and the formation of the oxide layer on the inner wall of the isolation trench 33 can be formed simultaneously in the same step.

[0130] Please refer to Figure 12 , after forming the oxide layer on the inner wall of the gate trench 32 and the inner wall of the isolation trench 33, the gate trench 32 and the isolation trench 33 are filled with a sacrificial material 34, and the sacrificial material 34 may include a carbon coating (Spin On Carbon, SOC), carbon (Carbon), etc.

[0131] Up to this point, please refer to Figure 13 , a plurality of semiconductor pillars 5 surrounded by the dielectric material 31 and the sacrificial material 34 are formed on the remaining semiconductor layer 28. The semiconductor pillars 5 extend along the first direction, and the plurality of semiconductor pillars 5 are spaced apart along the second direction. In the second direction Y, there is a sacrificial material 34 between adjacent semiconductor pillars 5, and in the third direction Z, there is a dielectric material 31 between adjacent semiconductor pillars 5.

[0132] S200: Form a gate structure in the gate trench and form an isolation structure in the isolation trench, so that the gate structure and the isolation structure are alternately spaced along the second direction.

[0133] In step S200, the gate structure 6 can be formed before forming the isolation structure 16, or the gate structure 6 can be formed after forming the isolation structure 16, or the gate structure 6 can be formed during the formation of the isolation structure 16.

[0134] S300: Forming the isolation structure includes: forming a first insulating block, a conductive block, and a second insulating block along the first direction, with the conductive block located between the first insulating block and the second insulating block; wherein, forming the first insulating block includes: forming a first insulating layer and a second insulating layer, with the first insulating layer located on the side of the conductive block away from the second insulating block and in contact with the conductive block in the first direction; and making the second insulating layer located between the first insulating layer and the semiconductor pillar in the second direction.

[0135] Please refer to Figure 14 And contrast and refer to Figure 12, before forming the isolation structure 16 in step S300, the preparation method provided by the embodiment of the present application further includes removing all the sacrificial materials 34 located in the isolation trench 33. In the implementation manner where the sacrificial material 34 includes carbon, the process of removing all the sacrificial materials 34 in the isolation trench 33 may include ashing to remove all the sacrificial materials 34 in the isolation trench 33.

[0136] During the process of removing all the sacrificial materials 34 in the isolation trench 33, a part of the oxide layer on the inner wall of the isolation trench 33 will be removed simultaneously. Therefore, before forming the isolation structure 16, please refer to Figure 15 , the preparation method provided by the embodiment of the present application further includes: forming an initial isolation layer 35 in the isolation trench 33, and the initial isolation layer 35 covers the side wall of the isolation trench 33 extending in the first direction and covers the bottom wall of the isolation trench 33.

[0137] In some embodiments, the initial isolation layer 35 is a single-layer structure, and the initial isolation layer 35 can be made of an insulating material. Exemplarily, the initial isolation layer 35 may include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. In this embodiment, the initial isolation layer 35 includes an insulating oxide. Then forming the initial isolation layer 35 includes depositing an oxide layer in the isolation trench 33, and this oxide layer and the remaining part of the oxide layer on the inner wall of the isolation trench 33 together form the initial isolation layer 35.

[0138] In the above embodiment, please refer to Figures 16 to 21 , forming the isolation structure 16 in step S300 further includes sequentially forming a first insulating block 17, a conductive block 18, and a second insulating block 19 in the isolation trench 33, so that the conductive block 18 is located between the first insulating layer 20 and the second insulating block 19.

[0139] Please refer to Figure 16 and Figure 17 , in the implementation manner where the initial isolation layer 35 includes an insulating oxide, forming the first insulating block 17 includes forming an initial first insulating layer 36 above the initial isolation layer 35 and removing a part of the initial first insulating layer 36 to form the first insulating layer 20, so that the vertical distance from one end of each first insulating layer 20 away from the bottom wall of the isolation trench 33 to the bottom wall of the isolation trench 33 is the same.

[0140] In the above implementation manner, the initial first insulating layer 36 may include silicon nitride (SiN). Forming the initial first insulating layer 36 above the initial isolation layer 35 may include depositing SiN in the isolation trench 33 to form the initial first insulating layer 36. During the subsequent process of forming the conductive block 18 (as shown in Figure 19 ), the first insulating layer 20 can make the conductive block 18 have a certain height.

[0141] In one implementation, the thickness of the deposited SiN is greater than 1 / 2 of the width of the isolation trench 33 in the second direction Y, so that the formed initial first insulating layer 36 almost fills the isolation trench 33, and there are no gap defects on the first insulating layer 20 formed after removing part of the initial first insulating layer 36 subsequently. In the above implementation, the same height of part of the initial first insulating layer 36 is removed from each isolation trench 33, and the remaining part of the initial first insulating layer 36 forms the first insulating layer 20, so that the vertical distance from one end of each first insulating layer 20 away from the bottom wall of the isolation trench 33 to the bottom wall of the isolation trench 33 is the same, thereby realizing the alignment of one end of each conductive block 18 away from the second insulating block 19 in the second direction Y.

[0142] In another implementation, there is no limitation on the thickness of the deposited SiN. In the case where the thickness of the SiN is insufficient, there will be gap defects extending along the first direction X in the initial first insulating layer 36. In the process of removing part of the initial first insulating layer 36, part of the initial first insulating layer 36 is removed by using phosphoric acid (H3PO4) solution. The silicon nitride (SI3N4) forming the initial first insulating layer 36 can first react with water in the phosphoric acid solution to generate silicon dioxide (SIO2) and ammonia (NH3). Subsequently, the generated SIO2 can react with H3PO4 to generate silicic acid (H2SiO3) and diphosphorus pentoxide (P2O5). Then, during the process of removing part of the initial first insulating layer 36, the precipitate generated by the reaction of silicon nitride and the phosphoric acid solution can adhere to the gap defects, so that the side of the formed first insulating layer 20 away from the bottom wall of the isolation trench 33 is a flat surface.

[0143] In the above implementation, the chemical reaction formula of silicon nitride and the phosphoric acid solution is SI3N4 + 6H2O → 3SIO2↓ + 4NH3↑, Similarly, in the above implementation, the same height of part of the initial first insulating layer 36 is removed from each isolation trench 33, and the remaining part of the initial first insulating layer 36 forms the first insulating layer 20, so that the vertical distance from one end of each first insulating layer 20 away from the bottom wall of the isolation trench 33 to the bottom wall of the isolation trench 33 is the same, thereby realizing the alignment of one end of each conductive block 18 away from the second insulating block 19 in the second direction Y.

[0144] Please refer to Figure 18 and Figure 19 In the above embodiments, the formation of the conductive block 18 in the preparation method provided by the embodiments of the present application may include: after forming the first insulating layer 20, forming an initial conductive block 37, and removing part of the initial conductive block 37 to form the conductive block 18, so that the first insulating layer 20 and the conductive block 18 are in contact along the second direction; and making the initial isolation layer 35 located between the conductive block 18 and the semiconductor pillar 5.

[0145] In the above implementation manner, the initial conductive block 37 may include titanium nitride (TiN). Forming the initial conductive block 37 above the first insulating layer 20 may include depositing TiN in the isolation trench 33 to form the initial conductive block 37. The initial conductive block 37 fills the isolation trench 33. In the subsequent step of removing a part of the initial conductive block 37, the same height of the part of the initial conductive block 37 in each isolation trench 33 is removed, and the remaining part of the initial conductive block 37 forms the conductive block 18, so that the first insulating layer 20 and the conductive block 18 are in contact with each other in the second direction. The lengths of the plurality of conductive blocks 18 formed in each isolation trench 33 are the same, and in the above embodiment, the plurality of conductive blocks 18 are aligned in the second direction Y; the influence of each conductive block 18 on the coupling effect between the adjacent vertical transistors 4 is the same, improving the stability of the semiconductor structure 1. And the initial isolation layer 35 is located between the conductive block 18 and the semiconductor pillar 5. The initial isolation layer 35 can achieve insulation between the conductive block 18 and the semiconductor pillar 5 in the second direction Y.

[0146] Please refer to Figure 20 and Figure 21 In the above embodiment, forming the second insulating block 19 in the manufacturing method provided by the embodiment of the present application may include: after forming the conductive block 18, forming an initial second insulating block 38, and removing a part of the initial second insulating block 38 to form the second insulating block 19, so that the conductive block 18 is located between the first insulating block 17 and the second insulating block 19.

[0147] In the above implementation manner, the initial second insulating block 38 may include silicon nitride (SiN). Forming the initial second insulating block 38 above the conductive block 18 may include depositing SiN in the isolation trench 33 to form the initial second insulating block 38. The initial second insulating block 38 fills the isolation trench 33 and covers the mask plate 29; in the subsequent step of removing a part of the initial second insulating block 38, a part of the initial second insulating block 38 may be removed by CMP, so that the remaining part of the initial second insulating block 38 forms the second insulating block 19, and the second insulating block 19 is used to achieve insulation of one end of the conductive block 18 away from the first insulating block 17. One end of the second insulating block 19 away from the isolation trench 33 is aligned with the mask plate 29, and the formed first insulating layer 20, conductive block 18, and second insulating block 19 fill the isolation trench 33. The initial isolation layer 35 may also be located between the second insulating block 19 and the semiconductor pillar 5 adjacent to the second insulating block 19 in the second direction.

[0148] Please refer to Figure 22, in some other embodiments, the initial isolation layer 35 is divided into a two-layer structure, and the formation of the initial isolation layer 35 includes forming an initial first isolation layer 39 and forming an initial second isolation layer 40. In the preparation method provided by the embodiments of the present application, after the initial first isolation layer 39 is formed, the initial first isolation layer 39 covers the side walls of the isolation trench 33 extending along the first direction X and covers the bottom wall of the isolation trench 33; then the initial second isolation layer 40 is formed on the initial first isolation layer 39, and the initial second isolation layer 40 covers the side of the initial first isolation layer 39 facing away from the side wall of the isolation trench 33 and covers the side of the initial first isolation layer 39 facing away from the bottom wall of the isolation trench 33. Among them, both the initial first isolation layer 39 and the initial second isolation layer 40 can be made of insulating materials. Exemplarily, the initial first isolation layer 39 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide. The initial second isolation layer 40 can include at least one of silicon nitride (SiN), insulating oxide, and nitrogen oxide.

[0149] In the implementation manner where the initial isolation layer 35 includes the initial first isolation layer 39 and the initial second isolation layer 40, if the material of the initial first insulating layer 20 is an insulating oxide material, then forming the initial first isolation layer 39 includes depositing an oxide layer in the isolation trench 33, and the oxide and the remaining part of the oxide layer on the inner wall of the isolation trench 33 together form the initial first isolation layer 39. The material of the initial first isolation layer 39 is silicon nitride.

[0150] Please refer to Figure 23 and Figure 24 , in combination with the above embodiments, in the preparation method provided by the embodiments of the present application, forming the first insulating layer 20 includes forming an initial first insulating layer 36 above the initial second isolation layer 40 and removing a part of the initial first insulating layer 36 to form the first insulating layer 20, so that the vertical distance from one end of each first insulating layer 20 away from the bottom wall of the isolation trench 33 to the bottom wall of the isolation trench 33 is the same.

[0151] In the above implementation manner, the initial first insulating layer 36 can include an insulating oxide, and forming the initial first insulating layer 36 above the initial isolation layer 35 can include depositing an insulating oxide in the isolation trench 33 to form the initial first insulating layer 36.

[0152] In the above implementation manner, the formed initial first insulating layer 36 almost fills the isolation trench 33. The same height of a part of the initial first insulating layer 36 is removed from each isolation trench 33, and the remaining part of the initial first insulating layer 36 forms the first insulating layer 20, so that the vertical distance from one end of each first insulating layer 20 away from the bottom wall of the isolation trench 33 to the bottom wall of the isolation trench 33 is the same.

[0153] Among them, the initial second isolation layer 40 is located between the initial first isolation layer 39 and the initial first insulating layer 36. Since both the initial first isolation layer 39 and the initial first insulating layer 36 include insulating oxides, during the process of removing a part of the initial first insulating layer 36, the initial second isolation layer 40 including SiN can protect the initial first isolation layer 39, preventing the initial first isolation layer 39 and the part of the initial first insulating layer 36 to be removed from being removed simultaneously, and thus losing the function of insulating the conductive block 18 from the semiconductor column 5 in the second direction Y after the conductive block 18 is formed subsequently.

[0154] Please refer to Figure 25 and Figure 26 In the above implementation manner, in the preparation method provided by the embodiment of the present application, forming the conductive block 18 may include: after forming the first insulating layer 20, forming an initial conductive block 37, and removing a part of the initial conductive block 37 to form the conductive block 18, so that the first insulating layer 20 and the conductive block 18 are in contact with each other in the second direction; and making the initial first isolation layer 39 and the initial second isolation layer 40 be located between the conductive block 18 and the semiconductor column 5, wherein the first isolation layer 24 and the second isolation layer 25 are stacked along the second direction, the first isolation layer 24 is located between the second isolation layer 25 and the semiconductor column 5, and the second isolation layer 25 is located between the first isolation layer 24 and the conductive block 18.

[0155] In the above implementation manner, the initial conductive block 37 may include titanium nitride (TiN). Forming the initial conductive block 37 above the first insulating layer 20 may include depositing TiN in the isolation groove 33 to form the initial conductive block 37. The initial conductive block 37 fills the isolation groove 33. In the subsequent step of removing a part of the initial conductive block 37, the same height of the part of the initial conductive block 37 in each isolation groove 33 is removed, and the remaining part of the initial conductive block 37 forms the conductive block 18, so that the first insulating layer 20 and the conductive block 18 are in contact with each other in the second direction. The lengths of the plurality of conductive blocks 18 formed in each isolation groove 33 are the same, and the plurality of conductive blocks 18 are aligned in the second direction Y; the influence of each conductive block 18 on the coupling effect between the adjacent vertical transistors 4 is the same, improving the stability of the semiconductor structure 1. And making the initial isolation layer 35 be located between the conductive block 18 and the semiconductor column 5. The first isolation layer 24 and the second isolation layer 25 can jointly achieve the insulation between the conductive block 18 and the semiconductor column 5 in the second direction Y.

[0156] Please refer to Figure 27 and Figure 28, in combination with the above embodiments, forming the second insulating block 19 in the manufacturing method provided by the embodiments of the present application may include: after forming the conductive block 18, forming an initial second insulating block 38, and removing a part of the initial second insulating block 38 to form the second insulating block 19, so that the conductive block 18 is located between the first insulating block 17 and the second insulating block 19. After forming the second insulating block 19, the initial first isolation layer 39 and the initial second isolation layer 40 may also be located between the second insulating block 19 and the semiconductor pillar 5, wherein the first isolation layer 24 and the second isolation layer 25 are stacked along the second direction, the first isolation layer 24 is located between the second isolation layer 25 and the semiconductor pillar 5, and the second isolation layer 25 is located between the first isolation layer 24 and the second insulating block 19.

[0157] In the above implementation, the initial second insulating block 38 may include silicon nitride (SiN). Forming the initial second insulating block 38 above the conductive block 18 may include depositing SiN in the isolation groove 33 to form the initial second insulating block 38. The initial second insulating block 38 fills the isolation groove 33 and covers the mask plate 29; in the subsequent step of removing a part of the initial second insulating block 38, a part of the initial second insulating block 38 may be removed by CMP, so that the remaining part of the initial second insulating block 38 forms the second insulating block 19, and the second insulating block 19 is used to insulate the end of the conductive block 18 away from the first insulating block 17. One end of the second insulating block 19 away from the isolation groove 33 is aligned with the mask plate 29, and the formed first insulating layer 20, conductive block 18, and second insulating block 19 fill the isolation groove 33.

[0158] Please refer to Figures 29 to 31 , and compare and refer to Figure 21 , in step S300, after forming the second insulating block 19, the embodiments of the present application further include forming a gate structure 6.

[0159] Before forming the gate structure 6, the manufacturing method provided by the embodiments of the present application further includes removing all the sacrificial materials 34 located in the gate groove 32. Similarly, in the implementation where the sacrificial material 34 includes carbon, the process of removing all the sacrificial materials 34 may include ashing to remove the sacrificial materials 34. During the process of removing all the sacrificial materials 34 in the gate groove 32, a part of the oxide layer on the sidewall of the gate groove 32 will be removed simultaneously, and the remaining part of the oxide layer forms the above-mentioned gate dielectric layer 7. The formed gate dielectric layer 7 includes a part on the sidewall of the gate groove 32 and a part on the bottom wall of the gate groove 32.

[0160] Please refer to Figure 29, forming the gate structure 6 includes forming an initial first gate layer 41 within the gate trench 32, the initial first gate layer 41 covering the sidewalls of the gate trench 32 extending along the first direction X, and covering the bottom wall of the gate trench 32. The initial first gate layer 41 may include at least one of titanium nitride (TiN) and tungsten (W). In the embodiments of the present application, the initial first gate layer 41 includes tungsten.

[0161] Please refer to Figure 29 and Figure 30 , forming the gate structure 6 further includes removing a portion of the initial first gate layer 41 to form an initial second gate layer 42, the initial second gate layer 42 covering the sidewalls of the gate trench 32 extending along the first direction X, and covering the bottom wall of the gate trench 32. In the cross-section of the semiconductor structure 1X-Y, the initial second gate layer 42 forms a structure similar to a "U" shape, and the end of the initial second gate layer 42 away from the bottom wall of the gate trench 32 extends upward in the first direction X beyond the end of the conductive block 18 away from the bottom wall of the isolation trench 33, that is, the vertical distance from the end of the initial second gate layer 42 away from the bottom wall of the gate trench 32 to the bottom wall of the gate trench 32 is greater than the vertical distance from the end of the conductive block 18 away from the bottom wall of the isolation trench 33 to the bottom wall of the isolation trench 33.

[0162] Please refer to Figure 31 , forming the gate structure 6 further includes forming a filling layer 43. The filling layer 43 is located between the portions of the initial second gate layer 42 covering the sidewalls of the gate trench 32 and completely fills the gate trench 32. Exemplarily, the filling layer 43 may include at least one of silicon nitride (SiN), insulating oxide, and oxynitride. In the above embodiments, the filling layer 43 includes an insulating oxide layer.

[0163] Combined with Figure 2 , in some embodiments, after forming the filling layer 43, the manufacturing method provided by the embodiments of the present application may further include forming a storage capacitor 8, where the formed storage capacitor 8 is located on a side of the semiconductor pillar 5 away from the bottom wall of the gate trench 32 or the bottom wall of the isolation trench 33, and the storage capacitor 8 is correspondingly connected to an end of the semiconductor pillar 5 away from the bottom wall of the gate trench 32 or the bottom wall of the isolation trench 33.

[0164] Please refer to Figure 32, in step S400, forming the first insulating block 17 includes: removing a part of the initial isolation layer 35 adjacent to the first insulating layer 20; the part of the initial isolation layer 35 adjacent to the first insulating layer 20 includes the part of the initial isolation layer 35 located between the first insulating layer 20 and the semiconductor pillar 5 in the second direction Y, and the part of the initial isolation layer 35 located between the first insulating layer 20 and the bottom wall of the isolation groove 33. The remaining part of the initial isolation layer 35 forms the final isolation layer 23, and the isolation layer 23 is located between the conductive block 18 and the semiconductor pillar 5 in the second direction Y; meanwhile, the isolation layer 23 is also located between the second insulating block 19 and the semiconductor pillar 5 adjacent to the second insulating block 19 in the second direction Y; so as to achieve insulation between the conductive block 18 and the semiconductor pillar 5 in the second direction Y.

[0165] Continue to refer to Figure 32 , in the implementation manner of removing a part of the initial isolation layer 35 adjacent to the first insulating layer 20, the part of the oxide layer located at the bottom wall of the gate groove 32 and the part of the oxide layer located on the side wall of the gate groove 32 in the gate groove 32 will be removed simultaneously, and the height of the part of the oxide layer removed on the side wall of the gate groove 32 is the same as the height of the part of the initial isolation layer 35 removed between the first insulating layer 20 and the semiconductor pillar 5 in the second direction Y, so as to expose one end of the initial second gate layer 42 close to the bottom wall of the gate groove 32.

[0166] Please refer to Figure 33 , and compare and refer to Figure 32 , in the above implementation manner, after exposing the initial second gate layer 42, it further includes removing a part of the initial second gate layer 42 to form two gate layers 15 spaced apart in the second direction Y. The gate layer 15 and the adjacent semiconductor pillar 5 form a vertical transistor 4. In a semiconductor pillar group 14, the two gate layers 15 are mirror-symmetrically distributed, that is, the formed vertical transistor 4 is an MSG vertical transistor 4. Combining with the conductive block 18 in the isolation structure 16, the conductive block 18 in the isolation structure 16 is located between two adjacent vertical transistors 4; during the conduction process of the vertical transistor 4, the conductive block 18 between the vertical transistors 4 can prevent the electrons in the conducted vertical transistor 4 from easily passing through the conductive block 18 and moving to the adjacent vertical transistor 4, reducing the coupling effect between the adjacent vertical transistors 4, and further reducing the leakage between the adjacent vertical transistors 4.

[0167] In the above implementation, one end of the gate layer 15 close to the bottom wall of the gate groove 32 extends downward in the first direction X beyond one end of the conductive block 18 close to the bottom wall of the isolation groove 33, that is, the vertical distance from one end of the gate layer 15 close to the bottom wall of the gate groove 32 to the bottom wall of the gate groove 32 is less than the vertical distance from one end of the conductive block 18 close to the bottom wall of the isolation groove 33 to the bottom wall of the isolation groove 33. While the conductive block 18 can reduce the coupling effect between adjacent vertical transistors 4, it can avoid one end of the conductive block 18 in the first direction exceeding one end of the adjacent gate layer 15 in the first direction, thereby avoiding the electrons in the conductive block 18 being reversely coupled to the gate layer 15 adjacent to the conductive block 18 when the conductive block 18 is energized, and further affecting the operation of the adjacent vertical transistor 4.

[0168] Please refer to Figure 34 and Figure 35 and compare with Figure 27 In the above embodiment, in combination with the implementation where the initial isolation layer 35 includes the initial first isolation layer 39 and the initial second isolation layer 40, removing a part of the initial isolation layer 35 adjacent to the first insulating layer 20 includes removing a part of the initial first isolation layer 39 corresponding to the position of the first insulating layer 20 along the second direction Y. The remaining initial first isolation layer 39 forms the first isolation layer 24, a part of the initial second isolation layer 40 adjacent to the conductive block 18 and the second insulating block 19 forms the second isolation layer 25, and a part of the initial second isolation layer 40 adjacent to the first insulating layer 20 forms the third insulating layer 26. That is, the third insulating layer 26 and the second isolation layer 25 are formed simultaneously in the same step, and the third insulating layer 26 and the second isolation layer 25 can be an integral structure. The above first isolation layer 24 and second isolation layer 25 are stacked along the second direction Y. The first isolation layer 24 is located between the second isolation layer 25 and the semiconductor column 5, and the second isolation layer 25 is located between the first isolation layer 24 and the conductive block 18. The first isolation layer 24 and the second isolation layer 25 together form the isolation layer 23. At the same time, the isolation layer 23 formed by the first isolation layer 24 and the second isolation layer 25 together is also located between the second insulating block 19 and the semiconductor column 5 adjacent to the second insulating block 19 in the second direction Y; the first isolation layer 24 and the second isolation layer 25 can jointly achieve insulation between the conductive block 18 and the semiconductor column 5 in the second direction Y.

[0169] Continue to refer to Figure 34, in the implementation of removing a part of the initial first isolation layer 39 corresponding to the position of the first insulating layer 20 in the second direction Y, a part of the oxide layer located at the bottom wall of the gate trench 32 and a part of the oxide layer located at the side wall of the gate trench 32 in the gate trench 32 will be removed simultaneously, wherein the height of the part of the oxide layer removed from the side wall of the gate trench 32 is the same as the height of the part of the initial isolation layer 35 between the first insulating layer 20 and the semiconductor pillar 5 in the second direction Y, so as to expose one end of the part of the initial second gate layer 42 close to the bottom wall of the gate trench 32.

[0170] Please refer to Figure 35 , and compare with reference to Figure 34 In the above implementation, after exposing the part of the initial second gate layer 42, it further includes removing the part of the initial second gate layer 42 to form two gate layers 15 arranged at intervals in the second direction Y. The gate layer 15 and the adjacent semiconductor pillar 5 form a vertical transistor 4. In a semiconductor pillar group 14, the two gate layers 15 are symmetrically distributed in a mirror image, that is, the formed vertical transistor 4 is an MSG vertical transistor 4. Combining with the conductive block 18 in the isolation structure 16, the conductive block 18 in the isolation structure 16 is located between two adjacent vertical transistors 4; during the conduction process of the vertical transistor 4, the conductive block 18 between the vertical transistors 4 can prevent the electrons in the turned-on vertical transistor 4 from easily passing through the conductive block 18 and moving to the adjacent vertical transistor 4, reducing the coupling effect between the adjacent vertical transistors 4, and further reducing the leakage between the adjacent vertical transistors 4.

[0171] Please refer to Figure 36 , and compare with reference to Figure 33 In the above embodiment, in the implementation where the initial isolation layer 35 is a single-layer structure, forming the first insulating block 17 further includes removing a part of the initial isolation layer 35 adjacent to the first insulating layer 20 to expose the side wall of a part of the semiconductor pillar 5 on the side of the conductive block 18 close to the bottom wall of the isolation trench 33 at the bottom wall of the isolation trench 33, and forming a second insulating layer 21 at the position of the removed part of the initial isolation layer 35.

[0172] In the above embodiment, the second insulating layer 21 may include silicon nitride. During the formation of the second insulating layer 21, the silicon nitride can simultaneously cover one end of the gate layer 15 exposed in the gate trench 32. Exemplarily, the silicon nitride can fill the gate trench 32 to achieve insulation between the gate layer 15 and the semiconductor pillar 5.

[0173] Please refer to Figure 37 , and compare with reference to Figure 35, in an implementation where the initial isolation layer 35 includes an initial first isolation layer 39 and an initial second isolation layer 40, forming the first insulating block 17 further includes removing a part of the initial first isolation layer 39 corresponding to the first insulating layer 20 in the second direction Y to expose the bottom wall of the isolation groove 33 and the side wall of a part of the semiconductor pillar 5 located on the side of the conductive block 18 close to the bottom wall of the isolation groove 33. A fourth insulating layer 27 is formed at the position of the removed part of the initial first isolation layer 39. The third insulating layer 26 and the fourth insulating layer 27 form the second insulating layer 21. The second insulating layer 21 and the first insulating layer 20 form the first insulating block 17.

[0174] In the above embodiment, the fourth insulating layer 27 may include silicon nitride. During the formation of the fourth insulating layer 27, the silicon nitride may simultaneously cover one end of the gate layer 15 exposed in the gate groove 32. Exemplarily, the silicon nitride may fill the gate groove 32 to achieve insulation between the gate layer 15 and the semiconductor pillar 5.

[0175] With reference to Figure 2 , in some embodiments, after forming the second insulating block 19, forming a plurality of bit lines 9 is further included. Among them, in an implementation where the semiconductor structure 1 includes a storage capacitor 8, forming a plurality of bit lines 9 includes forming a plurality of bit lines 9 on the side of the semiconductor layer 28 facing away from the storage capacitor 8. The bit lines 9 extend in the second direction Y. The plurality of bit lines 9 are spaced apart in the third direction Z. The plurality of semiconductor pillars 5 spaced apart in the second direction Y are connected to the same bit line 9. The plurality of semiconductor pillars 5 spaced apart in the third direction Z are respectively connected to different bit lines 9. After forming the bit lines 9, a wiring layer 10 is formed on the side of the bit lines 9 facing away from the semiconductor layer 28. The wiring layer 10 is used to connect to the peripheral circuit layer 11.

[0176] Please refer to Figure 38 , in step S300, after forming the second insulating block 19, removing a part of the second insulating block 19 to form a first conductive hole 45 extending in the first direction X is further included.

[0177] Continuing to refer to Figure 38 , after forming the conductive block 18, the conductive block 18 extends in the third direction Z. The plurality of conductive blocks 18 are spaced apart in the second direction Y, while the plurality of bit lines 9 are spaced apart in the third direction Z.

[0178] Please refer to Figure 38 and Figure 39, after forming the first conductive via 45, a first conductive pillar 22 is formed in the first conductive via 45, and the first conductive pillar 22 is connected to the conductive block 18 to form the isolation structure 16. The connection between the first conductive pillar 22 and the conductive block 18 is used to lead out the conductive block 18 to realize the grounding of the conductive block 18 or the connection of negative pressure. Furthermore, electrons in the vertically-conducted transistor 4 are not likely to pass through the conductive block 18 and move to adjacent vertically-conducted transistors 4, reducing the coupling effect between adjacent vertically-conducted transistors 4 and minimizing the leakage between adjacent vertically-conducted transistors 4. In the above implementation, a plurality of conductive blocks 18 are arranged at intervals in the second direction Y, and each conductive block 18 is correspondingly connected to a first conductive pillar 22. The first conductive pillar 22 is located at the edge of the semiconductor layer 28 to facilitate wiring in the semiconductor structure 1.

[0179] In the above embodiment, since the first conductive via 45 penetrates through part of the second insulating block 19, the first conductive pillar 22 formed in the first conductive via 45 is located on the side of the conductive block 18 away from the bit line 9. In the process of connecting the conductive block 18 through the first conductive pillar 22 to lead out the conductive block 18, the process of forming the first conductive pillar 22 does not need to consider the relationship with the bit line 9 (that is, the first conductive pillar 22 can be completed in the front end of line (FEOL), avoiding forming the first conductive pillar 22 in the backend of line (BEOL) to lead out the conductive block 18), thereby reducing the process difficulty of forming the semiconductor structure 1.

[0180] In the implementation of step S400, after forming the second insulating block 19, it further includes forming a second conductive via 46 extending along the first direction X.

[0181] Please refer to Figure 40 , after forming the gate layer 15, the gate layer 15 extends in the third direction Z, and two gate layers 15 belonging to the same gate structure 6 are connected at the edge of the semiconductor layer 28. Before forming the second conductive via 46 in the above implementation, the embodiment of the present application may further include forming a first gate notch 47 at one end of the gate layer 15 close to the edge of the semiconductor layer 28, and forming a second gate notch 48 at the other end of the gate layer 15 close to the edge of the semiconductor layer 28, so that two gate layers 15 belonging to the same gate structure 6 are not connected to each other. Among them, the first gate notch 47 and the second gate notch 48 are respectively located on the gate layers 15 on both sides of the gate structure 6. For example, if the first gate notch 47 is located on the first gate layer 15 along the second direction Y, then the second gate notch 48 is located on the second gate layer 15 in the second direction Y, and vice versa.

[0182] Please refer to Figure 40 and Figure 41, in the above implementation, forming the second conductive via 46 includes forming the second conductive via 46 at one end of the gate layer 15 located at the edge of the semiconductor layer 28, and forming another second conductive via 46 at the other end of the gate layer 15 located at the edge of the semiconductor layer 28. The second conductive via 46 penetrates through a part of the filling layer 43, and one end of the second conductive via 46 extends into the semiconductor layer 28 to the side of the gate layer 15 close to the second insulating block 19.

[0183] Please refer to Figure 41 and Figure 42 , after forming the second conductive via 46, a second conductive pillar 49 is formed in the second conductive via 46 to connect the second conductive pillar 49 to the gate layer 15. The gate layer 15 is led out for leading out the word line. Among them, one end of the second conductive pillar 49 extends into the semiconductor layer 28 to the gate layer 15 and contacts the gate layer 15. In the above implementation, the two second conductive pillars 49 for connecting the same gate structure 6 are respectively located at both ends of the gate structure 6 along the third direction Z. Combining with the implementation in which the gate structure 6 includes the first gate notch 47 and the second gate notch 48, since the first gate notch 47 and the second gate notch 48 are respectively located at both ends of the gate layer 15 close to the edge of the semiconductor layer 28, the space for connecting the end of the gate layer 15 in the third direction Z to the second conductive pillar 49 is increased, improving the process window; at the same time, since the first gate notch 47 and the second gate notch 48 are respectively located on the gate layers 15 on both sides of the gate structure 6, the problem that two gate layers 15 belonging to the same gate structure 6 are connected to the same second conductive pillar 49 is avoided.

[0184] In the above embodiment, since the second conductive via 46 penetrates through a part of the second insulating block 19, the second conductive pillar 49 formed in the second conductive via 46 is located on the side of the conductive block 18 away from the bit line 9. In the process of connecting the gate layer 15 through the second conductive pillar 49 to lead out the gate layer 15 to form the word line, the process of forming the second conductive pillar 49 does not need to consider the relationship with the bit line 9 (that is, the second conductive pillar 49 can be completed in the front end of line (FEOL), avoiding forming the second conductive pillar 49 in the back end of line (BEOL) to lead out the gate layer 15), thereby reducing the process difficulty of forming the semiconductor structure 1.

[0185] Please refer to Figure 43 and Figure 44, some embodiments of the present application further provide a storage system 1000. The storage system 1000 includes a controller 50 and a 3D memory 51. The 3D memory 51 may include the semiconductor structure 1 as described above. The controller 50 is coupled to the 3D memory 51 to control the 3D memory 51 to store data. The term "3D memory 51" refers to a semiconductor device formed by transistors (referred to as "vertical transistors 4" herein, such as DRAM vertical transistors 4) that are arranged in an array on the main surface of a substrate and extend along a direction perpendicular to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the substrate (i.e., the lateral surface).

[0186] Among them, the storage system 1000 can be integrated into various types of storage devices. For example, it can be included in the same package (such as a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is to say, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, Virtual Reality (VR) devices, Augmented Reality (AR) devices, or any other suitable electronic devices with a memory.

[0187] In some embodiments, referring to Figure 43 , the storage system 1000 includes a controller 50 and a 3D memory 51, and the storage system 1000 can be integrated into a memory card.

[0188] Among them, the memory card includes any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD) card, and a UFS.

[0189] In other embodiments, referring to Figure 44 , the storage system 1000 includes a controller 50 and multiple 3D memories 51, and the storage system 1000 is integrated into a Solid State Drive (SSD).

[0190] In the storage system 1000, in some embodiments, the controller 50 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0191] In other embodiments, the controller 50 is configured to operate in a high duty cycle environment such as an SSD or an eMMC, which are used as data storage for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0192] In some embodiments, the controller 50 may be configured to manage data stored in the 3D memory 51 and communicate with external devices (such as a host). In some embodiments, the controller 50 may also be configured to control the operations of the 3D memory 51, such as read, erase, and program operations. In some embodiments, the controller 50 may also be configured to manage various functions regarding the data stored in or to be stored in the 3D memory 51, including at least one of bad block management, garbage collection, logical to physical address translation, and wear leveling. In some embodiments, the controller 50, 20 is also configured to process error correction codes for data read from or written to the 3D memory 51.

[0193] Of course, the controller 50 may also perform any other suitable functions, such as formatting the 3D memory 51; for example, the controller 50 may communicate with external devices (such as a host) through at least one of various interface protocols.

[0194] It should be noted that the interface protocols include at least one of the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, and the Firewire protocol.

[0195] Some embodiments of the present application also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0196] The electronic device may include a host and the storage system 1000 described above, wherein the host and the storage system 1000 are coupled and may further include at least one of a central processing unit (CPU) and a cache, etc.

[0197] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A plurality of semiconductor pillars, the semiconductor pillars extending in a first direction, and the plurality of semiconductor pillars being spaced apart in a second direction, wherein the second direction is perpendicular to the first direction; A gate structure and an isolation structure, the gate structure and the isolation structure being alternately spaced apart in the second direction, the gate structure being located between two adjacent semiconductor pillars, and the isolation structure also being located between two adjacent semiconductor pillars; The isolation structure includes: a first insulating block, a conductive block, and a second insulating block. Along the first direction, the conductive block is located between the first insulating block and the second insulating block. The first insulating block includes a first insulating layer and a second insulating layer, and the first insulating layer is located on a side of the conductive block away from the second insulating block; In the first direction, the first insulating layer is in contact with the conductive block; in the second direction, the second insulating layer is located between the first insulating layer and the semiconductor pillar.

2. The semiconductor structure according to claim 1, wherein The material of the first insulating layer includes silicon nitride or an insulating oxide material, and the material of the second insulating layer includes silicon nitride or an insulating oxide material.

3. The semiconductor structure according to claim 1, wherein The second insulating layer includes a third insulating layer and a fourth insulating layer. The third insulating layer is located on a side of the first insulating layer away from the second insulating block and on both sides of the first insulating layer in the second direction; the fourth insulating layer is located on a side of the third insulating layer away from the second insulating block and on both sides of the third insulating layer in the second direction.

4. The semiconductor structure according to claim 1, wherein, The lengths of the plurality of conductive blocks in the first direction are equal, and one end of each conductive block away from the second insulating block is aligned in the second direction.

5. The semiconductor structure according to claim 1, characterized in that, The isolation structure further includes an isolation layer, and the isolation layer is also located between the conductive block and the semiconductor pillar.

6. The semiconductor structure according to claim 5, wherein The isolation layer includes a first isolation layer and a second isolation layer stacked in the second direction. The first isolation layer is located between the second isolation layer and the semiconductor pillar, and the second isolation layer is located between the first isolation layer and the conductive block.

7. The semiconductor structure according to claim 6, wherein One side of the first isolation layer close to the semiconductor pillar is in contact with the semiconductor pillar, one side of the first isolation layer away from the semiconductor pillar is in contact with the second isolation layer, and one side of the second isolation layer away from the first isolation layer is in contact with the conductive block.

8. The semiconductor structure according to claim 1, wherein The isolation structure further includes a first conductive pillar, and the first conductive pillar passes through a part of the second insulating block and is in contact with the conductive block.

9. A method for preparing a semiconductor structure, characterized in that, Comprising: Forming a plurality of semiconductor pillars, the semiconductor pillars extending in a first direction, and the plurality of semiconductor pillars being spaced apart in a second direction to form gate trenches and isolation trenches alternately spaced apart in the second direction, wherein the second direction is perpendicular to the first direction; Forming a gate structure in the gate trench and forming an isolation structure in the isolation trench, so that the gate structure and the isolation structure are alternately spaced apart in the second direction; Forming the isolation structure includes: forming a first insulating block, a conductive block, and a second insulating block along the first direction, so that the conductive block is located between the first insulating block and the second insulating block; Forming the first insulating block includes: forming a first insulating layer and a second insulating layer, with the first insulating layer located on a side of the conductive block away from the second insulating block and in contact with the conductive block in a first direction; and the second insulating layer is located between the first insulating layer and the semiconductor column in a second direction.

10. The manufacturing method of the semiconductor structure according to claim 9, characterized in that, Before forming the isolation structure, it further includes: Forming an initial isolation layer in the isolation groove, the initial isolation layer covering the side walls of the isolation groove extending in the first direction and covering the bottom wall of the isolation groove; Sequentially forming the first insulating layer, the conductive block, and the second insulating block in the isolation groove, with the conductive block located between the first insulating layer and the second insulating block; Forming the first insulating layer includes: forming an initial first insulating layer above the initial isolation layer and removing part of the initial first insulating layer to form the first insulating layer, such that the vertical distance from one end of each first insulating layer away from the bottom wall of the isolation groove to the bottom wall of the isolation groove is the same.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein, Forming the first insulating layer includes: Removing part of the initial isolation layer adjacent to the first insulating layer, and the remaining initial isolation layer forms the isolation layer; Forming the second insulating layer at the position of the removed part of the initial isolation layer.

12. The method for manufacturing a semiconductor structure according to claim 10, wherein, Forming the conductive block includes: After forming the first insulating layer, forming an initial conductive block and removing part of the initial conductive block to form the conductive block, such that the first insulating layer and the conductive block are in contact with each other in the second direction; and the initial isolation layer is located between the conductive block and the semiconductor column.

13. The method for manufacturing a semiconductor structure according to claim 10, wherein, Forming the initial isolation layer includes: forming an initial first isolation layer and forming an initial second isolation layer; The remaining initial isolation layer forms the isolation layer includes: after removing part of the initial isolation layer adjacent to the first insulating layer, the remaining initial first isolation layer forms the first isolation layer, and the remaining initial second isolation layer forms the second isolation layer, and the first isolation layer and the second isolation layer form the isolation layer.

14. The method for manufacturing a semiconductor structure according to claim 7, wherein After forming the second insulating block, it further includes: Removing part of the second insulating block to form a first conductive hole extending in the first direction, with one end of the first conductive hole located on a side of the conductive block away from the first insulating layer; Forming a first conductive column in the first conductive hole, such that the first conductive column is connected to the conductive block to form the isolation structure.

15. A storage system, characterized in that, It includes: A three-dimensional memory, the three-dimensional memory being a semiconductor structure as described in any one of claims 1-8; A controller, the controller being coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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