Semiconductor device and method for manufacturing the same

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, relating to the field of semiconductor technology, and is intended to solve the reliability problem of trench-type semiconductor devices. The semiconductor device includes a collector region, a drift region, an emitter region, a gate dielectric layer, a gate region, and a first shielding portion, wherein the drift region is arranged above the collector region, a first groove is provided on the surface of the drift region away from the collector region, the emitter region is arranged on the side of the drift region away from the collector region, the gate dielectric layer is arranged on the bottom surface and sidewall surface of the first groove, the gate region is arranged in the first groove and is covered by the gate dielectric layer, the first shielding portion is arranged at the bottom of the first groove and contacts the gate dielectric layer, wherein the drift region includes a first sub-drift region and a second sub-drift region arranged in a stacked manner, the second sub-drift region is located on the side of the first sub-drift region away from the collector region, the first sub-drift region and the second sub-drift region have different doping types, and the first shielding portion contacts the second sub-drift region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Insulated-gate bipolar transistors (IGBTs), a composite power semiconductor device that combines the high input impedance of MOSFETs with the low on-state voltage drop of bipolar transistors, are widely used in power electronics systems such as renewable energy power converters, electric vehicle drive modules, and industrial motor controllers. As power systems continue to demand higher efficiency and higher power density, optimizing the performance of IGBT devices has become a hot topic in industry research.

[0003] Traditional planar-gate IGBTs form a conductive channel by laterally laying out the gate region. However, due to the limited mobility of the surface channel and the circuitous current path beneath the gate region, there is a significant trade-off between on-resistance and blocking voltage. Furthermore, the tail current generated between the collector and emitter regions during the turn-off process leads to high turn-off losses, limiting the increase in switching frequency.

[0004] To overcome this bottleneck, the industry has proposed a trench gate structure, which replaces the planar gate region with a vertically etched trench, allowing the channel to run perpendicular to the chip surface. This vertical conduction mode shortens the carrier path, reduces on-resistance, and increases cell density. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, aiming to solve the reliability problem of trench-type semiconductor devices.

[0006] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0007] On the one hand, a semiconductor device is provided, comprising a collector region, a drift region, an emitter region, a gate dielectric layer, a gate region, and a first shielding portion. The drift region is provided above the collector region, and a first groove is provided on the surface of the drift region away from the collector region. The emitter region is provided on the side of the drift region away from the collector region. The gate dielectric layer is provided on the bottom surface and sidewall surface of the first groove. The gate region is provided in the first groove and is covered by the gate dielectric layer. The first shielding portion is provided at the bottom of the first groove and is in contact with the gate dielectric layer. The drift region comprises a first sub-drift region and a second sub-drift region arranged in a stacked manner, the second sub-drift region being located on the side of the first sub-drift region away from the collector region, and the first sub-drift region and the second sub-drift region have different doping types. The first shielding portion is in contact with the second sub-drift region.

[0008] If the semiconductor device operates in a withstand voltage state, the gate region channel is closed, and the collector region and emitter region are subjected to a blocking voltage, the first shielding portion can reduce the electric field experienced by the gate dielectric layer, thereby protecting the gate dielectric layer. Furthermore, the PN junction formed by the second sub-drift region and the first sub-drift region is in a reverse biased state, bearing part of the electric field. This can further reduce the electric field experienced by the gate dielectric layer, making the electric field distribution more uniform, which is beneficial for increasing the breakdown voltage of the semiconductor device, thereby improving the life expectancy and reliability of the semiconductor device. This improved electric field distribution can also make the temperature distribution more uniform, preventing local overheating of the semiconductor device and further improving the life expectancy and reliability of the semiconductor device.

[0009] In some feasible embodiments, the semiconductor device further includes a second groove, an emitter region dielectric layer, an emitter region conductor, and a second shielding portion. The second groove is provided on a surface of the drift region away from the collector region, with the second groove and the first groove being located on either side of the emitter region, respectively. The emitter region dielectric layer is provided on the bottom surface and sidewall surfaces of the second groove. The emitter region conductor is provided within the second groove and is covered by the emitter region dielectric layer. The second shielding portion is provided at the bottom of the second groove and in contact with the emitter region dielectric layer. The second shielding portion also contacts the second sub-drift region.

[0010] If the semiconductor device operates in a withstand voltage state, with the gate region channel closed and a blocking voltage applied between the collector region and the emitter region, the second shielding portion can reduce the electric field experienced by the emitter region's dielectric layer, thereby protecting the emitter region's dielectric layer. Furthermore, the PN junction formed by the second sub-drift region and the first sub-drift region is in a reverse-biased state, bearing part of the electric field. This further reduces the electric field experienced by the emitter region's dielectric layer, making the electric field distribution more uniform and facilitating an increase in the breakdown voltage of the semiconductor device, thereby improving the expected lifespan and reliability of the semiconductor device.

[0011] In some feasible embodiments, the first shielding portion and the second sub-drift region have the same doping type, and the doping concentration of the first shielding portion is greater than the doping concentration of the second sub-drift region.

[0012] In some feasible embodiments, the semiconductor device further includes a carrier storage layer. The carrier storage layer is located between the emitter region and the second drift sub-region, and between the first groove and the second groove. The carrier storage layer is in contact with the gate dielectric layer and the emitter region dielectric layer, respectively. The carrier storage layer and the second drift sub-region have different doping types.

[0013] If the semiconductor device is in the on state, the holes injected from the collector region are partially blocked by the carrier storage layer when diffusing in the drift region, forming local hole accumulation, significantly increasing the carrier concentration in the drift region, thereby reducing the on-resistance of the semiconductor device.

[0014] In some feasible embodiments, along a first direction, the first shielding portion and the second shielding portion do not contact each other. The first direction is an arrangement direction of the first groove and the second groove.

[0015] In some feasible embodiments, the first shielding portion includes a carrier storage layer, the carrier storage layer extending from the bottom of the first groove to the second shielding portion and contacting the second shielding portion. The carrier storage layer and the second sub-drift region have different doping types.

[0016] Using the carrier storage layer as the first shield eliminates the need to consider the spacing between the first and second shields, reducing the cell width of the semiconductor device. Furthermore, during the turn-on process of the semiconductor device, holes are less likely to accumulate at the bottom of the gate region, effectively preventing negative capacitance in the gate region and improving the gate control capability of the semiconductor device.

[0017] The carrier storage layer serving as the first shielding portion surrounds the gate dielectric layer and the gate region. During the turn-on process of the semiconductor device, due to the blocking of the first shielding portion, the holes injected from the emitter region are not easily gathered around the gate dielectric layer, which can reduce the influence of the hole injection on the gate region current of the semiconductor device during the turn-on process and improve the gate region control capability of the semiconductor device.

[0018] In some feasible embodiments, the carrier storage layer is also in contact with the emitter region dielectric layer.

[0019] In some feasible embodiments, the second shielding portion and the second sub-drift region have the same doping type, and the doping concentration of the second shielding portion is greater than the doping concentration of the second sub-drift region.

[0020] In some feasible embodiments, the bottom of the gate dielectric layer extends into the first shielding portion, and the first shielding portion contacts a portion of the side surface of the gate dielectric layer; and / or the bottom of the emitter region dielectric layer extends into the second shielding portion, and the second shielding portion contacts a portion of the side surface of the emitter region dielectric layer.

[0021] In some feasible embodiments, the size of the gate region in the thickness direction of the second sub-drift region is smaller than the size of the emitter region conductor in the thickness direction of the second sub-drift region; or, the size of the gate region in the thickness direction of the second sub-drift region is equal to the size of the emitter region conductor in the thickness direction of the second sub-drift region.

[0022] The dimensions of the gate region in the thickness direction of the second drift sub-region are smaller than the dimensions of the emitter region conductor in the thickness direction of the second drift sub-region, and a carrier storage layer is used as the first shielding portion at the bottom of the first groove. During the turn-on process of the semiconductor device, holes injected into the collector region flow to an area with a lower potential. For holes, the first shielding portion, including the carrier storage layer, presents a certain potential barrier height, while the second shielding portion does not. Therefore, holes are more likely to gather in the second shielding portion and are less likely to pass through the first shielding portion, which has a certain potential barrier and is farther away. This reduces the impact of holes on the gate region capacitance and improves the gate control capability of the semiconductor device.

[0023] In some feasible embodiments, the semiconductor device further includes a first well region, the first well region being located between the emitter region and the carrier storage layer and between the first groove and the second groove, the first well region being in contact with the gate dielectric layer and the emitter dielectric layer, respectively.

[0024] If the semiconductor device operates in a withstand voltage state, the gate region channel is closed, and the collector region and the emitter region are subjected to a blocking voltage, the first shielding portion and / or the second shielding portion can assist in the depletion of the carrier storage layer to reduce the electric field between the first well region and the carrier storage layer, thereby reducing the electric field borne by the gate dielectric layer and / or the emitter region dielectric layer, which is beneficial to improving the breakdown voltage of the semiconductor device, thereby improving the expected life and reliability of the semiconductor device.

[0025] When the semiconductor device operates in the forward conduction state, the gate region channel is open, and a positive voltage is applied between the collector region and the emitter region, the channel opens, forming an electron inversion layer on the surface of the first well region. The second sub-emitter region is connected to the carrier storage layer through the electron inversion layer on the surface of the first well region. A P-type collector region, an N-type buffer layer, an N-type first sub-drift region, a P-type second sub-drift region, and an N-type carrier storage layer form a PNPN thyristor, which gradually turns on as the collector region current increases. When the PNPN thyristor is fully turned on, a large number of free carriers are present in the first sub-drift region, the second sub-drift region, and the second well region, and the PN junction formed by the well region and the carrier storage layer is reverse biased.

[0026] When the semiconductor device switches from the on state to the withstand voltage state, i.e., turns off, the gate region channel switches from open to closed, and the voltage between the collector region and the emitter region gradually increases. As the channel gradually turns off, the depletion region of the semiconductor device gradually expands. The depletion region, formed by the PN junction of the first well region and the carrier storage layer, gradually expands toward the second sub-drift region. The presence of the second sub-drift region makes the electric field there very small, allowing holes in the second sub-drift region to be extracted at a lower voltage, accelerating hole extraction during shutdown and improving shutdown speed, thereby reducing the turn-off loss of the semiconductor device and improving semiconductor device reliability.

[0027] In addition, when preparing the first well region and the carrier storage layer, the two can use the same mask (such as a photoresist), which is beneficial for saving process steps and reducing production costs.

[0028] In some feasible embodiments, the semiconductor device further includes a second well region, which is disposed on a side of the second drift sub-region away from the collector region and is located on both sides of the second groove together with the first well region.

[0029] In some feasible embodiments, the emission area includes a first sub-emission area and a second sub-emission area, and the first sub-emission area and the second sub-emission area are arranged along a first direction, which is the arrangement direction of the first groove and the second groove; the first sub-emission area and the second sub-emission area have different doping types.

[0030] In some feasible embodiments, the semiconductor device further comprises a first metal layer, a second metal layer, and an isolation dielectric layer. The first metal layer is located on a side of the collector region away from the drift region. The second metal layer is located on a side of the drift region away from the collector region and is in ohmic contact with the emitter region and the emitter region conductor, respectively. The isolation dielectric layer is located between the second metal layer and the second well region, and between the second metal layer and the gate region.

[0031] On the other hand, a method for preparing a semiconductor device is provided, comprising: sequentially forming a collector region, a first sub-drift region and a second sub-drift region in a stacked arrangement, the first sub-drift region and the second sub-drift region having different doping types: forming an emitter region on a side of the second sub-drift region away from the collector region; etching the second sub-drift region to form a first groove; forming a first shielding portion at the bottom of the first groove; forming a gate dielectric layer on the bottom surface and sidewall surface of the first groove, and forming a gate region in the first groove; the gate dielectric layer wraps the gate region.

[0032] It can be understood that the beneficial effects achieved by the method for preparing the semiconductor device provided by the above embodiment of the present disclosure can be referred to the beneficial effects of the semiconductor device described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure.

[0034] Figure 1 A structural diagram of an electronic device provided according to some embodiments;

[0035] Figure 2 A structural diagram of a chip provided according to some embodiments;

[0036] Figure 3 A structural diagram of a semiconductor device provided according to some embodiments;

[0037] Figure 4 is a structural diagram of another semiconductor device provided according to some embodiments;

[0038] Figure 5 is a structural diagram of another semiconductor device provided according to some embodiments;

[0039] Figure 6 is a structural diagram of another semiconductor device provided according to some embodiments;

[0040] Figure 7 is a structural diagram of another semiconductor device provided according to some embodiments;

[0041] Figure 8 A flow chart of a method for manufacturing a semiconductor device according to some embodiments;

[0042] Figure 9 A flow chart of another method for manufacturing a semiconductor device according to some embodiments;

[0043] Figure 10 A flow chart of another method for manufacturing a semiconductor device according to some embodiments;

[0044] Figures 11-20 for Figure 10 Diagram of the semiconductor structure at each step in the fabrication method. DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0046] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0047] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0048] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0049] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0050] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0051] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0052] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0053] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0054] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes “on something” with intervening features or layers, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something with no intervening features or layers (i.e., directly on something).

[0055] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0056] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art. In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, "at least one of a, b, or c" can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or plural. In addition, in the embodiments of this application, words such as "first" and "second" do not limit quantity or order.

[0058] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0059] Figure 1 FIG. 1 is a structural diagram of an electronic device provided according to some embodiments. Figure 1 As shown, an embodiment of the present disclosure provides an electronic device 1000. The electronic device 1000 can be a product or component with a power conversion function, such as a power conversion system for an electric vehicle, a charging device for a mobile phone, or a power adapter for a laptop computer. The electronic device 1000 can also be different types of user equipment or terminal devices, such as a laptop computer, a tablet computer, a mobile phone, a wearable device, and an in-vehicle device. It can also be a power amplification device used in the above electronic devices. It should be understood that the electronic device 1000 can also be a device or component with a signal receiving / transmitting function in a device such as an amplifier, a modulator, a base station, or a radar. The embodiments of the present application do not place any special restrictions on the specific form of the above electronic device 1000.

[0060] The following uses the electronic device 1000 as an example of an electronic device having a power conversion function to schematically illustrate some embodiments of the present disclosure. However, the implementation of the present disclosure is not limited to this, and any other display device can also be considered as long as the same technical concept is applied.

[0061] exist Figure 1 In the embodiment, the electronic device 1000 includes a chip 1001 and a circuit board 1002, wherein the chip 1001 is coupled to the circuit board 1002, and the circuit board 1002 is configured to supply power to the chip 1001 and transmit signals. Figure 2 , Figure 2 FIG1 is a structural diagram of a chip according to some embodiments. The chip 1001 includes a semiconductor device 100 and a package substrate 200 , and the semiconductor device 100 is coupled to the package substrate 200 .

[0062] Figure 3FIG1 is a structural diagram of a semiconductor device according to some embodiments. Semiconductor device 100 can be a semiconductor device made of silicon, silicon carbide, gallium nitride, or the like. Semiconductor device 100 includes a collector region 101, a buffer layer 102, a drift region 103, an emitter region 107, a gate region 302, and a gate dielectric layer 303. Exemplarily, the buffer layer 102 is located on one side of the collector region 101. The drift region 103 is located on the side of the buffer layer 102 away from the collector region 101. At least one first recess 401 is provided on the surface of the drift region 103 away from the emitter region 107. The emitter region 107 is located on the side of the drift region 103 away from the collector region 101, and the projection of the emitter region 107 on a first reference plane overlaps with the projection of the collector region 101 on the first reference plane. The first reference plane is parallel to the thickness direction z of the drift region 103. Exemplarily, the collector region 101 is doped P-type, and the buffer layer 102 and the drift region 103 are doped N-type.

[0063] The gate dielectric layer 303 is disposed on the bottom surface and sidewall surfaces of the first groove 401 . The gate region 302 is disposed in the first groove 401 and is covered by the gate dielectric layer 303 .

[0064] In some feasible embodiments, the emitter region 107 includes a first sub-emitter region 107a and a second sub-emitter region 107b having different doping types. The first sub-emitter region 107a and the second sub-emitter region 107b are arranged along the first direction x, and the first sub-emitter region 107a is farther away from the gate region 302 than the second sub-emitter region 107b. Exemplarily, the doping type of the first sub-emitter region 107a is P-type, and the doping type of the second sub-emitter region 107b is N-type.

[0065] exist Figure 3 In the embodiment, the semiconductor device 100 includes two gate regions 302 as an example. The two gate regions 302 are arranged along the first direction x, and the two gate regions 302 include the second sub-emitting region 107b, the first sub-emitting region 107a and the second sub-emitting region 107b arranged in sequence along the first direction x. Figure 3 The figure shows that the semiconductor device 100 includes two gate regions 302. In the first direction x, the first sub-emitter region 107a, the second sub-emitter region 107b, the gate region 302, the second sub-emitter region 107b, the first sub-emitter region 107a, the second sub-emitter region 107b, the gate region 302, the second sub-emitter region 107b, and the first sub-emitter region 107a are arranged in sequence.

[0066] In some feasible embodiments, the semiconductor device 100 further includes a well region 106, a first metal layer 301, an isolation dielectric layer 304, and a second metal layer 305. The first metal layer 301 is located on a side of the collector region 101 away from the buffer layer 102. The second metal layer 305 is located on a side of the drift region 103 away from the collector region 101 and is in ohmic contact with the emitter region 107. The isolation dielectric layer 304 is located on a side of the gate region 302 away from the collector region 101, that is, between the gate region 302 and the second metal layer 305, to electrically isolate the gate region 302 from the second metal layer 305.

[0067] Exemplarily, the material of the gate dielectric layer 303 and / or the isolation dielectric layer 304 includes any one or a combination of silicon oxide (SiO2), hafnium oxide (HfO2), aluminum oxide (Al2O3), and silicon nitride (Si3N4). The material of the gate dielectric layer 303 may be the same as or different from that of the isolation dielectric layer 304. If the material of the gate dielectric layer 303 is the same as that of the isolation dielectric layer 304, the gate dielectric layer 303 and the isolation dielectric layer 304 may be considered as a whole.

[0068] The well region 106 is located between the drift region 103 and the emitter region 107. Exemplarily, the doping type of the well region 106 is P-type, and the doping concentration of the well region 106 is less than the doping concentration of the first sub-emitter region 107a.

[0069] Figure 4 This is a structural diagram of another semiconductor device according to some embodiments. For example, a semiconductor device 100 comprising silicon carbide material is used for illustration. The semiconductor device 100 includes a collector region 101, a buffer layer 102, a drift region 103, a carrier storage layer 105, a well region 106, an emitter region 107, a first shielding portion 108, a gate region 302, and a gate dielectric layer 303.

[0070] The buffer layer 102 is located on one side of the collector region 101. The drift region 103 is located on the side of the buffer layer 102 away from the collector region 101. The drift region 103 includes a first sub-drift region 103a and a second sub-drift region 103b. The first sub-drift region 103a is located on the side of the buffer layer 102 away from the collector region 101, and the second sub-drift region 103b is located on the side of the first sub-drift region 103a away from the collector region 101. The first sub-drift region 103a and the second sub-drift region 103b have different doping types. Exemplarily, the first sub-drift region 103a has an N-type doping type, and the second sub-drift region 103b has a P-type doping type.

[0071] The emitter region 107 is located on a side of the second drift sub-region 103 b away from the collector region 101 , and the projection of the emitter region 107 on the first reference plane overlaps with the projection of the drift region 103 on the first reference plane. The first reference plane is parallel to the thickness direction z of the drift region 103 .

[0072] A first recess 401 is provided on the surface of the drift region 103 away from the collector region 101. For example, a first recess 401 is provided on the surface of the second sub-drift region 103b away from the collector region 101. A gate dielectric layer 303 is provided on the bottom and sidewalls of the first recess 401. The gate region 302 is provided within the first recess 401 and is covered by the gate dielectric layer 303. A first shielding portion 108 is provided at the bottom of the first recess 401. The first shielding portion 108 contacts the gate dielectric layer 303 and the second sub-drift region 103b. The bottom of the gate dielectric layer 303 extends into the first shielding portion 108, and the first shielding portion 108 also contacts a portion of the side surface of the gate dielectric layer 303. The exemplary first shielding portion 108 has the same doping type as the second sub-drift region 103b, and the doping concentration of the first shielding portion 108 is greater than that of the second sub-drift region 103b.

[0073] In some feasible embodiments, the semiconductor device 100 further includes an emitter conductor 307 and an emitter dielectric layer 308. A second recess 402 is further defined on the surface of the drift region 103 remote from the collector region 101. For example, a second recess 402 is further defined on the surface of the second sub-drift region 103b remote from the collector region 101. The emitter dielectric layer 308 is defined on the bottom and sidewalls of the second recess 402. The emitter conductor 307 is defined within the second recess 402 and is encapsulated by the emitter dielectric layer 308. A second shielding portion 109 is defined at the bottom of the second recess 402. The second shielding portion 109 contacts the gate dielectric layer 303 and the second sub-drift region 103b. The bottom of the emitter dielectric layer 308 extends into the second shielding portion 109, and the second shielding portion 109 also contacts a portion of the side surface of the emitter dielectric layer 308. Exemplarily, the second shielding portion 109 and the second drift sub-region 103 b have the same doping type, and the doping concentration of the second shielding portion 109 is greater than the doping concentration of the second drift sub-region 103 b .

[0074] In some feasible embodiments, there is a gap between the first shielding portion 108 and the second shielding portion 109 , that is, they are not in contact with each other, and a portion of the second sub-drift region 103 b is located within the gap.

[0075] Continue to see Figure 4The carrier storage layer 105 is located between the second sub-drift region 103b and the emitter region 107, and between the first recess 401 and the second recess 402. The carrier storage layer 105 contacts the gate dielectric layer 303 and the emitter dielectric layer 308. When the semiconductor device 100 is in the on state, holes injected from the collector region 101 are partially blocked by the carrier storage layer 105 when diffusing in the drift region 103, resulting in local hole accumulation. This significantly increases the carrier concentration in the drift region 103, thereby reducing the on-resistance of the semiconductor device 100.

[0076] In some feasible embodiments, the well region 106 includes a first well region 106a. The first well region 106a is located between the carrier storage layer 105 and the emitter region 107, and between the first recess 401 and the second recess 402. The first well region 106a is in contact with the gate dielectric layer 303 and the emitter dielectric layer 308, respectively.

[0077] When the carrier storage layer 105 and the first well region 106 a are prepared, the same mask (eg, photoresist) can be used for both, which helps save process steps and reduce production costs.

[0078] In some feasible embodiments, the well region 106 further includes a second well region 106b, such as Figure 5 As shown, Figure 5 FIG2 is a structural diagram of another semiconductor device according to some embodiments. The second well region 106 b is provided on a side of the second drift sub-region 103 b away from the collector region 101 and is located on either side of the second recess 402 along with the first well region 106 a. The first well region 106 a and the second well region 106 b are arranged, for example, along a first direction x. The second well region 106 b is in contact with the second drift sub-region 103 b and is also in contact with the isolation dielectric layer 304 and the emitter dielectric layer 308.

[0079] There is no carrier storage layer on the side of the second well region 106b close to the collector region 101, so that the size of this location in the first direction x will not be limited by the carrier storage layer. The width of the semiconductor device 100 can be flexibly adjusted according to the requirements of the actual application scenario, thereby improving the voltage resistance of the semiconductor device 100.

[0080] exist Figure 5 In the semiconductor device 100 shown, the contact area between the second well region 106b and the gate dielectric layer 303 is small. During the start-up process of the semiconductor device 100, the charging effect of holes on the gate region 302 and / or the gate dielectric layer 303 is smaller, which is beneficial to improving the gate region control capability of the semiconductor device 100.

[0081] Emitter region 107 includes a first sub-emitter region 107a and a second sub-emitter region 107b having different doping types. The first sub-emitter region 107a and the second sub-emitter region 107b are arranged along a first direction x, which is, for example, the direction in which the first grooves 401 and the second grooves 402 are arranged. The first sub-emitter region 107a contacts the emitter region dielectric layer 308, the second sub-emitter region 107b contacts the first sub-emitter region 107a, and the second sub-emitter region 107b contacts the gate dielectric layer 303. Exemplarily, the doping type of the first sub-emitter region 107a is P-type, and the doping type of the second sub-emitter region 107b is N-type.

[0082] In some feasible embodiments, the semiconductor device 100 further includes a first metal layer 301, an isolation dielectric layer 304, and a second metal layer 305. The first metal layer 301 is located on a side of the collector region 101 away from the buffer layer 102. The second metal layer 305 is located on a side of the second sub-drift region 103 b away from the collector region 101 and forms an ohmic contact with the emitter regions 107 and 207. The isolation dielectric layer 304 is located between the gate region 302 and the second metal layer 305 to electrically isolate the gate region 302 from the second metal layer 305. The isolation dielectric layer 304 is also located between the second well region 106 b and the second metal layer 305 to electrically isolate the second well region 106 b from the second metal layer 305.

[0083] If the semiconductor device 100 operates in a withstand voltage state, the voltage of the gate region 302 is less than or equal to 0V, the voltage of the second metal layer 305, i.e., the emitter region 107, is equal to 0V, and the voltage of the first metal layer 301, i.e., the collector region 101, is greater than 0V. At this time, the channel of the gate region 302 is closed, and the collector region 101 and the emitter region 107 are subjected to a blocking voltage. Due to the presence of the first shielding portion 108 and the second shielding portion 109, the depletion of the carrier storage layer 105 can be assisted, thereby reducing the electric field between the first well region 106a and the carrier storage layer 105; and the presence of the first shielding portion 108 and the second shielding portion 109 can reduce the electric field borne by the gate dielectric layer 303 and the emitter dielectric layer 308, thereby protecting the gate dielectric layer 303 and the emitter dielectric layer 308. Furthermore, the PN junction formed by the second sub-drift region 103b and the first sub-drift region 103a is in a reverse biased state and bears part of the electric field. This further reduces the electric field in the gate dielectric layer 303, the emitter dielectric layer 308, and the carrier storage layer 105, making the electric field distribution more uniform and increasing the breakdown voltage of the semiconductor device 100, thereby improving the life expectancy and reliability of the semiconductor device 100. This improved electric field distribution also makes the temperature distribution more uniform, preventing local overheating of the semiconductor device 100 and further improving the life expectancy and reliability of the semiconductor device 100.

[0084] When semiconductor device 100 operates in the forward conduction state, the voltage of gate region 302 is greater than 0V, the voltage of second metal layer 305 (emitter region 107) is equal to 0V, and the voltage of first metal layer 301 (collector region 101) is greater than 0V. At this time, the channel of gate region 302 is open. Due to the open channel of gate region 302, an electron inversion layer forms on the surface of first well region 106a. The second sub-emitter region 107b is connected to the carrier storage layer 105 through the electron inversion layer on the surface of first well region 106a. The P-type collector region 101, N-type buffer layer 102, N-type first sub-drift region 103a, P-type second sub-drift region 103b, and N-type carrier storage layer 105 form a PNPN thyristor, which gradually turns on as the current in collector region 101 increases. If the PNPN thyristor is fully turned on, the first drift sub-region 103a, the second drift sub-region 103b and the second well region 106b include a large number of free carriers, and the PN junction formed by the well region 106 and the carrier storage layer 105 is in a reverse bias state.

[0085] When the semiconductor device 100 switches from the on state to the withstand voltage state, i.e., turns off, the voltage of the gate region 302 changes from greater than 0V to less than or equal to 0V. At this time, the channel of the gate region 302 switches from being open to being closed, and the voltage between the collector region 101 and the emitter region 107 gradually increases. As the channel gradually turns off, the depletion region of the semiconductor device 100 gradually expands. The depletion region, formed by the PN junction formed by the first well region 106a and the carrier storage layer 105, gradually extends toward the second drift sub-region 103b. The presence of the second drift sub-region 103b minimizes the electric field there, allowing holes in the second drift sub-region 103b to be extracted at a lower voltage. This accelerates hole extraction during turn-off and improves turn-off speed, thereby reducing turn-off losses in the semiconductor device 100 and enhancing the reliability of the semiconductor device 100.

[0086] Figure 6 FIG1 is a structural diagram of another semiconductor device according to some embodiments. The semiconductor device 100 includes a collector region 101, a buffer layer 102, a drift region 103, a well region 106, an emitter region 107, a first metal layer 301, a gate region 302, a gate dielectric layer 303, an isolation dielectric layer 304, a second metal layer 305, an emitter region conductor 307, and an emitter region dielectric layer 308. Figure 6 In the embodiment shown, the first shielding portion 108 includes the carrier storage layer 105, that is, the bottom of the gate dielectric layer 303 is located in the carrier storage layer 105. Figure 6 The first shielding portion 108 extends from the bottom of the first groove 401 to the emitter region dielectric layer 308 , and the first shielding portion 108 contacts the emitter region dielectric layer 308 .

[0087] In some feasible embodiments, a dimension of the emitter region conductor 307 in the thickness direction z of the drift region 103 is greater than a dimension of the gate region 302 in the thickness direction z of the drift region 103 . Figure 6 The remaining structure of the semiconductor device 100 is similar to that of Figure 4 The semiconductor devices 100 shown are basically the same, so they are not described in detail again.

[0088] exist Figure 6 In the illustrated semiconductor device 100, the depth of the first recess 401 is less than the depth of the second recess 402. The dimension of the gate dielectric layer 303 or the gate region 302 in the thickness direction z of the second drift sub-region 103b is less than the dimension of the emitter dielectric layer 308 or the emitter conductor 307 in the thickness direction z of the second drift sub-region 103b. Furthermore, the first shielding portion 108 at the bottom of the first recess 401 comprises a carrier storage layer 105. During the turn-on process of the semiconductor device 100, holes injected from the collector region 101 flow to a region with a lower potential. For holes, the first shielding portion 108, including the carrier storage layer 105, has a certain potential barrier height, while the second shielding portion 109 does not. Therefore, holes are more likely to gather in the second shielding portion 109 and are less likely to pass through the first shielding portion 108, which has a certain potential barrier and is farther from the collector region 101. This reduces the impact of holes on the capacitance of the gate region 302 and improves the gate control capability of the semiconductor device 100. Furthermore, the cell width of the semiconductor device 100 can be reduced without taking into account the interval between the first shield portion 108 and the second shield portion 109 .

[0089] Compared to the emitter conductor 307, the gate region 302 has a smaller dimension in the thickness direction z of the drift region 103. Therefore, during the turn-on process of the semiconductor device 100, holes are less likely to accumulate at the bottom of the gate region 302, and the hole charging effect on the gate current is less significant, resulting in a stronger gate control capability for the semiconductor device 100. Furthermore, the emitter conductor 307 has a larger dimension in the thickness direction z of the drift region 103. The second shielding portion 109 at its bottom can better shield the electric field of the gate dielectric layer 303 at the bottom of the first recess 401, reducing the probability of gate dielectric layer 303 breakdown and improving its reliability.

[0090] Figure 7 FIG1 is a structural diagram of another semiconductor device according to some embodiments. The semiconductor device 100 includes a collector region 101, a buffer layer 102, a drift region 103, a well region 106, an emitter region 107, a first metal layer 301, a gate region 302, a gate dielectric layer 303, an isolation dielectric layer 304, a second metal layer 305, an emitter region conductor 307, and an emitter region dielectric layer 308. Figure 6 In the embodiment shown, the first shielding portion 108 includes the carrier storage layer 105, that is, the bottom of the gate dielectric layer 303 is located in the carrier storage layer 105. Figure 6The first shielding portion 108 extends from the bottom of the first groove 401 to the second shielding portion 109 , and the first shielding portion 108 contacts the second shielding portion 109 . Figure 7 The remaining structure of the semiconductor device 100 is similar to that of Figure 6 The semiconductor devices 100 shown are basically the same, so they are not described in detail again.

[0091] In some feasible embodiments, the first shielding portion 108 is further in contact with the emission region dielectric layer 308 .

[0092] In some feasible embodiments, the first groove 401 and the second groove 402 have the same size in the thickness direction z of the drift region 103 .

[0093] exist Figure 7 In the semiconductor device 100 shown, the carrier storage layer 105 serving as the first shielding portion 108 surrounds the gate dielectric layer 303 and the gate region 302. During the turn-on process of the semiconductor device 100, due to the blocking of the first shielding portion 108, the holes injected from the emitter region 107 are not easily gathered around the gate dielectric layer 303, thereby reducing the influence of the hole injection on the gate region current of the semiconductor device 100 during the turn-on process and improving the gate region control capability of the semiconductor device 100.

[0094] Figure 8 1 is a flow chart of a method for manufacturing a semiconductor device according to some embodiments. The method for manufacturing a semiconductor device 100 includes steps S10 to S50.

[0095] In step S10, a collector region 101, a first sub-drift region 103a and a second sub-drift region 103b are formed in sequence. The first sub-drift region 103a and the second sub-drift region 103b have different doping types, and the following is obtained: Figure 11 As shown in the semiconductor structure, for example, the collector region 101 is doped with a P-type, the first drift sub-region 103 a is doped with an N-type, and the second drift sub-region 103 b is doped with a P-type.

[0096] In step S20, an emitter region 107 is formed on a side of the second drift sub-region 103b away from the collector region 101, and the following is obtained: Figure 12 The semiconductor structure shown.

[0097] The projection of the emitter region 107 on a first reference plane overlaps with the projection of the second sub-drift region 103b on the first reference plane. The first reference plane is parallel to the thickness direction z of the second sub-drift region 103b. The emitter region 107 includes a first sub-emitter region 107a and a second sub-emitter region 107b having different doping types, and the first sub-emitter region 107a and the second sub-emitter region 107b are arranged along a first direction x. Exemplarily, the doping type of the first sub-emitter region 107a is P-type, and the doping type of the second sub-emitter region 107b is N-type.

[0098] In step S30, the second drift sub-region 103b is etched to form a first groove 401, and the Figure 13 The semiconductor structure shown.

[0099] In step S40, a first shielding portion 108 is formed at the bottom of the first groove 401. The bottom of the first groove 401 is located on the surface or inside of the first shielding portion 108. Figure 14 The semiconductor structure shown.

[0100] In step S50, a gate dielectric layer 303 is formed on the bottom surface and sidewall surface of the first groove 401, and a gate region 302 is formed in the first groove 401. The gate dielectric layer 303 wraps the gate region 302, and the gate dielectric layer 303 is formed. Figure 4 The semiconductor device 100 is shown.

[0101] Figure 9 1 is a flow chart of another method for manufacturing a semiconductor device according to some embodiments. The method for manufacturing a semiconductor device 100 includes steps S10, S60, S70, and S80.

[0102] In step S10, a collector region 101, a first sub-drift region 103a and a second sub-drift region 103b are formed in sequence. The first sub-drift region 103a and the second sub-drift region 103b have different doping types, and the following is obtained: Figure 11 As shown in the semiconductor structure, for example, the collector region 101 is doped with a P-type, the first drift sub-region 103 a is doped with an N-type, and the second drift sub-region 103 b is doped with a P-type.

[0103] In step S60, a first shielding portion and an emitter region 107 are formed on a side of the second sub-drift region 103b away from the collector region 101. The first shielding portion is closer to the collector region 101 than the emitter region 107. Figure 12 The semiconductor structure shown in FIG. 4 is a schematic diagram of a semiconductor structure shown in FIG. 4 . Exemplarily, the first shielding portion includes a carrier storage layer 105 , and the doping type of the first shielding portion is N-type.

[0104] The projection of the emitter region 107 on a first reference plane overlaps with the projection of the second sub-drift region 103b on the first reference plane. The first reference plane is parallel to the thickness direction z of the second sub-drift region 103b. The emitter region 107 includes a first sub-emitter region 107a and a second sub-emitter region 107b having different doping types, and the first sub-emitter region 107a and the second sub-emitter region 107b are arranged along a first direction x. Exemplarily, the doping type of the first sub-emitter region 107a is P-type, and the doping type of the second sub-emitter region 107b is N-type.

[0105] In step S70 , the second drift sub-region 103 b is etched to form a first groove 401 . The bottom of the first groove 401 is located on the surface or inside of the first shielding portion 108 .

[0106] In step S80, a gate dielectric layer 303 is formed on the bottom surface and sidewall surface of the first groove 401, and a gate region 302 is formed in the first groove 401. The gate dielectric layer 303 wraps the gate region 302, and the gate dielectric layer 303 is formed. Figure 6 or Figure 7 The semiconductor device 100 is shown.

[0107] Figure 10 is a flow chart of another method for manufacturing a semiconductor device according to some embodiments. Figures 11-20 for Figure 10 The semiconductor structure diagram of each step in the preparation method. Figure 10 and Figures 11-20 , a method for manufacturing the semiconductor device 100 is described. The method for manufacturing the semiconductor device 100 includes step S11, step S21, step S31, step S41, step S51, step S52, and steps S61 to S65.

[0108] In step S11, a collector region 101, a buffer layer 102, a first sub-drift region 103a and a second sub-drift region 103b are sequentially formed on one side of the substrate 306 to obtain the following: Figure 11 The semiconductor structure shown. In some feasible embodiments, epitaxial growth can be used to sequentially form the collector region 101, buffer layer 102, first sub-drift region 103a, and second sub-drift region 103b on one side of the substrate 306. For example, the second metal layer 305 is an N-type substrate, the collector region 101 is doped with P-type, the buffer layer 102 is doped with N-type, the first sub-drift region 103a is doped with N-type, and the second sub-drift region 103b is doped with P-type.

[0109] The doping concentration of the substrate 306 is, for example, greater than the doping concentration of the buffer layer 102 , and the doping concentration of the collector region 101 is, for example, greater than the doping concentration of the second drift sub-region 103 b .

[0110] In step S21 , a carrier storage layer 105 , an initial well region 106 c and an emitter region 107 are formed on a side of the second drift sub-region 103 b away from the collector region 101 .

[0111] In some feasible embodiments, the initial well region 106c has the same size as the carrier storage layer 105 in the first direction x, and the final result is as follows: Figure 4 In this case, when the carrier storage layer 105 and the initial well region 106c are formed respectively by ion implantation, the same mask, ie the same photoresist, can be used for both, which is beneficial to save process steps and reduce production costs.

[0112] In some feasible embodiments, a hard mask layer is formed on a side of the second sub-drift region 103b away from the collector region 101, the hard mask layer is patterned, and ion implantation is performed on the side of the second sub-drift region 103b away from the collector region 101 using an ion implantation process to form an N-type carrier storage layer 105, a P-type initial well region 106c, and an emitter region 107. The emitter region 107 includes a first sub-emitter region 107a of P-type doping and a second sub-emitter region 107b of N-type doping. Figure 12 The semiconductor structure shown.

[0113] In step S31, the second drift sub-region 103b is etched to form a first groove 401 and a second groove 402, and the following is obtained: Figure 13 The semiconductor structure shown in FIG. Exemplarily, the second groove 402 separates the initial well region 106 c, thereby forming the well region 106 . The well region 106 includes a first well region 106 a and a second well region 106 b , respectively located on either side of the second groove 402 . The first well region 106 a and the second well region 106 b are arranged along a first direction x, which is the arrangement direction of the first groove 401 and the second groove 402 .

[0114] In step S41, a first shielding portion 108 is formed at the bottom of the first groove 401, and a second shielding portion 109 is formed at the bottom of the second groove 402, so as to obtain Figure 14 The semiconductor structure shown.

[0115] In some feasible embodiments, P-type impurities are selectively implanted to form a first shielding portion 108 at the bottom of the first groove 401 and a second shielding portion 109 at the bottom of the second groove 402 , and high-temperature annealing is performed to activate the implanted impurities.

[0116] In step S51, a first initial dielectric layer 303a and an initial conductor layer 302a are sequentially formed on a side of the second sub-drift region 103b away from the collector region 101, and the following is obtained: Figure 15The semiconductor structure shown. The first initial dielectric layer 303a is located on the surface of the second drift sub-region 103b away from the collector region 101, as well as on the bottom and sidewall surfaces of the first and second recesses 401, 402. The initial conductor layer 302a is located on the surface of the first initial dielectric layer 303a away from the collector region 101, as well as in the first and second recesses 401, 402.

[0117] In step S52, the first initial dielectric layer 303a and the initial conductor layer 302a located on the surface of the second sub-drift region 103b away from the collector region 101 are removed, and the following is obtained: Figure 16 As shown in the semiconductor structure, for example, only the first initial dielectric layer 303a and the initial conductor layer 302a located in the first groove 401 and the second groove 402 are retained to obtain the gate region 302, the gate dielectric layer 303, the emitter conductor 307 and the emitter dielectric layer 308.

[0118] In step S61, a second initial dielectric layer 304a is formed on the side of the second sub-drift region 103b away from the collector region 101, and the following is obtained: Figure 17 The semiconductor structure shown.

[0119] In step S62, the selected area of ​​the second initial dielectric layer 304a is etched to form an isolation dielectric layer 304, and the result is as follows: Figure 18 The semiconductor structure shown in FIG. At least a portion of the emitter region 107 is exposed away from the surface of the collector region 101, and at least a portion of the emitter region conductor 307 is exposed away from the surface of the collector region 101, to form an emitter region contact region. At least a portion of the gate region 302 is exposed away from the surface of the collector region 101, to form a gate region contact region (not shown). For example, the emitter region contact region and the gate region contact region may be contact holes.

[0120] In step S63, a second metal layer 305 is formed on the side of the second drift sub-region 103b away from the collector region 101, and the following is obtained: Figure 19 The semiconductor structure shown in FIG. The second metal layer 305 covers at least the surface of the isolation dielectric layer 304 away from the collector region 101. Exemplarily, a process such as sputtering is used to fill the source contact region and the gate contact region, and to cover the surface of the isolation dielectric layer 304 away from the collector region 101, thereby forming the second metal layer 305.

[0121] In a feasible embodiment, a conductor layer is formed on a side of the second sub-drift region 103b away from the collector region 101, and the conductor layer at least covers the surface of the isolation dielectric layer 304 away from the collector region 101. The conductor layer is selectively etched to form a second metal layer 305 and a gate region conductive layer (not shown in the figure).

[0122] In step S64, the substrate 306 is thinned until the collector region 101 is exposed, and the following is obtained: Figure 20 The semiconductor structure shown in FIG. Exemplarily, a backside thinning process is used to remove the substrate 306 until the surface of the collector region 101 away from the buffer layer 102 is exposed. In some feasible embodiments, the collector region 101 may be overetched, that is, when the backside thinning process is performed to expose the surface of the collector region 101, the thinning process is continued to thin a portion of the collector region 101.

[0123] In step S65, a first metal layer 301 is formed on the side of the collector region 101 away from the buffer layer 102, and the following is obtained: Figure 4 The semiconductor device 100 is shown. Exemplarily, the first metal layer 301 is formed by sputtering on the side of the collector region 101 away from the buffer layer 102. Exemplarily, the first metal layer 301 is formed by sputtering on the side of the collector region 101 away from the drift region 103.

[0124] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: collector area; A drift region is provided on the collector region, wherein a first groove is provided on a surface of the drift region away from the collector region; an emitter region, disposed on a side of the drift region away from the collector region; a gate dielectric layer, disposed on the bottom surface and sidewall surfaces of the first groove; a gate region, disposed in the first groove and covered by the gate dielectric layer; a first shielding portion, disposed at the bottom of the first groove and in contact with the gate dielectric layer; The drift region includes a first sub-drift region and a second sub-drift region that are stacked, the second sub-drift region is located on a side of the first sub-drift region away from the collector region, and the first sub-drift region and the second sub-drift region have different doping types; the first shielding portion is in contact with the second sub-drift region; The semiconductor device further includes: a second groove, provided on a surface of the drift region away from the collector region, wherein the second groove and the first groove are respectively located on both sides of the emitter region; an emitting region dielectric layer, provided on the bottom surface and sidewall surfaces of the second groove; an emitting region conductor, disposed in the second groove and covered by the emitting region dielectric layer; a second shielding portion, disposed at the bottom of the second groove and in contact with the emitter region dielectric layer; the second shielding portion also in contact with the second sub-drift region; The first shielding portion includes a carrier storage layer. The bottom of the gate dielectric layer is located in the carrier storage layer. The carrier storage layer and the second sub-drift region have different doping types.

2. The semiconductor device according to claim 1, wherein The carrier storage layer extends from the bottom of the first groove to the second shielding portion and contacts the second shielding portion.

3. The semiconductor device according to claim 2, wherein The carrier storage layer is also in contact with the emitter region dielectric layer.

4. The semiconductor device according to claim 2, wherein The second shielding portion and the second sub-drift region have the same doping type, and the doping concentration of the second shielding portion is greater than the doping concentration of the second sub-drift region.

5. The semiconductor device according to claim 2, wherein The bottom of the gate dielectric layer extends into the first shielding portion, and the first shielding portion contacts a portion of a side surface of the gate dielectric layer; And / or, the bottom of the emitting region dielectric layer extends into the second shielding portion, and the second shielding portion contacts a portion of the side surface of the emitting region dielectric layer.

6. The semiconductor device according to claim 2, wherein The size of the gate region in the thickness direction of the second sub-drift region is smaller than the size of the emitter region conductor in the thickness direction of the second sub-drift region; Alternatively, a dimension of the gate region in the thickness direction of the second sub-drift region is equal to a dimension of the emitter region conductor in the thickness direction of the second sub-drift region.

7. The semiconductor device according to claim 2, wherein: Also includes: a first well region, located between the emitter region and the carrier storage layer, and between the first groove and the second groove; The first well region is in contact with the gate dielectric layer and the emitter dielectric layer respectively.

8. The semiconductor device according to claim 7, wherein: Also includes: The second well region is provided on a side of the second sub-drift region away from the collector region, and is located on two sides of the second groove together with the first well region.

9. The semiconductor device according to any one of claims 1 to 3, wherein: The transmitting area includes: A first sub-emitting area and a second sub-emitting area, wherein the first sub-emitting area and the second sub-emitting area are arranged along a first direction, and the first direction is an arrangement direction of the first grooves and the second grooves; The first sub-emitting region and the second sub-emitting region have different doping types.

10. The semiconductor device according to any one of claims 1 to 3, wherein: Also includes: a first metal layer, located on a side of the collector region away from the drift region; A second metal layer is located on a side of the drift region away from the collector region and is in ohmic contact with the emitter region and the emitter region conductor respectively; An isolation dielectric layer is located between the second metal layer and the second well region, and between the second metal layer and the gate region.

11. A method for preparing a semiconductor device, for preparing the semiconductor device according to any one of claims 1 to 10, characterized in that: include: A collector region, a first sub-drift region, and a second sub-drift region are stacked in sequence, wherein the first sub-drift region and the second sub-drift region have different doping types: forming an emitter region on a side of the second sub-drift region away from the collector region; etching the second drift sub-region to form a first groove and a second groove; forming a first shielding portion at the bottom of the first groove and forming a second shielding portion at the bottom of the second groove; forming a gate dielectric layer on the bottom surface and sidewall surface of the first groove, and forming a gate region in the first groove; the gate dielectric layer wraps the gate region; An emitting region dielectric layer is formed on the bottom surface and sidewall surface of the second groove, and an emitting region conductor is formed in the second groove, wherein the emitting region dielectric layer wraps the emitting region conductor.

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