Preparation method of semiconductor structure and semiconductor structure
By forming a target oxide layer at a preset temperature during the preparation of the semiconductor transistor, and forming the first and second semiconductor layers in sequence on the first region, the problem of transistor device damage in the prior art is solved, and device performance and switching speed are improved.
Patent Information
- Application Number
- CN202311791717.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-22
- Publication Date
- 2025-06-27
Smart Images
Figure CN120224713A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a method for fabricating a semiconductor structure and its structure. Background Art
[0002] In semiconductor technology, the switching speed of a transistor directly affects the response time of the transistor, and thus affects the performance and response speed of the entire system.
[0003] However, the existing manufacturing processes for transistors that can improve the switching speed easily cause device damage to the transistors. Therefore, how to avoid device damage when forming transistors has become one of the technical problems that need to be solved urgently. Summary of the Invention
[0004] Based on this, it is necessary to provide a method for fabricating a semiconductor structure and its structure for the problem of device damage caused by the manufacturing process of transistors in the prior art.
[0005] To achieve the above object, on the one hand, this application provides a method for fabricating a semiconductor structure, including: providing a substrate, where the substrate includes a first region and a second region for forming transistors; wherein, the first region is used to form source / drain, and the second region is used to form a gate; forming a dielectric layer on the substrate in part of the second region; forming a target oxide layer on the region of the substrate that is not covered by the dielectric layer at a preset temperature; forming a target dielectric layer that exposes the substrate of the first region; sequentially forming a first semiconductor layer including a first target element and a second semiconductor layer including a second target element on the exposed substrate of the first region, where the first semiconductor layer is located between the substrate and the second semiconductor layer; the lattice constant of the first target element is greater than the lattice constant of the second target element; removing the target dielectric layer; forming the gate on at least the exposed substrate of the second region.
[0006] In one embodiment, the preset temperature is 800°C - 1200°C; forming the target oxide layer includes: forming the target oxide layer on the region of the substrate that is not covered by the dielectric layer at the preset temperature by using an epitaxial growth process.
[0007] In one embodiment, the first target element includes germanium, and the second target element includes silicon; the first semiconductor layer includes a germanium-silicon layer, and the second semiconductor layer includes a silicon layer; forming the first semiconductor layer and the second semiconductor layer includes: sequentially forming the germanium-silicon layer and the silicon layer on the exposed substrate of the first region by using an epitaxial growth process.
[0008] In one embodiment, the dielectric layer includes a first oxide layer and a first nitride layer; forming the dielectric layer on a part of the second region includes: forming the first oxide layer, the first nitride layer, and a second oxide layer on the substrate in a stacked manner along a direction away from the substrate; forming a first patterned photoresist layer on the top surface of the second oxide layer within a part of the second region; the first patterned photoresist layer covering a reference region of the substrate; etching and removing the second oxide layer using the first patterned photoresist layer as a mask; removing the first patterned photoresist layer; removing the first nitride layer on the region of the substrate except for the reference region; removing the first oxide layer on the region of the substrate except for the reference region and the second oxide layer within the reference region, and the first oxide layer and the first nitride layer within the reference region are used to jointly form the dielectric layer.
[0009] In one embodiment, forming a target dielectric layer on the substrate to expose the first region includes: forming a second nitride layer on at least the target oxide layer outside the reference region; forming a third oxide layer covering the second nitride layer and the first nitride layer; forming a second patterned photoresist layer on the third oxide layer, the second patterned photoresist layer exposing the third oxide layer of the first region; removing the third oxide layer of the first region; removing the second patterned photoresist layer and the third oxide layer directly below the second patterned photoresist layer; removing the second nitride layer and the target oxide layer of the first region to expose the substrate of the first region; the remaining first nitride layer and the second nitride layer are used to jointly form the target dielectric layer.
[0010] In one embodiment, forming the gate on at least the substrate exposed in the second region includes: forming a protective layer on at least the first oxide layer in the second region; forming a gate conductive layer on at least the protective layer and the target oxide layer, and the first oxide layer, the target oxide layer, the protective layer, and the gate conductive layer are used to jointly form the gate.
[0011] In one embodiment, the protective layer includes a target nitride layer; forming the protective layer on at least the first oxide layer in the second region includes: forming a third patterned photoresist layer exposing the first oxide layer in the second region; forming the target nitride layer on the exposed first oxide layer in the second region; removing the third patterned photoresist layer.
[0012] In one embodiment, forming the gate further includes: after removing the third patterned photoresist layer, forming an interlayer oxide layer covering at least the target nitride layer; forming the gate conductive layer on the interlayer oxide layer.
[0013] In one embodiment, forming an interlayer oxide layer covering at least the target nitride layer includes: forming an interlayer oxide layer covering at least the target nitride layer by a deposition process.
[0014] On the other hand, the present application provides a semiconductor structure prepared by using the preparation method of the semiconductor structure according to any one of the embodiments of the present application.
[0015] The preparation method of the semiconductor structure of the present application and its structure have the following beneficial effects:
[0016] The preparation method of the semiconductor structure of the present application includes providing a substrate, where the substrate includes a first region and a second region for forming transistors. Among them, the first region is used to form source / drain electrodes, and the second region is used to form a gate. A dielectric layer is formed on the substrate in a part of the second region, and then a target oxide layer is formed on the region of the substrate that is not covered by the dielectric layer at a preset temperature. A target dielectric layer that exposes the substrate of the first region is formed. A first semiconductor layer including a first target element and a second semiconductor layer including a second target element are sequentially formed on the exposed substrate of the first region. The first semiconductor layer is located between the substrate and the second semiconductor layer, and the lattice constant of the first target element is greater than that of the second target element. The target dielectric layer is removed, and a gate is formed at least on the exposed substrate of the second region. By forming the target oxide layer at a preset temperature first and then sequentially forming the first semiconductor layer and the second semiconductor layer in the first region, the present application avoids damage to the first semiconductor layer and the second semiconductor layer caused by the preset temperature, and improves the device performance of the semiconductor structure.
[0017] The semiconductor structure of the present application includes a substrate, where the substrate includes a first region and a second region for forming transistors. Among them, the first region is used to form source / drain electrodes, and the second region is used to form a gate. A dielectric layer is located on the substrate in a part of the second region, and a target oxide layer is located on the substrate in the second region that is not covered by the dielectric layer. A first semiconductor layer is located on the substrate of the first region, and a second semiconductor layer is located on the first semiconductor layer. Among them, the first semiconductor layer includes a first target element, the second semiconductor layer includes a second target element, and the lattice constant of the first target element is greater than that of the second target element. The gate is located on the substrate of the second region. By forming a first semiconductor layer including a first target element and a second semiconductor layer including a second target element on the substrate of the first region, and the lattice constant of the first target element is greater than that of the second target element, therefore, the first semiconductor layer generates compressive stress on the lateral channel, deforms the lattice of the channel, reduces the conductivity effective mass of holes in the channel direction, and further improves the switching speed of the transistor. Description of the Drawings
[0018] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0019] Figures 1a - 1d It is a schematic cross-sectional view of a source / drain in a semiconductor structure provided in an embodiment;
[0020] Figure 2 It is a flowchart of a method for manufacturing a semiconductor structure provided in an embodiment;
[0021] Figure 3 It is a flowchart of a method for manufacturing a semiconductor structure provided in another embodiment;
[0022] Figure 4a It is a top view schematic of the structure obtained in step S202a in a method for manufacturing a semiconductor structure provided in an embodiment;
[0023] Figure 4b It is a schematic cross-sectional view of the structure obtained in step S202a in a method for manufacturing a semiconductor structure provided in an embodiment;
[0024] Figure 5a It is a top view schematic of the structure obtained in step S202b in a method for manufacturing a semiconductor structure provided in an embodiment;
[0025] Figure 5b It is a schematic cross-sectional view of the structure obtained in step S202b in a method for manufacturing a semiconductor structure provided in an embodiment;
[0026] Figure 6a It is a top view schematic of the structure obtained in step S202c in a method for manufacturing a semiconductor structure provided in an embodiment;
[0027] Figure 6b It is a schematic cross-sectional view of the structure obtained in step S202c in a method for manufacturing a semiconductor structure provided in an embodiment;
[0028] Figure 7a It is a top view schematic of the structure obtained in step S202d in a method for manufacturing a semiconductor structure provided in an embodiment;
[0029] Figure 7b It is a schematic cross-sectional view of the structure obtained in step S202d in a method for manufacturing a semiconductor structure provided in an embodiment;
[0030] Figure 8aA top view schematic diagram of the structure obtained in step S202f in the manufacturing method of the semiconductor structure provided in an embodiment;
[0031] Figure 8b A cross-sectional schematic diagram of the structure obtained in step S202f in the manufacturing method of the semiconductor structure provided in an embodiment;
[0032] Figure 9a A top view schematic diagram of the structure obtained in step S203 in the manufacturing method of the semiconductor structure provided in an embodiment;
[0033] Figure 9b A cross-sectional schematic diagram of the structure obtained in step S203 in the manufacturing method of the semiconductor structure provided in an embodiment;
[0034] Figure 10 A flowchart of the manufacturing method of the semiconductor structure provided in another embodiment;
[0035] Figure 11a A top view schematic diagram of the structure obtained in step S204b in the manufacturing method of the semiconductor structure provided in an embodiment;
[0036] Figure 11b A cross-sectional schematic diagram of the structure obtained in step S204b in the manufacturing method of the semiconductor structure provided in an embodiment;
[0037] Figure 12a A top view schematic diagram of the structure obtained in step S204c in the manufacturing method of the semiconductor structure provided in an embodiment;
[0038] Figure 12b A cross-sectional schematic diagram of the structure obtained in step S204c in the manufacturing method of the semiconductor structure provided in an embodiment;
[0039] Figure 13a A top view schematic diagram of the structure obtained in step S204d in the manufacturing method of the semiconductor structure provided in an embodiment;
[0040] Figure 13b A cross-sectional schematic diagram of the structure obtained in step S204d in the manufacturing method of the semiconductor structure provided in an embodiment;
[0041] Figure 14a A top view schematic diagram of the structure obtained in step S204e in the manufacturing method of the semiconductor structure provided in an embodiment;
[0042] Figure 14b A cross-sectional schematic diagram of the structure obtained in step S204e in the manufacturing method of the semiconductor structure provided in an embodiment;
[0043] Figure 15aA top view schematic diagram of the structure obtained in step S204f in the method for preparing a semiconductor structure provided in an embodiment;
[0044] Figure 15b A cross-sectional schematic diagram of the structure obtained in step S204f in the method for preparing a semiconductor structure provided in an embodiment;
[0045] Figure 16a A top view schematic diagram of the structure obtained in step S205 in the method for preparing a semiconductor structure provided in an embodiment;
[0046] Figure 16b A cross-sectional schematic diagram of the structure obtained in step S205 in the method for preparing a semiconductor structure provided in an embodiment;
[0047] Figure 17a A top view schematic diagram of the structure obtained in step S206 in the method for preparing a semiconductor structure provided in an embodiment;
[0048] Figure 17b A cross-sectional schematic diagram of the structure obtained in step S206 in the method for preparing a semiconductor structure provided in an embodiment;
[0049] Figure 18a A top view schematic diagram of the structure obtained in step S207 in the method for preparing a semiconductor structure provided in an embodiment;
[0050] Figure 18b A cross-sectional schematic diagram of the structure obtained in step S207 in the method for preparing a semiconductor structure provided in an embodiment;
[0051] Figure 19a A top view schematic diagram of the structure obtained in step S207 in the method for preparing a semiconductor structure provided in an embodiment;
[0052] Figure 19b A cross-sectional schematic diagram of the structure obtained in step S207 in the method for preparing a semiconductor structure provided in an embodiment;
[0053] Figure 20 A cross-sectional schematic diagram of the structure obtained in step S207 in the method for preparing a semiconductor structure provided in an embodiment.
[0054] Explanation of reference numerals:
[0055] 10. Substrate; 20. Protective layer; 301. Fourth oxide layer; 301a. Silicon dioxide layer; 302. High-k dielectric layer; 40. Gate conductive layer; 401. First titanium nitride layer; 402. Metal layer; 403. Second titanium nitride layer; 404. Polysilicon layer; 50. First semiconductor layer; 60. Second semiconductor layer; 70. Dielectric layer; 701. First oxide layer; 702. First nitride layer; 703. Second oxide layer; 705. First patterned photoresist layer; 80. Target oxide layer; 90. Target dielectric layer; 901. Second nitride layer; 902. Third oxide layer; 905. Second patterned photoresist layer. Detailed implementation manners
[0056] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is thorough and comprehensive.
[0057] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.
[0058] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below can be represented as the second element, component, region, layer or part; for example, the first doping type can be referred to as the second doping type, and similarly, the second doping type can be referred to as the first doping type; the first doping type and the second doping type are different doping types. For example, the first doping type can be P-type and the second doping type can be N-type, or the first doping type can be N-type and the second doping type can be P-type.
[0059] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatial relationship terms include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the figures is flipped, an element or feature described as "under other elements" or "beneath them" or "underneath them" will be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also have other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.
[0060] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprises" and / or "comprising" are used in this specification, the presence of the stated features, integers, steps, operations, elements and / or components can be ascertained, but one or more other features, integers, steps, operations, elements, components and / or groups thereof are not precluded from the presence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.
[0061] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, and such can be expected to vary due to, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present application should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implanted region to the non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of regions of the device, and do not limit the scope of the present application.
[0062] In a related art, please refer to Figures 1a - 1d, the film layer structure of the source / drain in a transistor includes a substrate 10, a silicon dioxide layer 301a, a high-k dielectric layer 302, and a gate conductive layer 40. By forming a first semiconductor layer 50 and a second semiconductor layer 60 within the film layer structure of the source / drain, the switching speed of the transistor can be enhanced. However, during the process of forming the target oxide layer (not shown) in the gate, the preset temperature is likely to cause the diffusion of a first target element in the first semiconductor layer 50 into the second semiconductor layer 60, resulting in device damage to the semiconductor structure.
[0063] Regarding the above problems, please refer to Figure 2 , this application provides a method for fabricating a semiconductor structure, including the following steps:
[0064] Step S201: Provide a substrate, which includes a first region and a second region for forming transistors thereon; wherein, the first region is for forming the source / drain, and the second region is for forming the gate.
[0065] As an example, the substrate can be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate can be a layered substrate including, such as, Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator. Therefore, the type of the substrate should not limit the protection scope of the present disclosure. In addition, a shallow trench isolation (STI) structure can be formed within the substrate, and the shallow trench isolation structure can isolate several active areas (AAs) arranged at intervals within the substrate.
[0066] It can be understood that in an embodiment where the substrate includes a P-type substrate, an N-type ion can be implanted to form a source region; correspondingly, in an embodiment where the substrate includes an N-type substrate, a P-type ion can be implanted to form a source region. The embodiments of the present disclosure do not specifically limit the type of P-type impurity ions. As an example, the P-type impurity ions may include, but are not limited to, any one or several of boron (B) ions, gallium (Ga) or indium (In) ions, etc. Similarly, the embodiments of the present disclosure do not specifically limit the type of N-type impurity ions. As an example, the N-type impurity ions may include, but are not limited to, any one or several of phosphorus (P) ions, arsenic (As) ions or antimony (Sb) ions.
[0067] Step S202: Form a dielectric layer on the substrate in a partial second region.
[0068] As an example, the dielectric layer may include a single-layer structure or a multi-layer structure, and generally an insulating material can be used, which can be used as an insulating layer to prevent direct current passing through. The material of the dielectric layer can be selected from silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum oxynitride (AlON) and their combinations.
[0069] Step S203: Form a target oxide layer on the region of the substrate where the dielectric layer is not covered at a preset temperature.
[0070] As an example, the material of the target oxide layer may include silicon dioxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), aluminum oxynitride (AlON) and their combinations.
[0071] Step S204: Form a target dielectric layer that exposes the substrate in the first region.
[0072] As an example, the target dielectric layer may include a single-layer structure or a multi-layer structure, and the material of the target dielectric layer can be selected from silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum oxynitride (AlON) and their combinations.
[0073] Step S205: Sequentially form a first semiconductor layer including a first target element and a second semiconductor layer including a second target element on the exposed substrate in the first region. The first semiconductor layer is located between the substrate and the second semiconductor layer; the lattice constant of the first target element is greater than the lattice constant of the second target element.
[0074] Step S206: Remove the target dielectric layer.
[0075] Step S207: Form a gate on at least the substrate exposed in the second region. The gate may include a dielectric layer, a target oxide layer, a gate conductive layer, etc.
[0076] In the above embodiment, by providing a substrate, the substrate includes a first region and a second region for forming transistors. Among them, the first region is used to form source / drain, and the second region is used to form a gate. A dielectric layer is formed on the substrate in a part of the second region, and then a target oxide layer is formed on the region of the substrate where the dielectric layer is not covered at a preset temperature to form a target dielectric layer exposing the first region of the substrate. A first semiconductor layer including a first target element and a second semiconductor layer including a second target element are sequentially formed on the exposed substrate of the first region. The first semiconductor layer is located between the substrate and the second semiconductor layer. The lattice constant of the first target element is greater than that of the second target element. The target dielectric layer is removed, and a gate is formed on at least the substrate exposed in the second region. In this application, by first forming the target oxide layer at a preset temperature and then sequentially forming the first semiconductor layer and the second semiconductor layer in the first region, damage to the first semiconductor layer and the second semiconductor layer caused by the preset temperature is avoided, and the device performance of the semiconductor structure is improved. Moreover, by forming a first semiconductor layer including a first target element and a second semiconductor layer including a second target element on the substrate of the first region, the first semiconductor layer generates compressive stress on the lateral channel, deforms the lattice of the channel, reduces the conductivity effective mass of holes in the channel direction, and thus improves the speed of the transistor.
[0077] In one embodiment, please refer to Figure 3 , forming a dielectric layer on a part of the second region includes: steps S202a - S202f.
[0078] Step S202a: Form a first oxide layer, a first nitride layer, and a second oxide layer sequentially stacked in a direction away from the substrate on the substrate.
[0079] Please refer to Figure 4a and Figure 4b , it should be noted that the cross-sectional schematic diagram is a cross-sectional view taken perpendicular to the top surface of the substrate in the Aa direction or Bb direction in the top view schematic diagram. For the sake of brevity, it will not be repeated in the subsequent embodiments. As an example, the materials of the first oxide layer 701 and the second oxide layer 703 may include silicon dioxide (SiO2), and the material of the first nitride layer 702 may include silicon nitride (Si3N4). The first oxide layer 701, the first nitride layer 702, and the second oxide layer 703 can be sequentially formed on the substrate by a deposition process. Among them, the deposition process may include, but is not limited to, a chemical vapor deposition process (Chemical Vapor Deposition, CVD), an atomic layer deposition process (Atomic
[0080] One or more of the following processes: Atomic Layer Deposition (ALD), High Density Plasma (HDP) process, Plasma Enhanced Chemical Vapor Deposition (PECVD), and Spin-on Dielectric (SOD).
[0081] Step S202b: Form a first patterned photoresist layer on the top surface of the second oxide layer in a part of the second region. Please refer to Figure 5a and Figure 5b , the first patterned photoresist layer 705 covers the reference area of the substrate 10, where the reference area is located within the second region and is used to form a gate.
[0082] Step S202c: Etch and remove the second oxide layer using the first patterned photoresist layer as a mask.
[0083] Please refer to Figure 6a and Figure 6b , as an example, one or more of wet etching and dry etching can be used to remove the second oxide layer 703. Among them, wet etching can include reacting the second oxide layer 703 with a hydrofluoric acid (HF) solution; dry etching can include any one of reactive ion etching (RIE), inductively coupled plasma etching (ICP), or high-density plasma etching (HDP).
[0084] Step S202d: Remove the first patterned photoresist layer.
[0085] Please continue to refer to Figure 6a and Figure 6b , and Figure 7a and Figure 7b , as an example, a chemical mechanical polishing process or an ashing reaction can be used to remove the first patterned photoresist layer 705. This application does not specifically limit the material of the first patterned photoresist layer 705 and the removal process, and it can be selected according to actual needs.
[0086] Step S202e: Remove the first nitride layer in the area of the substrate except for the reference area.
[0087] Please continue to refer to Figure 7a and Figure 7b , and Figure 8a and Figure 8b , as an example, a fluoride such as HF, CF4, CHF3, CH2F2, or CH3F can be used as an etching gas for dry etching the first nitride layer 702.
[0088] Step S202f: Remove the first oxide layer in the area other than the reference area on the substrate and the second oxide layer in the reference area.
[0089] Please continue to refer to Figure 8a and Figure 8b , for example, the first oxide layer 701 and the second oxide layer 703 can be removed simultaneously by wet etching or dry etching. The first oxide layer 701 and the first nitride layer 702 in the reference area are used to jointly form the dielectric layer 70.
[0090] In the above embodiment, through the combination of the deposition process and the photolithography process, a dielectric layer is formed on the substrate in the reference area, thereby isolating areas with different electrical properties and preventing direct current passage.
[0091] In one embodiment, forming the target oxide layer includes: at a preset temperature, forming the target oxide layer on the area of the substrate not covered by the dielectric layer by using an epitaxial growth process. Wherein, the film thickness of the target oxide layer is less than the film thickness of the first oxide layer.
[0092] Please refer to Figure 9a and Figure 9b , for example, the material of the target oxide layer 80 can include silicon dioxide. SiH4 or SiCl4 can be used as the precursor gas to react with O2 to form silicon dioxide on the area of the substrate 10 not covered by the dielectric layer 70. Wherein, the preset temperature is 800°C - 1200°C, for example: 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C, 1150°C, etc.
[0093] In the above embodiment, since the temperature for forming the target oxide layer is relatively high, therefore, by forming the target oxide layer before forming the first semiconductor layer and the second semiconductor layer, it is possible to avoid the diffusion of the first target element in the first semiconductor layer into the second semiconductor layer due to high temperature, resulting in device damage to the semiconductor structure.
[0094] In one embodiment, please refer to Figure 10 , forming the target dielectric layer on the substrate to expose the first area includes: Step S204a - Step S204f.
[0095] Step S204a: Form a second nitride layer on at least the target oxide layer outside the reference area.
[0096] For example, please refer to Figure 11a and Figure 11b , the material of the second nitride layer 901 can include silicon nitride (Si3N4). Wherein, the film thickness of the second nitride layer 901 is less than the film thickness of the first nitride layer 702. In addition, the second nitride layer 901 can also cover the first nitride layer 702.
[0097] Step S204b: Form a third oxide layer covering the second nitride layer and the first nitride layer.
[0098] As an example, please continue to refer to Figure 11a and Figure 11b , the material of the third oxide layer 902 may include silicon dioxide (SiO2).
[0099] Step S204c: Form a second patterned photoresist layer on the third oxide layer. Among them, please refer to Figure 12a and Figure 12b , the second patterned photoresist layer 905 covers the third oxide layer 902 in the second region, exposing the third oxide layer 902 in the first region.
[0100] Step S204d: Remove the third oxide layer in the first region.
[0101] As an example, please refer to Figure 13a and Figure 13b , the material of the third oxide layer 902 may include silicon dioxide (SiO2), and one or more of wet etching and dry etching can be used to remove the third oxide layer 902.
[0102] Step S204e: Remove the second patterned photoresist layer and the third oxide layer directly under the second patterned photoresist layer.
[0103] As an example, please refer to 13a- Figure 15b , a chemical mechanical polishing process or an ashing reaction can be used to remove the second patterned photoresist layer 905, and wet etching or dry etching can be used to remove the third oxide layer 902. This application does not specifically limit the material and removal process of the second patterned photoresist layer 905, and it can be selected according to actual needs.
[0104] Step S204f: Remove the second nitride layer and the target oxide layer in the first region, exposing the substrate in the first region.
[0105] Please continue to refer to Figure 15a and Figure 15b , dry etching of the second nitride layer 901 can be performed using a fluoride such as HF, CF4, CHF3, CH2F2, or CH3F as an etching gas, and wet etching or dry etching can be used to remove the target oxide layer 80. The remaining first nitride layer 702 and second nitride layer 901 are used to jointly form the target dielectric layer 90. Among them, the target oxide layer 80 can be removed simultaneously with the third oxide layer, thereby saving process steps and improving economic efficiency.
[0106] In the above embodiments, by adopting a combination of a deposition process and a photolithography process, in the case of exposing the substrate in the first region, a film layer structure including a first oxide layer, a first nitride layer, and a second nitride layer is formed on the substrate of the reference region in the second region, and a film layer structure including a target oxide layer and a second nitride layer is formed on the substrate in the second region except for the reference region, so as to form a thick gate dielectric layer and a thin gate dielectric layer in the second region, which is convenient for forming a gate in the second region subsequently.
[0107] In one embodiment, forming a first semiconductor layer and a second semiconductor layer includes: a step of sequentially forming a germanium-silicon layer and a silicon layer on the substrate in the exposed first region by using an epitaxial growth process. Wherein, the first target element includes germanium, and the second target element includes silicon; the first semiconductor layer includes a germanium-silicon layer, and the second semiconductor layer includes a silicon layer.
[0108] As an example, please refer to Figure 16a and Figure 16b , SiCl4, SiH2Cl3, SiHCl3, SiH4, etc. can be used as silicon sources, and GeH4 can be used as a germanium source to form a germanium-silicon layer (the first semiconductor layer 50) on the substrate 10, and then a silicon layer (the second semiconductor layer 60) is formed on the germanium-silicon layer. Among them, the chlorine atoms in the silicon source can improve the activity of atoms, and the more the number of chlorine atoms, the better the selectivity. In addition, the greater the content of the first target element in the first semiconductor layer 50, the greater the stress generated, but if the content of the first target element is too large, it is easy to cause dislocation, which will instead affect the stress effect. Therefore, the content of the first target element cannot be too small or too large.
[0109] In the above embodiments, the lattice constant of germanium is 5.653 angstroms, and the lattice constant of silicon is 5.431 angstroms. The lattice constant of germanium is greater than that of silicon. By adding a germanium-silicon layer into the film layer structure of the source and drain, the germanium-silicon layer generates a lateral compressive stress on the channel, thereby reducing the conduction effective mass of holes in the channel direction, and further improving the switching speed of the transistor.
[0110] In one embodiment, forming a gate on at least the substrate exposed in the second region includes: a step of forming a protective layer on at least the first oxide layer in the second region, and forming a gate conductive layer on at least the protective layer and the target oxide layer. Wherein, the first oxide layer, the target oxide layer, the protective layer, and the gate conductive layer are used to jointly form a gate.
[0111] As an example, please refer to Figures 17a - 19b, the protective layer 20 can be made of a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 4). The gate conductive layer 40 can include, but is not limited to, any one or several of titanium nitride (TiN), titanium (Ti), tungsten silicide (Si2W), tungsten (W), and the like.
[0112] In the above embodiment, the protective layer 20 can protect the first oxide layer 701, prevent damage to the first oxide layer 701 during wet etching, and the dielectric constant of the protective layer is relatively high, which can effectively reduce the gate leakage current and prevent impurity diffusion.
[0113] In one embodiment, the protective layer includes a target nitride layer; forming the protective layer on the first oxide layer in at least the second region includes: forming a third patterned photoresist layer that exposes the first oxide layer in the second region, forming the target nitride layer on the exposed first oxide layer in the second region, and removing the third patterned photoresist layer.
[0114] As an example, the material of the target silicon nitride layer can include silicon nitride (Si3N4). This application does not specifically limit the material of the third patterned photoresist layer and the removal process, and can be selected according to actual needs.
[0115] In one embodiment, forming the gate further includes: after removing the third patterned photoresist layer, forming an interlayer oxide layer that at least covers the target nitride layer; forming a gate conductive layer on the interlayer oxide layer.
[0116] As an example, please refer to Figure 20 , the interlayer oxide layer 30 can be a multi-layer structure, including a fourth oxide layer 301 and a high-k dielectric layer 302. The gate conductive layer 40 can be a multi-layer structure, including a first titanium nitride layer 401, a metal layer 402, a second titanium nitride layer 403, and a polysilicon layer 404. In addition, the interlayer oxide layer 30 and the gate conductive layer 40 can be formed in a stacked manner on the target nitride layer, the target oxide layer, and the second semiconductor layer.
[0117] In the above embodiment, the material of the fourth oxide layer can include ion liquid enhanced silica (IL-SiO2) to reduce interface scattering, and the high-k dielectric layer 302 can use HfSiO2. Among them, the oxygen surrounded by Hf is easy to form oxygen vacancies. Using HfSiO2 with an increased silicon percentage as the high-k dielectric layer can effectively reduce the Fermi level pinning effect of the transistor.
[0118] In one embodiment, forming the interlayer oxide layer that at least covers the target nitride layer includes: forming the interlayer oxide layer that at least covers the target nitride layer by a deposition process.
[0119] As an example, please continue to refer to Figure 20 , a fourth patterned photoresist layer (not shown) that exposes a target nitride layer (not shown) in the second region is formed. An interlayer oxide layer 30 is formed on the exposed target nitride layer in the second region, and the fourth patterned photoresist layer is removed. Among them, the temperature for forming the interlayer oxide layer 30 is less than 800 degrees Celsius to avoid the diffusion of the first target element in the first semiconductor layer 50 into the second semiconductor layer 60 at high temperature, resulting in device damage.
[0120] It should be understood that although Figure 2 the steps in the flowchart of Figure 2 are shown in sequence according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, there is no strict order limit for the execution of these steps, and these steps can be executed in other orders. Moreover,
[0121] This application also provides a semiconductor structure prepared by using the preparation method of the semiconductor structure described in any one of the embodiments of this application.
[0122] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0123] The above embodiments only represent several implementation manners of this application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several deformations and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of the patent of this application should be subject to the appended claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that, Including: Providing a substrate, on which there are a first region and a second region for forming transistors; wherein, the first region is for forming source / drain, and the second region is for forming a gate; Forming a dielectric layer on the substrate within part of the second region; Forming a target oxide layer on the region of the substrate that is not covered by the dielectric layer at a preset temperature; Forming a target dielectric layer that exposes the substrate of the first region; Sequentially forming a first semiconductor layer including a first target element and a second semiconductor layer including a second target element on the exposed substrate of the first region, with the first semiconductor layer located between the substrate and the second semiconductor layer; the lattice constant of the first target element is greater than that of the second target element; Removing the target dielectric layer; Forming the gate at least on the exposed substrate of the second region.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein The preset temperature is 800°C - 1200°C; Forming the target oxide layer includes: At the preset temperature, using an epitaxial growth process to form the target oxide layer on the region of the substrate that is not covered by the dielectric layer.
3. The method for preparing a semiconductor structure according to claim 2, wherein, The first target element includes germanium, and the second target element includes silicon; the first semiconductor layer includes a germanium-silicon layer, and the second semiconductor layer includes a silicon layer; Forming the first semiconductor layer and the second semiconductor layer includes: Using an epitaxial growth process to sequentially form the germanium-silicon layer and the silicon layer on the exposed substrate of the first region.
4. The manufacturing method of the semiconductor structure according to any one of claims 1-3, characterized in that, The dielectric layer includes a first oxide layer and a first nitride layer; forming a dielectric layer on part of the second region includes: Forming on the substrate the first oxide layer, the first nitride layer, and a second oxide layer that are sequentially stacked in a direction away from the substrate; Forming a first patterned photoresist layer on the top surface of the second oxide layer within part of the second region; the first patterned photoresist layer covers a reference region of the substrate; Using the first patterned photoresist layer as a mask to etch and remove the second oxide layer; Removing the first patterned photoresist layer; Removing the first nitride layer on the region of the substrate except the reference region; Removing the first oxide layer on the region of the substrate except the reference region and the second oxide layer within the reference region, and the first oxide layer and the first nitride layer within the reference region are used to jointly form the dielectric layer.
5. The manufacturing method of the semiconductor structure according to claim 4, characterized in that, Forming a target dielectric layer on the substrate that exposes the first region includes: Forming a second nitride layer at least on the target oxide layer outside the reference region; Forming a third oxide layer that covers the second nitride layer and the first nitride layer; Forming a second patterned photoresist layer on the third oxide layer, with the second patterned photoresist layer exposing the third oxide layer of the first region; Removing the third oxide layer of the first region; Removing the second patterned photoresist layer and the third oxide layer directly below the second patterned photoresist layer; Removing the second nitride layer and the target oxide layer of the first region to expose the substrate of the first region; the remaining first nitride layer and the second nitride layer are used to jointly form the target dielectric layer.
6. The method for preparing a semiconductor structure according to claim 5, wherein, Forming the gate on at least the substrate exposed in the second region includes: Forming a protective layer on at least the first oxide layer in the second region; Forming a gate conductive layer on at least the protective layer and the target oxide layer, where the first oxide layer, the target oxide layer, the protective layer, and the gate conductive layer are used to jointly form the gate.
7. The method for manufacturing a semiconductor structure according to claim 6, wherein, The protective layer includes a target nitride layer; Forming a protective layer on at least the first oxide layer in the second region includes: Forming a third patterned photoresist layer that exposes the first oxide layer in the second region; Forming the target nitride layer on the exposed first oxide layer in the second region; Removing the third patterned photoresist layer.
8. The method for preparing a semiconductor structure according to claim 7, wherein Forming the gate further includes: After removing the third patterned photoresist layer, forming an interlayer oxide layer that at least covers the target nitride layer; Forming the gate conductive layer on the interlayer oxide layer.
9. The method for manufacturing a semiconductor structure according to claim 8, wherein, Forming an interlayer oxide layer that at least covers the target nitride layer includes: Forming an interlayer oxide layer that at least covers the target nitride layer by using a deposition process.
10. A semiconductor structure, characterized in that, Prepared by using the preparation method of the semiconductor structure according to any one of claims 1-9.