Method of forming semiconductor device and semiconductor structure

Abstract

A method of forming a semiconductor device includes forming a first fin in a first region, and forming a second fin in a second region, forming a first suspended nanostructure in the first fin, and forming a second suspended nanostructure in the second fin, forming a third semiconductor layer surrounding each second suspended nanostructure in the second fin, an annealing process is performed to incorporate a material contained in the third semiconductor layer into the second suspended nanostructure in the second fin such that a thickness of the second suspended nanostructure increases to greater than a thickness of the first suspended nanostructure, and a gate stack is formed surrounding each of the first suspended nanostructure and the second suspended nanostructure. The embodiment of the invention also provides a semiconductor structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to methods of forming semiconductor devices and semiconductor structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each of which has smaller and more complex circuits than the previous generation. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down of the process generally provides benefits by increasing production efficiency and reducing related costs. This scaling down also increases the complexity of processing and manufacturing ICs, and to achieve these advancements, similar progress in IC processing and manufacturing is required.

[0003] For example, multi-gate devices have been introduced by increasing gate-channel coupling to improve gate control, reduce off-state current, and reduce short-channel effects (SCEs). One such multi-gate device is the gate-all-around (GAA) transistor, in which vertically stacked semiconductor nanostructures serve as channel layers within the channel region of the GAA transistor, and a gate structure surrounds each semiconductor nanostructure, providing access to the channel region on all four sides. GAA transistors are compatible with traditional complementary metal-oxide-semiconductor (CMOS) processes, allowing them to be significantly scaled down while maintaining gate control and mitigating SCEs. In the context of CMOS devices, the n-type channel region and the p-type channel region share a gate structure. The semiconductor nanostructures in the n-type channel region and the p-type channel region typically have the same material composition (e.g., silicon) and the same thickness. However, n-type GAA transistors generally benefit from having thinner semiconductor nanostructures to improve short-channel control, and p-type GAA transistors generally benefit from having thicker semiconductor nanostructures to improve hole mobility. Accordingly, although existing CMOS processes generally meet their intended purposes, they are not entirely satisfactory in all respects. Summary of the Invention

[0004] Some embodiments of the present disclosure provide a method of forming a semiconductor device, the method comprising: providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed above the substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and are alternately disposed relative to each other in a vertical direction, and wherein each of the first semiconductor layers and the second semiconductor layers extends over a first region and a second region of the substrate; patterning the first semiconductor layers and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first fin and the second fin such that a first portion of the patterned second semiconductor layer becomes a first suspended nanostructure in the first fin and a second portion of the patterned second semiconductor layer becomes a second suspended nanostructure in the second fin; forming a third semiconductor layer surrounding each of the second suspended nanostructures in the second fin, wherein the second semiconductor layer and the third semiconductor layer have different material compositions; performing an annealing process to incorporate the material contained in the third semiconductor layer into the second suspended nanostructures in the second fin such that the thickness of the second suspended nanostructures increases to be greater than the thickness of the first suspended nanostructures; and forming a gate stack surrounding each of the first suspended nanostructures and the second suspended nanostructures.

[0005] Some other embodiments of the present disclosure provide a method of forming a semiconductor device, the method comprising: forming a sacrificial gate structure over the channel regions of a first fin and a second fin; removing the sacrificial gate structure to expose the channel regions of the first fin and the second fin; removing a sacrificial layer from the first fin and the second fin to form a plurality of first suspended layers in the first fin and a plurality of second suspended layers in the second fin, wherein the first suspended layers and the second suspended layers comprise the same first semiconductor material; forming a mask covering the first suspended layers; performing a doping process to introduce a second semiconductor material different from the first semiconductor material into the second suspended layers while the mask covers the first suspended layers; removing the mask; performing an annealing process after removing the mask to adjust the distribution of the second semiconductor material in the second suspended layers; and forming a metal gate stack surrounding each of the first suspended layers and the second suspended layers.

[0006] Another embodiment of the present disclosure provides a semiconductor structure, the semiconductor structure comprising: a substrate; a first nanostructure suspended above the substrate and longitudinally extending in a first direction; a second nanostructure suspended above the substrate and longitudinally extending in the first direction; a gate stack bonded to the first nanostructure to form an n-type transistor and bonded to the second nanostructure to form a p-type transistor, wherein in a top view of the semiconductor structure, the gate stack longitudinally extends in a second direction perpendicular to the first direction; and a gate spacer disposed on sidewalls of the gate stack, wherein in a first cross-section cut along the second direction and perpendicular to the top surface of the substrate, the gate stack surrounds the first nanostructure and the second nanostructure, and the second nanostructure is thicker than the first nanostructure and comprises a material composition different from that of the first nanostructure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart illustrating an exemplary method for manufacturing a semiconductor device in accordance with some embodiments of the present disclosure is shown.

[0009] Figure 2 、 Figure 3 、 Figure 4 and Figure 5 A cross-sectional view of an exemplary semiconductor device in accordance with some embodiments of the present disclosure is shown.

[0010] Figure 6 A perspective view of an exemplary semiconductor device in accordance with some embodiments of the present disclosure is shown.

[0011] Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 、 Figure 21 、 Figure 22 、 Figure 23 、 Figure 24 、 Figure 26 、 Figure 27 、 Figure 28 、 Figure 29 、 Figure 30and Figure 31 shows an exemplary cross-sectional view of a semiconductor device at an intermediate stage of an embodiment of a method according to some embodiments of the present disclosure. Figure 1

[0012] Figure 25A and Figure 25B shows an exemplary concentration profile in a p-type channel layer of a semiconductor device according to some embodiments of the present disclosure.

[0013] Figure 32 shows an exemplary top view of a semiconductor device at the end of an embodiment of a method according to some embodiments of the present disclosure. Figure 1

[0014] Figure 33 shows a layout of a memory macro of an exemplary semiconductor device implementing as Figure 32 shown according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing different components of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0016] Moreover, in the following disclosure, a component formed on, connected to, and / or coupled to another component may include embodiments where the components are in direct contact, and may also include embodiments where additional components may be inserted between the components such that the components may not be in direct contact. Additionally, spatial relative terms such as "lower", "upper", "horizontal", "vertical", "above", "over", "below", "beneath", "upward", "downward", "top", "bottom", etc., and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used to facilitate an understanding of the relationship between one component and another component of embodiments of the disclosure. The spatial relative terms are intended to cover different orientations of devices including the components. Still further, when a numerical value or numerical range is described with "about", "approximately", etc., the term is intended to cover values within a reasonable range including the recited value, such as within + / - 10% of the recited value or other values understood by those skilled in the art. For example, the term "about 5 nm" covers a size range from 4.5 nm to 5.5 nm.

[0017] The present disclosure generally relates to semiconductor devices and methods of manufacturing the same, and more particularly to the formation of channels in n-type and p-type gate-all-around (GAA) transistors in complementary metal-oxide-semiconductor (CMOS) devices.

[0018] A GAA transistor includes any device in which its gate structure or a portion thereof is formed on four sides of a channel region (e.g., surrounding a channel layer in the channel region). GAA transistors can be used to implement n-type and p-type transistors placed close to each other and sharing the same gate structure, which is commonly referred to as a dual transistor in the CMOS context. The channel region of an n-type GAA transistor having a channel layer in the form of vertically stacked semiconductor nanostructures (or simply referred to as nanostructures), and its corresponding structure in a p-type GAA transistor, are also referred to as a dual-channel region. The vertically stacked nanostructures can be in the form of nanosheets, nanowires, bars, and / or other suitable configurations. Embodiments of devices having one or more channel layers (e.g., nanosheets) associated with a single continuous gate structure are described herein. However, those of ordinary skill in the art will recognize that the teachings can be applied to a single channel layer or any number of channel layers. Those of ordinary skill in the art can recognize other examples of semiconductor devices that may benefit from aspects of the present disclosure, such as semiconductor devices other than CMOS devices.

[0019] In an n-type GAA transistor, a thinner channel layer and correspondingly a smaller nanostructure thickness (or, if the nanostructure is in the form of nanosheets, the sheet thickness) generally facilitate better short-channel control in the n-type transistor. In a p-type GAA transistor, a thicker channel layer and correspondingly a larger nanostructure thickness generally facilitate better hole mobility in the p-type transistor. Additionally, forming nanostructures in n-type and p-type transistors from different semiconductor materials allows for the performance of transistors of opposite conduction types to be optimized separately. However, existing semiconductor manufacturing processes typically result in nanostructures in the dual-channel regions of CMOS devices having the same material composition (e.g., silicon) and the same thickness.

[0020] The present disclosure solves the above problems by providing an improved channel formation method for forming a dual-channel region in a CMOS device. According to some embodiments, after growing a stack of alternating first semiconductor layers (e.g., silicon germanium) and second semiconductor layers (e.g., silicon), the method directly patterns the stack to create a first fin and a second fin, and then removes the first semiconductor layer to create suspended nanostructures (e.g., nanowires or nanosheets) in the dual-channel region. The method wraps the suspended nanostructures in the p-type transistor with a thin semiconductor layer (e.g., silicon germanium), and then performs an annealing process to drive germanium into the suspended nanostructures in the p-type transistor. In an example, germanium atoms are driven from the silicon germanium layer into the nanostructures made of silicon. Thus, the exemplary method converts the channel layer in the p-type transistor into a semiconductor compound different from the channel layer with a larger sheet thickness in the n-type transistor. As a result, the dual-channel region can be optimized for both n-type and p-type transistors in a simplified manufacturing process.

[0021] Figure 1 FIG. 7 is a flowchart of a method 100 for forming a semiconductor device structure 200 (or device 200) in accordance with various aspects of the present disclosure. Method 100 is merely an example and is not intended to limit the present disclosure beyond the scope expressly recited in the claims. Additional operations may be provided before, during, and after method 100, and for additional embodiments of the method, some of the operations described may be replaced, eliminated, or moved. As with the exemplary devices and methods discussed herein, it will be understood that portions of device 200 may be fabricated through a CMOS technology process flow, and thus only some processes are briefly described herein. Additionally, the exemplary device may include various other devices and components, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memories (SRAMs), and / or other logic circuits, etc., but the exemplary device has been simplified for a better understanding of the inventive concept of the present disclosure.

[0022] The following will be combined with Figures 2 to 33 descriptionFigure 1 Note that the process steps of method 100, including any description given with reference to Figures 2 to 33 are merely exemplary, like the rest of the method and the exemplary Figure 1 provided in this disclosure, and are not intended to limit beyond what is specifically recited in the appended claims. Figures 2 to 5 is a cross-sectional view of device 200 at various stages of manufacturing according to method 100. Figure 6 is a perspective view of device 200 at an intermediate stage of manufacturing according to method 100. Figures 7 to 24 and Figures 26 to 31 are cross-sectional views of device 200 at various other stages of manufacturing according to method 100 Figure 6 in (also as Figure 32 shown). Figure 25A and Figure 25B show an exemplary germanium concentration profile in the p-type channel layer of device 200. Figure 32 is a top view of device 200 at the end of method 100. Figure 33 shows an embodiment of device 200 as part of a memory macro.

[0023] At operation 102, method 100 ( Figure 1 ) provides substrate 202, as Figure 2 shown. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. In some embodiments, substrate 202 includes a single-crystalline semiconductor layer at least on its surface portion. Substrate 202 may include a single-crystalline semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Optionally, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Substrate 202 may include various layers, including a conductive layer or an insulating layer formed on the semiconductor substrate. Substrate 202 is at Figure 2It is divided into regions 204 and 206 by a dashed line. In some embodiments, two or more transistors are formed in and / or above regions 204 and 206 of the substrate 202. In some embodiments, an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) are formed in and / or above regions 204 and 206, respectively. Thus, in the present disclosure, region 204 is also referred to as NFET region 204, and region 206 is also referred to as PFET region 206. Depending on the design requirements known in the art, regions 204 and 206 may include various doping configurations. For example, different doping profiles (e.g., a p-well in region 204 and an n-well in region 206) may be formed in the respective regions designed for different device types (e.g., NFET or PFET). Appropriate doping may include ion implantation and / or diffusion processes of dopants, such as boron (B) for forming a p-well in region 204 and phosphorus (P) for forming an n-well in region 206).

[0024] At operation 104, method 100 ( Figure 1 ) forms one or more epitaxial layers over the substrate 202, as Figure 3 shown. In some embodiments, an epitaxial stack 212 is formed over regions 204 and 206. The epitaxial stack 212 includes an epitaxial layer 214 of a first component that is interleaved with an epitaxial layer 216 of a second component. The first and second components may be different. In an embodiment, the epitaxial layer 214 is SiGe, and the epitaxial layer 216 is silicon. However, other embodiments are possible, including those that provide first and second components with different oxidation rates and / or etching selectivities. In some embodiments, the epitaxial layer 214 includes SiGe, and in the case where the epitaxial layer 216 includes silicon, the silicon oxidation rate is less than the SiGe oxidation rate. It should be noted that four (4) layers of each of the epitaxial layers 214 and 216 are shown in Figure 3 , which is for illustrative purposes only and is not intended to limit beyond the scope specifically recited in the claims. It can be understood that any number of epitaxial layers may be formed in the epitaxial stack 212; however, the number of layers depends on the desired number of channel layers of the device 200. In some embodiments, the number of epitaxial layers 216 is between 2 and 10, such as 3 or 4.

[0025] In some embodiments, the thickness of the epitaxial layer 214 is in the range of about 4.5 nm to about 15 nm. The thickness of the epitaxial layer 214 can be substantially uniform. In some embodiments, the thickness of the epitaxial layer 216 is in the range of about 3 nm to about 8 nm. In some embodiments, the thickness of the epitaxial layer 216 of the stack is substantially uniform. As described in more detail below, the epitaxial layer 216 can serve as the channel layer of a subsequently formed GAA transistor, and its thickness is selected based on device performance considerations. The epitaxial layer 214 can be used to provide a pitch (or gap) between adjacent channel layers of a subsequently formed GAA transistor, and its thickness is selected based on device performance considerations.

[0026] For example, the epitaxial growth of the epitaxial stack 212 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer, such as the epitaxial layer 216, includes the same material as the substrate 202, such as silicon (Si). In some embodiments, the epitaxial growth layers 214 and 216 include materials different from the substrate 202. As described above, in at least some instances, the epitaxial layer 214 includes an epitaxially grown Si 1-x Ge x layer (e.g., x is about 25% to 55%), and the epitaxial layer 216 includes an epitaxially grown Si layer. Optionally, in some embodiments, either the epitaxial layer 214 or 216 can include other materials, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP, or combinations thereof. As discussed, the materials of the epitaxial layers 214 and 216 can be selected based on providing different oxidation and etch selectivity characteristics. In various embodiments, the epitaxial layers 214 and 216 are substantially free of dopants, where, for example, no intentional doping is performed during the epitaxial growth process.

[0027] At operation 106, method 100 ( Figure 1 ) patterns the epitaxial stack 212 to form fins 220-1 and 220-2 (collectively fins 220), as Figure 4As shown. In the illustrated embodiment, the top of the patterned substrate 202 is also patterned. In various embodiments, each fin 220 includes an upper portion of the interleaved epitaxial layers 214 and 216 and a bottom portion protruding from the substrate 202. The bottom portion protruding from the substrate 202 is also referred to as the fin-shaped base 215 or the mesa 215. In some embodiments, operation 106 includes forming a mask layer 218 over the epitaxial stack 212. The mask layer 218 includes a first mask layer 218A and a second mask layer 218B. In some embodiments, the first mask layer 218A is a pad oxide layer made of silicon oxide, and the first mask layer 218A can be formed by thermal oxidation; the second mask layer 218B is made of silicon nitride (SiN) and is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes including low-pressure CVD (LPCVD) and plasma-enhanced CVD (PECVD). A patterning operation including photolithography and etching is used to pattern the mask layer 218 into a mask pattern.

[0028] In some embodiments, operation 106 uses a suitable process including a double patterning or multiple patterning process to pattern the epitaxial stack 212. Generally, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thus allowing the creation of patterns with smaller pitch, for example, than those obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over the substrate, and the material layer is patterned using a photolithography process. A spacer is formed adjacent to the patterned material layer using a self-alignment process. Then the material layer is removed, and then the remaining spacer or mandrel can be used to pattern the epitaxial stack 212 in an etching process (such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes) by defining openings in the patterned mask layer 218. Thus, the stacked epitaxial layers 214 and 216 are patterned into fins 220 with trenches between adjacent fins. Each fin 220 protrudes upward from the substrate 202 in the Z direction and extends longitudinally in the Y direction. In Figure 4 this example, two (2) fins 220 are spaced apart in the X direction, with one fin disposed over the NFET region 204 and one fin disposed over the PFET region 206. However, the number of fins is not limited to two and can be as small as one or more than two.

[0029] At operation 108, method 100 ( Figure 1 ) fills the trenches between adjacent fins 220 with a dielectric material to form an isolation component 222, as Figure 5As shown. The isolation component 222 may include one or more dielectric layers. Suitable dielectric materials for the isolation component 222 may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material may be deposited by any suitable technique including thermal growth, CVD, HDP-CVD, PVD, ALD, and / or spin coating techniques. At operation 108, method 100 then recesses the isolation component 222 to form a shallow trench isolation (STI) component (also denoted as STI component 222). In the illustrated embodiment, the STI component 222 is disposed on the sidewalls of the protruding portions of the substrate 202. The top surface of the STI component 222 may be coplanar with the bottom surface of the epitaxial stack 212, or about 1 nm to about 10 nm lower than the bottom surface of the epitaxial stack 212. Any suitable etching technique may be used to recess the isolation component 222, including dry etching, wet etching, RIE, and / or other etching methods, and in an exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation component 222 without etching the fins 220. The mask layer 218 may also be removed before, during, and / or after the recessing of the isolation component 222. In some embodiments, the mask layer 218 is removed by a CMP process performed before the recessing of the isolation component 222. In some embodiments, the mask layer 218 is removed by using an etchant that recesses the isolation component 222.

[0030] At operation 110, method 100 ( Figure 1 ) forms sacrificial (dummy) gate structures 224-1, 224-2, 224-3, and 224-4 (collectively referred to as sacrificial gate structure 224), as Figure 6As shown. It can be understood that any number of sacrificial gate structures can be formed at operation 110. Each sacrificial gate structure 224 is formed over a portion of the fin 220 that will become the channel region. The sacrificial gate structure 224 defines the channel region of the GAA transistor. The sacrificial gate structure 224 includes a sacrificial gate dielectric layer 226 and a sacrificial gate electrode layer 228. The sacrificial gate structure 224 is formed by first blanket depositing the sacrificial gate dielectric layer 226 over the fin 220. Then, the sacrificial gate electrode layer 228 is blanket deposited over the sacrificial gate dielectric layer 226 and over the fin 220. The sacrificial gate electrode layer 228 includes silicon, such as polysilicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer is in the range of about 1 nm to about 5 nm. In some embodiments, the thickness of the sacrificial gate electrode layer is in the range of about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer is subjected to a planarization operation. CVD, PVD, ALD, or other suitable processes including LPCVD and PECVD are used to deposit the sacrificial gate dielectric layer 226 and the sacrificial gate electrode layer 228. Subsequently, a mask layer 230 is formed over the sacrificial gate electrode layer. The mask layer 230 may include a pad oxide layer 230A and a silicon nitride mask layer 230B. Subsequently, a patterning operation is performed on the mask layer 230, and the sacrificial gate dielectric layer and the sacrificial gate electrode layer are patterned into the sacrificial gate structure 224. By patterning the sacrificial gate structure 224, the fin 220 is partially exposed on opposite sides of each sacrificial gate structure 224, thereby defining the source / drain (S / D) regions. In the present disclosure, the source / drain regions may refer to the source or the drain individually or collectively, depending on the context.

[0031] At operation 112, method 100( Figure 1 ) forms gate sidewall spacers 232 on the sidewalls of the sacrificial gate structures 224, as Figure 7 shown, Figure 7 is a cross-sectional view along the length direction of one of the fins 220 (line A - A in Figure 6 ). The cross-sectional view along the length direction of the other fin 220 is similar to Figure 7The content shown in [reference] is omitted here for simplicity. The gate sidewall spacer 232 also covers a portion of the top surface of the fin 220. The gate sidewall spacer 232 may include a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, the gate sidewall spacer 232 includes multiple layers such as a main spacer wall, a liner layer, etc. For example, a dielectric material layer can be deposited over the sacrificial gate structure 224 using processes such as CVD process, sub-atmospheric CVD (SACVD) process, flowable CVD process, ALD process, PVD process, or other suitable processes to form the gate sidewall spacer 232. In some embodiments, after the deposition of the dielectric material layer, an etch-back (e.g., anisotropic) process is performed to expose the portions of the fin 220 adjacent to the sacrificial gate structure 224 and not covered by the sacrificial gate structure 224 (e.g., the S / D regions). The dielectric material layer remains on the sidewalls of the sacrificial gate structure 224 as the gate sidewall spacer 232. In some embodiments, the etch-back process may include a wet etch process, a dry etch process, a multi-step etch process, and / or combinations thereof. The gate sidewall spacer 232 may have a thickness in the range of about 5 nm to about 20 nm.

[0032] At operation 114, method 100 ( Figure 1 ) recesses portions of the fin 220 to form a trench 234 in the S / D regions, as Figure 8 shown, Figure 8 which is a cross-sectional view along the A-A line of the device 200 in Figure 6 . The stacked epitaxial layers 214 and 216 are etched downward at the S / D regions. In the illustrated embodiment, the top of the substrate 202 is also etched. In some embodiments, at operation 114, method 100 forms the trench 234 through a suitable etch process such as a dry etch process, a wet etch process, or an RIE process. The etch process at operation 114 can implement a dry etch process using an etchant including a bromine-containing gas (e.g., HBr and / or CHBR3), a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), other suitable gases, or combinations thereof.

[0033] At operation 116, method 100 ( Figure 1 ) forms an inner spacer directly under the gate sidewall spacer 232. In some embodiments, operation 116 first laterally etches the epitaxial layer 214 in the y direction to form a cavity 236, as Figure 9 shown, Figure 9 which is a cross-sectional view along Figure 6Cross-sectional view of line A-A of device 200 in []. In some embodiments, the etch amount of epitaxial layer 214 is in the range of about 1 nm to about 4 nm. The epitaxial layer 214 can be selectively etched by using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution. Optionally, at operation 116, method 100 can first selectively oxidize the lateral ends of the epitaxial layer 214 exposed in the groove 234 to increase the etch selectivity between the epitaxial layers 214 and 216. In some instances, the oxidation process can be performed by exposing device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof.

[0034] Subsequently, at operation 116, method 100 forms an internal spacer material layer 238 on the lateral ends of the epitaxial layer 214, as well as on the epitaxial layer 216 in the cavity 236 and in the groove 234, as Figure 10 shown. Figure 10 along Figure 6 is a cross-sectional view of line A-A of device 200 in []. The internal spacer material layer 238 can include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbide, carbon oxynitride, and / or other suitable dielectric materials. In some embodiments, the internal spacer material layer 238 is deposited as a conformal layer. The internal spacer material layer 238 can be formed by ALD or any other suitable method. By conformally forming the internal spacer material layer 238, the size of the cavity 236 is reduced or completely filled.

[0035] After forming the internal spacer material layer 238, an etching operation is performed to partially remove the internal spacer material layer 238, as Figure 11 shown. Figure 11 along Figure 6 is a cross-sectional view of line A-A of device 200 in []. By this etching, since the volume of the cavity is small, the internal spacer material layer 238 remains substantially within the cavity 236. Generally, plasma dry etching etches layers in wide and flat areas faster than layers in recessed (e.g., holes, notches, and / or slits) portions. Thus, the internal spacer material layer 238 can remain inside the cavity 236. The remaining portion of the internal spacer material layer 238 is denoted as the internal spacer 238.

[0036] At operation 118, method 100 ( Figure 1 ) forms an epitaxial S / D component 240 in the groove 234, as Figure 12 shown. Figure 12 along Figure 6Cross-sectional view of line A-A of device 200 in []. In some embodiments, the epitaxial S / D component 240 of the NFET may include silicon, and the epitaxial S / D component 240 of the PFET may include SiGe. In some embodiments, the epitaxial S / D components 240 of both the NFET and the PFET may include silicon. The epitaxial S / D component 240 of the NFET may be doped with dopants such as arsenic (As) or phosphorus (P), and the epitaxial S / D component 240 of the PFET may be doped with dopants such as germanium (Ge) or boron (B). In some embodiments, the epitaxial S / D component 240 is formed by an epitaxial growth method such as vapor phase epitaxy (VPE), CVD, ALD, or molecular beam epitaxy (MBE). The epitaxial S / D component 240 is formed to contact the epitaxial layer 216, and the epitaxial S / D component 240 is separated from the epitaxial layer 214 by an internal spacer 238. In some embodiments, the cavity 236 is not filled with the internal spacer material 238, but is covered by the epitaxial S / D component 240. Therefore, the covered cavity 236 is also referred to as an "air spacer".

[0037] Figure 13 An optional resulting structure at the end of operation 118 is shown Figure 13 is along Figure 6 Cross-sectional view of line A-A of device 200 in []. Figure 12 and Figure 13Many aspects of the device 200 shown are the same. One difference is that a dielectric film 242 is deposited in the bottom of the trench 234 and over the substrate 202. In some embodiments, the dielectric film 242 may include a metal oxide or a metal nitride, such as La2O3, Al2O3, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Y2O3, AlON, TaCN, other suitable materials, or combinations thereof. In some embodiments, the dielectric film 242 may include silicon oxide, silicon carbonitride, silicon nitride, silicon oxynitride, silicon oxycarbide, carbon-rich silicon carbonitride, or a low-k dielectric material. The dielectric film 242 is selected to have an etch selectivity different from that of the inner spacer 238, thereby allowing the dielectric film 242 to be formed by a directed deposition and etch-back process without causing etch loss to the inner spacer 238. The dielectric film 242 may include a single layer or multiple layers. In some embodiments, the dielectric film 242 has a thickness in the range of about 1 nm to about 30 nm. The dielectric film 242 partially covers the sidewalls of the bottommost inner spacer 238. The dielectric film 242 separates the epitaxial S / D component 240 from the substrate 202 and prevents contact with the substrate 202, thereby improving the suppression of leakage current from the S / D region to the substrate. In some embodiments, the space reserved for the dielectric film 242 is replaced by an "air cavity". The air cavity also separates the epitaxial S / D component 240 from the substrate 202 and prevents contact with the substrate 202, or at least reduces the contact area between the epitaxial S / D component 240 and the substrate 202, which also improves the suppression of leakage current from the S / D region to the substrate. In some embodiments, the dielectric film 242 is formed in the trenches 234 in both the NFET region 204 and the PFET region 206. In some embodiments, the dielectric film 242 is formed only in the trenches 234 in the NFET region 204 and not in the trenches 234 in the PFET region 206. The absence of the dielectric film 242 in the PFET region 206 allows the epitaxial S / D component 240 subsequently formed in the PFET region 206 to extend down into the substrate 202 and benefit from better strain performance due to its greater depth and greater volume compared to the corresponding structure in the NFET region 204.

[0038] Figure 14 An optional resulting structure at the end of operation 118 is shown, Figure 14 is a cross-sectional view along Figure 6 the A-A line of the device 200 in Figure 14 and Figure 13Many aspects of the device 200 shown in [Figure] are the same. One difference is that a buffer epitaxial layer 244 is deposited in the bottom of the trench 234 and stacked between the substrate 202 and the subsequently formed dielectric film 242. The buffer epitaxial layer 244 grows epitaxially from the trench 234. For example, the epitaxial growth of the buffer epitaxial layer 244 can be performed by VPE, ultra-high vacuum CVD (UHV-CVD), MBE, and / or other suitable epitaxial growth processes. In some embodiments, the buffer epitaxial layer 244 includes the same material as the substrate 202, such as silicon. In some alternative embodiments, the buffer epitaxial layer 244 includes a semiconductor material different from the silicon substrate 202, such as SiGe, SiSn, or other suitable semiconductor materials. In some embodiments, the buffer epitaxial layer 244 does not contain dopants. For example, no intentional doping is performed during the epitaxial growth process. By comparison, in one example, the substrate 202 is lightly doped and has a higher doping concentration than the buffer epitaxial layer 244. The buffer epitaxial layer 244 provides a high-resistance path from the S / D regions to the semiconductor substrate, so that the leakage current in the semiconductor substrate is suppressed. In some embodiments, the dielectric film 242 disposed on the buffer epitaxial layer 244 has a thickness in the range of about 1 nm to about 30 nm.

[0039] At operation 120, method 100 ( Figure 1 ) forms a contact etch stop layer (CESL) 246 over the epitaxial S / D component 240 and forms an interlayer dielectric (ILD) layer 248 over the CESL layer 246, as Figure 15 shown, Figure 15 is a cross-sectional view along the Figure 6 A-A line of the device 200 in [Figure]. It should be understood that the various configurations in the S / D regions shown in Figure 12 , Figure 13 and Figure 14 are equally applicable during subsequent operations of method 100. However, for simplicity and clarity, it will be described in Figure 12The subsequent operations of method 100 are discussed in the context of the illustrated embodiments. The CESL layer 246 may include silicon nitride, silicon oxynitride, silicon nitride having oxygen (O) or carbon (C) elements, and / or other materials; and the CESL layer 246 may be formed by CVD, PVD (Physical Vapor Deposition), ALD, or other suitable methods. The ILD layer 248 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 248 may be formed by PECVD, flowable CVD (FCVD), or other suitable methods. In some embodiments, forming the ILD layer 248 further includes performing a CMP process to planarize the top surface of the device 200 such that the top surface of the sacrificial gate structure 224 is exposed.

[0040] At operation 122, method 100 ( Figure 1 ) removes the sacrificial gate structure 224 to form a gate trench 254, as Figure 16 shown, Figure 16 which is a cross-sectional view along the Figure 6 A - A line of the device 200 in

[0041] The gate trench 254 exposes the fins 220 in the channel region. During the removal of the sacrificial gate structure 224, the ILD layer 248 and the CESL layer 246 protect the epitaxial S / D components 240. The sacrificial gate structure 224 can be removed using plasma dry etching and / or wet etching. When the sacrificial gate electrode layer is polysilicon and the ILD layer 248 is an oxide, a wet etchant (such as a TMAH solution) can be used to selectively remove the sacrificial gate electrode layer. Then, plasma dry etching and / or wet etching are used to remove the sacrificial gate dielectric layer. Figure 1 At operation 124, method 100 ( Figure 17 ) releases the channel layer (or referred to as the channel member) from the channel region of the GAA transistor, as Figure 17 shown, Figure 6Cross-sectional view of line A-A of device 200 in []. In the illustrated embodiment, the channel layer is an epitaxial layer 216 in the form of a nanostructure, particularly in the form of nanosheets in the illustrated embodiment. It can be understood that the nanostructure can be nanowires, strips, or other suitable shapes. In the present embodiment, the epitaxial layer 216 includes silicon, and the epitaxial layer 214 includes silicon germanium. A plurality of epitaxial layers 214 can be selectively removed. In some embodiments, the selective removal process includes using a suitable oxidant (such as ozone) to oxidize the plurality of epitaxial layers 214. Thereafter, the oxidized epitaxial layer 214 can be selectively removed from the gate trench 254. To further implement this embodiment, operation 124 includes a dry etching process to selectively remove the epitaxial layer 214, for example, by applying HCl gas at a temperature of about 500 degrees Celsius to about 700 degrees Celsius, or by applying a gas mixture of CF4, SF6, and CHF3. For simplicity and clarity, after operation 124, the epitaxial layer 216 is represented as nanostructure 216 or nanosheet 216.

[0042] At the end of operation 124, two sets of vertically stacked nanostructures 216 are formed respectively above regions 204 and 206, as Figure 18 shown, Figure 18 is a cross-sectional view of line B-B of device 200 in Figure 6 []. Along the X direction, the nanostructures 216 in fin 220-1 and the nanostructures 216 in fin 220-2 are sandwiched between two opposing gate end dielectric components 256. In some embodiments, the gate end dielectric component 256 can be a multi-layer structure, and the multi-layer structure includes a gate sidewall spacer 232, a CESL layer 246, and an ILD layer 248. The gate end dielectric component 256 isolates the subsequently formed n-type and p-type GAA transistors, which are double transistors in a CMOS device, from other adjacent devices. In the present embodiment, the nanostructures 216 in fin 220-1 above region 204 are used to form an n-type GAA transistor, and the nanostructures 216 in fin 220-2 above region 206 are used to form a p-type GAA transistor. This configuration is for illustrative purposes only and does not limit the present disclosure. In some embodiments, each nanostructure 216 has a channel thickness (denoted as T1) of about 3 nm to about 8 nm, and is spaced apart from adjacent nanosheets by a channel pitch (denoted as S1) of about 4.5 nm to about 15 nm. In some embodiments, the vertical channel pitch (denoted as P, where P = T1 + S1) is about 8 nm to about 24 nm.

[0043] At operation 126, method 100 ( Figure 1 ) forms a patterned mask 258 in the gate trench 254, as Figure 19 shown, Figure 19 is along Figure 6Cross-sectional view of line B-B of device 200 in []. The patterned mask 258 covers the nanostructures 216 in fin 220-1 in the NFET region 204 and includes an opening that exposes the nanostructures 216 in fin 220-2 in the PFET region 206. In one embodiment, the patterned mask 258 is a soft mask, such as a patterned resist layer. In one embodiment, the patterned mask 258 includes a hard mask (instead of a soft mask). In some instances, the hard mask includes silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, other semiconductor materials, and / or other dielectric materials. The hard mask can be formed by thermal oxidation, CVD, ALD, or any other suitable method. Any suitable method can be used to pattern the hard mask, such as a lithography process, which can include forming a resist layer on the hard mask, exposing the resist by a lithographic exposure process, performing a post-exposure bake process, developing the photoresist layer to form a patterned photoresist layer that exposes portions of the hard mask, patterning the hard mask, and finally removing the patterned resist layer. The lithography process can optionally be replaced by other suitable techniques, such as electron beam writing, ion beam writing, maskless patterning, or molecular printing.

[0044] At operation 128, method 100 ( Figure 1 ) performs a trimming process on the nanostructures 216 in fin 220-2, as Figure 20 shown, Figure 20 which is a cross-sectional view of line B-B of device 200 in Figure 6 [].

[0045] Figure 20 The rectangular box with a dashed line in [] represents the shape of the nanostructures 216 before the trimming process for comparison. The trimming process is configured to thin the thickness of the nanostructures 216 to increase the channel spacing between adjacent nanostructures 216. The increased channel spacing facilitates the deposition of a semiconductor layer to surround the nanostructures 216 in fin 220-2 in subsequent operations. The trimming process can use any suitable etching process, such as dry etching, wet etching, and / or RIE. The trimming process can also reduce the width of the nanostructures 216 in fin 220-2. Due to partial etching, the trimmed nanostructures 216 can also have rounded corners instead of substantially right angles in the previous rectangular shape. In some embodiments, operation 128 can be optional, and method 100 can skip operation 128.

[0046] At operation 130, method 100 forms a semiconductor layer 260 that surrounds each nanostructure 216 in fin 220-2, as Figure 21 shown, Figure 21 which is a cross-sectional view along Figure 6Cross-sectional view of the B-B line of the device 200 in. Since the semiconductor layer 260 is used to convert the channel region in the PFET region 206 from the first type (e.g., n-type) to the second type (e.g., p-type), the semiconductor layer 260 has a different composition from the semiconductor material in the nanostructure 216. In various embodiments, the composition of the semiconductor layer 260 provides a different oxidation rate and / or different etching selectivity from the semiconductor material in the nanostructure 216. In an embodiment, the semiconductor layer 260 includes silicon germanium (Si 1-x Ge x ), while the nanostructure 216 in the fins 220-1 and 220-2 includes silicon (Si). In some embodiments, the semiconductor layer 260 includes Si 1-x Ge x , Si 1-x Ge x including Ge with a molar ratio of about 10% to about 100% (0.1 ≤ x ≤ 1). A sufficient amount of Ge in the semiconductor layer 260 helps to convert the channel region in the fin 220-2 from the first type (e.g., n-type) to the second type (e.g., p-type). For example, Ge can include Si 1-x Ge x with a molar ratio of about 60% to about 80%. This range of Ge in combination with subsequent processing steps effectively converts the channel region in the PFET region 206 from the first type to the second type.

[0047] In some embodiments, the semiconductor layer 260 is epitaxially grown from the semiconductor surface of the nanostructure 216 in the fin 220-2. For example, the semiconductor layer 260 can be grown by VPE, ultra-high vacuum CVD (UHV-CVD), MBE, and / or other suitable epitaxial growth processes. The epitaxial growth method allows the materials in the semiconductor layer 260 to form a lattice consistent with the materials in the nanostructure 216. In some embodiments, the semiconductor layer 260 is a conformal layer with a substantially uniform thickness. In some embodiments, the semiconductor layer 260 can have a thickness of about 2 nm to about 5 nm. In some embodiments, the thickness ratio between the surrounded nanostructure 216 and the surrounding semiconductor layer 260 is about 2:1 to about 10:1. In other words, the semiconductor layer 260 is thinner than its corresponding nanostructure 216. Such a thickness ratio provides an appropriate amount of germanium required to convert the channel region in the PFET region 206 from n-type to p-type. As Figure 21 shown, the semiconductor layer 260 can also be epitaxially grown from the semiconductor surface (top surface and sidewall surface) of the fin base 215 in the PFET region 206. Accordingly, at the end of operation 132, the top surface of the fin base 215 in the PFET region 206 can be higher than the top surface of the fin base 215 in the NFET region 204.

[0048] At operation 132, method 100 removes the patterned mask 258 from the gate trench 254, as Figure 22 shown, Figure 22 is a cross-sectional view along the B-B line of the device 200 in Figure 6 . Any suitable removal process can be used, including dry etching, wet etching, and / or reactive ion etching (RIE).

[0049] At operation 134, method 100 performs an annealing process to drive the germanium contained in the semiconductor layer 260 into each of the surrounded nanostructures 216 in the fin 220-2. The resulting structure is as Figure 23 and Figure 24 shown. Figure 23 is a cross-sectional view along the B-B line of the device 200 in Figure 6 (which is also the B-B line in Figure 24 ), and Figure 24 is a cross-sectional view along the A-A line of the device in Figure 6 (which is also the A-A line in Figure 23 ). In some embodiments, the device 200 is exposed to a gas containing nitrogen (N), phosphorus, or other suitable elements. To avoid oxidation of the semiconductor layer 260 (e.g., silicon germanium), in some embodiments, the gas does not contain oxygen. The conditions of the annealing process are adjusted to control the profile and characteristics of the resulting channel. In an example, the annealing process is performed at a temperature between about 600 degrees Celsius and about 1400 degrees Celsius. The annealing process can be performed for a relatively long period of time, such as 12 seconds to 120 seconds (referred to as "soaking"), or can be performed for a relatively short period of time, such as hundreds of milliseconds to a few seconds (e.g., 100 milliseconds to 1 second) (referred to as "spiking").

[0050] The annealing process causes the germanium atoms and possibly silicon atoms contained in the semiconductor layer 260 to diffuse or migrate into the corresponding surrounded nanostructures 216. On the other hand, the silicon atoms contained in the semiconductor layer 260 can also diffuse or migrate into the corresponding surrounded nanostructures 216. Due to the migration of atoms, the germanium content in the semiconductor layer 260 decreases, while the germanium content in the corresponding surrounded nanostructures 216 increases. In an embodiment, after the annealing process, the semiconductor layer 260 is Si 1- x Ge x ,Si 1-x Ge xComprising Ge in a molar ratio greater than 0% but equal to or less than about 70% (0.1 < x ≤ 0.7). This range of Ge is the result of the initial concentration of Ge in the diluted semiconductor layer 260 (e.g., as described above, from about 10% to about 100%), and effectively converts the channel region in the PFET region 206 from a first type (e.g., n-type) to a second type (e.g., p-type). As the material components of the semiconductor layer 260 and the corresponding surrounded nanostructures 216 become the same or similar (e.g., when germanium is uniformly distributed throughout the channel layer 216'), and the physical interface between the semiconductor layer 260 and the corresponding surrounded nanostructures 216 becomes indistinguishable or non-distinguishable, the semiconductor layer 260 and the corresponding surrounded nanostructures 216 can effectively combine to form a new suspended channel layer 216' (or nanostructures 216').

[0051] Since the suspended nanostructure 216' is formed by the combination of the corresponding semiconductor layer 260 and the nanostructure 216, the suspended nanostructure 216' in the fin 220-2 can be thicker and wider than the suspended nanostructure 216 in the fin 220-1. In some embodiments, each nanostructure 216' has a channel thickness (denoted as T2) of about 3.5 to about 10 nm, which is greater than the channel thickness T1 in the NFET region 204, and each nanostructure 216' is spaced apart from adjacent nanosheets by a channel pitch (denoted as S2) of about 4 nm to about 14 nm, and this channel pitch (denoted as S2) is less than the channel pitch S1 in the NFET region 204. The width of the nanostructure 216' is also wider than the width of the nanostructure 216. Since the center-to-center vertical distance between two adjacent nanostructures 216' remains unchanged, the vertical channel pitch P remains the same. In various embodiments, the ratio of the channel thickness T2 to the channel thickness T1 (T2 / T1) is in the range of about 1.05 to about 1.3, and the ratio of the channel pitch S2 to the channel pitch S1 (S2 / S1) is in the range of about 0.75 to about 0.95. These ranges are not insignificant or arbitrary. The additional 5% to about 30% thickness improves the hole mobility in the PFET transistor without complicating the manufacturing process. If the additional thickness is less than about 5%, the performance improvement of the PFET transistor is negligible; if the additional thickness is greater than 30%, the channel pitch becomes too small, making it difficult to deposit the work function metal layer in the subsequent gap between the nanostructures 216'. The difference in material composition and thickness between the nanostructures 216' and 216 also allows the PFET transistor to achieve a wider threshold voltage (Vt) adjustment range, making the resulting CMOS device more suitable for high-speed and / or low-power applications. It should be noted that due to the trimming process applied to the PFET region 206, the cross-sections of the nanostructures 216' and 216 can be different. In the illustrated embodiment, the cross-section of the nanostructure 216 has a substantially right-angled rectangular shape, while the cross-section of the nanostructure 216' has an oblong or elliptical shape with rounded corners.

[0052] Also as Figure 23As shown, due to the additional epitaxially grown semiconductor layer 260 on the top surface and sidewall surfaces of the fin base 215, the top of the fin base 215 in the PFET region 206 is higher and wider than the fin base 215 in the NFET region 204. The top of the fin base 215 in the PFET region 206 is also wider than its bottom stacked between the STI components 222. In comparison, the top and bottom of the fin base 215 in the NFET region 204 may have substantially the same width. Since the nanostructure 216' may have more etching loss in the lateral direction during the trimming process, the width of the top of the fin base 215 in the PFET region 206 can also be wider than the width of the nanostructure 216'. The annealing process also causes germanium atoms to diffuse into the fin base 215. Different from the germanium concentration in the nanostructure 216' that can be uniformly distributed throughout the nanostructure 216', the germanium concentration in the fin base 215 in the PFET region 206 has a gradient in the top-to-bottom direction. Germanium atoms may diffuse to the interface under the top surface of the STI component 222.

[0053] According to some embodiments disclosed herein, the driven-in germanium atoms are distributed in the suspended nanostructure 216' in various ways, which can be customized by controlling the conditions of the annealing process. As Figure 24 shown, when the semiconductor layer 260 is epitaxially grown, the semiconductor layer 260 adheres to the middle portion 216a of the suspended nanostructure. Therefore, during the annealing process, the germanium atoms in the semiconductor layer 260 can mainly diffuse into the middle portion 216a (instead of the end portion 216b) of each suspended nanostructure. Figure 25A An example concentration distribution of germanium along the Y direction is shown. As Figure 25A shown, the germanium concentration in the middle portion 216a of each channel layer 216' is higher than the germanium concentration in the two end portions 216b of the channel layer 216'. Any suitable concentration determination method can be used (e.g., by determining the average concentration or the median concentration). In an embodiment, the germanium concentration in the middle portion 216a of each channel layer 216' is substantially uniform, while the germanium concentration in the end portion 216b of each channel layer 216' exhibits a gradient distribution (e.g., gradually decreasing from the high concentration in the middle portion 216a until the concentration becomes zero). It is worth noting that due to the diffusion nature of germanium migration in the annealing process, the germanium concentration can start to decrease at Figure 25A the points C and C' shown in Figure 25A The points C and C' shown in can be only a few nanometers away from the interface between the middle portion 216a and the end portion 216b. In some embodiments (e.g., when the annealing process duration is short and / or the temperature is low), germanium cannot reach far enough under the gate sidewall spacer 232 to reach the S / D region 240. Instead, the germanium concentration is at Figure 25AIt drops to zero at the indicated points D and D'. Thus, at least a portion of the two end portions 216b (the portion in direct contact with the gate sidewall spacers 232 and the epitaxial S / D components 240) is substantially free of germanium. In an embodiment, the entire end portion 216b of the channel layer 216' is substantially free of germanium.

[0054] Figure 25B Some exemplary germanium concentration profiles in the X-Z plane are shown. As Figure 25B shown, the germanium concentration in the core portion of each channel layer 216' can be equal to or lower than the germanium concentration in the edge portion of the channel layer 216'. Different concentration profiles can be achieved by controlling various parameters (such as the thickness of the semiconductor layer 260, the germanium concentration in the semiconductor layer 260, and / or the conditions of the annealing process). For example, a thicker semiconductor layer 260 supplies more germanium atoms, and a longer annealing process (or performed at a higher temperature) drives the germanium further into the core of the channel layer 216', resulting in a more uniform germanium concentration.

[0055] In Figure 25B , the curves 302, 304, 306 represent three different germanium concentration profiles in the channel layer 216' corresponding to different parameter sets. The case represented by curve 302 is that the semiconductor layer 260 contains about 50% to about 60% germanium and is annealed at a soak temperature of about 1250 degrees Celsius to about 1300 degrees Celsius for about 60 seconds to about 100 seconds. A uniform germanium concentration of about 35% to 40% is achieved in both the core portion and the edge portion of the channel layer 216'. In curve 304, the semiconductor layer 260 contains approximately the same germanium concentration as in curve 302 and is annealed at a spike temperature of about 1100 degrees Celsius to about 1150 degrees Celsius for about 3 seconds to about 5 seconds. The germanium concentration follows a gradient distribution, decreasing from a maximum concentration of about 30% to about 35% at the edge of the channel layer 216' to a minimum concentration of about 15% to about 20% at the core of the channel layer 216'. In curve 306, the semiconductor layer 260 contains about 30% to about 40% germanium and is annealed at a spike temperature of about 1050 degrees Celsius to about 1080 degrees Celsius for about 500 milliseconds to about 1 second. The germanium concentration follows a gradient distribution, decreasing from a maximum concentration of about 20% to about 25% at the edge of the channel layer 216' and dropping to zero before reaching the core of the channel layer 216'. Thus, the central region at the core of the channel layer 216' can be germanium-free. Figure 25B The ellipse 308 represented by the dashed line in

[0056] shows such an embodiment. The ellipse 308 at the core of the channel layer 216' represents a silicon rod without germanium. This gradient distribution is caused by a relatively short duration of the annealing process (e.g., germanium does not have enough time to migrate to the core). Each specific set of parameters results in a unique germanium concentration profile in the channel layer 216'.It should be noted that introducing germanium into the suspended channel layer in the PFET region 206 can optionally be implemented by a doping process. That is, by selecting operation 130 and operation 130’, method 100( Figure 1 ) can dope the nanostructures 216 in the PFET region 206 to obtain a suspended channel layer 216’ similar to that described above. In some embodiments, the nanostructures in both the NFET region and the PFET region are in the form of lightly doped germanium silicon nanosheets, where the germanium concentration is less than about 1x10 17 cm -3 . After the doping process, the germanium concentration in the silicon nanosheets in the PFET region 206 increases, being more than 50% higher than the germanium concentration in the silicon nanosheets in the NFET region 204. The relationship between the channel layer thickness and the spacing discussed above, as well as Figure 25A and Figure 25B the germanium concentration distribution shown also apply.

[0057] At operation 136, method 100( Figure 1 ) forms metal gate stacks 280-1 and 280-2 (collectively referred to as metal gate stack 280), and the metal gate stacks 280-1 and 280-2 are respectively joined to the channel layer 216 in the NFET region 204 and the channel layer 216’ in the PFET region 206. The resulting structure is as shown in Figures 26 to 28 . Figure 26 is a cross-sectional view along the B—B line of the device 200 in Figure 6 (which is also the B—B line in Figure 27 and Figure 28 ), Figure 27 is a cross-sectional view along the A—A line of the device 200 in Figure 6 (which is also the A—A line in Figure 23 ), and Figure 28 is a cross-sectional view along the C—C line of the device 200 in Figure 26 . Referring jointly to Figures 26 to 28, the metal gate stacks 280-1 and 280-2 fill the gate trenches 254 and surround each exposed floating channel layer respectively, such as the nanostructures 216 in the NFET region 204 and the nanostructures 216' in the PFET region 206. The metal gate stacks 280-1 and 280-2 have similar structures, but different metals and / or different layer thicknesses are used in some embodiments. In the context of CMOS, the metal gate stacks 280-1 and 280-2 can also be regarded as two parts (segments) of a continuous metal gate stack 280. In this embodiment, the metal gate stack 280 includes a gate dielectric layer 282 and a gate electrode 284 located above the gate dielectric layer 282. The gate dielectric layer 282 may include one or more layers of dielectric material located on the inner surface of the gate trench 254 and directly surrounding each channel layer. The gate dielectric layer 282 includes an interface layer, such as silicon oxide or silicon oxynitride, and is formed by chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. In some embodiments, the gate dielectric layer further includes a high-k dielectric layer, such as hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, yttrium oxide, strontium titanate, other suitable metal oxides, or a combination thereof; and is formed by ALD and / or other suitable methods. The gate electrode 284 includes a work function metal layer and a metal fill layer located above the work function layer. The work function metal layer in the PFET region 206 is a p-type work function metal layer, or the work function metal layer in the NFET region 204 is an n-type work function metal layer. The p-type work function metal layer includes metals selected from the group consisting of, but not limited to, titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or a combination thereof. The n-type work function metal layer includes metals selected from the group consisting of, but not limited to, titanium, aluminum, tantalum carbide, tantalum carbonitride, tantalum silicon nitride, or a combination thereof. In some embodiments, the p-type work function metal layer or the n-type work function metal layer includes multiple layers deposited by CVD, PVD, and / or other suitable processes. The metal fill layer includes aluminum, tungsten, cobalt, copper, and / or other suitable materials, and the metal fill layer is formed by CVD, PVD, plating, and / or other suitable processes. In some embodiments, the metal gate stack 280 surrounds the vertically stacked horizontally oriented channel layers. Thus, the device 200 is a vertically stacked horizontal gate-all-around (HGAA) device. In an embodiment, after depositing the metal gate stack 280, a CMP process is performed to planarize the top surface of the device 200. It is noted that in Figure 27 and Figure 28 , as described above, the S / D regions of the n-type GAA transistor and the p-type GAA transistor can adopt any of the S / D region configurations shown in Figure 12 , Figure 13 and Figure 14 or a combination thereof.

[0058] Further processes may be performed to complete the fabrication of the device 200.Figure 29 , Figure 30 , Figure 31 and Figure 32 show the resulting structure after some exemplary further processes. Figure 32 is a top view of device 200, Figure 29 is a cross-sectional view along line B—B of device 200 in Figure 32 , Figure 30 is a cross-sectional view along line A—A of device 200 in Figure 32 , and Figure 31 is a cross-sectional view along line C—C of device 200 in Figure 32 . Referring jointly to Figures 29 to 32, this method can continue to recess the metal gate stack 280 in an etching process (such as dry etching, wet etching, RIE, and / or other etching methods), and at the positions of the sacrificial gate structures 224-1 and 224-4, replace the two metal gate stacks 280 with two dielectric isolation components 286 (such as SiO2, silicon oxynitride, FSG, low-k dielectric, their combinations, and / or other suitable dielectric materials). The replacement of the metal gate stack 280 is also referred to as the cut polycrystalline silicon (CPO) process, and the dielectric isolation component 286 is also referred to as the CPO component. The CPO component 286 can extend into the substrate 202, such as under the bottom surface of the epitaxial S / D component 240. This method can continue to form a capping layer 288 over the remaining metal gate stack 280 and the CPO component 286, and form a second ILD layer 290 over the capping layer 288. The capping layer 288 can include a semiconductor material such as silicon or a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, their combinations, or other suitable materials. The second ILD layer 290 can include the same or different materials as the ILD layer 248, such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. This method can continue to form contact openings and form contact plugs in the contact openings, such as gate contact plugs 292, source / drain contact plugs 294, and an optional silicide component 296 located between the source / drain contact plugs 294 and the epitaxial S / D component 240. Each contact plug can include a conduction barrier layer and a bulk metal layer. The conduction barrier layer can include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or their combinations, and the conduction barrier layer can be formed by CVD, PVD, ALD, and / or other suitable processes. The bulk metal layer can include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), nickel (Ni), copper (Cu), or other metals, and the bulk metal layer can be formed by CVD, PVD, ALD, plating, or other suitable processes.

[0059] This method can continue to form various other contact plugs, vias (such as, as Figure 32 shown source / drain contact via 298), wires, and multi-layer interconnect components (e.g., metal layers and interlayer dielectrics) over the device 200, configured to connect the respective components to form a functional circuit, which can include one or more multi-gate transistors, such as, as Figure 32The GAA transistors T1, T2, T3, and T4 shown. The n-type GAA transistor T1 and the p-type GAA transistor T2 form a dual transistor in the first CMOS device, and the n-type GAA transistor T3 and the p-type GAA transistor T4 form a dual transistor in the second CMOS device. The n-type and p-type transistors in the pair have different thicknesses and material compositions in the channel layer, which allows for the co-optimization of the device performance of transistors with opposite conduction types. The first CMOS device and the second CMOS device are stacked in the Y direction between two CPO components 286 and in the X direction between two gate-end dielectric components 256. The CPO components 286 and the gate-end dielectric components 256 isolate the first CMOS device and the second CMOS device from other adjacent devices and reduce interference from them. The structure shown can be implemented in various types of circuits, Figure 32 such as in logic circuits, memory circuits (e.g., such as SRAM, etc.), and / or other types of circuits. Figure 33 An embodiment is shown.

[0060] Now referring to Figure 33 , Figure 33 FIG. 400 shows a layout of a memory macro, which includes a memory array 402 and a logic circuit (or referred to as an input / output (I / O) circuit) 404. The logic circuit 404 includes Figure 32 the CMOS devices shown as some logic units. For simplicity, only the first two rows (rows 1-2) of the memory array 402 and a part of the logic circuit 404 are shown.

[0061] The SRAM cells in the memory array 402 and the logic units in the logic circuit 404 include active regions (such as in the form of stacked channel layers 216 and 216') arranged in the X direction and longitudinally oriented in the Y direction. The memory macro also includes a metal gate stack 280 arranged in the Y direction and longitudinally extending in the X direction. In the shown embodiment, the metal gate stack 280 is uniformly distributed in the Y direction, with a uniform distance between two adjacent gate structures 280. The uniform distance is denoted as the gate pitch or polysilicon pitch ("PP"). The SRAM cell width W can also be measured by the number of polysilicon pitches. In the shown embodiment, the SRAM cell width W is twice the polysilicon pitch. The width of the memory array 402 in the Y direction can also be measured by the number of polysilicon pitches. Since each SRAM cell has a width W that is twice the polysilicon pitch, for the case where there are N SRAM cells in a row (also N columns in the memory array 402), the memory array 402 has a width of 2*N polysilicon pitches.

[0062] The metal gate stack 280 intersects with the active regions to form transistors. The transistors formed at the intersections of the active regions within the memory array 402 and the metal gate stack 280 are used to form SRAM cells. The transistors formed at the intersections of the active regions within the logic circuit 404 and the metal gate stack 280 are used to form logic units. In the illustrated embodiment, the transistors in the SRAM array 402 form a plurality of SRAM cells, such as SRAM cell BC 11 , BC 12 , BC 21 , BC 22 (collectively referred to as SRAM cell BC). Each SRAM cell BC in the array may include six transistors: transfer gate transistor PG-1, transfer gate transistor PG-2, pull-up transistor PU-1, pull-up transistor PU-2, pull-down transistor PD-1, and pull-down transistor PD-2. In some embodiments, the pull-up transistors PU-1, PU-2 are configured as p-type GAA transistors, and the pull-down transistors PD-1, PD-2, transfer gate transistors PG-1, PG-2 are configured as n-type GAA transistors.

[0063] Some active regions extend through multiple SRAM cells in a row. For example, the active regions of the transistors PD-1, PG-1 in SRAM cell BC 11 extend through SRAM cell BC 12 as the active regions of its transistors PG-1, PD-1, and further extend through other SRAM cells BC in row 1; the active regions of the transistors PG-2, PD-2 in SRAM cell BC 11 extend through SRAM cell BC 12 as the active regions of its transistors PD-2, PG-2, and further extend through other SRAM cells BC in row 1; and the active region of the transistor PU-2 in SRAM cell BC 11 extends into SRAM cell BC 12 as the active region of its transistor PU-2. The active regions in SRAM cells BC 21 , BC 22 are similarly arranged.

[0064] Transistors in the logic circuit 404, such as transistors T1, T2, T3, and T4, form multiple logic units. The logic units can be standard cells, such as inverters (INV), AND gates, OR gates, NAND gates, NOR gates, flip-flops, scan chains, etc. The logic units implement various logic functions for the SRAM cell BC. The logic functions of the logic units include, for example, write and / or read decoding, word line selection, bit line selection, data driving, and memory self-testing. As shown in the figure, each logic unit has a logic unit height CH, which is half of the SRAM cell height H. Therefore, the relative edges of the boundaries of two logic units are aligned with the relative edges of the boundary of one SRAM cell, where the edges are spaced apart in the Y direction and each edge extends in the X direction.

[0065] Between the relative boundary lines of the SRAM cells in the memory array 402 and the logic circuit 404 is an active region transition region 406, or simply referred to as the transition region 406. Inside the transition region 406, the active regions extending from the edge columns of the SRAM cells meet the active regions extending from the edge columns of the logic units. Since adjacent active regions can have different widths, protrusions and depressions are created at the meeting point of the active regions. A protrusion and depression refers to the junction where two segments of different widths meet each other.

[0066] As shown in the layout 400, the transition region 406 can have a span of one polysilicon pitch in the Y direction between the relative boundary lines of the SRAM cells and the logic units. In the transition region 406, the CPO component (or isolation component) 286 is longitudinally oriented in the X direction and provides isolation between the active regions in the memory array 402 and the logic circuit 404. The CPO component 286 overlaps with the protrusion and depression. In the exemplary layout 400, the CPO components of the logic units in the same column are adjacent to each other and form a continuous CPO component 286, which continuously extends in the X direction along the boundary line between the SRAM cells and the logic units. In other words, the CPO component 286 can be higher than the SRAM cell height H. As discussed above, the CPO component 286 is formed by replacing a previously formed metal gate stack, and the CPO component 286 inherits the arrangement of the metal gate stack 280. That is to say, the CPO component 286 can have the same width as the metal gate stack 280 and the same pitch as the metal gate stack 280. The CPO component 286 (together with Figure 32 the shown gate end dielectric component 256) improves the signal integrity of the CMOS devices in the logic circuit 404 and protects them from interference from the SRAM cell BC in the memory array 402.

[0067] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits for semiconductor devices and their formation processes. For example, embodiments of the present disclosure form dual-channel GAA FET devices on multiple fins. According to some embodiments, after growing a stack of alternating n-type semiconductor layers and p-type semiconductor layers, the method directly patterns the stack to create a first fin and a second fin, and then removes the p-type semiconductor layer to create suspended p-type nanostructures on the two fins. The method then converts the suspended p-type nanostructures of the second fin into p-type nanostructures by growing a thin p-type semiconductor (e.g., germanium or silicon germanium) layer surrounding the suspended p-type nanostructures, and then performing an annealing process to drive germanium atoms into the suspended p-type nanostructures. As a result, a dual-channel GAA FET is achieved with a simplified manufacturing process. In some embodiments, the channel has germanium only at the gate contact region (rather than at the end portions under the gate spacers). Additionally, embodiments of the present disclosure can be integrated into existing CMOS manufacturing processes, thereby providing an improved process window.

[0068] In an exemplary aspect, the present disclosure provides a method of forming a semiconductor device. The method includes providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed above the substrate. The first semiconductor layers and the second semiconductor layers have different material compositions and are alternately disposed with respect to each other in a vertical direction. Each of the first semiconductor layers and the second semiconductor layers extends over a first region and a second region of the substrate. The method further includes patterning the first semiconductor layers and the second semiconductor layers to form a first fin in the first region and a second fin in the second region, removing the first semiconductor layers from the first fin and the second fin such that a first portion of the patterned second semiconductor layer becomes a first suspended nanostructure in the first fin and a second portion of the patterned second semiconductor layer becomes a second suspended nanostructure in the second fin, forming a third semiconductor layer that surrounds each of the second suspended nanostructures in the second fin, the second semiconductor layer and the third semiconductor layer having different material compositions, performing an annealing process to incorporate the material contained in the third semiconductor layer into the second suspended nanostructures in the second fin such that the thickness of the second suspended nanostructures increases to be greater than the thickness of the first suspended nanostructures, and forming a gate stack that surrounds each of the first suspended nanostructures and the second suspended nanostructures. In some embodiments, after the annealing process, the thickness of the second suspended nanostructures increases to be at least 5% greater than the thickness of the first suspended nanostructures. In some embodiments, after the annealing process, the thickness of the second suspended nanostructures is less than about 1.3 times the thickness of the first suspended nanostructures. In some embodiments, the method further includes trimming the second suspended nanostructures to reduce the thickness of the second suspended nanostructures to be less than the thickness of the first suspended nanostructures before forming the third semiconductor layer. In some embodiments, after the annealing process, the material contained in the third semiconductor layer is uniformly distributed in the middle portion of the second suspended nanostructures and the distribution in the end portions of the second suspended nanostructures follows a gradient distribution. In some embodiments, the first suspended nanostructures in the first fin are used to provide a channel region in an n-type transistor, and wherein, due to the material incorporated into the second suspended nanostructures, the second suspended nanostructures in the second fin are used to provide a channel region in a p-type transistor. In some embodiments, before the annealing process, the first suspended nanostructures and the second suspended nanostructures are substantially composed of silicon, and after the annealing process, at least an outer portion of the second suspended nanostructures is composed of silicon germanium. In some embodiments, before the annealing process, the first suspended nanostructures and the second suspended nanostructures are substantially composed of silicon, and after the annealing process, the second suspended nanostructures are composed of a silicon core surrounded by an outer silicon germanium layer.In some embodiments, after removing the first semiconductor layer, the first fin includes a first fin-shaped base located directly below the first suspended nanostructure, and the second fin includes a second fin-shaped base located directly below the second suspended nanostructure, and after the annealing process, the top of the second fin-shaped base is higher and wider than the top of the first fin-shaped base. In some embodiments, the method further includes: forming a first epitaxial component adjacent to the first suspended nanostructure, forming a first dielectric film directly below the first epitaxial component, the first dielectric film separating the first epitaxial component from the substrate and preventing physical contact with the substrate, forming a second epitaxial component adjacent to the second suspended nanostructure, and forming a second dielectric film directly below the second epitaxial component, the second dielectric film separating the second epitaxial component from the substrate and preventing physical contact with the substrate.

[0069] In another exemplary aspect, the present disclosure provides a method. The method includes forming a sacrificial gate structure over the channel regions of the first fin and the second fin, removing the sacrificial gate structure to expose the channel regions of the first fin and the second fin, removing a sacrificial layer from the first fin and the second fin to form a plurality of first suspended layers in the first fin and a plurality of second suspended layers in the second fin, the first suspended layers and the second suspended layers comprising the same first semiconductor material, forming a mask covering the first suspended layers, performing a doping process to introduce a second semiconductor material different from the first semiconductor material into the second suspended layers while the mask covers the first suspended layers, removing the mask, after removing the mask, performing an annealing process to adjust the distribution of the second semiconductor material in the second suspended layers, and forming a metal gate stack surrounding each of the first suspended layers and the second suspended layers. In some embodiments, the first semiconductor material is silicon and the second semiconductor material is germanium. In some embodiments, after the annealing process, the ratio of the thickness of the second suspended layer to the thickness of the first suspended layer is in the range between about 1.05 and about 1.3. In some embodiments, the first suspended layers further include the second semiconductor material, and wherein the concentration of the second semiconductor material in the second suspended layers is at least 50% higher than the concentration of the second semiconductor material in the first suspended layers. In some embodiments, the concentration of the second semiconductor material in the first suspended layers is less than about 1x10 17 cm -3 . In some embodiments, the method further includes: prior to the doping process, trimming the second suspended layers to reduce the thickness of the second suspended layers to be less than the thickness of the first suspended layers. In some embodiments, the method further includes: forming a first epitaxial component adjacent to the first suspended layers, forming a first dielectric layer directly below the first epitaxial component; forming a second epitaxial component adjacent to the second suspended layers, and forming a second dielectric layer directly below the second epitaxial component.

[0070] In yet another exemplary aspect, the present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate; a first nanostructure suspended above the substrate and longitudinally extending in a first direction; a second nanostructure suspended above the substrate and longitudinally extending in the first direction; and a gate stack coupled to the first nanostructure to form an n-type transistor and coupled to the second nanostructure to form a p-type transistor. In a top view of the semiconductor structure, the gate stack longitudinally extends in a second direction perpendicular to the first direction. The semiconductor structure further includes gate spacers disposed on sidewalls of the gate stack. In a first cross-section cut along the second direction and perpendicular to a top surface of the substrate, the gate stack surrounds the first nanostructure and the second nanostructure, and the second nanostructure is thicker than the first nanostructure and includes a material composition different from that of the first nanostructure. In some embodiments, the second nanostructure is at least 5% thicker than the first nanostructure. In some embodiments, in a second cross-section cut along the first direction and perpendicular to the top surface of the substrate, the second nanostructure has a middle portion in physical contact with the gate stack and an end portion in physical contact with the gate spacers, and the middle portion is thicker than the end portion.

[0071] Some embodiments of the present application provide a method of forming a semiconductor device, including: providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed above the substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and are alternately disposed relative to each other in a vertical direction, and wherein each of the first semiconductor layers and the second semiconductor layers extends above a first region and a second region of the substrate; patterning the first semiconductor layers and the second semiconductor layers to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layers from the first fin and the second fin such that a first portion of the patterned second semiconductor layer becomes a first suspended nanostructure in the first fin and a second portion of the patterned second semiconductor layer becomes a second suspended nanostructure in the second fin; forming a third semiconductor layer surrounding each of the second suspended nanostructures in the second fin, wherein the second semiconductor layer and the third semiconductor layer have different material compositions; performing an annealing process to incorporate materials included in the third semiconductor layer into the second suspended nanostructures in the second fin such that the thickness of the second suspended nanostructures is increased to be greater than the thickness of the first suspended nanostructures; and forming a gate stack surrounding each of the first suspended nanostructures and the second suspended nanostructures.

[0072] In some embodiments, after the annealing process, the thickness of the second suspended nanostructure is increased to be at least 5% greater than the thickness of the first suspended nanostructure. In some embodiments, after the annealing process, the thickness of the second suspended nanostructure is less than about 1.3 times the thickness of the first suspended nanostructure. In some embodiments, the method further includes: before forming the third semiconductor layer, trimming the second suspended nanostructure to reduce the thickness of the second suspended nanostructure to be less than the thickness of the first suspended nanostructure. In some embodiments, after the annealing process, the material contained in the third semiconductor layer is uniformly distributed in the middle portion of the second suspended nanostructure, and the distribution in the end portions of the second suspended nanostructure follows a gradient distribution. In some embodiments, the first suspended nanostructure in the first fin is used to provide a channel region in an n-type transistor, and wherein, due to the material incorporated into the second suspended nanostructure, the second suspended nanostructure in the second fin is used to provide a channel region in a p-type transistor. In some embodiments, before the annealing process, the first suspended nanostructure and the second suspended nanostructure are substantially composed of silicon, and wherein, after the annealing process, at least the outer portion of the second suspended nanostructure is composed of silicon germanium. In some embodiments, before the annealing process, the first suspended nanostructure and the second suspended nanostructure are substantially composed of silicon, and wherein, after the annealing process, the second suspended nanostructure is composed of a silicon core surrounded by an outer silicon germanium layer. In some embodiments, after removing the first semiconductor layer, the first fin includes a first fin-shaped base located directly below the first suspended nanostructure, and the second fin includes a second fin-shaped base located directly below the second suspended nanostructure, and wherein, after the annealing process, the top of the second fin-shaped base is higher and wider than the top of the first fin-shaped base. In some embodiments, the method further includes: forming a first epitaxial component adjacent to the first suspended nanostructure; forming a first dielectric film directly below the first epitaxial component, wherein the first dielectric film separates the first epitaxial component from the substrate and prevents physical contact with the substrate; forming a second epitaxial component adjacent to the second suspended nanostructure; and forming a second dielectric film directly below the second epitaxial component, wherein the second dielectric film separates the second epitaxial component from the substrate and prevents physical contact with the substrate.

[0073] Some other embodiments of the present application provide a method, including: forming a sacrificial gate structure over the channel regions of a first fin and a second fin; removing the sacrificial gate structure to expose the channel regions of the first fin and the second fin; removing a sacrificial layer from the first fin and the second fin to form a plurality of first suspended layers in the first fin and a plurality of second suspended layers in the second fin, wherein the first suspended layers and the second suspended layers comprise the same first semiconductor material; forming a mask covering the first suspended layers; when the mask covers the first suspended layers, performing a doping process to introduce a second semiconductor material different from the first semiconductor material into the second suspended layers; removing the mask; after removing the mask, performing an annealing process to adjust the distribution of the second semiconductor material in the second suspended layers; and forming a metal gate stack surrounding each of the first suspended layers and the second suspended layers.

[0074] In some embodiments, the first semiconductor material is silicon and the second semiconductor material is germanium. In some embodiments, after the annealing process, the ratio of the thickness of the second suspended layers to the thickness of the first suspended layers is in the range of about 1.05 and about 1.3. In some embodiments, the first suspended layers further comprise the second semiconductor material, and wherein the concentration of the second semiconductor material in the second suspended layers is at least 50% higher than the concentration of the second semiconductor material in the first suspended layers. In some embodiments, the concentration of the second semiconductor material in the first suspended layers is less than about 1x10 17 cm -3 . In some embodiments, the method further includes: trimming the second suspended layers to reduce the thickness of the second suspended layers to be less than the thickness of the first suspended layers before the doping process. In some embodiments, the method further includes: forming a first epitaxial component adjacent to the first suspended layers; forming a first dielectric layer directly under the first epitaxial component; forming a second epitaxial component adjacent to the second suspended layers; and forming a second dielectric layer directly under the second epitaxial component.

[0075] Some other embodiments of the present application provide a semiconductor structure, including: a substrate; a first nanostructure suspended above the substrate and longitudinally extending in a first direction; a second nanostructure suspended above the substrate and longitudinally extending in the first direction; a gate stack, which is joined to the first nanostructure to form an n-type transistor and joined to the second nanostructure to form a p-type transistor, wherein in a top view of the semiconductor structure, the gate stack longitudinally extends in a second direction perpendicular to the first direction; and a gate spacer disposed on a sidewall of the gate stack, wherein in a first cross-section cut along the second direction and perpendicular to a top surface of the substrate, the gate stack surrounds the first nanostructure and the second nanostructure, and the second nanostructure is thicker than the first nanostructure and includes a material composition different from that of the first nanostructure.

[0076] In some embodiments, the second nanostructure is at least 5% thicker than the first nanostructure. In some embodiments, in a second cross-section cut along the first direction and perpendicular to the top surface of the substrate, the second nanostructure has an intermediate portion in physical contact with the gate stack and an end portion in physical contact with the gate spacer, and the intermediate portion is thicker than the end portion.

[0077] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: Providing a substrate having a plurality of first semiconductor layers and a plurality of second semiconductor layers disposed over the substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and are alternately disposed relative to each other in a vertical direction, wherein each of the first semiconductor layers and the second semiconductor layers extends over a first region and a second region of the substrate; patterning the first semiconductor layer and the second semiconductor layer to form a first fin in the first region and a second fin in the second region; removing the first semiconductor layer from the first fin and the second fin so that a first portion of the patterned second semiconductor layer becomes a first suspended nanostructure in the first fin and a second portion of the patterned second semiconductor layer becomes a second suspended nanostructure in the second fin; forming a third semiconductor layer, the third semiconductor layer surrounding each of the second suspended nanostructures in the second fin, wherein the second semiconductor layer and the third semiconductor layer have different material compositions; performing an annealing process to incorporate a material included in the third semiconductor layer into the second suspended nanostructure in the second fin so that a thickness of the second suspended nanostructure increases to be greater than a thickness of the first suspended nanostructure; and A gate stack is formed surrounding each of the first suspended nanostructure and the second suspended nanostructure.

2. The method according to claim 1, wherein: After the annealing process, the thickness of the second suspended nanostructure increases to be at least 5% greater than the thickness of the first suspended nanostructure.

3. The method according to claim 1, wherein: After the annealing process, a thickness of the second suspended nanostructure is less than about 1.3 times a thickness of the first suspended nanostructure.

4. The method according to claim 1, further comprising: Before forming the third semiconductor layer, the second suspended nanostructure is trimmed to reduce a thickness of the second suspended nanostructure to be less than a thickness of the first suspended nanostructure.

5. The method according to claim 1, wherein: After the annealing process, the material included in the third semiconductor layer is uniformly distributed in a middle portion of the second suspended nanostructure, and the distribution in an end portion of the second suspended nanostructure follows a gradient distribution.

6. The method according to claim 1, wherein: The first suspended nanostructure in the first fin is used to provide a channel region in an n-type transistor, and wherein the second suspended nanostructure in the second fin is used to provide a channel region in a p-type transistor due to the material incorporated into the second suspended nanostructure.

7. The method according to claim 1, wherein: Prior to the annealing process, the first suspended nanostructure and the second suspended nanostructure consist essentially of silicon, and wherein after the annealing process, at least an outer portion of the second suspended nanostructure consists of silicon germanium.

8. The method according to claim 1, wherein: Prior to the annealing process, the first suspended nanostructure and the second suspended nanostructure consist essentially of silicon, and wherein after the annealing process, the second suspended nanostructure consists of a silicon core surrounded by an outer silicon germanium layer.

9. A method of forming a semiconductor device, comprising: forming a sacrificial gate structure over the channel regions of the first fin and the second fin; removing the sacrificial gate structure to expose the channel regions of the first fin and the second fin; removing the sacrificial layer from the first fin and the second fin to form a plurality of first suspension layers in the first fin, and forming a plurality of second suspension layers in the second fin, wherein the first suspension layers and the second suspension layers include the same first semiconductor material; forming a mask covering the first suspension layer; When the mask covers the first suspension layer, performing a doping process to introduce a second semiconductor material different from the first semiconductor material into the second suspension layer; removing the mask; After removing the mask, performing an annealing process to adjust the distribution of the second semiconductor material in the second suspension layer; and A metal gate stack is formed surrounding each of the first and second floating layers.

10. A semiconductor structure comprising: substrate; a first nanostructure suspended above the substrate and extending longitudinally along a first direction; a second nanostructure suspended above the substrate and extending longitudinally along the first direction; a gate stack joined with the first nanostructure to form an n-type transistor and joined with the second nanostructure to form a p-type transistor, wherein in a top view of the semiconductor structure, the gate stack extends longitudinally along a second direction perpendicular to the first direction; and a gate spacer disposed on a sidewall of the gate stack, Wherein, in a first cross section cut along the second direction and perpendicular to the top surface of the substrate, the gate stack surrounds the first nanostructure and the second nanostructure, and the second nanostructure is thicker than the first nanostructure and includes a material component different from that of the first nanostructure.

Images