Ferroelectric memory device manufacturing method of annealing-free hafnium oxide thin film, ferroelectric memory, memory chip and electronic equipment

Abstract

The invention relates to a ferroelectric memory device manufacturing method of an annealing-free hafnium oxide thin film, a ferroelectric memory, a memory chip and electronic equipment. The method comprises the following steps: depositing a first electrode layer on a substrate; depositing a hafnium oxide-based ferroelectric film layer on the first electrode layer; a second electrode layer is deposited on the hafnium oxide-based ferroelectric film layer, the second electrode layer is etched to obtain a patterned metal top electrode, and the reaction temperature for depositing the first electrode layer, the hafnium oxide-based ferroelectric film layer and the second electrode layer is smaller than or equal to the highest temperature of the semiconductor back-end process. According to the embodiment of the invention, an annealing process step in the manufacturing of the ferroelectric memory device can be omitted, so that the preparation cost is reduced, and the ferroelectric memory device is ensured to have high remanent polarization under a preparation process with low thermal budget.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a method for manufacturing a ferroelectric memory device of a hafnium oxide thin film without annealing, a ferroelectric memory, a memory chip, and an electronic device. Background Art

[0002] In this era of rapid information growth, the traditional von Neumann architecture has difficulty in solving the high energy consumption problems caused by a large amount of data in applications such as artificial intelligence (AI), machine learning, and the Internet of Things. Therefore, in recent years, the concept of breaking through the "memory wall" has been proposed. By utilizing the inherent physical effects and material characteristics of new non-volatile memories to store data, the back-and-forth transfer of data is avoided.

[0003] Among new non-volatile memories, ferroelectric random access memories are considered to be one of the most competitive new memories at present because of their advantages such as low power consumption, fast write speed, long data retention time, and good durability. Ferroelectric memories based on traditional perovskite materials have been developed and matured. However, with the gradual reduction of the process node and the continuous increase of the integration density, traditional perovskite materials face problems such as a sharp decline in ferroelectricity below 100 nm, difficulty in preparing 3D structures, and poor compatibility with complementary metal oxide semiconductor (CMOS) processes. Therefore, the commercialization of ferroelectric memories has stagnated at the 130 nm process node. In 2011, a new type of HfO2-based ferroelectric thin film material was proposed. The new ferroelectric material based on hafnium oxide can achieve ferroelectricity at an extremely thin thickness, has good data retention performance, is easy to deposit 3D structures, and is compatible with CMOS processes, and can solve the limitations faced by traditional perovskite materials. These numerous advantages have made hafnium oxide-based ferroelectric materials a hot research topic in the current ferroelectric memory field.

[0004] Although ferroelectric memories based on hafnium oxide have these advantages, there are still some challenges in achieving commercialization at the 130 nm or even more advanced processes. In current research, hafnium oxide-based ferroelectric memory devices usually require an annealing process to generate ferroelectricity, and the annealing process temperature requirements are usually in the range of 500 °C to 700 °C, which exceeds the highest temperature (400 °C) required by the current backend process, severely limiting the integration of ferroelectric memory devices in CMOS circuits.

[0005] Therefore, ferroelectric memories with a low thermal budget preparation process have received extensive attention. Summary of the Invention

[0006] According to one aspect of the present disclosure, there is provided a method for manufacturing a ferroelectric memory device of a hafnium oxide thin film without annealing, the method comprising:

[0007] Depositing a first electrode layer on a substrate;

[0008] Deposit a hafnium oxide-based ferroelectric thin film layer on the first electrode layer;

[0009] Deposit a second electrode layer on the hafnium oxide-based ferroelectric thin film layer, and etch the second electrode layer to obtain a patterned metal top electrode.

[0010] Wherein, the reaction temperatures for depositing the first electrode layer, the hafnium oxide-based ferroelectric thin film layer, and the second electrode layer are all less than or equal to the highest temperature of the semiconductor back-end process.

[0011] In a possible implementation manner, the deposition methods for depositing the first electrode layer, the hafnium oxide-based ferroelectric thin film layer, and the second electrode layer are all atomic layer deposition methods.

[0012] Wherein, the crystallization and phase transition process of the hafnium oxide-based ferroelectric thin film layer occur during the deposition process of the second electrode layer.

[0013] In a possible implementation manner, after depositing the first electrode layer on the substrate, the method further includes:

[0014] Introduce ozone gas into the first electrode layer within a preset time period to form a TiO x N y layer, where x and y are both positive numbers.

[0015] Deposit a hafnium oxide-based ferroelectric thin film layer on the TiO x N y layer.

[0016] In a possible implementation manner, depositing a hafnium oxide-based ferroelectric thin film layer on the first electrode layer includes:

[0017] Perform alternating and cyclic deposition of HfO2 thin film and ZrO2 thin film to obtain the hafnium oxide-based ferroelectric thin film layer.

[0018] Wherein, the reaction temperatures for depositing the HfO2 thin film and the ZrO2 thin film are controlled within the range of 270°C to 320°C.

[0019] In a possible implementation manner, the materials of the first electrode layer and the second electrode layer are selected from any one of titanium nitride (TiN), niobium nitride (NbN), tantalum nitride (TaN), tungsten nitride (WN), and ruthenium oxide (RuO2).

[0020] In a possible implementation manner, the reaction temperatures for depositing the first electrode layer, the hafnium oxide-based ferroelectric thin film layer, and the second electrode layer are less than or equal to 400°C and lower than the lowest temperature required for the annealing process.

[0021] According to one aspect of the present disclosure, a ferroelectric memory device is provided, which is obtained by the method for manufacturing a ferroelectric memory device with a hafnium oxide thin film without annealing.

[0022] Wherein, the ferroelectric memory device includes a substrate, a first electrode layer, a hafnium oxide-based ferroelectric thin film layer, and a second electrode layer from bottom to top, and the second electrode layer includes a patterned metal top electrode.

[0023] In a possible implementation, a TiO x N y layer is further included between the first electrode layer and the hafnium oxide-based ferroelectric thin film layer, where x and y are both positive numbers.

[0024] According to one aspect of the present disclosure, a memory chip is provided, and the memory chip includes the ferroelectric memory device.

[0025] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the memory chip.

[0026] In a possible implementation, the electronic device includes any one of a memory, a memory-computing integrated arithmetic unit, a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, an access control device, and an electronic door lock.

[0027] In the embodiments of the present disclosure, a first electrode layer is deposited on a substrate; a hafnium oxide-based ferroelectric thin film layer is deposited on the first electrode layer; a second electrode layer is deposited on the hafnium oxide-based ferroelectric thin film layer, and the second electrode layer is etched to obtain a patterned metal top electrode, and the reaction temperatures for depositing the first electrode layer, the hafnium oxide-based ferroelectric thin film layer, and the second electrode layer are all less than or equal to the highest temperature of the semiconductor backend process, which can eliminate the annealing process step in the manufacturing of the ferroelectric memory device, thereby reducing the preparation cost and ensuring that the ferroelectric memory device has a high remanent polarization intensity under a low thermal budget preparation process.

[0028] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear according to the following detailed description of the exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification. These drawings illustrate embodiments consistent with the present disclosure and are used together with the specification to explain the technical solutions of the present disclosure.

[0030] Figure 1The flowchart of a method for manufacturing a ferroelectric memory device with an anneal-free hafnium oxide thin film according to an embodiment of the present disclosure is shown;

[0031] Figure 2 The block diagram of a ferroelectric memory device manufactured by the method for manufacturing a ferroelectric memory device with an anneal-free hafnium oxide thin film according to an embodiment of the present disclosure is shown;

[0032] Figure 3 The flowchart of a method for manufacturing a ferroelectric memory device with an anneal-free hafnium oxide thin film according to an embodiment of the present disclosure is shown;

[0033] Figure 4 The block diagram of a ferroelectric memory device manufactured by the method for manufacturing a ferroelectric memory device with an anneal-free hafnium oxide thin film according to an embodiment of the present disclosure is shown;

[0034] Figure 5 The schematic perspective view of a ferroelectric memory device manufactured by the method for manufacturing a ferroelectric memory device with an anneal-free hafnium oxide thin film according to an embodiment of the present disclosure is shown;

[0035] Figure 6a It is a schematic diagram of a P-V hysteresis curve of a ferroelectric memory device without ozone treatment test and after ozone treatment of the first electrode layer under an applied voltage of 1.8V;

[0036] Figure 6b It is a schematic diagram of a P-V hysteresis curve of a ferroelectric memory device without ozone treatment test and after ozone treatment of the first electrode layer under an applied voltage of 3V. Detailed implementation manners

[0037] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the drawings denote elements having the same or similar functions. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise specified.

[0038] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present disclosure.

[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present disclosure, "a plurality of" means two or more unless otherwise specifically defined. In the context of the present disclosure, when a layer / component is referred to as being "on" another layer / component, the layer / component may be directly on the other layer / component, or there may be an intermediate layer / component therebetween. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component may be "under" the other layer / component.

[0040] In the present disclosure, unless otherwise clearly specified and defined, terms such as "mounted", "connected", "coupled", "fixed", etc. shall be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0041] The term "exemplary" used herein means "serving as an example, embodiment, or illustration". Any embodiment described as "exemplary" herein need not be construed as superior to or better than other embodiments.

[0042] The term "and / or" in this document merely describes an association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. Additionally, the term "at least one" in this document means any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C may represent including any one or more elements selected from the set composed of A, B, and C.

[0043] In addition, for better illustration of the present disclosure, numerous specific details are given in the following specific embodiments. Those skilled in the art should understand that the present disclosure can be implemented without some specific details. In some instances, methods, means, elements, and circuits well-known to those skilled in the art are not described in detail so as to highlight the gist of the present disclosure.

[0044] In the existing widely used technologies, the initial storage devices manufactured by related technologies do not have ferroelectricity and need an additional annealing process to generate ferroelectricity. In order to obtain a sufficiently high remanent polarization intensity and ensure a certain data storage window, the temperature requirement of the annealing process is usually between 500°C and 700°C. This temperature requirement has exceeded the highest temperature (400°C) required by the current backend process, severely limiting the integration of ferroelectric storage devices in CMOS circuits. Therefore, how to reduce the annealing process temperature of ferroelectric storage devices or eliminate the annealing process step is a crucial issue in the manufacturing process and has a breakthrough significance for realizing the integration of hafnium oxide-based ferroelectric materials in CMOS circuits.

[0045] Please refer to Figure 1 and Figure 2 , Figure 1 which shows a flowchart of a method for manufacturing a ferroelectric storage device with an annealing-free hafnium oxide thin film according to an embodiment of the present disclosure, Figure 2 and a block diagram of a ferroelectric storage device manufactured by the method for manufacturing a ferroelectric storage device with an annealing-free hafnium oxide thin film according to an embodiment of the present disclosure.

[0046] As Figure 1 and Figure 2 shown, the method includes:

[0047] Step S11, depositing a first electrode layer 120 on a substrate 110;

[0048] Step S12, depositing a hafnium oxide-based ferroelectric thin film layer 130 on the first electrode layer 120;

[0049] Step S13, depositing a second electrode layer 140 on the hafnium oxide-based ferroelectric thin film layer 130 and etching the second electrode layer 140 to obtain a patterned metal top electrode,

[0050] wherein the reaction temperatures for depositing the first electrode layer 120, the hafnium oxide-based ferroelectric thin film layer 130, and the second electrode layer 140 are all less than or equal to the highest temperature of the semiconductor backend process.

[0051] In an embodiment of the present disclosure, a first electrode layer 120 is deposited on a substrate 110; a hafnium oxide-based ferroelectric thin film layer 130 is deposited on the first electrode layer 120; a second electrode layer 140 is deposited on the hafnium oxide-based ferroelectric thin film layer 130, and the second electrode layer 140 is etched to obtain a patterned metal top electrode, and the reaction temperatures for depositing the first electrode layer 120, the hafnium oxide-based ferroelectric thin film layer 130, and the second electrode layer 140 are all less than or equal to the highest temperature of the semiconductor back-end process, which can eliminate the annealing process step in the manufacturing of ferroelectric memory devices, thereby reducing the preparation cost and ensuring that the ferroelectric memory devices have a high remanent polarization intensity under a low thermal budget preparation process.

[0052] First, a brief introduction to semiconductor processes is given. Semiconductor processes are divided into front-end processes and back-end processes. Among them, the front-end process refers to the process of manufacturing chips on a silicon wafer, which belongs to a "circular process", and the back-end process refers to the assembly and processing technology of separately cutting and packaging the chips made on the wafer, which belongs to a "Flow process". Front-end process: It is divided into the front-end process (Front-End) and the back-end process (Back-End). The front-end process is the transistor formation process, and the back-end process is the multi-layer wiring formation process, which requires heating at a certain temperature (i.e., the semiconductor process).

[0053] In an embodiment of the present disclosure, the specific thicknesses of the substrate 110, the first electrode layer 120, the hafnium oxide-based ferroelectric thin film layer 130, and the second electrode layer 140 are not limited, and the specific shape of the metal top electrode is not limited, and those skilled in the art can set according to the actual situation and needs.

[0054] In an embodiment of the present disclosure, the materials of the first electrode layer 120 and the second electrode layer 140 are not limited, and those skilled in the art can select according to the actual situation and needs. In a possible implementation manner, the first electrode layer 120 and the second electrode layer 140 can be selected from nitrides and oxides. Exemplarily, nitrides can include titanium nitride (TiN), niobium nitride (NbN), tantalum nitride (TaN), tungsten nitride (WN), and oxides can include ruthenium oxide (RuO2). In an embodiment of the present disclosure, the materials of the first electrode layer 120 and the second electrode layer 140 are both titanium nitride (TiN) for introduction.

[0055] The embodiments of the present disclosure do not limit the type of the substrate 110. Those skilled in the art can set it according to the actual situation and needs. The substrate 110 can be any substrate well-known to those skilled in the art for carrying the components of semiconductor integrated circuits, such as silicon-on-insulator (SOI), bulk silicon, germanium, germanium silicon, silicon carbide (SiC), gallium arsenide, gallium nitride (GaN), or germanium-on-insulator, etc. Correspondingly, the top semiconductor materials are silicon, germanium, germanium silicon, silicon carbide (SiC), gallium arsenide, gallium nitride (GaN), etc. It can also be a carrier on which other structures have been processed on the substrate 110 listed above. The carrier can be pre-cleaned.

[0056] The embodiments of the present disclosure do not limit the specific deposition methods for depositing the first electrode layer 120, the hafnium-based ferroelectric thin film layer 130, and the second electrode layer 140. Those skilled in the art can select a suitable deposition method according to the actual situation and needs. Exemplarily, the deposition methods include but are not limited to physical vapor deposition (PVD) and chemical vapor deposition (CVD). Specifically, it can include atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), high density plasma CVD (HDPCVD), and atomic layer deposition (ALD), etc.

[0057] In a possible implementation manner, in the embodiments of the present disclosure, the deposition method for depositing the first electrode layer 120, the hafnium-based ferroelectric thin film layer 130, and the second electrode layer 140 preferably adopts the atomic layer deposition method (ALD deposition process).

[0058] Among them, the crystallization and phase transition process of the hafnium-based ferroelectric thin film layer 130 occur during the deposition process of the second electrode layer 140.

[0059] In a possible implementation manner, the reaction temperature for depositing the first electrode layer 120, the hafnium-based ferroelectric thin film layer 130, and the second electrode layer 140 is less than or equal to 400 °C and lower than the lowest temperature required for the annealing process. Exemplarily, the reaction temperature for depositing the first electrode layer 120 and the second electrode layer 140 can be set to about 400 °C.

[0060] On the one hand, in the embodiments of the present disclosure, by setting the reaction temperatures for depositing the first electrode layer 120, the hafnium oxide-based ferroelectric thin film layer 130, and the second electrode layer 140 to be less than or equal to the maximum temperature of the semiconductor backend process, and the hafnium oxide-based ferroelectric thin film layer 130 already has ferroelectricity. Since the maximum temperature of the semiconductor backend process is generally lower than the minimum temperature of the annealing process, the annealing step can be omitted. Moreover, in the embodiments of the present disclosure, through the full ALD deposition process, the crystallization and phase transition process of the hafnium oxide-based ferroelectric thin film layer 130 can occur during the deposition process of the second electrode layer 140. This further makes the ferroelectricity of the hafnium oxide-based ferroelectric thin film layer 130 stronger when manufacturing the ferroelectric memory device. Therefore, no additional annealing step is required, and the temperature throughout the reaction process can be controlled not to exceed the maximum temperature of the semiconductor backend process. The specific magnitude of the maximum temperature of the semiconductor backend process in the embodiments of the present disclosure is not limited, and the temperature range of the annealing process is not limited. Those skilled in the art can set it according to the actual situation and needs. For example, the maximum temperature of the semiconductor backend process can be 400 °C, and the temperature requirement for the annealing process is usually in the range of 500 °C to 700 °C. That is, generally speaking, the minimum temperature of the annealing process is about 500 °C.

[0061] It can be seen that in the embodiments of the present disclosure, by controlling the deposition conditions of the specific hafnium oxide thin film and the device manufacturing process, a ferroelectric memory device of hafnium oxide thin film without additional annealing process steps is realized, and it has good ferroelectric characteristics. The temperature of the entire process does not exceed 400 °C, meeting the maximum temperature limit required by the backend process.

[0062] Since no annealing process is required, the method for manufacturing a ferroelectric memory device of hafnium oxide thin film without annealing provided by the embodiments of the present disclosure also has the characteristics of simple process flow and being convenient for manufacturing ferroelectric memory devices.

[0063] Please refer to Figure 3 、 Figure 4 and Figure 5 , Figure 3 which shows the flowchart of the method for manufacturing a ferroelectric memory device of hafnium oxide thin film without annealing according to the embodiments of the present disclosure, Figure 4 which shows the block diagram of the ferroelectric memory device manufactured by the method for manufacturing a ferroelectric memory device of hafnium oxide thin film without annealing according to the embodiments of the present disclosure, Figure 5 which shows the three-dimensional structure schematic diagram of the ferroelectric memory device manufactured by the method for manufacturing a ferroelectric memory device of hafnium oxide thin film without annealing according to the embodiments of the present disclosure.

[0064] In a possible implementation manner, as shown in Figure 3 、 Figure 4 and Figure 5 shown, after depositing the first electrode layer 120 on the substrate 110 in step S11, the method further includes:

[0065] Step S21, introduce ozone gas into the first electrode layer 120 within a preset time period to form TiO x N y layer 125 on the first electrode layer 120, where x and y are both positive numbers;

[0066] Deposit a hafnium oxide-based ferroelectric thin film layer 130 on the TiO x N y layer 125.

[0067] In the embodiment of the present disclosure, by introducing ozone gas into the first electrode layer 120 within a preset time period, TiO x N y layer 125 is formed on the first electrode layer 120, that is, a one-step oxygen treatment process is introduced on the surface of the first electrode layer 120, further improving the remanent polarization intensity of the ferroelectric memory device and meeting the non-volatile storage requirements.

[0068] In the embodiment of the present disclosure, the size of the preset time period is not limited, and those skilled in the art can set it according to actual situations and needs. For example, it can be 5s to 80s, and preferably, it can be 20s. The embodiment of the present disclosure does not limit the temperature or other conditions of the ozone treatment. For example, the ozone treatment temperature can be about 250°C. Of course, after the ozone treatment is completed, other steps can also be included, such as closing the ozone and purging the TiO x N y layer 125 to accelerate the dispersion and decomposition of ozone.

[0069] Exemplarily, as Figure 4 and Figure 5 shown, the ferroelectric memory device manufactured by the above method for manufacturing a ferroelectric memory device with an anneal-free hafnium oxide thin film includes a substrate 110 (Si / SiO2), a first electrode layer 120 (TiN electrode), TiO x N y layer 125, a hafnium oxide-based ferroelectric thin film layer 130 (an FE-HZO (Hf 1-x1 Zr x1 O2) thin film showing ferroelectricity, which can also be called a HfO2-based ferroelectric thin film, where x1 is a positive number), and a second electrode layer 140 (the top TiN electrode).

[0070] Please refer to Figure 6a 、 Figure 6b , Figure 6a which is a schematic diagram of the P-V hysteresis curve of the ferroelectric memory device without ozone treatment test and after using ozone to treat the first electrode layer 120 under an applied voltage of 1.8V, Figure 6bSchematic diagram of the P-V hysteresis curve of the ferroelectric memory device without ozone treatment test and after ozone treatment of the first electrode layer 120 under an external voltage of 3V.

[0071] Figure 6a , Figure 6b In, the blue curve is without ozone treatment, and the green curve is after ozone treatment. Among them, the ferroelectric remanent polarization is the polarization intensity value corresponding to the ordinate when the voltage on the curve is zero. The larger the polarization intensity value, the better.

[0072] As Figure 6a , Figure 6b shown, under the external voltages of 1.8V and 3V, when the voltage is 0, the polarization intensity value of the ferroelectric memory device after ozone treatment is greater than that of the ferroelectric memory device without ozone treatment. That is, after ozone treatment of the first electrode layer 120, the ferroelectric remanent polarization has been significantly improved.

[0073] The embodiments of the present disclosure do not limit the specific implementation manner of depositing the hafnium oxide-based ferroelectric thin film layer 130 on the first electrode layer 120. Those skilled in the art can implement it according to the actual situation and needs. For example, in a possible implementation manner, depositing the hafnium oxide-based ferroelectric thin film layer 130 on the first electrode layer 120 may include:

[0074] Performing alternating and cyclic deposition of HfO2 thin film and ZrO2 thin film to obtain the hafnium oxide-based ferroelectric thin film layer 130,

[0075] wherein, the reaction temperature for depositing the HfO2 thin film and the ZrO2 thin film is controlled within the range of 270°C to 320°C.

[0076] The embodiments of the present disclosure do not limit the number of alternating depositions (i.e., the number of cycles) of the HfO2 thin film and the ZrO2 thin film. Those skilled in the art can set it according to the actual situation and needs. Among them, one deposition cycle includes first depositing the HfO2 thin film and then depositing the ZrO2 thin film. Of course, the deposition order of the HfO2 thin film and the ZrO2 thin film can also be changed according to the actual situation and needs. The embodiments of the present disclosure do not limit this.

[0077] In the embodiments of the present disclosure, there is no limitation on the specific implementation manner of step S13 for etching the second electrode layer 140 to obtain a patterned metal top electrode. Those skilled in the art can select a suitable etching method for patterned etching according to the actual situation and needs. For example, dry etching, wet etching, etc. can be used. Preferably, dry etching is used in the embodiments of the present disclosure for the patterned etching of the metal top electrode. The embodiments of the present disclosure do not limit the specific process steps of photolithography and etching. Those skilled in the art can refer to related technologies and implement them according to the actual situation and needs. Generally speaking, photolithography and etching may include steps such as preparing a photolithography mask, coating a photoresist, baking, exposing, developing, etching, and removing the photoresist.

[0078] It can be understood that the above-mentioned various method embodiments mentioned in the present disclosure can be combined with each other to form a combined embodiment without violating the principle logic. Due to space limitations, the present disclosure will not elaborate further. Those skilled in the art can understand that in the above methods of the specific implementation manner, the specific execution order of each step should be determined according to its function and possible internal logic.

[0079] In the embodiments of the present disclosure, by controlling the deposition conditions of a specific hafnium oxide thin film and the device manufacturing process, and using ALD to deposit the three-layer structure of electrode-ferroelectric layer-electrode, an HZO ferroelectric capacitor memory device without an annealing step is realized. The highest temperature in the process does not exceed 400 °C, meeting the highest temperature requirement of the back-end process. And by performing oxygen treatment on the bottom electrode, a ferroelectric memory device with a low thermal budget and a high remanent polarization intensity is realized.

[0080] Compared with the prior art, the embodiments of the present disclosure realize an HZO ferroelectric capacitor memory device without an annealing step. The highest temperature in the entire process does not exceed 400 °C, meeting the highest temperature requirement of the back-end process, solving the problem of the prior art that requires high-temperature annealing at 500 °C - 700 °C, and ensuring that the device has a high remanent polarization intensity under the manufacturing process with a low thermal budget.

[0081] According to an aspect of the present disclosure, a ferroelectric memory device is provided. The ferroelectric memory device is obtained by the manufacturing method of the ferroelectric memory device with a hafnium oxide thin film without annealing.

[0082] Wherein, as Figure 2 shown, the ferroelectric memory device includes a substrate 110, a first electrode layer 120, a hafnium oxide-based ferroelectric thin film layer 130, and a second electrode layer 140 from bottom to top. The second electrode layer 140 includes a patterned metal top electrode.

[0083] In a possible implementation manner, TiO x N yLayer 125, where both x and y are positive numbers.

[0084] For a detailed introduction to the ferroelectric memory device and its manufacturing method, please refer to the previous description of the manufacturing method of the ferroelectric memory device with a hafnium oxide thin film without annealing, which will not be elaborated here.

[0085] According to one aspect of the present disclosure, a storage chip is provided, and the storage chip includes the ferroelectric memory device described above.

[0086] According to one aspect of the present disclosure, an electronic device is provided, and the electronic device includes the storage chip described above.

[0087] In a possible implementation manner, the electronic device includes any one of a memory, a memory-computation integrated arithmetic unit, a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a notebook computer, an all-in-one computer, an access control device, and an electronic door lock.

[0088] Of course, the electronic device can also be other terminal devices. The terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device, or a vehicle-mounted device, etc. Exemplarily, some examples of terminals are: mobile phone, tablet computer, notebook computer, palmtop computer, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, wireless terminal in vehicle-to-everything, etc. For example, the server can be a local server or a cloud server.

[0089] The embodiments of the present disclosure have been described above. The above description is exemplary and not exhaustive, and is also not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the improvement of the technology in the market, or to enable other ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for manufacturing a ferroelectric memory device of an annealing-free hafnium oxide thin film, characterized in that: The method comprises: depositing a first electrode layer on the substrate; depositing a hafnium oxide-based ferroelectric thin film layer on the first electrode layer; depositing a second electrode layer on the hafnium oxide-based ferroelectric thin film layer, and etching the second electrode layer to obtain a patterned metal top electrode, The reaction temperatures for depositing the first electrode layer, the hafnium oxide-based ferroelectric thin film layer and the second electrode layer are all less than or equal to the highest temperature of the semiconductor back-end process.

2. The method according to claim 1, characterized in that: The deposition methods of the first electrode layer, the hafnium oxide-based ferroelectric thin film layer and the second electrode layer are all atomic layer deposition methods. The crystallization and phase transformation process of the hafnium oxide-based ferroelectric thin film layer occurs during the deposition process of the second electrode layer.

3. The method according to claim 1, characterized in that: After depositing the first electrode layer on the substrate, the method further comprises: The first electrode layer is supplied with ozone gas for a preset time period to form a TiO x N y Layer, where x and y are both positive numbers; In the TiO x N y A hafnium oxide-based ferroelectric thin film layer is deposited on the layer.

4. The method according to claim 1, characterized in that: Depositing a hafnium oxide-based ferroelectric thin film layer on the first electrode layer comprises: Performing alternating and cyclic deposition of HfO2 thin films and ZrO2 thin films to obtain the hafnium oxide-based ferroelectric thin film layer, The reaction temperature of HfO2 film and ZrO2 film deposition is controlled within the range of 270°C to 320°C.

5. The method according to claim 1, characterized in that The material of the first electrode layer and the second electrode layer is selected from any one of titanium nitride (TiN), niobium nitride (NbN), tantalum nitride (TaN), tungsten nitride (WN), and ruthenium oxide (RuO2).

6. The method according to claim 1, characterized in that The reaction temperature for depositing the first electrode layer, the hafnium oxide-based ferroelectric thin film layer and the second electrode layer is less than or equal to 400° C. and lower than the minimum temperature required by the annealing process.

7. A ferroelectric memory device, characterized in that: The ferroelectric memory device is obtained by the method for manufacturing a ferroelectric memory device of an annealing-free hafnium oxide thin film as claimed in any one of claims 1 to 6, The ferroelectric memory device comprises, from bottom to top, a substrate, a first electrode layer, a hafnium oxide-based ferroelectric thin film layer, and a second electrode layer, wherein the second electrode layer comprises a patterned metal top electrode.

8. The ferroelectric memory device according to claim 7, characterized in that: A TiO x N y Layer, where x and y are both positive numbers.

9. A memory chip, characterized in that: The memory chip includes the ferroelectric memory device according to claim 7 or 8.

10. An electronic device, characterized in that: The electronic device comprises the memory chip as claimed in claim 9.

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