Trench gate super-junction MOS device and preparation method thereof

Abstract

The invention provides a trench gate super-junction MOS device and a preparation method thereof, the trench gate super-junction MOS device comprises a semiconductor structure, a trench structure, a source / contact region and a source / drain / gate, the semiconductor structure comprises a semiconductor layer and a column / body region, and the column region comprises a first column and a second column; the groove structure comprises a first groove structure and a second groove structure; the source region is located on the upper surface of the body region; the contact region comprises a first contact region and a third contact region which are respectively positioned between the adjacent first and second groove structures and two adjacent second groove structures, and a second contact region which is adjacent to the side wall of the second groove structure close to the first groove structure; the source electrode is electrically connected with the source region, the contact regions and the second groove structure, the second contact region, the third contact region and the source electrode form Schottky contact, and the drain / grid electrode is electrically connected with the substrate and the first groove structure respectively. Through the arrangement of the second groove structure, the second contact region and the third contact region, reverse recovery of the device is reduced, and meanwhile on resistance and leakage current are not increased.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit manufacturing, and relates to a trench-gate superjunction MOS device and a manufacturing method thereof. Background Art

[0002] Using the principle of charge compensation, the superjunction structure can greatly increase the doping concentration of the drift region without reducing the breakdown voltage. Applying the superjunction structure to a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor, abbreviated as MOS) can reduce the on-resistance of the device by more than 10 times, and as the cell size shrinks, the specific on-resistance of the superjunction MOSFET can continue to decrease. As the resistance of the drift region continues to decrease, the proportion of the JFET (Junction Field Effect Transistor) resistance will gradually increase. Using a trench gate can eliminate the JFET resistance, thereby further reducing the specific on-resistance of the superjunction MOSFET. For high-power applications, the body diode of the superjunction MOSFET is also required. However, since the current during the reverse conduction of the superjunction MOSFET all conducts through the PN junction diode, a large number of non-equilibrium carriers will be generated in the drift region. Therefore, the body diode of the superjunction MOSFET has a very large reverse recovery loss, which will reduce the operating efficiency of the entire system, as Figure 1 and Figure 2 shown, which are respectively the cross-sectional structure schematic diagram of the trench-gate superjunction MOS device and Figure 1 the equivalent circuit diagram of the device in (where G, S, and D in the figure respectively represent the gate, source, and drain of the device), including a substrate 01, a buffer layer 011, a column region 012, a first column 0121, a second column 0122, a body region 013, a source region 014, a contact region 015, a trench structure 02, a trench 021, a gate dielectric layer 022, a gate conductive layer 023, an interlayer dielectric layer 03, a source electrode 04, and a drain electrode 05.

[0003] In order to reduce the reverse recovery loss of the body diode of the superjunction MOSFET, currently, the carrier lifetime in the body region of the superjunction MOSFET can be reduced by using an electron irradiation or platinum doping process, so as to achieve the purpose of reducing the non-equilibrium carriers in the drift region, and further reduce the reverse recovery charge; an N-type Schottky diode can also be directly integrated in the superjunction MOSFET to reduce the injection efficiency of the PN junction, so as to achieve the purpose of reducing the non-equilibrium carriers in the drift region and reducing the reverse recovery loss. In addition, the reverse recovery loss can also be greatly reduced by suppressing the conduction of the PN junction diode in the superjunction MOSFET and anti-parallel connecting a silicon carbide diode.

[0004] However, while the above-mentioned technologies improve the switching characteristics of superjunction power MOSFETs, they are accompanied by the sacrifice of other characteristics. Specifically, the greater the dose of electron irradiation or platinum doping, the lower the reverse recovery charge, but it will also increase the specific on-resistance and leakage current of the superjunction MOSFET. Due to the increase in leakage current, it is difficult for the superjunction MOSFET to pass through high-temperature power cycling, thus limiting its application. Integrating an N-type Schottky diode will also significantly increase the leakage current of the device. Anti-parallel silicon carbide diodes will significantly increase the cost of the system, and since it is necessary to suppress the conduction of the PN junction diode in the superjunction MOSFET, a series of low-voltage Schottky diodes is usually adopted, which will further increase the cost of the system.

[0005] Therefore, there is an urgent need for a trench-gate superjunction MOS device that can reduce the reverse recovery loss of the device without increasing the on-resistance, leakage current, and cost of the device. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a trench-gate superjunction MOS device and a preparation method thereof, which are used to solve the problem that the on-resistance, leakage current, and cost of the device increase while reducing the reverse recovery of the superjunction MOS device in the prior art.

[0007] To achieve the above purpose and other related purposes, the present invention provides a trench-gate superjunction MOS device, including:

[0008] A semiconductor structure, including a first-conductivity-type semiconductor layer, a column region, and a second-conductivity-type body region stacked in sequence. The column region includes a plurality of first columns of the first conductivity type and second columns of the second conductivity type alternately arranged in the X direction;

[0009] A trench structure, including a plurality of first trench structures and second trench structures spaced apart in the X direction and penetrating the body region. The bottom surface of the first trench structure extends into the first column. At least two second trench structures with bottom surfaces extending into the same second column are spaced between two adjacent first trench structures in the X direction. The side wall of the second trench structure adjacent to the first trench structure extends into the first column in the X direction;

[0010] A first-conductivity-type source region, located on the upper surface layer of the body region on both sides of the first trench structure in the X direction and adjacent to the side wall of the first trench structure;

[0011] The contact region includes a first contact region of a second conductivity type, a second contact region of a first conductivity type, and a third contact region of a second conductivity type on the upper surface layer of the body region. The first contact region is located between the adjacent first trench structure and the second trench structure and is adjacent to the source region. The second contact region is adjacent to at least the sidewall of the second trench structure adjacent to the first trench structure. The third contact region is located between two adjacent second trench structures, and at least one third contact region is adjacent to the second contact region;

[0012] The interlayer dielectric layer covers the upper surface of the semiconductor structure;

[0013] The source electrode, the drain electrode, and the gate electrode. The source electrode is electrically connected to the source region, the contact region, and the second trench structure, and Schottky contacts are formed between the second contact region and the third contact region and the source electrode. The drain electrode is electrically connected to the semiconductor layer, and the gate electrode is electrically connected to the first trench structure.

[0014] Optionally, the semiconductor layer includes a first conductivity type substrate and a first conductivity type buffer layer stacked in sequence. The substrate is electrically connected to the drain electrode, and the pillar region is located on the upper surface of the buffer layer.

[0015] Optionally, the first trench structure includes a first trench, a first gate dielectric layer, and a first gate conductive layer. The second trench structure includes a second trench, a second gate dielectric layer, and a second gate conductive layer. The first trench and the second trench are embedded in the semiconductor structure. The first gate dielectric layer covers the inner wall and the bottom surface of the first trench. The second gate dielectric layer covers the inner wall and the bottom surface of the second trench. The first gate conductive layer fills the first trench, and the second gate conductive layer fills the second trench. The first gate conductive layer is electrically connected to the gate electrode, and the second gate conductive layer is electrically connected to the source electrode.

[0016] Optionally, the doping concentration of the body region gradually increases from bottom to top.

[0017] Optionally, in the X direction, the sidewall of the first contact region away from the source region is adjacent to the sidewall of the second trench structure.

[0018] Optionally, the upper surface layer of the second contact region is further provided with the third contact region adjacent to the second trench structure, and the third contact region located on the upper surface layer of the second contact region is spaced apart from the sidewall and the bottom surface of the second contact region away from the second trench structure by a preset distance.

[0019] Optionally, the second trench structure adjacent to the first trench structure is provided with the second contact regions on both sides in the X direction, and the second contact region adjacent to the side wall of the second trench structure close to the first trench structure is adjacent to the side wall of the first contact region away from the source region.

[0020] Optionally, the doping concentration of the body region below the second contact region is lower than the doping concentration of the second contact region.

[0021] Optionally, the barrier height range of the Schottky contact formed by the second contact region and the source electrode is 0.6 eV to 0.9 eV, and the turn-on voltage range of the Schottky diode formed by the second contact region and the source electrode is 0.3 V to 0.5 V.

[0022] Optionally, the turn-on voltage range of the MOS channel diode formed by the second contact region, the body region below the second contact region, the second pillar, the first pillar, and the second trench structure adjacent to the second contact region is 0.3 V to 0.7 V.

[0023] The present invention also provides a method for manufacturing a trench-gate superjunction MOS device, including the following steps:

[0024] Provide a semiconductor structure, which includes a first-conductivity-type semiconductor layer, a pillar region, and a second-conductivity-type body region stacked in sequence. The pillar region includes a plurality of first pillars of the first conductivity type and second pillars of the second conductivity type alternately arranged in the X direction;

[0025] Form a trench structure including a plurality of first trench structures and second trench structures spaced apart in the X direction and penetrating the body region on the upper surface layer of the semiconductor structure. The bottom surface of the first trench structure extends into the first pillar. At least two second trench structures with bottom surfaces extending into the same second pillar are spaced between two adjacent first trench structures in the X direction. The side wall of the second trench structure adjacent to the first trench structure extends into the first pillar in the X direction;

[0026] Form a first-conductivity-type source region on the upper surface layer of the body region on both sides of the first trench structure in the X direction. The source region is adjacent to the side wall of the first trench structure;

[0027] A contact region is formed, including a first contact region of a second conductivity type located on the upper surface layer of the body region, a second contact region of a first conductivity type, and a third contact region of a second conductivity type. The first contact region is located between the adjacent first trench structure and the second trench structure and is adjacent to the source region. The second contact region is adjacent to at least the sidewall of the second trench structure adjacent to the first trench structure. The third contact region is located between two adjacent second trench structures, and at least one third contact region is adjacent to the second contact region;

[0028] An interlayer dielectric layer is formed to cover the upper surface of the semiconductor structure;

[0029] A source electrode is formed and electrically connected to the source region, the contact region, and the second trench structure. Schottky contacts are formed between the second contact region and the third contact region and the source electrode. A gate electrode is formed and electrically connected to the first trench structure. A drain electrode is formed and electrically connected to the semiconductor layer.

[0030] As described above, the trench-gate superjunction MOS device and its manufacturing method of the present invention improve the device structure to form the first trench structure and the second trench structure penetrating the body region in the semiconductor structure. The bottom surface of the first trench structure extends into the first pillar, and the bottom surface of the second trench structure extends into the second pillar. There are at least two second trench structures whose bottom surfaces extend into the same second pillar. The side walls of the second trench structures adjacent to the first trench structure extend into the first pillar in the X direction. The second contact region and the third contact region are formed on the upper surface layer of the body region between two adjacent second trench structures above the same second pillar region. The second contact region and the source electrode form a Schottky diode with an opening voltage less than that of the PN junction. The second contact region, the body region located below the second contact region, the second pillar, the first pillar, and the second trench structure adjacent to the second contact region form a MOS channel diode with an opening voltage less than that of the PN junction. Due to the setting of the Schottky diode and the MOS channel diode, when the device conducts in the reverse direction, the single-carrier conducting Schottky diode and MOS channel diode can significantly reduce the injection efficiency of the PN junction diode in the device, reduce the number of carriers in the drift region, and then reduce the reverse recovery loss of the device. In addition, since the third contact region and the source electrode also form a Schottky diode, the occurrence of the conductance modulation effect in the device can be further suppressed through this Schottky diode, thereby further reducing the injection efficiency of the PN junction diode and the reverse recovery loss of the device. And because the second contact region and the third contact region are located on the upper surface layer of the body region between two adjacent second trench structures above the same second pillar region, the second trench structure and the body region can protect the Schottky diode formed by the second contact region and the third contact region and the source electrode, avoid the increase in the leakage current of the device caused by the introduction of Schottky contact, improve the performance of the device, and have high industrial utilization value. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It shows a schematic cross-sectional structure diagram of a trench-gate superjunction MOS device.

[0032] Figure 2 It shows Figure 1 the equivalent circuit diagram of the device in

[0033] Figure 3 It shows a schematic cross-sectional structure diagram of a trench-gate superjunction MOS device of the present invention.

[0034] Figure 4 It shows another schematic cross-sectional structure diagram of a trench-gate superjunction MOS device of the present invention.

[0035] Figure 5Shown is a schematic cross-sectional view of the third structure of the trench-gate superjunction MOS device of the present invention.

[0036] Figure 6 Shown is the equivalent circuit diagram of the trench-gate superjunction MOS device of the present invention.

[0037] Figure 7 Shown is the process flow diagram of the manufacturing method of the trench-gate superjunction MOS device of the present invention.

[0038] Figure 8 Shown is the schematic cross-sectional view of the semiconductor structure of the manufacturing method of the trench-gate superjunction MOS device of the present invention.

[0039] Figure 9 Shown is the schematic cross-sectional view after forming the trench structure of the manufacturing method of the trench-gate superjunction MOS device of the present invention.

[0040] Figure 10 Shown is the schematic cross-sectional view after forming the contact region of the manufacturing method of the trench-gate superjunction MOS device of the present invention.

[0041] Figure 11 Shown is the schematic cross-sectional view after forming the source contact hole of the manufacturing method of the trench-gate superjunction MOS device of the present invention.

[0042] Explanation of the reference numerals in the drawings

[0043] 01 Substrate

[0044] 011 Buffer layer

[0045] 012 Column region

[0046] 0121 First column

[0047] 0122 Second column

[0048] 013 Body region

[0049] 014 Source region

[0050] 015 Contact region

[0051] 02 Trench structure

[0052] 021 Trench

[0053] 022 Gate dielectric layer

[0054] 023 Gate conductive layer

[0055] 03 Interlayer dielectric layer

[0056] 04 Source

[0057] 05 Drain

[0058] 1 Semiconductor Structure

[0059] 11 Semiconductor Layer

[0060] 111 Substrate

[0061] 112 Buffer Layer

[0062] 12 Column Region

[0063] 121 First Column

[0064] 122 Second Column

[0065] 13 Body Region

[0066] 14 Source Region

[0067] 15 Contact Region

[0068] 151 First Contact Region

[0069] 152 Second Contact Region

[0070] 153 Third Contact Region

[0071] 2 Trench Structure

[0072] 21 First Trench Structure

[0073] 211 First Trench

[0074] 212 First Gate Dielectric Layer

[0075] 213 First Gate Conductive Layer

[0076] 22 Second Trench Structure

[0077] 221 Second Trench

[0078] 222 Second Gate Dielectric Layer

[0079] 223 Second Gate Conductive Layer

[0080] 3 Interlayer Dielectric Layer

[0081] 31 Source Contact Hole

[0082] 4 Source

[0083] 5 Drain Detailed Implementation Manner

[0084] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0085] Please refer to Figures 3 to 11 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0086] Embodiment 1

[0087] This embodiment provides a trench-gate superjunction MOS device, such as Figure 3 , Figure 4 , Figure 5 and Figure 6As shown, they are respectively a schematic cross-sectional structure diagram of the trench-gate superjunction MOS device, another schematic cross-sectional structure diagram of the trench-gate superjunction MOS device, a third schematic cross-sectional structure diagram of the trench-gate superjunction MOS device, and an equivalent circuit diagram of the trench-gate superjunction MOS device (G, S, and D in the figure respectively represent the gate, source, and drain of the device), including a semiconductor structure 1, a trench structure 2, a source region 14 of the first conductivity type, a contact region 15, an interlayer dielectric layer 3, a source electrode 4, a drain electrode 5, and a gate (not shown). Among them, the semiconductor structure 1 includes a first-conductivity-type semiconductor layer 11, a column region 12, and a second-conductivity-type body region 13 stacked in sequence. The column region 12 includes a plurality of first columns 121 of the first conductivity type and second columns 122 of the second conductivity type alternately arranged in the X direction in sequence; the trench structure 2 includes a plurality of first trench structures 21 and second trench structures 22 spaced apart in the X direction and penetrating the body region 13. The bottom surface of the first trench structure 21 extends into the first column 121. There are at least two second trench structures 22 with bottom surfaces extending into the same second column 122 spaced between two adjacent first trench structures 21 in the X direction. The side wall of the second trench structure 22 adjacent to the first trench structure 21 extends into the first column 121 in the X direction; the source region 14 is located on the upper surface layer of the body region 13 on both sides of the first trench structure 21 in the X direction and is adjacent to the side wall of the first trench structure 21; the contact region 15 includes a second-conductivity-type first contact region 151, a first-conductivity-type second contact region 152, and a second-conductivity-type third contact region 153 located on the upper surface layer of the body region 13. The first contact region 151 is located between the adjacent first trench structure 21 and the second trench structure 22 and is adjacent to the source region 14. The second contact region 152 is adjacent to at least the side wall of the second trench structure 22 adjacent to the first trench structure 21. The third contact region 153 is located between two adjacent second trench structures 22, and at least one third contact region 153 is adjacent to the second contact region 152; the interlayer dielectric layer 3 covers the upper surface of the semiconductor structure 1; the source electrode 4 is electrically connected to the source region 14, the contact region 15, and the second trench structure 22, and Schottky contacts are formed between the second contact region 152 and the third contact region 153 and the source electrode 4. The drain electrode 5 is electrically connected to the substrate 11, and the gate is electrically connected to the first trench structure 21.

[0088] Specifically, the first conductivity type includes one of N-type or P-type, the second conductivity type includes one of N-type or P-type, and the conductivity types of the first conductivity type and the second conductivity type are opposite. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0089] Specifically, on the premise of ensuring device performance, the size and shape of the substrate 11 can be selected according to actual circumstances and will not be limited here.

[0090] As an example, the semiconductor layer 11 further includes a first-conductivity-type substrate 111 and a first-conductivity-type buffer layer 112 stacked in sequence. The substrate 111 is electrically connected to the drain 5, and the pillar region 12 is located on the upper surface of the buffer layer 112.

[0091] Specifically, the substrate 111 forms an ohmic contact with the drain 5. On the premise of ensuring device performance, the doping concentration and thickness of the substrate 111 can be selected according to actual circumstances and will not be limited here.

[0092] Specifically, on the premise of ensuring device performance, the thickness and doping concentration of the buffer layer 112 can be selected according to actual circumstances and will not be limited here.

[0093] Specifically, the upper and lower surfaces of the first pillar 121 and the second pillar 122 are flush, that is, the first pillar 121 and the second pillar 122 have the same height. On the premise of ensuring device performance, the size of the first pillar 121 in the X direction and its height can be selected according to actual circumstances and will not be limited here; the size of the second pillar 122 in the X direction and its height can be selected according to actual circumstances and will not be limited here.

[0094] As an example, the doping concentration of the body region 13 gradually increases from bottom to top. In this embodiment, the doping concentration of the body region 13 decreases from 10 17 cm -3 order of magnitude to 10 15 cm -3 order of magnitude from top to bottom.

[0095] Specifically, on the premise of ensuring device performance, the thickness of the body region 13 can be selected according to actual circumstances and will not be limited here.

[0096] As an example, the first trench structure 21 includes a first trench 211, a first gate dielectric layer 212, and a first gate conductive layer 213. The second trench structure 22 includes a second trench 221, a first gate dielectric layer 222, and a second gate conductive layer 223. The first trench 211 and the second trench 221 are embedded in the semiconductor structure 1. The first gate dielectric layer 212 covers the inner wall and bottom surface of the first trench 211. The second gate dielectric layer 222 covers the inner wall and bottom surface of the second trench 221. The first gate conductive layer 213 fills the first trench 211. The second gate conductive layer 223 fills the second trench 221. The first gate conductive layer 213 is electrically connected to the gate electrode, and the second gate conductive layer 223 is electrically connected to the source electrode 4.

[0097] Specifically, the first gate dielectric layer 212 wraps the sidewalls and the bottom surface of the first gate conductive layer 213, and the second gate dielectric layer 222 wraps the sidewalls and the bottom surface of the second gate conductive layer 223.

[0098] Specifically, when the device performance is ensured, the opening size, the opening shape, and the depth of the bottom surface extending into the first pillar 121 of the first trench 211 can be selected according to actual conditions and are not limited here; the opening size, the opening shape, and the depth of the bottom surface extending into the second pillar 122 of the second trench can be selected according to actual conditions and are not limited here.

[0099] Specifically, the bottom surface of the second trench 221 adjacent to the first trench 211 extends downward into both the first pillar 121 and the second pillar 122 at the same time, that is, the sidewall of the second trench 221 adjacent to the first trench 211 extends into the first pillar 121. When the device performance is ensured, the distance that the sidewall of the second trench 221 adjacent to the first trench 211 extends into the first pillar 121 in the X direction can be selected according to actual conditions and is not limited here.

[0100] Specifically, when the device performance is ensured, the thickness of the first gate dielectric layer 212 can be selected according to actual conditions and is not limited here; the thickness of the second gate dielectric layer 222 can be selected according to actual conditions and is not limited here.

[0101] Specifically, the material of the first gate dielectric layer 212 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the material of the second gate dielectric layer 222 includes silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric materials; the material of the first gate conductive layer 213 includes polysilicon or other suitable conductive materials; the material of the second gate conductive layer 223 includes polysilicon or other suitable conductive materials.

[0102] Specifically, the source region 14 forms an ohmic contact with the source electrode 4. When the device performance is ensured, the size, the thickness, and the doping concentration of the source region 14 can be selected according to actual conditions and are not limited here.

[0103] Specifically, the first contact region 151 is located on the upper surface layer of the body region 13 between the first trench 211 and the second trench 221, and the first contact region 151 forms an ohmic contact with the source electrode 4.

[0104] As an example, in the X direction, the sidewall of the first contact region 151 away from the source region 14 is adjacent to the sidewall of the second trench structure 22, that is, while the first contact region 151 is adjacent to the source region 13, it is also adjacent to the sidewall of the second trench 221 adjacent to the first trench 211.

[0105] Specifically, while ensuring the device performance, the doping concentration and thickness of the first contact region 151 can be selected according to the actual situation, and are not limited here.

[0106] Specifically, while ensuring the device performance, the size of the second contact region 151 in the X direction can be selected according to the actual situation, and is not limited here.

[0107] Specifically, the doping concentration range of the second contact region 151 is 1×10 16 cm -3 ~1×10 17 cm -3 , so that the second contact region 152 forms a Schottky contact with the source electrode 4.

[0108] As an example, the doping concentration of the body region 13 below the second contact region 152 is lower than that of the second contact region 152, so that the second contact region 152, the body region 13 below the second contact region 152, the second pillar 122, the first pillar 121, and the second trench structure 22 adjacent to the contact region 152 form a MOS channel diode. In this embodiment, the doping concentration of the body region 13 below the second contact region 152 is lower than 10 16 cm -3 order of magnitude.

[0109] As an example, the bottom surface of the second contact region 152 is lower than the bottom surface of the third contact region 153, that is, the distance between the bottom surface of the second contact region 152 and the upper surface of the semiconductor layer 11 is greater than the distance between the third contact region 153 and the upper surface of the semiconductor layer 11.

[0110] Specifically, while ensuring the device performance, the bottom surface of the second contact region 152 is not lower than the bottom surface of the third contact region 153.

[0111] Specifically, the sidewall of the third contact region 153 away from the second contact region 152 is adjacent to the second trench 221 adjacent to the third contact region 153.

[0112] Specifically, while ensuring the device performance, the thickness and the size in the X direction of the third contact region 153 can be selected according to the actual situation, and are not limited here.

[0113] Specifically, the doping concentration range of the third contact region 153 is 1×10 16 cm -3 ~1×10 17 cm -3 , so that a Schottky contact is formed between the third contact region 153 and the source electrode 4.

[0114] As an example, the upper surface layer of the second contact region 152 is further provided with the third contact region 153 adjacent to the second trench structure 22, and the third contact region 153 located on the upper surface layer of the second contact region 152 is spaced apart from the side wall and the bottom surface of the second contact region 152 away from the second trench structure 22 by a preset distance.

[0115] Specifically, under the condition of ensuring the device performance, the size, thickness of the third contact region 153 located on the upper surface layer of the second contact region 152, and the distance from the side wall and the bottom surface of the second contact region 152 can be selected according to the actual situation, and will not be limited here.

[0116] As an example, the second trench structure 22 adjacent to the first trench structure 21 is provided with the second contact regions 152 on both sides along the X direction, and the second contact region 152 adjacent to the side wall of the second trench structure 22 close to the first trench structure 21 is adjacent to the side wall of the first contact region 151 away from the source region 14.

[0117] Specifically, under the condition of ensuring the device performance, the size along the X direction and the thickness of the third contact region 153 adjacent to the first contact region 151 can be selected according to the actual situation, and will not be limited here.

[0118] Specifically, the material of the interlayer dielectric layer 3 includes silicon oxide, silicon nitride, silicon oxynitride or other suitable dielectric materials.

[0119] Specifically, under the condition of ensuring the device performance, the thickness of the interlayer dielectric layer 3 can be selected according to the actual situation, and will not be limited here.

[0120] Specifically, a source electrode contact hole 31 and a gate contact hole (not shown) are further provided in the interlayer dielectric layer 3. The source electrode contact region 31 penetrates through the interlayer dielectric layer 3, and the bottom surface exposes the source region 14, the first contact region 151, the second contact region 152, the third contact region 153, and the second gate conductive layer 223. The gate contact hole penetrates through the interlayer dielectric layer 3, and the bottom surface exposes the first gate conductive layer 213.

[0121] Specifically, when ensuring the device performance, the opening size and shape of the source contact hole 31 can be selected according to the actual situation and are not limited here; the opening size and shape of the gate contact hole can be selected according to the actual situation and are not limited here.

[0122] Specifically, the source 4 fills the source contact hole 31 to achieve the electrical connection between the source 4 and the source region 14, the first contact region 151, the second contact region 152, the third contact region 153, and the second gate conductive layer 223. The gate fills the gate contact hole to achieve the electrical connection between the gate and the first gate conductive layer 213.

[0123] Specifically, the material of the source 4 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, or other suitable conductive materials; the material of the gate includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, or other suitable conductive materials; the material of the drain 5 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum, or other suitable conductive materials.

[0124] As an example, the barrier height range of the Schottky contact formed between the second contact region 152 and the source 4 is 0.6 eV to 0.9 eV, and the turn-on voltage range of the Schottky diode formed by the second contact region 152 and the source 4 is 0.3 V to 0.5 V.

[0125] As an example, the turn-on voltage range of the MOS channel diode formed by the second contact region 152, the body region 13 located below the second contact region 152, the second pillar 122, the first pillar 121, and the second trench structure 22 adjacent to the contact region 152 is 0.3 V to 0.7 V.

[0126] Specifically, by adjusting the distance between two adjacent second trench structures 22, the turn-on voltage of the MOS channel diode can be adjusted.

[0127] Specifically, since the turn-on voltages of the channel MOS diode formed by the second contact region 152, the body region 13 located below the second contact region 152, the second pillar 122, the first pillar 121, and the second trench structure 22 adjacent to the contact region 152 and the Schottky diode formed by the second contact region 152 and the source 4 are both lower than the turn-on voltage of the PN junction of the silicon device, when the device conducts in the reverse direction, the single-carrier conducting Schottky diode and MOS channel diode can significantly reduce the injection efficiency of the PN junction diode, thereby reducing the number of carriers in the drift region of the device, and then reducing the reverse recovery loss of the device. Moreover, since it does not adopt the carrier lifetime control technology, it will not increase the on-resistance and cost of the device.

[0128] Specifically, since a Schottky contact is formed between the third contact region 153 and the source electrode 4, the third contact region 153 and the source electrode 4 also form a Schottky diode. By adjusting the doping concentration of the third contact region 153, the occurrence of the conductance modulation effect in the device can be suppressed, the injection efficiency of the PN junction in the device can be reduced, and the reverse recovery loss of the device can be further reduced.

[0129] Specifically, the Schottky diodes formed by the third contact region 153 and the source electrode 4 and the Schottky diodes of the second contact region 152 and the trench of the source electrode 4 are both protected by the second trench structure 22 and the body region 13, avoiding the problem of high leakage current generated by the introduced Schottky diodes.

[0130] The trench-gate superjunction MOS device of this embodiment improves the structure of the device. While arranging the first trench structure 21 with a bottom surface penetrating the body region 13 and extending to the first column 121 above each first column 121, at least two second trench structures 22 penetrating the body region 13 and extending to the second column 122 are arranged above each second column 122. The side wall of the second trench structure 22 adjacent to the first trench structure 21 extends into the first column 121 in the X direction, and the second contact region 152 and the third contact region 153 are formed on the upper surface layer of the body region 13 between two adjacent second trench structures 22. Both the second contact region 152 and the third contact region 153 form Schottky contact diodes with the source electrode 4. The second contact region 152, the body region 13 below the second contact region 152, the second column 122, the first column 121, and the second trench structure 22 adjacent to the contact region 152 form a channel MOS diode. The turn-on voltages of the Schottky diode and the MOS channel diode are lower than the turn-on voltage of the PN junction. When the device conducts in the reverse direction, the Schottky diode with single-carrier conduction and the MOS channel diode can significantly reduce the injection efficiency of the PN junction diode, reduce the number of carriers in the drift region, and then reduce the reverse recovery loss of the device. In addition, due to the setting of the Schottky diode formed by the third contact region 153 and the source electrode 4, the occurrence of the conductance modulation effect in the device can be further suppressed, and then the injection efficiency of the PN junction diode can be further reduced, and the reverse recovery loss of the device can be reduced. Moreover, since the Schottky diodes formed by the second contact region 152 and the third contact region 153 and the source electrode 4 are protected by the second trench structure 22 and the body region 13, the problem of high leakage caused by introducing Schottky contacts is avoided, and the performance of the device is improved.

[0131] Embodiment 2

[0132] This embodiment provides a method for manufacturing a trench-gate superjunction MOS device. As Figure 7 shown, it is a process flow chart of the method for manufacturing the trench-gate superjunction MOS device, including the following steps:

[0133] S1: Provide a semiconductor structure, which includes a first-conductivity-type semiconductor layer, a pillar region, and a second-conductivity-type body region stacked in sequence. The pillar region includes a plurality of first-conductivity-type first pillars and second-conductivity-type second pillars alternately arranged in the X direction;

[0134] S2: Form a trench structure on the upper surface layer of the semiconductor structure, which includes a plurality of first trench structures and second trench structures spaced apart in the X direction and penetrating the body region. The bottom surface of the first trench structure extends into the first pillar. There are at least two second trench structures with bottom surfaces extending into the same second pillar spaced between two adjacent first trench structures in the X direction. The side wall of the second trench structure adjacent to the first trench structure extends into the first pillar in the X direction;

[0135] S3: Form a first-conductivity-type source region on the upper surface layer of the body region on both sides of the first trench structure in the X direction. The source region is adjacent to the side wall of the first trench structure;

[0136] S4: Form a contact region including a second-conductivity-type first contact region, a first-conductivity-type second contact region, and a second-conductivity-type third contact region on the upper surface layer of the body region. The first contact region is located between the adjacent first trench structure and the second trench structure and is adjacent to the source region. The second contact region is adjacent to at least the side wall of the second trench structure adjacent to the first trench structure. The third contact region is located between two adjacent second trench structures and at least one third contact region is adjacent to the second contact region;

[0137] S5: Form an interlayer dielectric layer covering the upper surface of the semiconductor structure;

[0138] S6: Form a source electrode electrically connected to the source region, the contact region, and the second trench structure. The second contact region and the third contact region both form Schottky contacts with the source electrode. Form a gate electrode electrically connected to the first trench structure, and form a drain electrode electrically connected to the semiconductor layer.

[0139] Please refer to Figures 8 to 9, perform the steps S1, S2, and S3: Provide a semiconductor structure 1, which includes a first-conductivity-type semiconductor layer 11, a column region 12, and a second-conductivity-type body region 13 stacked in sequence. The column region 12 includes a plurality of first-conductivity-type first columns 121 and second-conductivity-type second columns 122 alternately arranged in the X direction; form a trench structure 2 on the upper surface of the semiconductor structure 1, which includes a plurality of first trench structures 21 and second trench structures 22 spaced apart in the X direction and penetrating the body region. The bottom surface of the first trench structure 21 extends into the first column 121. At least two second trench structures 22 whose bottom surfaces extend into the same second column 122 are spaced between two adjacent first trench structures 21 in the X direction. The side wall of the second trench structure 22 adjacent to the first trench structure 21 extends into the first column 121 in the X direction; form a first-conductivity-type source region 14 on the upper surface of the body region 13 on both sides of the first trench structure 21 in the X direction. The source region 14 is adjacent to the side wall of the first trench structure 21.

[0140] Specifically, as Figure 8 shown, it is a schematic cross-sectional structure diagram of the semiconductor structure 1. The semiconductor layer 11 includes a first-conductivity-type substrate 111 and a first-conductivity-type buffer layer 112 stacked in sequence. The doping concentration of the substrate 111 is greater than that of the buffer layer 112.

[0141] Specifically, under the condition of ensuring device performance, the doping concentration of the first column 121 can be selected according to actual situations and will not be limited here; the doping concentration of the second column 122 can be selected according to actual situations and will not be limited here.

[0142] Specifically, the doping concentration of the body region 13 gradually increases from the bottom surface of the body region 13 upward.

[0143] Specifically, as Figure 9As shown, it is a schematic cross-sectional structure diagram after forming the trench structure 2. The first trench structure 21 includes a first trench 211, a first gate dielectric layer 212, and a first gate conductive layer 213. The second trench structure 22 includes a second trench 221, a second gate dielectric layer 222, and a second gate conductive layer 223. The first trench 211 and the second trench 221 are embedded in the semiconductor structure 1. The first gate dielectric layer 212 covers the inner wall and bottom surface of the first trench 211. The second gate dielectric layer 222 covers the inner wall and bottom surface of the second trench 221. The first gate conductive layer 213 fills the first trench 211. The second gate conductive layer 223 fills the second trench 221. The first gate conductive layer 213 is electrically connected to the gate of the device. The second gate conductive layer 223 is electrically connected to the source of the device. The first gate dielectric layer 212 wraps the side wall and bottom surface of the first gate conductive layer 213. The second gate dielectric layer 222 wraps the side wall and bottom surface of the second gate conductive layer 223.

[0144] Specifically, the method for forming the first trench 211 includes dry etching, wet etching, or other suitable methods; the method for forming the second trench 221 includes dry etching, wet etching, or other suitable methods.

[0145] Specifically, under the condition of ensuring device performance, the first trench 211 and the second trench 221 can be formed synchronously or step by step; the opening sizes and shapes of the first trench 211 and the second trench 221 can be the same or different. In this embodiment, in order to save costs and simplify the process, the first trench 211 and the second trench 221 are formed synchronously, and the opening sizes and shapes of the first trench 211 and the second trench 221 are also the same.

[0146] Specifically, the method for forming the first gate dielectric layer 212 includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the second gate dielectric layer 222 includes thermal oxidation, chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0147] Specifically, under the condition of ensuring device performance, the first gate dielectric layer 212 and the second gate dielectric layer 222 can be formed synchronously or step by step. In this embodiment, the first gate dielectric layer 212 and the second gate dielectric layer 222 are formed synchronously.

[0148] Specifically, the method for forming the first gate conductive layer 213 includes chemical vapor deposition, physical vapor deposition, or other suitable methods; the method for forming the second gate conductive layer 223 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0149] Specifically, on the premise of ensuring device performance, the first gate conductive layer 213 and the second gate conductive layer 223 can be formed synchronously or step by step. In this embodiment, the first gate conductive layer 213 and the second gate conductive layer 223 are formed synchronously.

[0150] Specifically, the method for forming the source region 14 includes ion implantation or other suitable methods.

[0151] Please refer to Figures 10 to 11 , and perform step S4, step S5, and step S6: form a contact region 15 including a first contact region 151 of the second conductivity type on the upper surface layer of the body region 13, a second contact region 152 of the first conductivity type, and a third contact region 153 of the second conductivity type. The first contact region 151 is located between the adjacent first trench structure 21 and the second trench structure 22 and is adjacent to the source region 14. The second contact region 152 is adjacent to at least the sidewall of the second trench structure 22 adjacent to the first trench structure 21. The third contact region 153 is located between two adjacent second trench structures 22, and at least one third contact region 153 is adjacent to the second contact region 152; form an interlayer dielectric layer 3 covering the upper surface of the semiconductor structure 1; form a source electrode 4 electrically connected to the source region 14, the contact region 15, and the second trench structure 22, and Schottky contacts are formed between the second contact region 152 and the third contact region 153 and the source electrode 4. Form a gate electrode electrically connected to the first trench structure 21, and form a drain electrode 5 electrically connected to the semiconductor layer 11.

[0152] Specifically, as Figure 10 shown, it is a schematic cross-sectional structure diagram after forming the contact region 15. The method for forming the first contact region 151 includes ion implantation or other suitable methods; the method for forming the second contact region 152 includes ion implantation or other suitable methods; the method for forming the third contact region 153 includes ion implantation or other suitable methods.

[0153] Specifically, in the X direction, the sidewall of the first contact region 151 away from the source region 14 is adjacent to the sidewall of the second trench structure 22, that is, the sidewall of the first contact region 151 and the sidewall of the second trench 221 between the adjacent first trench structure 21 and the second trench structure 22 are adjacent.

[0154] Specifically, the second contact regions 152 may also be formed on both sides of the second trench structure 22 adjacent to the first trench structure 21 in the X direction. The second contact region 152 adjacent to the sidewall of the second trench structure 22 close to the first trench structure 21 is adjacent to the sidewall of the first contact region 151 away from the source region 14. That is, the second contact region 152 may also be formed on the upper surface layer of the body region 13 between the first trench 211 and the second trench 221, and the sidewalls of the second contact region 152 in the X direction are adjacent to the second trench 221 and the first contact region 151 respectively.

[0155] Specifically, a third contact region 153 adjacent to the second trench structure 22 is further formed on the upper surface layer of the second contact region 152, and the third contact region 153 located on the upper surface layer of the second contact region 152 is spaced apart from the sidewall and the bottom surface of the second contact region 152 away from the second trench structure 22 by a preset distance.

[0156] Specifically, the method for forming the interlayer dielectric layer 3 includes chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0157] Specifically, after forming the interlayer dielectric layer 3 and before forming the source electrode 4 and the gate electrode, the steps of forming a source electrode contact hole 31 and a gate electrode contact hole are further included. The bottom surface of the source electrode contact hole 31 exposes the source region 14, the first contact region 151, the second contact region 152, the third contact region 153, and each of the second gate conductive layers 223, and the bottom surface of the gate electrode contact hole exposes the first gate conductive layer 213.

[0158] Specifically, as Figure 11 shown, it is a schematic cross-sectional structure diagram after forming the source electrode contact hole 31. The method for forming the source electrode contact hole 31 includes dry etching, wet etching, or other suitable methods; the method for forming the gate electrode contact hole includes dry etching, wet etching, or other suitable methods.

[0159] Specifically, the source electrode 4 fills the source electrode contact hole 31, the gate electrode fills the gate electrode contact hole, and the drain electrode 5 covers the bottom surface of the semiconductor layer 11.

[0160] Specifically, the method for forming the source 4 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; the method for forming the drain 5 includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods; the method for forming the gate includes magnetron sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0161] Specifically, at least two second trench structures 22 that penetrate the body region 13 and whose bottom surfaces extend into the second column 122 are formed above each of the second columns 122, a first trench structure 21 that penetrates the body region 13 and whose bottom surface extends into the first column 121 is formed above the first column 121, and the side walls of the second trench structures adjacent to the first trench structure 21 extend into the first column 121. The second contact region 152 and the third contact region 153 are formed on the upper surface layer of the body region 13 between two adjacent second trench structures 22 above the second column 122. The second contact region 152 and the source 4, and the third contact region 153 and the source 4 respectively form Schottky diodes with turn-on voltages less than the turn-on voltage of the PN junction. The second contact region 152, the body region 13 below the second contact region 152, the second column 122, the first column 121, and the second trench structure 22 adjacent to the second contact region 152 form a MOS channel diode with a turn-on voltage less than the turn-on voltage of the PN junction. Since the turn-on voltages of both the Schottky diode and the MOS channel diode are less than the turn-on voltage of the PN junction, the injection efficiency of the PN junction diode is reduced, thereby reducing the number of carriers in the drift region and lowering the reverse recovery loss of the device.

[0162] Specifically, since the third contact region 153 and the source 4 form a Schottky diode, the occurrence of the conductance modulation effect in the device can be suppressed, further reducing the injection efficiency of the PN junction, thereby reducing the reverse recovery loss of the device and improving the device performance.

[0163] The manufacturing method of the trench-gate superjunction MOS device of this embodiment forms at least two of the second trench structures 22 above the second column 122, and the sidewalls of the second trench structures 22 adjacent to the first trench structure 21 above the first column 121 extend into the first column 121, and the second contact region 152 and the third contact region 153 are formed on the upper surface layer of the body region 13 between two adjacent second trench structures 22 above the second column 122. The second contact region 152 and the third contact region 152 respectively form Schottky diodes with the source electrode 4. The second contact region 152, the body region 13 below the second contact region 152, the second column 122, the first column 121, and the second trench structure 22 adjacent to the second contact region 152 form a MOS channel diode, reducing the reverse recovery loss of the device and improving the performance of the device.

[0164] In summary, the trench-gate superjunction MOS device and its manufacturing method of the present invention improve the device structure by forming a first trench structure that penetrates the body region and whose bottom surface extends into the first column and a second trench structure that penetrates the body region and whose bottom surface extends into the second column in the semiconductor structure, and there are at least two second trench structures whose bottom surfaces extend into the same second column. The sidewalls of the second trench structures adjacent to the first trench structure extend into the first column in the X direction, and a second contact region and a third contact region are formed on the upper surface layer of the body region between two adjacent second trench structures above the same second column region. The second contact region forms a Schottky diode with the source electrode whose turn-on voltage is less than the turn-on voltage of the PN junction. The second contact region, the body region below the second contact region, the second column, the first column, and the second trench structure adjacent to the second contact region form a MOS channel diode whose turn-on voltage is less than the turn-on voltage of the PN junction. When the device conducts in the reverse direction, the Schottky diode with single-carrier conduction formed by the second contact region and the source electrode and the MOS channel diode can greatly reduce the injection efficiency of the PN junction diode, reduce the number of carriers in the drift region, and then reduce the reverse recovery loss of the device. In addition, due to the Schottky diode formed by the third contact region and the source electrode, the occurrence of the conductance modulation effect in the device can be further suppressed through this Schottky diode, and then the injection efficiency of the PN junction diode can be further reduced, reducing the reverse recovery loss of the device. And because the second contact region and the third contact region are located on the upper surface layer of the body region between two adjacent second trench structures above the same second column region, the second trench structure and the body region are used to protect the Schottky diodes formed by the second contact region and the third contact region and the source electrode, avoiding the problem of high leakage caused by introducing Schottky contacts and improving the performance of the device. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0165] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A trench-gate superjunction MOS device, characterized in that Comprising: A semiconductor structure, including a first-conductivity-type semiconductor layer, a column region, and a second-conductivity-type body region that are stacked in sequence. The column region includes a plurality of first-conductivity-type first columns and second-conductivity-type second columns that are alternately arranged in sequence along the X direction; A trench structure, including a plurality of first trench structures and second trench structures that are spaced apart along the X direction and penetrate the body region. The bottom surface of the first trench structure extends into the first column. There are at least two second trench structures with bottom surfaces extending into the same second column spaced between two adjacent first trench structures in the X direction. The side wall of the second trench structure adjacent to the first trench structure extends into the first column in the X direction; A first-conductivity-type source region, located on the upper surface layer of the body region on both sides of the first trench structure in the X direction and adjacent to the side wall of the first trench structure; A contact region, including a second-conductivity-type first contact region, a first-conductivity-type second contact region, and a second-conductivity-type third contact region located on the upper surface layer of the body region. The first contact region is located between the adjacent first trench structure and the second trench structure and is adjacent to the source region. The second contact region is adjacent to at least the side wall of the second trench structure adjacent to the first trench structure. The third contact region is located between two adjacent second trench structures, and at least one third contact region is adjacent to the second contact region; An interlayer dielectric layer, covering the upper surface of the semiconductor structure; A source electrode, a drain electrode, and a gate electrode. The source electrode is electrically connected to the source region, the contact region, and the second trench structure. Schottky contacts are formed between the second contact region and the third contact region and the source electrode. The drain electrode is electrically connected to the semiconductor layer. The gate electrode is electrically connected to the first trench structure.

2. The trench-gate superjunction MOS device according to claim 1, wherein: The semiconductor layer includes a first-conductivity-type substrate and a first-conductivity-type buffer layer that are stacked in sequence. The substrate is electrically connected to the drain electrode. The column region is located on the upper surface of the buffer layer.

3. The trench-gate superjunction MOS device according to claim 1, characterized in that: The first trench structure includes a first trench, a first gate dielectric layer, and a first gate conductive layer. The second trench structure includes a second trench, a second gate dielectric layer, and a second gate conductive layer. The first trench and the second trench are embedded in the semiconductor structure. The first gate dielectric layer covers the inner wall and the bottom surface of the first trench. The second gate dielectric layer covers the inner wall and the bottom surface of the second trench. The first gate conductive layer fills the first trench. The second gate conductive layer fills the second trench. The first gate conductive layer is electrically connected to the gate electrode. The second gate conductive layer is electrically connected to the source electrode.

4. The trench-gate superjunction MOS device according to claim 1, characterized in that: The doping concentration of the body region gradually increases from bottom to top.

5. The trench-gate superjunction MOS device according to claim 1, wherein: In the X direction, the side wall of the first contact region away from the source region is adjacent to the side wall of the second trench structure.

6. The trench-gate superjunction MOS device according to claim 1, characterized in that: The upper surface layer of the second contact region is further provided with the third contact region adjacent to the second trench structure, and the third contact region located on the upper surface layer of the second contact region is spaced apart from the side wall and the bottom surface of the second contact region away from the second trench structure by a preset distance.

7. The trench-gate superjunction MOS device according to claim 1, characterized in that: The second trench structure adjacent to the first trench structure is provided with the second contact regions on both sides in the X direction, and the second contact region adjacent to the side wall of the second trench structure close to the first trench structure is adjacent to the side wall of the first contact region away from the source region.

8. The trench-gate superjunction MOS device according to claim 1, wherein: The doping concentration of the body region below the second contact region is lower than that of the second contact region.

9. The trench-gate superjunction MOS device according to claim 1, wherein: The barrier height range of the Schottky contact formed by the second contact region and the source electrode is 0.6 eV to 0.9 eV, and the turn-on voltage range of the Schottky diode formed by the second contact region and the source electrode is 0.3 V to 0.5 V.

10. The trench-gate superjunction MOS device according to claim 1, wherein: The turn-on voltage range of the MOS channel diode formed by the second contact region, the body region below the second contact region, the second pillar, the first pillar, and the second trench structure adjacent to the second contact region is 0.3 V to 0.7 V.

11. A preparation method of a trench-gate superjunction MOS device, characterized in that, Comprising the following steps: Providing a semiconductor structure, the semiconductor structure includes a first-conductivity-type semiconductor layer, a pillar region, and a second-conductivity-type body region stacked in sequence, and the pillar region includes a plurality of first-conductivity-type first pillars and second-conductivity-type second pillars alternately arranged in the X direction; Forming a trench structure on the upper surface layer of the semiconductor structure, the trench structure includes a plurality of first trench structures and second trench structures arranged at intervals in the X direction and penetrating the body region, the bottom surface of the first trench structure extends into the first pillar, and at least two second trench structures with bottom surfaces extending into the same second pillar are spaced between two adjacent first trench structures in the X direction, and the side wall of the second trench structure adjacent to the first trench structure extends into the first pillar in the X direction; Forming a first-conductivity-type source region on the upper surface layer of the body region on both sides of the first trench structure in the X direction, and the source region is adjacent to the side wall of the first trench structure; Forming a contact region including a second-conductivity-type first contact region, a first-conductivity-type second contact region, and a second-conductivity-type third contact region on the upper surface layer of the body region, the first contact region is located between the adjacent first trench structure and the second trench structure and is adjacent to the source region, the second contact region is adjacent to at least the side wall of the second trench structure adjacent to the first trench structure, and the third contact region is located between two adjacent second trench structures and at least one third contact region is adjacent to the second contact region; Forming an interlayer dielectric layer covering the upper surface of the semiconductor structure; Forming a source electrode electrically connected to the source region, the contact region, and the second trench structure, and both the second contact region and the third contact region form Schottky contacts with the source electrode, forming a gate electrically connected to the first trench structure, and forming a drain electrically connected to the semiconductor layer.

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