Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a substrate which comprises a first surface and a second surface which are opposite to each other; the accumulation regions are located in the substrate, the deep doping regions are located between the adjacent accumulation regions, and the accumulation regions and the deep doping regions are exposed out of the first surface; the grid layers are located on the first surface, the deep doping regions are exposed between the adjacent grid layers, first openings are formed in the grid layers, and part of the accumulation regions are exposed out of the first openings; the connecting layer is positioned on the side wall and the bottom surface of the first opening; since the side wall and the bottom of the first opening of the connection layer located on the surface of the accumulation region replace the traditional whole block located on the surface of the accumulation region, the problem that the surface is easy to peel due to overlarge area of the connection layer is avoided; and on the other hand, the deep doping layer is exposed between the adjacent gate layers, and the gate layers are internally provided with the first openings for exposing part of the accumulation region, so that the sparsity of the whole pattern is uniform due to the introduction of the first openings, and the photoetching and etching uniformity can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] Power devices are the basic electronic components for energy control and conversion in power electronic systems. The continuous development of power electronic technology has opened up a wide range of application fields for semiconductor power. The controllable characteristics of semiconductor power devices determine the efficiency, volume, and weight of power electronic systems. The first industrial general thyristor was developed by General Electric Company of the United States in 1957, which marked the birth of modern power electronic technology. Since then, power electronic conversion devices with power converters as the core have been applied to almost all fields of modern industry. Since the birth of power devices of vertical double-diffused transistors, power electronics has developed rapidly. Due to its unique characteristics such as high input impedance, low drive power, high switching speed, excellent frequency characteristics, and good thermal stability, it is widely used in various fields such as switching power supplies, automotive electronics, motor drives, and high-frequency oscillators.

[0003] For a vertical double-diffused MOSFET (VDMOS), the drain and source electrodes are respectively on both sides of the device, enabling the current to flow vertically inside the device, increasing the current density, improving the rated current, and having a relatively small on-resistance per unit area. It is a very widely used power device. Due to its good performance and high integration, VDMOS transistors are increasingly used in the field of semiconductor integrated circuits.

[0004] However, the performance of existing power devices is poor. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to improve the performance of the semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, including: a substrate including opposite first and second surfaces; a plurality of accumulation regions located in the substrate and deep doping regions located between adjacent accumulation regions, and the first surface exposes the accumulation regions and the deep doping regions; a plurality of gate layers located on the first surface, the deep doping regions are exposed between adjacent gate layers, the gate layers have first openings, and the first openings expose a part of the accumulation regions; a connection layer located on the sidewalls and bottom surfaces of the first openings.

[0007] Optionally, it further includes: a bulk doping region located in the deep doping region, a first source doping region and a second source doping region located in the bulk doping region, the second source doping region being located between adjacent first source doping regions, the bulk doping region being doped with P-type ions, the first source doping region being doped with N-type ions, the second source doping region being doped with P-type ions, the doping concentration of the first source doping region being greater than that of the bulk doping region, and the doping concentration of the second source doping region being greater than that of the bulk doping region.

[0008] Optionally, it further includes: a first conductive plug located on the surface of the second source doping region.

[0009] Optionally, it further includes: a second conductive plug located on the surface of the connection layer.

[0010] Optionally, the doping ions in the accumulation region are of the opposite type to those in the deep doping region, and the doping depth of the accumulation region is less than that of the deep doping region.

[0011] Optionally, it further includes a gate dielectric layer located between the first surface and the gate layer, and the material of the gate dielectric layer includes silicon oxide.

[0012] Optionally, the material of the gate layer includes polysilicon.

[0013] Optionally, it further includes: a drain doping region located in the substrate, and the second surface exposes the drain doping region.

[0014] Optionally, it further includes a sidewall layer located between the connection layer and the gate layer, and the material of the sidewall layer includes silicon oxide.

[0015] Correspondingly, the present invention also provides a method for forming a semiconductor structure, including: providing a substrate including opposite first and second surfaces; forming a plurality of deep doping regions in the substrate; forming an accumulation region in the substrate between adjacent deep doping regions, with the first surface exposing the accumulation region and the deep doping regions; forming a plurality of gate layers on the surface of the first surface, with the deep doping regions exposed between adjacent gate layers, and having a first opening in the gate layer, the first opening exposing a part of the accumulation region; and forming a connection layer on the sidewall and bottom surface of the first opening.

[0016] Optionally, the method for forming the substrate includes providing a substrate, and forming an N-type epitaxial layer on the surface of the substrate, and the N-type epitaxial layer is the first surface.

[0017] Optionally, the method for forming the deep doping region includes: forming a first photoresist layer on the surface of the first surface, the first photoresist layer exposing a part of the surface of the substrate; etching the exposed substrate to form a trench therein; and performing epitaxial growth and in-situ doping in the trench to form the deep doping region.

[0018] Optionally, the method of forming the accumulation region includes: forming a second photoresist layer on the surface of the first side, and the second photoresist layer exposes the surface of the substrate between adjacent deep doping regions; performing ion implantation on the exposed substrate and performing high-temperature activation to form the accumulation region.

[0019] Optionally, the method of forming the gate layer includes: forming a gate dielectric layer on the surface of the first side; forming an initial gate layer on the surface of the gate dielectric layer; patterning the initial gate layer to form the gate layer, and the gate layer has a first opening exposing a part of the accumulation region and a second opening exposing the deep doping region.

[0020] Optionally, after forming the gate layer, it further includes performing P-type ion implantation on the deep doping region to form a body doping region; performing N-type ion implantation on the body doping region to form a first source doping region; performing P-type ion implantation on the body doping region to form a second source doping region, and the second source doping region is located between adjacent first source doping regions, and the doping concentration of the first source doping region is greater than that of the body doping region, and the doping concentration of the second source doping region is greater than that of the body doping region.

[0021] Optionally, the method of forming the connection layer includes: forming an initial spacer layer on the surface of the gate layer, the sidewalls and the bottom of the first opening, and the sidewalls and the bottom of the second opening; forming an initial connection layer on the surface of the initial spacer layer; etching the initial connection layer and the initial spacer layer to form a spacer layer and a connection layer on the sidewalls of the first opening and the second opening.

[0022] Optionally, the material of the spacer layer includes silicon oxide, the material of the connection layer includes polysilicon, and the material of the gate layer includes polysilicon.

[0023] Optionally, after forming the connection layer, it further includes: forming a passivation layer on the surface of the gate layer, inside the first opening and inside the second opening; etching the passivation layer to form a first through hole exposing the surface of the second source doping region and a second through hole exposing the surface of the connection layer in the passivation layer; forming a first conductive plug in the first through hole; forming a second conductive plug in the second through hole.

[0024] Optionally, it further includes performing N-type heavy ion doping on the substrate of the second side to form a drain doping region.

[0025] Optionally, after forming the drain doping region, it further includes forming a conductive layer on the surface of the second side and the surface of the passivation layer respectively.

[0026] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0027] In the semiconductor structure of the technical solution of the present invention, the substrate includes opposite first and second surfaces. There are several accumulation regions and deep doping regions located between adjacent accumulation regions in the substrate. The first surface exposes the accumulation regions and the deep doping regions. The gate layer is located on the first surface, and a first opening exposing the accumulation region is formed in the gate layer. The sidewall and bottom surface of the first opening have a connection layer. Since the connection layer on the sidewall and bottom of the first opening on the surface of the accumulation region replaces the traditional monolithic one on the surface of the accumulation region, the problem of easy surface peeling due to the too large area of the connection layer is avoided. On the other hand, the deep doping layer is exposed between adjacent gate layers, and the gate layer has a first opening exposing a part of the accumulation region. The introduction of such a first opening makes the sparsity of the entire pattern uniform, thus contributing to improving the uniformity of lithography and etching. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1 to 9 are schematic structural diagrams of each step of a semiconductor structure and a method for forming the same according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] As in the background art, the performance of existing power devices is poor.

[0030] The inventors found that in the prior art, polysilicon is directly covered on the upper ends of the channel region and the accumulation region of the power device. The problem with this approach is that the area of the polysilicon is too large, bringing great stress to the process manufacturing of the entire wafer. At the same time, the too large area of the polysilicon is prone to cause the problem of surface peeling.

[0031] On this basis, the present invention provides a semiconductor structure. The substrate includes opposite first and second surfaces. There are several accumulation regions and deep doping regions located between adjacent accumulation regions in the substrate. The first surface exposes the accumulation regions and the deep doping regions. The gate layer is located on the first surface, and a first opening exposing the accumulation region is formed in the gate layer. The sidewall and bottom surface of the first opening have a connection layer. Since the connection layer on the sidewall and bottom of the first opening on the surface of the accumulation region replaces the traditional monolithic one on the surface of the accumulation region, the problem of easy surface peeling due to the too large area of the connection layer is avoided. On the other hand, the deep doping layer is exposed between adjacent gate layers, and the gate layer has a first opening exposing a part of the accumulation region. The introduction of such a first opening makes the sparsity of the entire pattern uniform, thus contributing to improving the uniformity of lithography and etching.

[0032] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0033] Figures 1 to 9 are schematic structural diagrams of each step of a semiconductor structure and a method for forming the same according to an embodiment of the present invention.

[0034] First, please refer toFigure 1 , a substrate 100 is provided, and the substrate 100 includes opposite first surface 100a and second surface 100b.

[0035] In this embodiment, the substrate 100 is an N-type substrate.

[0036] In this embodiment, the forming method of the substrate 100 includes providing a base, forming an N-type epitaxial layer on the surface of the base, and the N-type epitaxial layer is the first surface 100a.

[0037] Please refer to Figure 2 , a trench 101 is formed in the substrate 100, and epitaxial growth is carried out in the trench 101 and in-situ doping is carried out to form a deep doping region 102.

[0038] In this embodiment, the method of forming the trench 101 includes forming a first photoresist layer on the surface of the first surface 100a, and the first photoresist layer exposes a part of the surface of the substrate 100; etching the exposed substrate 100 to form a trench 101 in the substrate 100.

[0039] In this embodiment, after the trench 101 is formed, the first photoresist layer is removed.

[0040] In this embodiment, the depth range of the trench 101 is greater than 1 micron.

[0041] In this embodiment, the method of forming the trench 101 is a dry etching process, and the specific parameters include: the gases used include CF4 and CH3F, the flow rate of CF4 is 20 sccm to 200 sccm, the flow rate of CH3F is 20 sccm to 50 sccm, the source radio frequency power is 200 watts to 500 watts, and the chamber pressure is 1 torr to 10 torr..

[0042] In this embodiment, the process parameters of the epitaxial growth include the gases used include hydrogen gas, HCl gas, SiH2Cl2, PH3 and CH3SiH3 gases, the flow rate of hydrogen gas is 2000 sccm to 20000 sccm, the flow rate of HCl gas is 30 sccm to 150 sccm, the flow rate of SiH2Cl2 is 50 sccm to 1000 sccm, the flow rate of PH3 is 10 sccm to 2000 sccm, the flow rate of CH3SiH3 is 50 sccm to 5000 sccm, the chamber pressure is 10 torr to 600 torr, and the temperature is 650 degrees Celsius to 850 degrees Celsius.

[0043] In this embodiment, in-situ doping is carried out on the epitaxial layer of the epitaxial growth, and the doping ions include boron ions to form a deep doping region 102.

[0044] In other embodiments, the doping ions may also include BF 2- ions or indium ions.

[0045] Please refer to Figure 3 , and a plurality of accumulation regions 103 are formed in the substrate 100.

[0046] In this embodiment, the method for forming the accumulation region 103 includes forming a second photoresist layer on the surface of the first surface 100a, and the second photoresist layer exposes the surface of the substrate 100 between adjacent deep doping regions 102; performing ion implantation on the exposed substrate 100 and performing high-temperature activation to form the accumulation region 103.

[0047] In this embodiment, the second photoresist layer is removed after the accumulation region 103 is formed.

[0048] In this embodiment, phosphorus ion implantation is performed on the exposed substrate 100 to form the accumulation region 103, and the ion type implanted in the accumulation region 103 is opposite to the ion type implanted in the deep doping region 102.

[0049] In this embodiment, the ion implantation concentration of the accumulation region 103 is less than the ion implantation concentration of the deep doping region 102.

[0050] In this embodiment, after the accumulation region 103 is formed, the second photoresist layer is removed.

[0051] Please refer to the process of forming a plurality of gate layers on the surface of the first surface 100a, with the deep doping region 102 exposed between adjacent gate layers Figures 4 to 5 .

[0052] Please refer to Figure 4 , and a gate layer 105 is formed on the surface of the first surface 100a.

[0053] In this embodiment, the method for forming the gate layer 105 includes forming a gate dielectric layer 104 on the surface of the first surface 100a; forming an initial gate layer (not shown in the figure) on the surface of the gate dielectric layer 104, and patterning the initial gate layer to form the gate layer 105. The gate layer 105 has a first opening 106 exposing a part of the accumulation region 103 and a second opening 107 exposing the deep doping region 102.

[0054] In this embodiment, the material of the gate dielectric layer 104 is silicon oxide.

[0055] In this embodiment, the formation process of the gate dielectric layer 104 is a thermal oxidation process.

[0056] In other embodiments, the formation process of the gate dielectric layer 104 can also be a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, etc.

[0057] In this embodiment, the second opening 107 serves as an injection opening, and the existence of the first opening 106 reserves space for the subsequent formation of a connection layer.

[0058] In this embodiment, the first opening 106 exposes the surface of a part of the gate dielectric layer 104 on the surface of the accumulation region 103.

[0059] In this embodiment, due to the existence of the first opening 106, a common connection with the source end (the first source doping region SN and the second source doping region SP) is achieved, which is equivalent to increasing the length of the source end (the first source doping region SN and the second source doping region SP). During operation, it is always connected to the 0 potential, increasing the reverse breakdown voltage (BV).

[0060] In this embodiment, the material of the gate layer 105 includes polysilicon.

[0061] Please refer to Figure 5 , a P-type ion implantation is performed on the deep doping region 102 to form a body doping region 108; an N-type ion implantation is performed on the body doping region 108 to form a first source doping region 109; a P-type ion implantation is performed on the body doping region 108 to form a second source doping region 110. The second source doping region 110 is located between adjacent first source doping regions 109. The doping concentration of the first source doping region 109 is greater than that of the body doping region 108, and the doping concentration of the second source doping region 110 is greater than that of the body doping region 108.

[0062] In this embodiment, a P-type ion implantation is performed on the deep doping region 102 from the second opening 107 to form a body doping region 108, and the concentration of the implanted ions in the body doping region 108 is relatively high.

[0063] In this embodiment, the doping ions in the body doping region 108 include boron ions, BF 2- ions or indium ions.

[0064] In this embodiment, an N-type ion implantation is performed on the body doping region 108 to form a first source doping region 109 for the body doping region 108 through a self-alignment process; a P-type ion implantation is performed on the body doping region 108 using a mask layer to form a second source doping region 110. The second source doping region 110 is located between adjacent first source doping regions 109.

[0065] In this embodiment, both the first source doping region 109 and the second source doping region 110 have a relatively high doping concentration. The doping concentration of the first source doping region 109 is greater than that of the body doping region 108, and the doping concentration of the second source doping region 110 is greater than that of the body doping region 108.

[0066] In this embodiment, the doping ions of the first source doping region 109 include phosphorus ions or arsenic ions.

[0067] In this embodiment, the doping ions of the second source doping region 110 include boron ions, BF 2- ions or indium ions.

[0068] Please refer to Figure 6 , a connection layer 112 is formed on the sidewall and bottom surface of the first opening 106.

[0069] In this embodiment, the method of forming the connection layer includes: forming an initial sidewall layer (not shown in the figure) on the surface of the gate layer 105, the sidewalls and bottom of the first opening 106, and the sidewalls and bottom of the second opening 107; forming an initial connection layer (not shown in the figure) on the surface of the initial sidewall layer; etching the initial connection layer and the initial sidewall layer to form a sidewall layer 111 and a connection layer 112 on the sidewalls of the first opening 106 and the second opening 107.

[0070] In this embodiment, the material of the sidewall layer 111 includes silicon oxide, and the material of the connection layer 112 includes polysilicon.

[0071] In this embodiment, the first opening 106 exposes the surface of a part of the accumulation region 103, and the connection layer 112 is formed on the sidewall and bottom of the first opening, replacing the traditional connection layer 112 formed directly and integrally on the surface of the accumulation region 103, thus avoiding the problem of easy surface peeling due to the too large area of the connection layer 112; on the other hand, the gate layer 105 has both the first opening 106 and the second opening 107 at the same time, replacing the traditional pattern with only the second opening 107. The introduction of this first opening 106 makes the sparsity of the entire pattern uniform, thereby contributing to improving the uniformity of photolithography and etching and preparing for improving the quality of the semiconductor structure.

[0072] Please refer to Figure 7 , after forming the connection layer 112, it further includes: forming a passivation layer 113 on the surface of the gate layer 105, inside the first opening 106 and inside the second opening 107; etching the passivation layer 113 to form a first through hole exposing the surface of the second source doping region 110 and a second through hole exposing the surface of the connection layer 112 in the passivation layer 113; forming a first conductive plug 114 in the first through hole; forming a second conductive plug 115 in the second through hole.

[0073] In this embodiment, the material of the passivation layer 113 is silicon oxide.

[0074] In other embodiments, the material of the passivation layer 113 can also be silicon carbide, silicon nitride, etc.

[0075] In this embodiment, the process for forming the passivation layer 113 is an atomic layer deposition process. The specific process parameters include using an organic gas containing Si and O, a temperature of 80 °C to 300 °C, a pressure of 5 mtorr to 20 torr, and a process number of 5 to 100 times. Since atomic layer deposition has good step coverage ability, it can well fill into the first opening 106 and the second opening 107, reducing the generation of gaps and holes and improving the formation quality of the passivation layer 113.

[0076] In other embodiments, the process for forming the passivation layer 113 can also be a physical vapor deposition process, a chemical vapor deposition process, and so on.

[0077] In this embodiment, the etching process for etching the passivation layer 113 is a dry etching process. The parameters include: the gases used include CF4 gas, CH3F gas, and O2. The flow rate of CF4 gas is 5 sccm to 100 sccm, the flow rate of CH3F gas is 8 sccm to 50 sccm, the flow rate of O2 is 10 sccm to 100 sccm, the chamber pressure is 10 mtorr to 2000 mtorr, the radio frequency power is 50 W to 300 W, the bias voltage is 30 V to 100 V, and the time is 4 seconds to 50 seconds.

[0078] In this embodiment, the material of the first conductive plug 114 is tungsten.

[0079] In other embodiments, the material of the first conductive plug 114 can also include one or more of cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and ruthenium.

[0080] In this embodiment, the material of the second conductive plug 115 is tungsten.

[0081] In other embodiments, the material of the second conductive plug 115 can also include one or more of cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and ruthenium.

[0082] Please refer to Figure 8 , and further include performing N-type heavy ion doping on the substrate 100 of the second surface 100b to form a drain doping region 116.

[0083] In this embodiment, in this embodiment, the doping ions in the drain doping region 116 include phosphorus ions or arsenic ions.

[0084] Please refer to Figure 9 , after forming the drain doping region 116, it further includes forming a conductive layer 117 on the surface of the second surface 100b and the surface of the passivation layer 113 respectively.

[0085] In this embodiment, the material of the conductive layer 117 is a metal material, specifically tungsten is used.

[0086] In other embodiments, the material of the conductive layer 117 may also be one or more of cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and ruthenium.

[0087] In this embodiment, the forming method of the conductive layer 117 is a chemical vapor deposition process.

[0088] In other embodiments, the forming method of the conductive layer 117 may also be a physical vapor deposition process, an atomic layer deposition process, and so on.

[0089] In this embodiment, the top surface of the first conductive plug 114 and the top surface of the second conductive plug 115 are respectively connected to the conductive layer 117.

[0090] Correspondingly, the present invention also provides a semiconductor structure. Please refer to Figure 9 , including a substrate 100, the substrate 100 includes opposite first surface 100a and second surface 100b; a plurality of accumulation regions 103 located in the substrate 100, and deep doping regions 102 located between adjacent accumulation regions 103, and the first surface 100a exposes the accumulation regions 103 and the deep doping regions 102; a plurality of gate layers 105 located on the first surface 100a, the deep doping regions 102 are exposed between adjacent gate layers 105, and the gate layer 105 has a first opening 106, and the first opening 106 exposes a part of the accumulation region 103; a connection layer 112 located on the sidewall and the bottom surface of the first opening 106.

[0091] In this embodiment, since the connection layer 112 replaces the traditional integral one located on the surface of the accumulation region 103 on the sidewall and the bottom of the first opening 106 on the surface of the accumulation region 103, the problem of easy surface peeling due to the too large area of the connection layer 112 is avoided; on the other hand, the deep doping layer is exposed between adjacent gate layers 105, and the gate layer 105 has a first opening 106 that exposes a part of the accumulation region 103. The introduction of the first opening 106 makes the entire pattern sparsity uniform, thereby contributing to improving the uniformity of lithography and etching.

[0092] In this embodiment, it further includes a body doping region 108 located in the deep doping region 102, a first source doping region 109 and a second source doping region 110 located in the body doping region 108, the second source doping region 110 is located between adjacent first source doping regions 109, the body doping region 108 is doped with P-type ions, the first source doping region 109 is doped with N-type ions, the second source doping region 110 is doped with P-type ions, the doping concentration of the first source doping region 109 is greater than the doping concentration of the body doping region 108, and the doping concentration of the second source doping region 110 is greater than the doping concentration of the body doping region 108.

[0093] In this embodiment, the doping ions of the first source doping region 109 include phosphorus ions or arsenic ions.

[0094] In this embodiment, the doping ions in the second source doping region 110 include boron ions, BF 2- ions or indium ions.

[0095] In this embodiment, the types of doping ions in the accumulation region 103 are opposite to those in the deep doping region 102, and the doping depth of the accumulation region 103 is less than that of the deep doping region 102.

[0096] In this embodiment, a gate dielectric layer 104 is further included between the first surface 100a and the gate layer 105, and the material of the gate dielectric layer 104 includes silicon oxide.

[0097] In this embodiment, the material of the gate layer 105 includes polysilicon.

[0098] In this embodiment, a drain doping region 116 located in the substrate 100 is further included, and the second surface 100b exposes the drain doping region 116.

[0099] In this embodiment, a sidewall layer 111 located between the connection layer 112 and the gate layer 105 is further included, and the material of the sidewall layer 111 includes silicon oxide.

[0100] In this embodiment, a passivation layer 113 located on the surface of the gate layer 105, inside the first opening 106 and inside the second opening 107 is further included; a first conductive plug 114 and a second conductive plug 115 are located inside the passivation layer 113, the first conductive plug 114 is located on the surface of the second source doping region 110, and the second conductive plug 115 is located on the surface of the connection layer 112.

[0101] In this embodiment, the material of the passivation layer 113 is silicon oxide.

[0102] In other embodiments, the material of the passivation layer 113 can also be silicon nitride, silicon carbide, etc.

[0103] In this embodiment, the process for forming the passivation layer 113 is a chemical vapor deposition process.

[0104] In other embodiments, the process for forming the passivation layer 113 can also be a physical vapor deposition process, an atomic layer deposition process, etc.

[0105] In this embodiment, the etching process for etching the passivation layer 113 is a dry etching process. The parameters include: the gases used include CF4 gas, CH3F gas, and O2. The flow rate of CF4 gas is 5 sccm to 100 sccm, the flow rate of CH3F gas is 8 sccm to 50 sccm, the flow rate of O2 is 10 sccm to 100 sccm, the chamber pressure is 10 mtorr to 2000 mtorr, the RF power is 50 W to 300 W, the bias voltage is 30 V to 100 V, and the time is 4 seconds to 50 seconds.

[0106] In this embodiment, the material of the first conductive plug 114 is tungsten.

[0107] In other embodiments, the material of the first conductive plug 114 may further include one or more of cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and ruthenium.

[0108] In this embodiment, the material of the second conductive plug 115 is tungsten.

[0109] In other embodiments, the material of the second conductive plug 115 may further include one or more of cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and ruthenium.

[0110] In this embodiment, it further includes forming a conductive layer 117 on the surface of the second surface 100b and the surface of the passivation layer 113 respectively.

[0111] In this embodiment, the material of the conductive layer 117 is a metal material, specifically tungsten is used.

[0112] In other embodiments, the material of the conductive layer 117 may also be one or more of cobalt, tungsten, aluminum, titanium, titanium nitride, tantalum, tantalum nitride, and ruthenium.

[0113] In this embodiment, the top surface of the first conductive plug 114 and the top surface of the second conductive plug 115 are respectively connected to the conductive layer 117.

[0114] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate comprising opposite first and second surfaces; A plurality of accumulation regions located within the substrate, and deep doping regions located between adjacent accumulation regions, and the first surface exposes the accumulation regions and the deep doping regions; A plurality of gate layers located on the first surface, the deep doping regions being exposed between adjacent gate layers, the gate layers having first openings therein, the first openings exposing a portion of the accumulation regions; A connection layer located on sidewalls and bottom surfaces of the first openings.

2. The semiconductor structure according to claim 1, wherein Further comprising: A body doping region located within the deep doping region, a first source doping region and a second source doping region located within the body doping region, the second source doping region being located between adjacent first source doping regions, the body doping region being doped with P-type ions, the first source doping region being doped with N-type ions, the second source doping region being doped with P-type ions, the doping concentration of the first source doping region being greater than the doping concentration of the body doping region, and the doping concentration of the second source doping region being greater than the doping concentration of the body doping region.

3. The semiconductor structure according to claim 2, wherein, Further comprising: A first conductive plug located on the surface of the second source doping region.

4. The semiconductor structure according to claim 1, wherein Further comprising: A second conductive plug located on the surface of the connection layer.

5. The semiconductor structure according to claim 1, wherein The doping ions within the accumulation regions are of a type opposite to the doping ions within the deep doping regions, and the doping depth of the accumulation regions is less than the doping depth of the deep doping regions.

6. The semiconductor structure according to claim 1, wherein Further comprising a gate dielectric layer located between the first surface and the gate layers, the material of the gate dielectric layer including silicon oxide.

7. The semiconductor structure according to claim 1, wherein The material of the gate layers includes polysilicon.

8. The semiconductor structure according to claim 1, wherein, Further comprising: A drain doping region located within the substrate, the second surface exposing the drain doping region.

9. The semiconductor structure according to claim 1, wherein Further comprising a sidewall layer located between the connection layer and the gate layers, the material of the sidewall layer including silicon oxide.

10. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate comprising opposite first and second surfaces; Forming a plurality of deep doping regions within the substrate; Forming accumulation regions within the substrate adjacent to the deep doping regions, the first surface exposing the accumulation regions and the deep doping regions; Forming a plurality of gate layers on the surface of the first surface, the deep doping regions being exposed between adjacent gate layers, the gate layers having first openings therein, the first openings exposing a portion of the accumulation regions; Forming a connection layer on sidewalls and bottom surfaces of the first openings.

11. The method for forming a semiconductor structure according to claim 10, wherein The method for forming the substrate includes providing a substrate, and forming an N-type epitaxial layer on the surface of the substrate, the N-type epitaxial layer being the first surface.

12. The method for forming a semiconductor structure according to claim 10, wherein, The method for forming the deep doping regions includes: Forming a first photoresist layer on the surface of the first surface, the first photoresist layer exposing a portion of the surface of the substrate; Etching the exposed substrate to form trenches therein; Performing epitaxial growth and in-situ doping within the trenches to form the deep doping regions.

13. The method for forming a semiconductor structure according to claim 12, wherein The method for forming the accumulation regions includes: Forming a second photoresist layer on the surface of the first surface, the second photoresist layer exposing the surface of the substrate between adjacent deep doping regions; Performing ion implantation on the exposed substrate, and performing high-temperature activation to form the accumulation regions.

14. The method for forming a semiconductor structure according to claim 13, wherein The method for forming the gate layer includes: forming a gate dielectric layer on the surface of the first surface; forming an initial gate layer on the surface of the gate dielectric layer; patterning the initial gate layer to form a gate layer, where the gate layer has a first opening exposing a part of the accumulation region and a second opening exposing the deep doping region.

15. The method for forming a semiconductor structure according to claim 14, wherein, After forming the gate layer, it further includes performing P-type ion implantation on the deep doping region to form a body doping region; performing N-type ion implantation on the body doping region to form a first source doping region; performing P-type ion implantation on the body doping region to form a second source doping region, where the second source doping region is located between adjacent first source doping regions, the doping concentration of the first source doping region is greater than that of the body doping region, and the doping concentration of the second source doping region is greater than that of the body doping region.

16. The method for forming a semiconductor structure according to claim 15, wherein, The method for forming the connection layer includes: forming an initial sidewall layer on the surface of the gate layer, on the sidewalls and bottom of the first opening, and on the sidewalls and bottom of the second opening; forming an initial connection layer on the surface of the initial sidewall layer; etching the initial connection layer and the initial sidewall layer to form a sidewall layer and the connection layer on the sidewalls of the first opening and the second opening.

17. The method for forming a semiconductor structure according to claim 16, wherein, The material of the sidewall layer includes silicon oxide, the material of the connection layer includes polysilicon, and the material of the gate layer includes polysilicon.

18. The method for forming a semiconductor structure according to claim 16, wherein, After forming the connection layer, it further includes: forming a passivation layer on the surface of the gate layer, inside the first opening, and inside the second opening; etching the passivation layer to form a first through hole exposing the surface of the second source doping region and a second through hole exposing the surface of the connection layer in the passivation layer; forming a first conductive plug in the first through hole; forming a second conductive plug in the second through hole.

19. The method for forming a semiconductor structure according to claim 18, wherein, It further includes performing N-type heavy ion doping on the substrate of the second surface to form a drain doping region.

20. The method for forming a semiconductor structure according to claim 19, wherein, After forming the drain doping region, it further includes forming a conductive layer on the surface of the second surface and on the surface of the passivation layer respectively.

Images