Power device and manufacturing method thereof

Abstract

The invention provides a power device and a manufacturing method thereof, and relates to the technical field of semiconductors. The power device comprises a plurality of parallel cellular structures. The cellular structure comprises an N + type substrate, a first N-type epitaxial layer, a current expansion layer, an N-type injection region and two P-type injection regions. A first N-type epitaxial layer and a current expansion layer are sequentially arranged at the top of the N + type substrate; the N-type injection region is arranged on one side, far away from the first N-type epitaxial layer, of the current expansion layer and comprises a first part and a second part, and the first part is arranged below the second part; the width of the first part is smaller than that of the second part in the direction parallel to the N + type substrate. The two P-type injection regions are arranged on the two sides of the N-type injection region respectively. According to the invention, the protruding parts of the two P-type injection regions are close to each other, so that the reverse voltage resistance and the forward surge resistance of the power device can be improved; and the N-type injection region adopts a self-aligned high-concentration injection process, so that the forward on-resistance of the device can be reduced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology. Specifically, this application relates to a power device and a manufacturing method thereof. Background Art

[0002] The breakdown field strength of silicon carbide can reach 3.5 (MV / cm), about 10 times that of silicon. Therefore, the thickness of the silicon carbide epitaxial layer required for high voltage withstand is reduced, and it has the characteristics of high voltage withstand, low on-resistance, and low conduction thermal resistance. The thermal conductivity of silicon carbide can reach 4.0 (W / cm·K), about 3 times that of silicon, and is suitable for high-temperature working conditions. The saturated electron drift rate of silicon carbide is about 2 times that of silicon, enabling high-frequency applications. Therefore, the power electronic system based on silicon carbide power devices is the development direction of the new generation of power electronic systems.

[0003] However, the current power devices still have technical problems such as a relatively large on-resistance, poor reverse voltage withstand or forward surge resistance. Summary of the Invention

[0004] In view of the disadvantages of the existing methods, this application proposes a power device and a manufacturing method thereof to solve the above technical problems.

[0005] In a first aspect, an embodiment of this application provides a power device, including a plurality of juxtaposed cell structures.

[0006] The cell structure includes:

[0007] An N+-type substrate;

[0008] A first N-type epitaxial layer disposed on one side of the N+-type substrate;

[0009] A current spreading layer disposed on the side of the first N-type epitaxial layer away from the N+-type substrate;

[0010] An N-type implantation region disposed above the top of the current spreading layer away from the first N-type epitaxial layer, including a first part and a second part, the first part being disposed below the second part; in a direction parallel to the N+-type substrate, the width of the first part is smaller than the width of the second part;

[0011] Two P-type implantation regions are respectively disposed on both sides of the N-type implantation region; the P-type implantation region includes a protruding portion, and the protruding portion is located in a space formed by the side surface of the first part of the N-type implantation region and the bottom surface of the second part.

[0012] In a second aspect, an embodiment of this application provides a manufacturing method of the power device according to the first aspect, including:

[0013] A first N-type epitaxial layer 2, a current spreading layer 3, and a second N-type epitaxial layer 4 are fabricated on an N+-type substrate 1; the first N-type epitaxial layer 2, the current spreading layer 3, and the second N-type epitaxial layer 4 are formed by one-time doped growth;

[0014] On one side of the second N-type epitaxial layer away from the current spreading layer, two oppositely arranged P-type implantation regions are fabricated, such that a protruding portion is provided at the bottom of the P-type implantation region, and the protruding portions of the two P-type implantation regions are close to each other;

[0015] An N-type implantation region is fabricated between the two P-type implantation regions, such that the N-type implantation region includes a first portion and a second portion, and the first portion is disposed below the second portion; in a direction parallel to the N+-type substrate, the width of the first portion is smaller than the width of the second portion, and the protruding portion is located at a space formed by the side surface of the first portion and the bottom surface of the second portion of the N-type implantation region.

[0016] The beneficial technical effects brought by the technical solution provided by the embodiment of the present application include:

[0017] The protruding portions of the two P-type implantation regions are close to each other, which can improve the reverse breakdown voltage and forward surge resistance of the power device. The N-type implantation region has a higher concentration, which can reduce the forward on-resistance of the power device. Moreover, the N-type implantation region adopts a self-aligned implantation process, which does not involve the problem of interlayer alignment, and is beneficial to improving the stability of the power device during processing and use.

[0018] The additional aspects and advantages of the present application will be partially given in the following description, and these will become obvious from the following description, or can be understood through the practice of the present application. Description of the Drawings

[0019] The above and / or additional aspects and advantages of the present application will become obvious and easy to understand from the following description of the embodiments in conjunction with the drawings, where:

[0020] Figure 1 is a schematic structural diagram of a power device provided by an embodiment of the present application;

[0021] Figure 2 is a schematic flow diagram of a manufacturing method of a power device provided by an embodiment of the present application;

[0022] Figures 3 - 12 is a schematic structural diagram of each step in a manufacturing method of a power device provided by an embodiment of the present application.

[0023] Description of the Reference Numerals:

[0024] 1. N+-type substrate; 2. First N-type epitaxial layer; 3. Current spreading layer; 4. Second N-type epitaxial layer; 5. P+-type implantation region; 6. P-type implantation region; 61. Protrusion; 7. N+-type implantation region; 8. N-type implantation region; 81. First part; 82. Second part; 9. Gate oxide layer; 10. Gate electrode; 11. Interlayer dielectric layer; 12. Source ohmic contact metal; 13. Source metal electrode; 14. Drain metal electrode;

[0025] 100. Cell structure; 101. Oxide mask; 102. First polysilicon mask layer; 103. Second polysilicon mask layer; 104. Photoresist mask layer. Detailed implementation manners

[0026] The embodiments of the present application will be described below with reference to the accompanying drawings in the present application. It should be understood that the implementation manners described below in conjunction with the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application, and do not constitute limitations on the technical solutions of the embodiments of the present application.

[0027] Those skilled in the art of the present technology can understand that, unless specifically stated, the ″the″ and ″this″ used here may also include the plural form. It should be further understood that the term ″including″ used in the specification of the present application means the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the implementation of other features, information, data, steps, operations, elements, components and / or their combinations, etc. supported by the art of the present technology. It should be understood that when we say an element is ″connected″ or ″coupled″ to another element, this element can be directly connected or coupled to the other element, or it can mean that this element and the other element establish a connection relationship through an intermediate element. In addition, the ″connection″ or ″coupling″ used here may include wireless connection or wireless coupling. The term ″and / or″ used here means at least one of the items defined by this term. For example, ″A and / or B″ can be implemented as ″A″, or implemented as ″B″, or implemented as ″A and B″.

[0028] To make the objectives, technical solutions and advantages of the present application clearer, the implementation manners of the present application will be further described in detail below with reference to the accompanying drawings.

[0029] The technical solutions of the present application and how the technical solutions of the present application solve the above technical problems will be described in detail below with specific embodiments. It should be noted that the following implementation manners can refer to, draw on or combine with each other. For the same terms, similar features and similar implementation steps in different implementation manners, they will not be described repeatedly.

[0030] The embodiments of the present application provide a power device, and the structural schematic diagram of the power device is as Figure 1 shown, including: a plurality of juxtaposed cell structures 100.

[0031] The cell structure 100 includes: an N+-type substrate 1, a first N-type epitaxial layer 2, a current spreading layer 3, an N-type implantation region 8, and two P-type implantation regions 6.

[0032] The first N-type epitaxial layer 2 is disposed on one side of the N+-type substrate 1.

[0033] The current spreading layer 3 is disposed on a side far from the first N-type epitaxial layer 2.

[0034] The N-type implantation region 8 is disposed above the top of the current spreading layer 3 far from the first N-type epitaxial layer 2. The N-type implantation region 8 includes a first portion 81 and a second portion 82. The first portion 81 is disposed below the second portion 82; in a direction parallel to the N+-type substrate 1, the width of the first portion 81 is smaller than the width of the second portion 82.

[0035] The two P-type implantation regions 6 are respectively disposed on both sides of the N-type implantation region 8; the P-type implantation region 6 includes a protruding portion 61, and the protruding portion 61 is located at a space formed by the side surface of the first portion 81 of the N-type implantation region 8 and the bottom surface of the second portion 82.

[0036] In this embodiment, the protruding portions 61 of the two P-type implantation regions 6 are close to each other, which can improve the reverse breakdown voltage and the forward surge resistance of the power device. The N-type implantation region 8 has a relatively high concentration, which can reduce the forward conduction resistance of the power device. Moreover, the N-type implantation region 8 adopts a self-aligned implantation process, which does not involve the problem of interlayer alignment, and is beneficial to improving the stability of the power device during processing and use.

[0037] In this embodiment, the current spreading layer 3 is a buried layer design.

[0038] Optionally, the doping concentration of the current spreading layer 3 is greater than the doping concentration of the first N-type epitaxial layer 2.

[0039] In this embodiment, when the current conducts forward, the forward conduction resistance at the current spreading layer 3 can be reduced.

[0040] Optionally, the doping concentration of the N-type implantation region 8 is not less than 5*10 16 / cm 3 ; in a direction perpendicular to the N+-type substrate 1, the doping concentration of the N-type implantation region 8 is uniformly distributed, or, from the top to the bottom of the N-type implantation region 8, the doping concentration of the N-type implantation region 8 gradually increases.

[0041] In this embodiment, the doping concentration of the N-type implantation region 8 is not less than 5*10 16 / cm 3, which means that the doping concentration of the N-type injection region 8 of this application is more than 10 times higher than that of the N-type injection region formed by general injection. The high-concentration N-type injection region 8 can reduce the forward conduction resistance of this region. From the top to the bottom of the N-type injection region 8, the doping concentration of the N-type injection region 8 gradually increases, that is, the doping concentration of the top region of the N-type injection region 8 is relatively low, and the doping concentration of the bottom region of the N-type injection region 8 is relatively high.

[0042] Optionally, the cell structure 100 further includes a P+-type injection region 5 and an N+-type injection region 7 disposed on the top of the P-type injection region 6. The tops of the P+-type injection region 5 and the N+-type injection region 7 are flush with the top of the P-type injection region 6.

[0043] The N+-type injection region 7 is located on the side of the P+-type injection region 5.

[0044] Optionally, the current spreading layer 3 has no misalignment deviation with the P+-type injection region 5, the P-type injection region 6, the N+-type injection region 7, and the N-type injection region 8.

[0045] Optionally, the cell structure 100 further includes: a gate oxide layer 9, a gate 10, an interlayer dielectric layer 11, a source ohmic contact metal 12, a source metal electrode 13, and a drain metal electrode 14.

[0046] The gate oxide layer 9 covers the upper surfaces of the N-type injection region 8, the two P-type injection regions 6, and a part of the N+-type injection region 7.

[0047] The gate 10 is located above the gate oxide layer 9.

[0048] The interlayer dielectric layer 11 covers the side and top surfaces of the gate 10.

[0049] Along the direction parallel to the N+-type substrate 1, the source ohmic contact metal 12 is disposed on the side of the interlayer dielectric layer 11 and extends to the top surfaces of the P+-type injection region 5 and a part of the N+-type injection region 7.

[0050] The source metal electrode 13 covers the interlayer dielectric layer 11 and the source ohmic contact metal 12;

[0051] The drain metal electrode 14 is located below the N+-type substrate 1.

[0052] In this embodiment, the material of the gate oxide layer 9 is an oxide. The material of the gate 10 is P-doped polysilicon or metal.

[0053] Based on the same inventive concept, the embodiment of this application provides a manufacturing method of a power device according to the above, and the flow schematic diagram of this method is as Figure 2 shown, and this method includes:

[0054] S1: Fabricate a first N-type epitaxial layer 2, a current spreading layer 3, and a second N-type epitaxial layer 4 on an N+-type substrate 1; the first N-type epitaxial layer 2, the current spreading layer 3, and the second N-type epitaxial layer 4 are formed by one-time doped growth. The obtained result is as shown in Figure 3 shown.

[0055] S2: Fabricate two oppositely disposed P-type injection regions 6 on a side of the second N-type epitaxial layer 4 away from the current spreading layer 3, such that a protruding portion 61 is provided at the bottom of the P-type injection region 6, and the protruding portions 61 of the two P-type injection regions 6 are close to each other.

[0056] S3: Fabricate an N-type injection region 8 between the two P-type injection regions 6, such that the N-type injection region 8 includes a first portion 81 and a second portion 82, and the first portion 81 is disposed below the second portion 82; along a direction parallel to the N+-type substrate 1, the width of the first portion 81 is smaller than the width of the second portion 82, and the protruding portion 61 is located at a space formed by a side surface of the first portion 81 of the N-type injection region 8 and a bottom surface of the second portion 82.

[0057] In this embodiment, a first N-type epitaxial layer 2, a current spreading layer 3, and a second N-type epitaxial layer 4 having a vertical concentration gradient distribution are grown on the N+-type substrate 1 at one time.

[0058] Since the current spreading layer 3 is formed by epitaxial doping growth, there is no misalignment deviation between the current spreading layer 3 and the P+-type injection region 5, the P-type injection region 6, the N+-type injection region 7, and the N-type injection region 8.

[0059] Specifically, the current spreading layer 3 is grown by doping with nitrogen or phosphorus, and the thickness of the current spreading layer 3 is 1 um - 2 um. The concentration of the current spreading layer 3 is greater than 5*10 16 / cm 3 . The thickness of the second N-type epitaxial layer 4 is 0.5 - 1.2 um, and the concentration of the second N-type epitaxial layer 4 is greater than 1*10 14 / cm 3 . The doping concentration of the current spreading layer 3 is greater than the doping concentrations of the first N-type epitaxial layer 2 and the second N-type epitaxial layer 4, and can reduce the conduction resistance here when the forward conduction current flows through in the subsequent process.

[0060] In this embodiment, the protruding portions 61 of the two P-type injection regions 6 are close to each other, which can improve the reverse breakdown voltage and the forward surge resistance of the power device.

[0061] Specifically, the thickness of the N+-type substrate 1 is not less than 100 um and not greater than 500 um. The concentration of the N+-type substrate 1 is 1*10 18 -1*10 20 / cm 3. The first N-type epitaxial layer 2 is grown by doping with nitrogen or phosphorus, and the thickness of the first N-type epitaxial layer 2 is 1 um - 50 um. The concentration of the first N-type epitaxial layer 2 is greater than 1*10 14 / cm 3 .

[0062] Optionally, after step S1 and before step S2, the manufacturing method further includes:

[0063] Manufacture two opposite P+-type implantation regions 5 on the top of the second N-type epitaxial layer 4, such that the top of the P+-type implantation region 5 is flush with the top of the second N-type epitaxial layer 4, and the obtained result is as shown in Figure 4 .

[0064] In this embodiment, the P+-type implantation region 5 is formed by mask deposition, photolithography, etching, implantation, and mask removal. The mask material generally uses an oxide layer. The mask thickness is determined by the type of implanted element, energy, and dose. Expose and develop the spin-coated photoresist and define the implantation region through etching. Inject aluminum at a high temperature of 200 - 500°C. The doping concentration of the P+-type implantation region is about 1*10 18 -1*10 19 / cm 3 , and the depth is 0.3 - 0.6 um.

[0065] Optionally, in step S2, it includes:

[0066] Manufacture a stacked oxide mask 101 and a first polysilicon mask layer 102 above the two opposite P+-type implantation regions 5, such that the width of the oxide mask 101 is less than that of the first polysilicon mask layer 102.

[0067] Under the masks of the oxide mask 101 and the first polysilicon mask layer 102, obliquely inject metal ions to form a protrusion 61 of the P-type implantation region 6.

[0068] Remove the first polysilicon mask layer 102, and under the mask of the oxide mask 101, inject metal ions to form the P-type implantation region 6, and the obtained result is as shown in Figure 5 .

[0069] In this embodiment, the protruding portion 61 of the P-type injection region 6 is formed by inclined injection. Specifically, an oxide layer and a first polysilicon mask layer 102 are sequentially fabricated above the two opposite P+-type injection regions 5. The oxide layer is wet etched back using a solution with a relatively high selectivity to obtain the oxide layer mask 101, such that the width of the oxide layer mask 101 is smaller than that of the first polysilicon mask layer 102. Aluminum is inclinedly injected at a high temperature of 200-500 °C to form the protruding portion 61 of the P-type injection region 6. The oxide layer mask 101 and the first polysilicon mask layer 102 are determined by the type of injected element, energy, and dose. The doping concentration of the P-type injection region 6 is approximately 6*10 16 -5*10 17 / cm 3 , and the depth is 0.5-1.2 um. The design of the bottom of the P-type injection region 6 protruding and extending (the protruding portion 61) makes the bottoms of the two side P-type injection regions 6 close to each other. Without significantly increasing the forward conduction resistance, the reverse breakdown voltage and the forward short-circuit resistance of the power device can be improved.

[0070] Optionally, after step S2 and before step S3, the manufacturing method further includes:

[0071] Fabricate a second polysilicon mask layer 103 above the P+-type injection region 5 and on both sides of the oxide layer mask 101.

[0072] Under the masks of the oxide layer mask 101 and the second polysilicon mask layer 103, fabricate an N+-type injection region 7 such that the N+-type injection region 7 is located on the side of the P+-type injection region 5, and the obtained result is as Figure 6 shown.

[0073] Remove the oxide layer mask 101.

[0074] In this embodiment, the second polysilicon mask layer 103 is formed by polysilicon mask deposition, photolithography, and etching. Under the masks of the oxide layer mask 101 and the second polysilicon mask layer 103, nitrogen or phosphorus is injected at a high temperature of 200-500 °C to form the N+-type injection region 7. The doping concentration of the N+-type injection region 7 is approximately 1*10 18 -1*10 19 / cm 3 , and the depth is 0.2 um - 0.4 um. The oxide layer mask 101 is removed by isotropic etching.

[0075] Optionally, in step S3, the manufacturing method includes: fabricating a photoresist mask layer 104 above the N+-type injection region 7. Under the masks of the second polysilicon mask layer 103 and the photoresist mask layer 104, fabricate an N-type injection region 8, and the obtained result is as Figure 7 shown.

[0076] In this embodiment, the isotropic etching is used to precisely open the area to be implanted in the N-type implantation region 8, that is, the oxide mask 101 above the N-type implantation region 8 is removed by the same-direction etching, and then the N-type implantation region 8 is formed by self-aligned implantation, achieving extremely precise directional implantation. Therefore, there is no alignment deviation between the N-type implantation region 8 and the P-type implantation region 6, which is beneficial to improving the stability of the power device during processing and use.

[0077] The concentration of the N-type implantation region 8 formed by self-aligned implantation is more than 10 times higher than that of the N-type implantation region formed by general implantation. Exemplarily, the concentration of the N-type implantation region 8 is greater than 5*10 16 / cm 3 . It should be noted that, along the vertical direction, the concentration of the N-type implantation region 8 is uniformly distributed, or, from top to bottom, the concentration of the N-type implantation region 8 gradually increases, that is, the bottom concentration of the N-type implantation region 8 is relatively high, which can reduce the forward conduction resistance of the bottom region.

[0078] Specifically, under the masks of the second polysilicon mask layer 103 and the photoresist mask layer 104, nitrogen or phosphorus is implanted to form the N-type implantation region 8. The doping concentration of the N-type implantation region 8 is greater than 5*10 16 / cm 3 , and the depth is 0.5 - 1.2 um.

[0079] Optionally, after step S3, the manufacturing method further includes:

[0080] Removing the second polysilicon mask layer 103 and the photoresist mask layer 104.

[0081] Manufacturing a gate oxide layer 9 on the upper surfaces of the N-type implantation region 8, the two P-type implantation regions 6, and a part of the N+-type implantation region 7, and the result is as Figure 8 shown.

[0082] Manufacturing a gate electrode 10 above the gate oxide layer 9, and the result is as Figure 9 shown.

[0083] Manufacturing an interlayer dielectric layer 11 on the side and top surfaces of the gate electrode 10, and the result is as Figure 10 shown.

[0084] Manufacturing a source ohmic contact metal 12 between adjacent interlayer dielectric layers 11, and the result is as Figure 11 shown.

[0085] Manufacturing a source metal electrode 13 on the upper surfaces of the source ohmic contact metal 12 and the interlayer dielectric layer 11, and the result is as Figure 12 shown.

[0086] Manufacturing a drain metal electrode 14 under the N+-type substrate 1.

[0087] In this embodiment, the gate oxide layer 9 is formed by high-temperature self-oxidation of silicon carbide, and its material is oxide. The oxidation temperature is generally between 1200 and 1400 °C. After the growth of the gate oxide layer 9 is completed, N-doping annealing is performed to reduce the interface state density, improve the carrier mobility, and thus reduce the channel resistance. The thickness of the gate oxide layer 9 is 10 nm - 100 nm.

[0088] The material of the gate 10 is P-doped polysilicon or metal. Among them, P-doped polysilicon is obtained by depositing P-doped polysilicon or implanting P after depositing undoped polysilicon. The thickness of the gate 10 is 0.2 um - 1.0 um.

[0089] The interlayer dielectric layer 11 is formed by initial dielectric layer deposition, photolithography, and etching. The material of the interlayer dielectric layer 11 includes one or more combinations of oxide or boron-phosphorus-containing oxide, and the thickness is 0.1 - 2 um.

[0090] The source ohmic contact metal 12 is formed by metal deposition, rapid thermal annealing (RTA), and metal lift-off on the dielectric layer. Its material is nickel silicide, and the thickness is 50 nm - 500 nm.

[0091] The source metal electrode 13 is formed by metal deposition, photolithography, and etching. Its material is titanium aluminum nitride titanium or titanium aluminum nitride titanium copper or titanium aluminum nitride titanium silicon copper. The thickness of titanium is 10 nm - 500 nm, the thickness of titanium nitride is 10 - 200 nm, and the thickness of aluminum or aluminum copper or aluminum silicon copper is 1 um - 8 um. The spin-coated photoresist is exposed and developed, and the coverage area of the source metal electrode is defined by etching.

[0092] The drain metal electrode 14 is formed by thinning the back of the silicon carbide wafer, evaporating the ohmic contact metal, annealing, and evaporating the drain metal. Annealing generally uses laser annealing or rapid thermal annealing (RTA) to form the ohmic contact area on the back of the chip and reduce the forward conduction resistance. The material of the drain metal electrode 14 is nickel silicide titanium nickel silver. Among them, the thickness of nickel silicide is 50 nm - 500 nm, the thickness of titanium is 0.1 nm - 2 um, the thickness of nickel is 0.1 um - 1.5 um, and the thickness of silver is 0.5 um - 3 um. By thinning the thickness of the N+-type substrate, the forward conduction resistance and heat generation can be reduced, and the thin chip thickness is also beneficial to reducing the volume of the subsequent packaged power device.

[0093] Those skilled in the art of the present application can understand that the various operations, methods, steps, measures, and solutions in the processes discussed in the present application can be alternated, changed, combined, or deleted. Further, other steps, measures, and solutions in the various operations, methods, and processes discussed in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and solutions in the related art that are the same as those disclosed in the various operations, methods, and processes in the present application can also be alternated, changed, rearranged, decomposed, combined, or deleted.

[0094] In the description of the present application, the directions or positional relationships indicated by the words "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are the exemplary directions or positional relationships based on the drawings, which are for the convenience of describing or simplifying the embodiments of the present application, rather than indicating or implying that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0095] The terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, unless otherwise specified, the meaning of "a plurality" is two or more.

[0096] In the description of the present application, it should be noted that unless otherwise clearly specified and defined, the terms "install", "connect", and "couple" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a direct connection or an indirect connection through an intermediate medium, and it may be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0097] In the description of this specification, specific features, structures, materials, or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0098] The above are only some embodiments of the present application. It should be noted that for those of ordinary skill in the art of the present technology, without departing from the technical concept of the solution of the present application, adopting other similar implementation means based on the technical idea of the present application also belongs to the protection scope of the embodiments of the present application.

Claims

1. A power device, characterized in that: The invention comprises a plurality of parallel cellular structures, wherein the cellular structure comprises: N+ type substrate; A first N-type epitaxial layer, disposed on one side of the N+ type substrate; A current spreading layer is arranged on a side of the first N-type epitaxial layer away from the N+ type substrate; An N-type injection region is arranged above the top of the current spreading layer away from the first N-type epitaxial layer, and comprises a first portion and a second portion, wherein the first portion is arranged below the second portion; along a direction parallel to the N+ type substrate, a width of the first portion is smaller than a width of the second portion; Two P-type injection regions are respectively arranged on both sides of the N-type injection region; the P-type injection region includes a protrusion, and the protrusion is located in the space formed by the side surface of the first part and the bottom surface of the second part of the N-type injection region.

2. The power device according to claim 1, characterized in that: The doping concentration of the current spreading layer is greater than the doping concentration of the first N-type epitaxial layer.

3. The power device according to claim 1, characterized in that: The doping concentration of the N-type implantation region is not less than 5*10 16 / cm 3 ; Along the direction perpendicular to the N+ type substrate, the doping concentration of the N-type injection region is uniformly distributed, or, from the top to the bottom of the N-type injection region, the doping concentration of the N-type injection region gradually increases.

4. The power device according to claim 1, characterized in that: The cell structure further includes a P+ type injection region and an N+ type injection region disposed on the top of the P- type injection region, and the tops of the P+ type injection region and the N+ type injection region are both flush with the top of the P- type injection region; The N+ type implantation region is located on the side of the P+ type implantation region.

5. The power device according to claim 1, characterized in that: The current spreading layer has no registration deviation with the P+ type injection area, the P- type injection area, the N+ type injection area, and the N- type injection area.

6. The power device according to claim 5, characterized in that: The cellular structure also includes: A gate oxide layer, the gate oxide layer covers the upper surfaces of the N-type implantation region, the two P-type implantation regions and a portion of the N+ type implantation region; A gate, located above the gate oxide layer; An interlayer dielectric layer, covering the side surfaces and top surface of the gate; A source ohmic contact metal is arranged on the side of the interlayer dielectric layer in a direction parallel to the N+ type substrate and extends to the top surface of the P+ type injection region and part of the N+ type injection region; A source metal electrode, covering the interlayer dielectric layer and the source ohmic contact metal; The drain metal electrode is located below the N+ type substrate.

7. A method for manufacturing a power device according to any one of claims 1 to 6, characterized in that: include: Manufacturing a first N-type epitaxial layer, a current spreading layer and a second N-type epitaxial layer on an N+ type substrate; wherein the first N-type epitaxial layer, the current spreading layer and the second N-type epitaxial layer are formed by one-time doping growth; Manufacturing two oppositely disposed P-type injection regions on a side of the second N-type epitaxial layer away from the current spreading layer, so that a protrusion is provided at the bottom of the P-type injection region, and the protrusions of the two P-type injection regions are close to each other; An N-type injection region is manufactured between the two P-type injection regions, so that the N-type injection region includes a first part and a second part, and the first part is arranged below the second part; along the direction parallel to the N+ type substrate 1, the width of the first part is smaller than the width of the second part, and the protrusion is located in the space formed by the side surface of the first part of the N-type injection region and the bottom surface of the second part.

8. The manufacturing method according to claim 7, characterized in that: After manufacturing a first N-type epitaxial layer, a current spreading layer and a second N-type epitaxial layer on an N+ type substrate, and before manufacturing two oppositely disposed P-type injection regions on a side of the second N-type epitaxial layer away from the current spreading layer, the method further includes: Fabricating two opposite P+ type implantation regions on the top of the second N-type epitaxial layer, so that the top of the P+ type implantation region is flush with the top of the second N-type epitaxial layer; And, manufacturing two oppositely disposed P-type injection regions on a side of the second N-type epitaxial layer away from the current spreading layer, including: Manufacturing a stacked oxide layer mask and a first polysilicon mask layer above two opposite P+ type implantation regions, so that the oxide layer mask has a width smaller than that of the first polysilicon mask layer; Under the mask of the oxide layer mask and the first polysilicon mask layer, metal ions are obliquely implanted to form a protruding portion of the P-type implantation region; The first polysilicon mask layer is removed, and the metal ions are implanted under the mask of the oxide layer mask to form the P-type implantation region.

9. The manufacturing method according to claim 8, characterized in that: After manufacturing two oppositely disposed P-type implantation regions on a side of the second N-type epitaxial layer away from the current spreading layer and before manufacturing an N-type implantation region between the two P-type implantation regions, the method further includes: Manufacturing a second polysilicon mask layer above the P+ type implantation region and on both sides of the oxide layer mask; Under the oxide layer mask and the second polysilicon mask layer, an N+ type implantation region is manufactured so that the N+ type implantation region is located on the side of the P+ type implantation region; removing the oxide layer mask; And, manufacturing an N-type implantation region between the two P-type implantation regions, comprising: A photoresist mask layer is manufactured above the N+ type implantation region, and the N- type implantation region is manufactured under the mask of the second polysilicon mask layer and the photoresist mask layer.

10. The manufacturing method according to claim 9, characterized in that: After manufacturing an N-type implantation region between the two P-type implantation regions, the method further comprises: removing the second polysilicon mask layer and the photoresist mask layer; Manufacturing a gate oxide layer on the upper surfaces of the N-type implantation region, the two P-type implantation regions and a portion of the N+ type implantation region; Manufacturing a gate on the gate oxide layer; Manufacturing an interlayer dielectric layer on the side and top surface of the gate; Manufacturing source ohmic contact metal between adjacent interlayer dielectric layers; Manufacturing a source metal electrode on the upper surface of the source ohmic contact metal and the interlayer dielectric layer; A drain metal electrode is fabricated under the N+ type substrate.

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