Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a forming method thereof, which are at least beneficial to improving the isolation performance of a top gate structure. The semiconductor structure comprises a semiconductor substrate and a top gate structure located on the semiconductor substrate; the isolation structure is arranged on the side wall of the top gate structure in a surrounding manner; the isolation structure comprises a first protection layer, a first isolation layer, a second protection layer and a second isolation layer, and the first protection layer is arranged around the side wall of the top gate structure; the first isolation layer is arranged around the side wall of one side, far away from the top gate structure, of the first protection layer; the second protection layer is arranged around the side wall of one side, far away from the first protection layer, of the first isolation layer and covers the top of the top gate structure; the second isolation layer is arranged on the side wall of the side, away from the first isolation layer, of the second protection layer in a surrounding mode, and the height of the second isolation layer is lower than that of the top gate structure in the direction perpendicular to the top surface of the semiconductor substrate; and the third protection layer covers the top of the second protection layer and the top of the second isolation layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] Semiconductor components are indispensable in many modern applications. Among them, transistors, as important semiconductor components, are widely used in various fields.

[0003] With the development of electronic technology, the size of semiconductor components is getting smaller and smaller. However, when scaling down semiconductor devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs) through various technology nodes, the device density and performance are challenged by device layout and required isolation.

[0004] For metal-oxide-semiconductor field-effect transistors formed based on a top-gate structure in a memory, when the size of semiconductor components is further reduced, the isolation performance of its top-gate structure needs to be improved. Summary of the Invention

[0005] The present disclosure provides a semiconductor structure and a method for forming the same, which are at least beneficial to improving the isolation performance of the top-gate structure.

[0006] In a first aspect of an embodiment of the present disclosure, a semiconductor structure is provided, including: a semiconductor substrate, and a top-gate structure located on the semiconductor substrate; an isolation structure disposed around a sidewall of the top-gate structure; the isolation structure includes: a first protective layer, a first isolation layer, a second protective layer, and a second isolation layer, wherein the first protective layer is disposed around the sidewall of the top-gate structure; the first isolation layer is disposed around a sidewall of the first protective layer away from the top-gate structure; the second protective layer is disposed around a sidewall of the first isolation layer away from the first protective layer and covers a top of the top-gate structure; the second isolation layer is disposed around a sidewall of the second protective layer away from the first isolation layer, and in a direction perpendicular to a top surface of the semiconductor substrate, a height of the second isolation layer is lower than a height of the top-gate structure; a third protective layer covering a top of the second protective layer and a top of the second isolation layer.

[0007] In some embodiments, in a direction perpendicular to a sidewall of the top-gate structure, a thickness of the first protective layer is 1 nm to 100 nm, a thickness of the first isolation layer is 1 nm to 100 nm, and a thickness of the second protective layer is 1 nm to 100 nm.

[0008] In some embodiments, in a direction perpendicular to a sidewall of the top-gate structure, a thickness of the second isolation layer is used to adjust a size of the semiconductor structure.

[0009] In some embodiments, the thickness of the second isolation layer is from 0.1 nm to 100 nm.

[0010] In some embodiments, the material of the first isolation layer is the same as that of the second isolation layer.

[0011] In some embodiments, the materials of the first protection layer, the second protection layer, and the third protection layer are the same.

[0012] In some embodiments, the top gate structure includes: a channel layer located on top of the semiconductor substrate; a gate isolation layer located on top of the side of the channel layer away from the semiconductor substrate; a gate conductive layer located on top of the side of the gate isolation layer away from the channel layer; and a gate capping layer located on top of the side of the gate conductive layer away from the gate conductive layer.

[0013] A second aspect of the embodiments of the present disclosure further provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, and forming a top gate structure on the semiconductor substrate; forming a first protection layer and a first isolation layer, the first protection layer being disposed around the sidewalls of the top gate structure, and the first isolation layer being disposed around the sidewalls of the side of the first protection layer away from the top gate structure; depositing a second protection layer, the second protection layer being located on the sidewalls of the side of the first isolation layer away from the first protection layer and covering the top of the top gate structure; forming a second isolation layer, the second isolation layer being located on the sidewalls of the side of the second protection layer away from the first isolation layer, and in a direction perpendicular to the top surface of the semiconductor substrate, the height of the second isolation layer is lower than the height of the top gate structure; and forming a third protection layer, the third protection layer covering the top of the second protection layer and the top of the second isolation layer.

[0014] In some embodiments, the method for forming the first protection layer and the first isolation layer includes: depositing a first protection film on the surfaces of the semiconductor substrate and the top gate structure; depositing a first isolation film on the surface of the first protection film; etching away the first protection film and the first isolation film located on the top of the top gate structure and the top of the semiconductor substrate, and the remaining first protection film located on the sidewalls of the top gate structure forms the first protection layer, and the remaining first isolation film located on the sidewalls of the first protection layer forms the first isolation layer.

[0015] In some embodiments, the method of forming the second isolation layer includes: depositing a second isolation film on the surface of the second protection layer, and spin-coating a carbon coating on the surface of the second isolation film; etching the carbon coating to expose the top surface of the second isolation film, and etching the second isolation film until the height of the second isolation film is lower than the height of the top gate structure in a direction perpendicular to the top surface of the semiconductor substrate, and the remaining second isolation film constitutes the second isolation layer.

[0016] In some embodiments, the method of forming the third protection layer includes: forming a third protection film, the third protection film being located on top of the second isolation layer and on top of the second protection layer; patterning the third protection film to expose the carbon coating located on the sidewall of the second isolation layer; removing the carbon coating; etching the top of the semiconductor substrate and the top of the top gate structure based on an etching process to expose the semiconductor substrate, and the remaining third protection film constitutes the third protection layer.

[0017] In some embodiments, the etching selectivity of the etching process for the second isolation layer and the third protection layer is 3:1 to 10:1.

[0018] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: (1) The sidewall of the top gate structure has a four-layer isolation structure composed of a first protection layer, a first isolation layer, a second protection layer, and a second isolation layer, which has better insulation performance and can effectively prevent ion diffusion in the top gate structure.

[0019] (2) The second protection layer and the third protection layer also form a "cap-like" structure on top of the top gate structure to prevent the subsequent process after forming the semiconductor structure from grinding back the top gate structure, and prevent the etching solution of the subsequent process from remaining in the isolation structure and the gap between the top gate structure and the isolation structure, thereby causing the semiconductor structure to be damaged. Description of the Drawings

[0020] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, the drawings in the figures do not constitute a scale limitation; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the traditional technology, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1Schematic cross-sectional structure diagram of a semiconductor substrate and a top gate structure provided by an embodiment of the present disclosure; Figure 2 Schematic cross-sectional structure diagram of a top gate structure provided by an embodiment of the present disclosure; Figure 3 Schematic cross-sectional structure diagram of a first protective film and a first isolation film provided by an embodiment of the present disclosure; Figure 4 Schematic cross-sectional structure diagram of a first protective layer and a first isolation layer provided by an embodiment of the present disclosure; Figure 5 Schematic cross-sectional structure diagram of a second protective layer provided by an embodiment of the present disclosure; Figure 6 Schematic cross-sectional structure diagram of a second isolation film provided by an embodiment of the present disclosure; Figure 7 Schematic cross-sectional structure diagram of a carbon coating provided by an embodiment of the present disclosure; Figure 8 Schematic cross-sectional structure diagram of a second isolation layer provided by an embodiment of the present disclosure; Figure 9 Schematic cross-sectional structure diagram of a third protective film provided by an embodiment of the present disclosure; Figure 10 Schematic cross-sectional structure diagram of the third protective film after removing the carbon coating provided by an embodiment of the present disclosure; Figure 11 Schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure. Detailed implementation manners

[0022] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity, specific order or primary-secondary relationship of the indicated technical features. In the description of the embodiments of the present disclosure, "a plurality" means more than two, unless otherwise specifically defined.

[0023] Referring to "embodiments" herein means that specific features, structures or characteristics described in connection with the embodiments can be included in at least one embodiment of the present disclosure. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0024] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: the existence of A, the simultaneous existence of A and B, and the existence of B. Additionally, the character " / " in this document generally indicates an "or" relationship between the associated objects before and after.

[0025] In the description of the embodiments of the present disclosure, the term "plurality" refers to two or more (including two). Similarly, "multiple groups" refers to two or more groups (including two groups), and "multiple pieces" refers to two or more pieces (including two pieces).

[0026] In the description of the embodiments of the present disclosure, the orientation or positional relationship indicated by technical terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the embodiments of the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation on the embodiments of the present disclosure.

[0027] In the description of the embodiments of the present disclosure, unless otherwise clearly specified and limited, technical terms such as "installation", "connection", "connection", "fixation", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or integrated; it can also be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0028] In the corresponding drawings of the embodiments of the present disclosure, for better understanding and convenience of description, the thickness and area of the layer are enlarged. When describing a component (such as a layer, film, region, or substrate) on another component or on the surface of another component, the component can be "directly" located on the surface of the other component, or there can be a third component between the two components. On the contrary, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. Additionally, when describing a component "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor on a partial edge of the entire surface.

[0029] In the description of the embodiments of the present disclosure, when a certain component "includes" another component, unless otherwise specified, other components are not excluded, and other components may further be included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it may be "directly on" another component (i.e., located on the surface of another component with no other components therebetween), or there may be other components therebetween. In addition, when a layer, film, region, plate, etc. component is "directly located on" another component, or when a layer, film, region, plate, etc. component is located on the surface of another component, it means that no other components are located therebetween.

[0030] The terms used in the description of the various embodiments herein are only for describing specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is also intended to include the plural form, unless the context clearly indicates otherwise. Among them, the component includes components such as a layer, film, region, or plate.

[0031] As can be seen from the background art, for a metal oxide semiconductor field effect transistor formed based on a top gate structure in a memory, when the size of semiconductor components is further reduced, the isolation performance of its top gate structure needs to be improved.

[0032] The embodiments of the present disclosure provide a semiconductor structure, a semiconductor substrate, and a top gate structure located on the semiconductor substrate; an isolation structure disposed around the sidewalls of the top gate structure; the isolation structure includes: a first protective layer, a first isolation layer, a second protective layer, and a second isolation layer, wherein the first protective layer is disposed around the sidewalls of the top gate structure; the first isolation layer is disposed around the sidewall of the first protective layer away from the top gate structure; the second protective layer is disposed around the sidewall of the first isolation layer away from the first protective layer and covers the top of the top gate structure; the second isolation layer is disposed around the sidewall of the second protective layer away from the first isolation layer, and in the direction perpendicular to the top surface of the semiconductor substrate, the height of the second isolation layer is lower than the height of the top gate structure; a third protective layer covering the top of the second protective layer and the top of the second isolation layer.

[0033] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are provided to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0034] Reference Figure 2 and Figure 11 , Figure 2 is a schematic cross-sectional structure diagram of a top gate structure provided for some embodiments. Figure 11Schematic cross-sectional structure diagram of a semiconductor structure provided for some embodiments. In some embodiments, the semiconductor structure includes a semiconductor substrate 101 and a top gate structure 102 located on the semiconductor substrate 101.

[0035] For the semiconductor substrate 101, in some embodiments, the semiconductor substrate 101 includes a silicon substrate, a silicon-germanium substrate, a gallium arsenide substrate, a silicon carbide substrate, a gallium nitride substrate, etc.

[0036] The semiconductor structure further includes an isolation structure, and the isolation structure is disposed around the sidewalls of the top gate structure 102. Among them, the isolation structure includes a first protective layer 301, a first isolation layer 302, a second protective layer 303, and a second isolation layer 304.

[0037] The first protective layer 301 is disposed around the sidewalls of the top gate structure 102.

[0038] The first isolation layer 302 is disposed around the sidewall of the first protective layer 301 away from the top gate structure 102.

[0039] For the first protective layer 301, the material of the first protective layer 301 is a semiconductor material with insulating properties. For example, silicon oxide, silicon nitride, silicon oxynitride, etc. In some embodiments, the material of the first protective layer 301 is silicon oxide.

[0040] For the first isolation layer 302, the material of the first isolation layer 302 is also a semiconductor material with insulating properties. For example, silicon oxide, silicon nitride, silicon oxynitride, etc. However, the material selection of the first isolation layer 302 needs to be different from that of the first protective layer 301 to form insulating layers of different materials. In some embodiments, the material of the first isolation layer 302 is NIT [the main components are silicon nitride (SiN) and aluminum nitride (AlN)].

[0041] During semiconductor manufacturing, the thermal stability of the NIT material provides guarantee for the high-temperature working environment of the device. The NIT material can improve the interface characteristics of the semiconductor and reduce the influence of interface defects on the performance. In advanced semiconductor processes, the NIT material helps to reduce the leakage current and enhance the reliability of the circuit. The NIT material used in semiconductor manufacturing has good chemical stability and resists various chemical erosions. The NIT material can optimize the crystal structure of the semiconductor and improve the crystallization quality of the material. It can enhance the optical performance of the semiconductor and create favorable conditions for the manufacture of optoelectronic devices. During semiconductor manufacturing, the NIT material helps to improve the integration degree of the device. The NIT material can reduce the resistance of the semiconductor and reduce energy loss.

[0042] It should be noted that in Figure 11In the corresponding example, at the contact interface between the semiconductor substrate 101 and the top gate structure 102, the first protective layer 301 is in an "L" shape at the contact interface. The first isolation layer 302 is located on the first protective layer 301 and is formed based on the corresponding formation process (after sequentially depositing the film layers corresponding to the first protective layer 301 and the first isolation layer 302, the first protective layer 301 and the first isolation layer 302 are etched), which does not constitute a limitation to this embodiment. In other embodiments, at the contact interface between the semiconductor substrate 101 and the top gate structure 102, the first isolation layer 302 is parallel to the first protective layer 301, and both are in an "I" shape at the contact interface. At this time, the corresponding formation process is: after depositing and forming the film layer corresponding to the first protective layer 301, the first protective layer 301 is etched, and then after depositing and forming the film layer corresponding to the first isolation layer 302, the first isolation layer 302 is etched.

[0043] The second protective layer 303 is disposed around the side wall of the first isolation layer 302 away from the first protective layer 301 and covers the top of the top gate structure 102.

[0044] For the second protective layer 303, the material of the first protective layer 301 is a semiconductor material with insulating properties, such as silicon oxide, silicon nitride, silicon oxynitride, etc. However, the material selection of the second protective layer 303 needs to be different from the material selection of the first isolation layer 302 to form insulating layers of different materials. In some embodiments, the material of the first protective layer 301 is silicon oxide.

[0045] It should be noted that in Figure 11 In the corresponding example, at the contact interface between the semiconductor substrate 101 and the top gate structure 102, the second protective layer 303 is in an "L" shape at the contact interface, that is, after depositing and forming the second protective layer 303, the next process is directly carried out. At this time, the second protective layer 303 is still located on the semiconductor substrate 101. In other embodiments, at the contact interface between the semiconductor substrate 101 and the top gate structure 102, the second protective layer 303 is in an "I" shape at the contact interface, that is, after depositing and forming the second protective layer 303, the second protective layer 303 in the area located on the top surface of the semiconductor substrate 101 is etched.

[0046] The second isolation layer 304 is disposed around the side wall of the second protective layer 303 away from the first isolation layer 302. In the direction perpendicular to the top surface of the semiconductor substrate 101, the height of the second isolation layer 304 is lower than the height of the top gate structure 102.

[0047] For the second isolation layer 304, the material of the second isolation layer 304 is also a semiconductor material with insulating properties, such as silicon oxide, silicon nitride, silicon oxynitride, etc. However, the material selection of the second isolation layer 304 needs to be different from the material selection of the second protective layer 303 to form insulating layers of different materials. In some embodiments, the material of the second isolation layer 304 is NIT.

[0048] It should be noted that, in the Figure 11 corresponding example, since the second protective layer 303 is "L"-shaped at the contact interface, at this time, the second isolation layer 304 is located on the second protective layer 303 at the contact interface; in other embodiments, if the second protective layer 303 is "I"-shaped at the contact interface, at this time, the second isolation layer 304 is located on the semiconductor substrate 101 at the contact interface.

[0049] The semiconductor structure further includes a third protective layer 306, and the third protective layer 306 covers the top of the second protective layer 303 and the top of the second isolation layer 304.

[0050] For the above semiconductor structure, the sidewall of the top gate structure 102 has a four-layer isolation structure composed of the first protective layer 301, the first isolation layer 302, the second protective layer 303, and the second isolation layer 304, which has better insulation performance and can effectively prevent ion diffusion in the top gate structure 102. In addition, the second protective layer 303 and the third protective layer 306 are also located on the top of the top gate structure 102 to form a "cap" structure, so as to prevent the subsequent process after forming the semiconductor structure from grinding back the top gate structure, and prevent the etching solution of the subsequent process from remaining in the isolation structure and the gap between the top gate structure 102 and the isolation structure, thereby causing the semiconductor structure to be damaged.

[0051] In some embodiments, the material of the first isolation layer 302 is the same as the material of the second isolation layer 304.

[0052] In some embodiments, the material of the first protective layer 301, the material of the second protective layer 303, and the material of the third protective layer 306 are the same.

[0053] In some embodiments, in the direction perpendicular to the sidewall of the top gate structure 102, the thickness of the first protective layer 301 is 1 nm to 100 nm, the thickness of the first isolation layer 302 is 1 nm to 100 nm, and the thickness of the second protective layer 303 is 1 nm to 100 nm. For example, the thickness of the first protective layer 301, the thickness of the first isolation layer 302, and the thickness of the first protective layer 301 can be 3 nm, 5 nm, 7 nm, and 9 nm respectively.

[0054] In some embodiments, the thickness of the first protective layer 301, the thickness of the first isolation layer 302, and the thickness of the first protective layer 301 can be the same, can be partially the same, or can be completely different. For example, the thicknesses of the above three are the same, or the thicknesses of two of them are the same, and the other is different from the thicknesses of these two, or the thicknesses of the three are all different.

[0055] It should be noted that those skilled in the art can expand the isolation structure to more layers based on the 4-layer isolation structure of this embodiment, but it is necessary to ensure that the third protective layer can cover the isolation structure.

[0056] In addition, due to the increase in the number of layers of the isolation structure, in the direction perpendicular to the sidewall of the top gate structure 102, in order to ensure the overall thickness of the isolation structure, the more layers the isolation structure has, the thickness of each protective layer / isolation layer in the isolation structure needs to be correspondingly thinned to adapt to the overall size of the semiconductor structure.

[0057] In some embodiments, in the direction perpendicular to the sidewall of the top gate structure 102, the thickness of the second isolation layer 304 is used to adjust the size of the semiconductor structure.

[0058] For example, if the semiconductor structures to be formed in the memory include three sizes a, b, and c, for the semiconductor structure provided by the embodiments of the present disclosure, whether it is a semiconductor structure of sizes a, b, or c, the corresponding top gate structure 102, as well as the first protective layer 301, the first isolation layer 302, and the second protective layer 303 can be formed based on the same process, and then based on the sizes of a, b, and c, the size of the second isolation layer 304 is adaptively adjusted to form semiconductor structures of sizes a, b, and c, and to ensure the similarity of the isolation effect on the top gate structure 102 in semiconductor structures of different sizes.

[0059] In some embodiments, the thickness of the second isolation layer 304 is 0.1 nm to 100 nm. Based on the foregoing, it can be known that in actual application, the thickness of the second isolation layer 304 is correspondingly adjusted based on the required size of the semiconductor structure to adaptively form a semiconductor structure of the required size, so as to improve the adaptability of the semiconductor structure provided by the embodiments of the present disclosure.

[0060] For the top gate structure 102, in some embodiments, the top gate structure 102 includes a channel layer 201, a gate isolation layer 202, a gate conductive layer 203, and a gate capping layer 204.

[0061] Among them, the channel layer 201 is located on the top of the semiconductor substrate 101, the gate isolation layer 202 is located on the top of the side of the channel layer 201 away from the semiconductor substrate 101, the gate conductive layer 203 is located on the top of the side of the gate isolation layer 202 away from the channel layer 201, and the gate capping layer 204 is located on the top of the side of the gate conductive layer 203 away from the gate isolation layer 202.

[0062] For the channel layer 201, the channel layer 201 is used to form a conductive channel between the source region and the drain region in the transistor corresponding to the top gate structure 102. In some embodiments, the material of the channel layer 201 includes silicon, germanium, silicon germanium, etc.

[0063] For the gate isolation layer 202, the gate isolation layer 202 serves as the gate oxide structure of the top gate structure 102. In some embodiments, the material of the gate isolation layer 202 includes silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicide, high-K material, ferroelectric material, antiferroelectric material, or a combination thereof. For example, the gate dielectric layer may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, or HfSiON, etc.

[0064] For the gate conductive layer 203, the gate conductive layer 203 is used to receive the corresponding gate control signal to form a conductive channel in the channel layer 201 based on the gate control signal, thereby connecting the source region and the drain region in the transistor corresponding to the top gate structure 102.

[0065] To optimize the conductive performance of the gate conductive layer 203, in some embodiments, the gate conductive layer 203 includes a high dielectric constant (high-K) layer 210, a work function layer 220, a non-metal conductive layer 230, an adhesion layer 240, and a metal conductive layer 250.

[0066] The high dielectric constant (high-K) layer 210 is used to increase the dielectric constant of the gate conductive layer 203. In some embodiments, the high dielectric constant (high-K) layer 210 includes a HfSiON (Hafnium Silicon Oxynitride) high-k gate dielectric layer. Among them, the performance of HfSiON can be regulated by adjusting the proportions of elements such as Hf, Si, O, and N therein. Different compositions may affect properties such as the dielectric constant and bandgap of the high dielectric constant (high-K) layer 210.

[0067] The work function layer 220 is used to increase the work function of the gate conductive layer 203. In some embodiments, the material of the work function layer 220 includes titanium nitride (TiN). Among them, the work function layer 220 formed based on titanium nitride is used to increase the work function of the gate conductive layer 203. In addition, based on the adhesion and conductivity of the titanium nitride layer, the formed work function layer 220 can form an interface with low contact resistance and strong adhesion.

[0068] In some embodiments, the material of the non-metal conductive layer 230 includes silicon, germanium, silicon germanium, etc.

[0069] The adhesion layer 240 is disposed between the non-metal conductive layer 230 and the metal conductive layer 250 and is used for adhesion and conductive contact between the non-metal conductive layer 230 and the metal conductive layer 250. In some embodiments, the material of the adhesion layer 240 includes titanium nitride (TiN).

[0070] In some embodiments, the material of the metal conductive layer 250 includes metal elemental materials such as tungsten, copper, aluminum, silver, or alloy materials formed by combining them.

[0071] For the gate capping layer 204, the gate capping layer 204 is used for the top insulation of the top gate structure 102 and the structural protection of the top gate structure 102. In some embodiments, the material of the gate capping layer 204 is the same as the materials of the first isolation layer 302 and the second isolation layer 304.

[0072] Based on the foregoing, in the direction perpendicular to the top surface of the semiconductor substrate 101, the height of the second isolation layer 304 is lower than the height of the top gate structure 102. In this embodiment, the height of the second isolation layer 304 is lower than the top surface height of the gate capping layer 304 and higher than the bottom surface height of the gate capping layer 204. By maintaining the height of the second isolation layer 304 higher than the bottom surface height of the gate capping layer 204, the isolation performance of the second isolation layer 304 for the top gate structure 102 is ensured.

[0073] For the semiconductor structure provided by the embodiments of the present disclosure, the sidewall of the top gate structure 102 has a four-layer isolation structure composed of a first protection layer 301, a first isolation layer 302, a second protection layer 303, and a second isolation layer 304, which has better insulation performance and can effectively prevent ion diffusion in the top gate structure 102. In addition, the second protection layer 303 and the third protection layer 306 also form a "cap-shaped" structure on the top of the top gate structure 102 to prevent the subsequent process after forming the semiconductor structure from grinding back the top gate structure, and prevent the etching solution of the subsequent process from remaining in the isolation structure and the gap between the top gate structure 102 and the isolation structure, thereby causing damage to the semiconductor structure.

[0074] It should be noted that, without conflict, the features disclosed in the semiconductor structures provided by the above embodiments can be randomly combined to obtain new embodiments of semiconductor structures.

[0075] Another embodiment of the present disclosure provides a method for forming a semiconductor structure, including: providing a semiconductor substrate and forming a top gate structure on the semiconductor substrate; forming a first protection layer and a first isolation layer, the first protection layer is disposed around the sidewall of the top gate structure, and the first isolation layer is disposed around the sidewall of the first protection layer away from the top gate structure; depositing and forming a second protection layer, the second protection layer is located on the sidewall of the first isolation layer away from the first protection layer and covers the top of the top gate structure; forming a second isolation layer, the second isolation layer is located on the sidewall of the second protection layer away from the first isolation layer, and in the direction perpendicular to the top surface of the semiconductor substrate, the height of the second isolation layer is lower than the height of the top gate structure; forming a third protection layer, the third protection layer covers the top of the second protection layer and the top of the second isolation layer.

[0076] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those in the above embodiments, reference may be made to the corresponding descriptions in the foregoing embodiments, and details will not be repeated hereinafter.

[0077] In some embodiments, a method for forming a semiconductor structure includes the following steps: Step S1: Provide a semiconductor substrate and form a top gate structure on the semiconductor substrate.

[0078] Reference Figure 1 and Figure 2 , Figure 1 FIGS. and are schematic cross-sectional views of a semiconductor substrate and a top gate structure provided for some embodiments. Figure 2 FIG. is a schematic cross-sectional view of a top gate structure provided for some embodiments.

[0079] For the top gate structure 102, in some embodiments, the method for forming the top gate structure 102 includes: depositing and forming a channel layer 201 on the top surface of the semiconductor substrate 101, depositing and forming a gate isolation layer 202 on the top surface of the channel layer 201, depositing and forming a gate conductive layer 203 on the top surface of the gate isolation layer 202, and depositing and forming a gate capping layer 204 on the top surface of the gate conductive layer 203.

[0080] In some embodiments, the method for forming the gate conductive layer 203 includes: sequentially depositing and forming a high-k dielectric layer 210, a work function layer 220, a non-metal conductive layer 230, an adhesion layer 240, and a metal conductive layer 250 on the top surface of the gate isolation layer 202.

[0081] It should be noted that the "deposition" mentioned in the embodiments of the present disclosure refers to forming a corresponding material layer on a substrate by means of a deposition process, where the deposition process may be Physical Vapor Deposition (PVD), spin coating, Chemical Vapor Deposition (CVD), Epitaxy (EPI), or the like.

[0082] Step S2: Form a first protective layer and a first isolation layer. The first protective layer is disposed around the sidewalls of the top gate structure, and the first isolation layer is disposed around the sidewall of the first protective layer away from the top gate structure.

[0083] Reference Figure 3 and Figure 4 , Figure 3 FIGS. and are schematic cross-sectional views of a first protective film and a first isolation film provided for some embodiments. Figure 4Schematic cross-sectional structure diagrams of the first protective layer and the first isolation layer provided for some embodiments. In some embodiments, the method of forming the first protective layer 301 and the first isolation layer 302 includes: depositing a first protective film 310 on the surfaces of the semiconductor substrate 101 and the top gate structure 102; depositing a first isolation film 320 on the surface of the first protective film 310, and etching away the first protective film 310 and the first isolation film 320 located on the top of the top gate structure 102 and the top of the semiconductor substrate 101. The remaining first protective film 310 located on the sidewalls of the top gate structure 102 forms the first protective layer 301, and the remaining first isolation film 320 located on the sidewalls of the first protective layer 301 forms the first isolation layer 302.

[0084] It should be noted that, due to Figure 3 and Figure 4 In the examples of, after forming the first protective film 310, the first isolation film 320 is directly formed. At the contact interface between the semiconductor substrate 101 and the top gate structure 102, the subsequently formed first isolation layer 302 is located on the first protective layer 301, and the first protective layer 301 is in an "L" shape at the contact interface. In some embodiments, after forming the first protective film 310, the first protective layer 301 is first etched and then the first isolation film 320 is formed. At this time, at the contact interface between the semiconductor substrate 101 and the top gate structure 102, the subsequently formed first isolation layer 302 is parallel to the first protective layer 301, and both are in an "I" shape at the contact interface.

[0085] Step S3, forming a second protective layer, the second protective layer is located on the sidewall of the first isolation layer away from the first protective layer and covers the top of the top gate structure. Refer to Figure 5 , Figure 5 Schematic cross-sectional structure diagram of the second protective layer provided for some embodiments.

[0086] It should be noted that, Figure 5 In the examples of, the second protective layer 303 is also located on the top surface of the semiconductor substrate 101. At the contact interface between the semiconductor substrate 101 and the top gate structure 102, the second protective layer 303 is in an "L" shape at the contact interface. In other embodiments, the second protective layer 303 located on the top surface of the semiconductor substrate 101 can also be removed. At the contact interface between the semiconductor substrate 101 and the top gate structure 102, the second protective layer 303 is in an "I" shape at the contact interface.

[0087] Step S4, forming a second isolation layer, the second isolation layer is located on the sidewall of the second protective layer away from the first isolation layer, and in the direction perpendicular to the top surface of the semiconductor substrate, the height of the second isolation layer is lower than the height of the top gate structure.

[0088] Refer to Figures 6 - 8 , Figure 6 Schematic cross-sectional structure diagram of the second isolation film provided for some embodiments,Figure 7 Schematic cross-sectional structure diagram of the carbon coating provided for some embodiments Figure 8 Schematic cross-sectional structure diagram of the second isolation layer provided for some embodiments. In some embodiments, the method of forming the second isolation layer 304 includes: depositing a second isolation film 340 on the surface of the second protective layer 303, spin-coating a carbon coating (Spin On Carbon, SOC) on the surface of the second isolation film 340, etching to expose the top surface of the second isolation film 340, and etching the second isolation film 340 until the height of the second isolation film 340 is lower than the height of the top gate structure 102 in a direction perpendicular to the top surface of the semiconductor substrate 101, and the remaining second isolation film 340 constitutes the second isolation layer 304.

[0089] It should be noted that due to Figures 6 - 8 In the strength of, after forming the second isolation film 340, a spin-coating process is directly performed to form the carbon coating 305. At the contact interface between the semiconductor substrate 101 and the top gate structure 102, the subsequently formed second isolation layer 304 is in an "L" shape at the contact interface.

[0090] In some embodiments, after forming the second isolation film 340, the second isolation film 340 located on the top of the semiconductor substrate 101 is first etched and then a spin-coating process is directly performed to form the carbon coating 305. At this time, at the contact interface between the semiconductor substrate 101 and the top gate structure 102, the subsequently formed second isolation layer 304 is in an "I" shape at the contact interface.

[0091] In addition, referring to Figure 1 、 Figure 2 and Figure 8 , if the top gate structure 102 includes, as described above, a channel layer 201, a gate isolation layer 202, a high dielectric constant (high-K) layer 210, a work function layer 220, a non-metal conductive layer 230, an adhesion layer 240, a metal conductive layer 250, and a gate capping layer 204 stacked in sequence. At this time, the height of the second isolation layer 304 is lower than the top surface height of the gate capping layer 204 and higher than the bottom surface height of the gate capping layer 204.

[0092] Step S5, forming a third protective layer, and the third protective layer covers the top of the second protective layer and the top of the second isolation layer.

[0093] Referring to Figures 9 - 11 , Figure 9 Schematic cross-sectional structure diagram of the third protective film provided for some embodiments Figure 10 Schematic cross-sectional structure diagram of the third protective film after removing the carbon coating provided for some embodiments Figure 11Schematic cross-sectional structure diagram of a semiconductor structure provided for some embodiments. In some embodiments, the method of forming the third protective layer 306 includes: forming a third protective film 360, the third protective film 360 being located on top of the second isolation layer 304 and on top of the second protective layer 303, patterning the third protective film 360 to expose the carbon coating 305 on the sidewall of the second isolation layer 304, removing the carbon coating 305, etching the top of the semiconductor substrate 101 and the top of the top gate structure 102 based on an etching process to expose the semiconductor substrate 101, and the remaining third protective film 360 constitutes the third protective layer 306.

[0094] In some embodiments, the etching selectivity of the etching process for the second isolation layer and the third protective layer is 3:1 to 10:1. In a specific application, the etching selectivity of the etching process for the second isolation layer and the third protective layer can be 4:1, 5:1, 6:1, 7:1, 8:1, or 9:1, etc. By controlling the etching selectivity of the etching process, the etching rate of the etching process for the second isolation layer is relatively fast, and the etching rate for the third protective layer is relatively slow. Thus, after etching the top of the semiconductor substrate 101 to expose the top surface of the semiconductor substrate 101, at the top of the top gate structure 102, there is still remaining third protective film 360, that is, the third protective layer 306 formed by the remaining third protective film 360 covers the top of the second protective layer 303 and the top of the second isolation layer 304.

[0095] In the above embodiments, the descriptions of each embodiment have their own emphases. For parts not detailed in a certain embodiment, reference can be made to the detailed descriptions of other embodiments above, and details will not be repeated here.

[0096] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation to the present disclosure. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to the present disclosure. Such modifications, improvements, and corrections are proposed in the present disclosure, so such modifications, improvements, and corrections still belong to the spirit and scope of the exemplary embodiments of the present disclosure.

[0097] The above has introduced in detail a semiconductor structure and a method for forming the same provided by the embodiments of the present disclosure. Specific examples are used herein to elaborate on the principles and implementation manners of the present disclosure. The description of the above embodiments is only used to help understand the method and its core idea of the present disclosure; at the same time, for those skilled in the art, according to the idea of the present disclosure, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present disclosure.

Claims

1. A semiconductor structure, characterized in that: include: A semiconductor substrate, and a top gate structure located on the semiconductor substrate; An isolation structure, arranged around the side wall of the top gate structure; The isolation structure comprises: a first protective layer, a first isolation layer, a second protective layer and a second isolation layer, wherein the first protective layer is disposed around the side wall of the top gate structure; the first isolation layer is disposed around the side wall of the first protective layer away from the top gate structure; the second protective layer is disposed around the side wall of the first isolation layer away from the first protective layer and covers the top of the top gate structure; the second isolation layer is disposed around the side wall of the second protective layer away from the first isolation layer, and in a direction perpendicular to the top surface of the semiconductor substrate, the height of the second isolation layer is lower than the height of the top gate structure; The third protection layer covers the top of the second protection layer and the top of the second isolation layer.

2. The semiconductor structure according to claim 1, characterized in that: In a direction perpendicular to the side wall of the top gate structure, the thickness of the first protection layer is 1 nm to 100 nm, the thickness of the first isolation layer is 1 nm to 100 nm, and the thickness of the second protection layer is 1 nm to 100 nm.

3. The semiconductor structure according to claim 1, characterized in that: In a direction perpendicular to the sidewall of the top gate structure, the thickness of the second isolation layer is used to adjust the size of the semiconductor structure.

4. The semiconductor structure according to claim 3, characterized in that: The thickness of the second isolation layer is 0.1 nm to 100 nm.

5. The semiconductor structure according to claim 1, characterized in that: The material of the first isolation layer is the same as that of the second isolation layer.

6. The semiconductor structure according to claim 1, characterized in that The material of the first protective layer, the material of the second protective layer and the material of the third protective layer are the same.

7. The semiconductor structure according to claim 1, characterized in that: The top gate structure comprises: A channel layer, located on the top of the semiconductor substrate; A gate isolation layer, located on the top of a side of the channel layer away from the semiconductor substrate; A gate conductive layer, located on a top of a side of the gate isolation layer away from the channel layer; The gate capping layer is located on the top of a side of the gate conductive layer away from the gate conductive layer.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a semiconductor substrate, and forming a top gate structure on the semiconductor substrate; forming a first protection layer and a first isolation layer, wherein the first protection layer is disposed around the side wall of the top gate structure, and the first isolation layer is disposed around the side wall of the first protection layer away from the top gate structure; Depositing to form a second protection layer, the second protection layer is located on a side wall of the first isolation layer away from the first protection layer and covers the top of the top gate structure; forming a second isolation layer, wherein the second isolation layer is located on a side wall of the second protection layer away from the first isolation layer, and in a direction perpendicular to the top surface of the semiconductor substrate, a height of the second isolation layer is lower than a height of the top gate structure; A third protection layer is formed, wherein the third protection layer covers a top portion of the second protection layer and a top portion of the second isolation layer.

9. The method for forming a semiconductor structure according to claim 8, characterized in that: The method of forming the first protection layer and the first isolation layer includes: Depositing a first protective film on the surface of the semiconductor substrate and the top gate structure; Depositing a first isolation film on the surface of the first protective film; The first protective film and the first isolation film located at the top of the top gate structure and the top of the semiconductor substrate are etched and removed, and the remaining first protective film located at the side wall of the top gate structure forms the first protective layer, and the remaining first isolation film located at the side wall of the first protective layer forms the first isolation layer.

10. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the second isolation layer comprises: Depositing a second isolation film on the surface of the second protective layer, and spin coating to form a carbon coating on the surface of the second isolation film; The carbon coating is etched to expose the top surface of the second isolation film, and the second isolation film is etched until the height of the second isolation film is lower than the height of the top gate structure in a direction perpendicular to the top surface of the semiconductor substrate, and the remaining second isolation film constitutes the second isolation layer.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: The method for forming the third protective layer comprises: forming a third protective film, wherein the third protective film is located on top of the second isolation layer and on top of the second protective layer; Patterning the third protection film to expose the carbon coating on the sidewall of the second isolation layer; removing the carbon coating; The top of the semiconductor substrate and the top gate structure are etched based on an etching process to expose the semiconductor substrate, and the remaining third protection film constitutes the third protection layer.

12. The method for forming a semiconductor structure according to claim 11, characterized in that: The etching selection ratio of the etching process to the second isolation layer and the third protection layer is 3:1-10:1.

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