Integrated circuit (IC) with dopant profile control in heterojunction bipolar transistor (HBT)

Abstract

The present disclosure relates to an integrated circuit (IC) with dopant profile control in a heterojunction bipolar transistor (HBT). An integrated circuit (IC) device (100) includes a semiconductor substrate (102) and a heterojunction bipolar transistor including a collector region (106) formed in or above the semiconductor substrate (102), a base region (112) disposed between the collector region (106) and the emitter region (120), and an emitter region (120) disposed between the base region (112) and the emitter region (120). The base region (112) includes a heteroepitaxial portion that includes a narrow band of n-dopant regions.

Description

Technical Field

[0001] The disclosed embodiments generally relate to the field of integrated circuits (ICs) and IC fabrication. More specifically but not exclusively, the disclosed embodiments relate to an IC device that includes a heterojunction bipolar transistor (HBT) with dopant profile control. Background Art

[0002] Epitaxy is used in semiconductor fabrication to produce a suitable crystalline base layer on which semiconductor devices are built, to deposit a crystalline film with engineered electrical properties, and / or to modify the mechanical properties of the underlying layer in a manner that improves the underlying conductivity. In some cases, the epitaxial layer can be doped during deposition by adding impurities to the source gas in order to obtain the desired electrical properties of the epitaxial layer.

[0003] A heterojunction bipolar transistor (HBT) is generally a bipolar junction transistor (BJT) that implements different semiconductor materials for different regions of the transistor, such as an emitter region, a base region, and / or a collector region. For example, an emitter region having a semiconductor material different from the epitaxially grown material of the base region creates a heterojunction in an HBT. HBTs can have a high operating frequency and can thus be implemented in high-frequency circuits such as radio frequency (RF) applications. Summary of the Invention

[0004] A simplified summary is presented below in order to provide a basic understanding of some examples of the present disclosure. This summary of the invention is not an extensive overview of the examples and is neither intended to identify key or important elements of the examples nor to delineate their scope. Indeed, the primary purpose of the summary of the invention is to present some concepts of the present disclosure in a simplified form as a prelude to the more detailed description presented in the subsequent parts below.

[0005] In one example, a method of fabricating an IC device is disclosed. The method may particularly include: forming a first portion of a base region over a collector region of a heterojunction bipolar transistor (HBT), the first portion being epitaxially formed at a first temperature; forming a second portion of the base region over the first portion, the second portion being epitaxially formed at a lower second temperature; and forming a third portion of the base region over the second portion, the third portion being epitaxially formed at the first temperature. In some arrangements, a first type of silicon precursor may be used to form the first and third portions, while a different second type of silicon precursor may be used to form the second portion. In some arrangements, the first type of silicon precursor includes dichlorosilane (DCS, SiCl2H2), and the second type of silicon precursor includes silane (SiH4). In some arrangements, the example method may further include applying hydrogen chloride (HCl) as an etchant at a first flow rate while forming the second portion of the HBT, and applying HCl as an etchant at one or more second flow rates higher than the first flow rate while forming the first and third portions of the HBT.

[0006] In one example, a method of fabricating an IC device is disclosed. The method may particularly include: forming a first portion of a base region over a collector region of an HBT, the first portion being epitaxially formed using a first type of silicon precursor (e.g., DCS); forming a second portion of the base region over the first portion, the second portion being epitaxially formed using a different second type of silicon precursor (e.g., silane); and forming a third portion of the base region over the second portion, the third portion being epitaxially formed using the first type of silicon precursor. In some arrangements, the first and third portions are formed at a first temperature, and the second portion is formed at a lower second temperature.

[0007] In one example, an IC device is disclosed. The IC device may particularly include: a semiconductor substrate; and an HBT including a collector region, a base region, and an emitter region, the collector region being formed in or over the semiconductor substrate, the base region being disposed between the collector region and the emitter region, the base region including a heteroepitaxial portion that includes a narrow band of an n-dopant region, where the thickness of the narrow band may be about one-tenth of the thickness of the heteroepitaxial portion. In some arrangements, the heteroepitaxial portion may include silicon germanium (SiGe) material, and the n-dopant region may be doped with phosphorus having a peak concentration range of about 5×10 18 atoms / cm 19 3 to 5×10 BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In the figures of the accompanying drawings, embodiments of the present disclosure are shown by way of example and not limitation. Different references to "an" or "one" embodiment in the present disclosure do not necessarily refer to the same embodiment, and such references may mean at least one. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, such feature, structure, or characteristic is operable in connection with other embodiments whether or not explicitly described.

[0009] To illustrate one or more exemplary embodiments of the present disclosure, the accompanying drawings are incorporated into and form a part of the specification. The various advantages and features of the present disclosure will be understood from the following detailed description taken in conjunction with the appended claims and with reference to the accompanying drawings, in which:

[0010] Figure 1 A cross-sectional view of an IC device according to some examples is depicted;

[0011] Figure 2 A cross-sectional view of an IC device according to some examples is depicted;

[0012] Figure 3 A cross-sectional view of a layered structure of a base region of an HBT according to some examples is depicted;

[0013] Figure 4A and 4B A flowchart of a method of IC manufacturing according to some examples is depicted;

[0014] Figure 5 A table of processing conditions for manufacturing a layered base region as part of an HBT according to some examples is depicted;

[0015] Figure 6 To depict, according to some examples, for use Figure 5 of processing conditions for manufacturing Figure 3 a graph of the base target concentration gradients of germanium, phosphorus, and carbon at different growth stages of a layered structure; and

[0016] Figure 7 A graph depicting dopant profiles in an HBT according to some examples is shown. Detailed Description

[0017] The examples of the present disclosure are described with reference to the accompanying drawings, in which like reference numerals generally refer to like elements. The figures are not drawn to scale and are provided only to illustrate the examples. Many specific details, relationships, and methods are set forth below to provide an understanding of one or more examples. However, it should be understood that some examples may be practiced without such specific details. In other examples, well-known subsystems, components, structures, and techniques have not been shown in detail so as not to obscure the understanding of the examples. Accordingly, the examples of the present disclosure may be practiced without such specific components.

[0018] Additionally, terms such as "coupled" and "connected" and their derivatives may be used in the following detailed description, claims, or both. It should be understood that these terms are not necessarily intended as synonyms for each other. "Coupled" may be used to indicate that two or more elements, which may or may not be in direct physical or electrical contact with each other, cooperate or interact with each other. "Connected" may be used to indicate the establishment of communication between two or more elements that are coupled to each other, i.e., a communication relationship. Additionally, in one or more examples set forth herein, generally, if an element can be programmed to perform or otherwise be structurally arranged to perform a certain function, then the element, component, or module can be configured to perform the function.

[0019] By way of non-limiting example, examples of IC devices that include one or more heterojunction bipolar transistors (HBTs) and techniques for controlling the dopant profile in the base region of the HBTs will be described below in the context of a P-N-P HBT having an epitaxially grown layered base region that may be doped with a Group V dopant such as phosphorus.

[0020] Some examples of the present disclosure generally relate to providing dopant profile control in HBTs, where the base region may include a compound semiconductor material. Semiconductor processing methods for fabricating IC devices that include HBTs and semiconductor device structures for implementing HBTs having a multi-layer base region are described. The various examples described herein may implement specific semiconductor material systems and specific dopants. For example, some arrangements implement a p-doped silicon (Si) emitter region, an n-doped silicon germanium (SiGe) base region, and a p-doped Si collector region having multiple sub-layers, which are collectively referred to herein as the "Si / SiGe system" for simplicity, where the n-type dopant may include phosphorus (P) or arsenic (As) to achieve a heterojunction in the base region, and the p-type dopant may include boron. Although dopant profile control in p-n-p HBTs is described herein, some aspects of the present disclosure may be more generally applicable to different material systems and different dopants in implementations of HBTs that include combinations of elements selected from Group III, Group IV, and / or Group V.

[0021] The Si / SiGe system for HBT has been observed to have a high operating speed. A higher concentration of germanium in the SiGe base region can result in a higher current gain, and a steep germanium concentration profile can enable a strong drift field to improve device speed. Additionally, a high concentration of phosphorus doping in the SiGe base region can have a narrow width to avoid punch-through.

[0022] It has been observed that processing the Si / SiGe system doped with phosphorus for HBT has various challenges related to the phosphorus concentration profile. For example, the segregation diffusion of phosphorus can cause phosphorus to diffuse from the SiGe layer with a higher germanium concentration to the interface between (i) the silicon-germanium layer and (ii) the silicon layer with a lower germanium concentration or another SiGe layer (or sub-layer). The segregation diffusion of phosphorus can occur during processing at any temperature, even at low temperatures. The segregation diffusion of phosphorus can be particularly exacerbated after processing at temperatures greater than 650 °C, such as in the range of about 650 °C to about 800 °C.

[0023] Furthermore, it has been observed that surface segregation of phosphorus occurs during the epitaxial growth of a SiGe layer (or a sub-layer in a multi-layer architecture) in-situ doped with phosphorus during epitaxial growth. The surface segregation during the epitaxial growth of the SiGe layer can cause phosphorus to accumulate on the top surface or upper surface of the SiGe layer / sublayer.

[0024] In addition, it has been observed that phosphorus has a relatively high diffusion mobility in the silicon-germanium materials used in HBT. Specifically, depending on the device integration of the process flow and / or technology node, phosphorus can diffuse relatively rapidly during periods of high thermal stress, which may occur during processing after depositing the phosphorus-doped SiGe layer. As an example, in complementary bipolar and complementary metal-oxide semiconductor (CBiCMOS) applications, the phosphorus-doped SiGe layer can undergo annealing, such as rapid thermal annealing (RTA), which is implemented to activate the dopants in the CMOS components. Therefore, due to the co-integration of other devices in the CBiCMOS design, the HBT can generate many thermal stresses after forming the base of the HBT.

[0025] Any one of these challenges, individually and / or in combination, may have a detrimental effect on the performance of the HBT. For example, the distribution profile of phosphorus in the SiGe base region can be altered such that the peak concentration of phosphorus can be set outside the SiGe material, which can create a PN junction outside the SiGe region. Therefore, an HBT with such an altered dopant profile may not be able to achieve the benefits of the desired heterojunction.

[0026] The various aspects described herein address these challenges. Any aspect may be implemented alone or in combination with others to address one or more of the above challenges. By implementing the aspects described herein, other challenges regarding applications involving different Group V dopants (e.g., As) and / or other compound semiconductor material systems may be addressed. According to some examples, a layered structure is deposited to form the base region of an HBT, where at least some of the sublayers may be epitaxially grown in a sequential manner (e.g., the Nth sublayer may be epitaxially grown on or above the (N - 1)th sublayer, and so on, where the Nth sublayer may or may not be in-situ doped with a suitable dopant species). Additionally, in the sense that the epitaxial sublayers may include different materials or compositions or polymorphs (e.g., in terms of constituting semiconductor materials, different dopant ratios, concentrations, etc.), the epitaxial sublayers may be heteroepitaxial with respect to adjacent sublayers. Additionally and / or alternatively, in some examples, due to the diffusion of species in the layered structure of the base region, there may not be a clear demarcation between the sublayers.

[0027] In some arrangements, the base region of an exemplary HBT may include a plurality of sublayers, also referred to as "layers", "portions", or "sub-portions", or similar terms depending on the context, where the layers may include a suitable compound semiconductor material (e.g., SiGe material), and the first sublayer may be formed above the collector region of the HBT. A silicon cap layer may cover the sublayers of the HBT. Thus, depending on the context, the base region of the exemplary HBT may appear to have a total of six layers / sublayers (including the cap layer / sublayer), or may appear to be a five-layer / sublayer heteroepitaxial portion located beneath the cap layer / sublayer composed of single-crystalline silicon. To address the segregation diffusion of phosphorus, examples of the present disclosure may include epitaxially growing a portion of three sublayers based on processing conditions to achieve a concentration profile of a semiconductor species (e.g., germanium) such that the percentage concentration of the species in the middle sublayer of the portion is less than the percentage concentration of the species in the two sublayers of the portion adjacent to or immediately surrounding the middle sublayer. Additionally, the middle sublayer of the portion may be in-situ doped with a dopant, such as phosphorus, during the epitaxial growth of the middle sublayer, while the two surrounding sublayers may not be in-situ doped with a dopant during the respective epitaxial growths of each surrounding sublayer. Since the concentration (e.g., percentage concentration) of the semiconductor species in the two sublayers is greater than the concentration of the semiconductor species in the middle sublayer of the portion, the concentration profile of the semiconductor species in the three-sublayer portion may generally resemble a profile that may be referred to as a double-peaked hump. Thus, in some examples of the present disclosure, the base region of the HBT may have a germanium profile that may include at least a portion of what is commonly referred to as a hump profile.

[0028] In the above HBT example, the concentration of germanium implemented in such a layered structure allows a dopant (e.g., phosphorus) to be disposed in a sublayer having a lower germanium concentration, where the sublayer interfaces with a sublayer having a higher germanium concentration. Such an interface boundary between different concentrations is expected to help confine the dopant within the sublayer and thus reduce segregation diffusion outside the heteroepitaxial portion of the base region.

[0029] To address surface segregation, examples of the present disclosure may include epitaxially growing a sublayer in-situ doped with a dopant and a sublayer immediately above the in-situ doped sublayer at a temperature range below the temperature range that may be implemented for the epitaxial growth of the sublayer surrounding the two sublayers. Reducing the temperature of the epitaxial growth is expected to reduce the occurrence of surface segregation. Additionally, to accommodate the lower temperature epitaxial processing of the two sublayers, the silicon precursor mixture for the two sublayers may also be modulated without adversely affecting the overall growth of the layered structure of the base region. As will be seen in detail below, an exemplary embodiment may involve using a first type of silicon precursor that supports a higher growth rate but requires a higher temperature for certain portions of the layered base region, while a second type of silicon precursor that allows for lower temperature processing may be used to grow the in-situ doped sublayer and the sublayer immediately above the in-situ doped sublayer. In an additional arrangement, various etchants and / or co-etchants for the epitaxial growth process may also be modulated according to some examples, such as including but not limited to selective epitaxial growth (SEG) processes (also known as selective area epitaxy or SAE). In cases where the silicon precursor also serves as an etchant, the flow rate of the co-etchant may be modulated if the silicon precursor is replaced by another silicon precursor that does not have etching characteristics during the growth stage.

[0030] Regarding the issue of high diffusion mobility, some examples herein may include doping one or more sublayers of the base region with other Group IV species such as carbon, e.g., by in-situ doping using a suitable precursor. The presence of carbon is expected to reduce the diffusion of another dopant (e.g., a Group V species such as phosphorus) within the heteroepitaxial portion of the base region.

[0031] Any of the foregoing aspects, either alone or in combination with one or more other aspects, may be implemented according to examples of the present disclosure, which may be configured to achieve a concentration profile of an n-type dopant having a peak concentration within a narrow region of the resulting heteroepitaxial portion or layer, thereby helping to achieve the putative benefits of the heterostructure of the HBT. Additionally, regarding the Si / SiGe system, a higher concentration of germanium may be achieved in the SiGe base sublayer such that the HBT may have an increased operating speed. As described above, where applicable, the above aspects may be implemented in any material system involving various compound semiconductor materials and / or any dopants, but are not limited thereto.

[0032] As will be further elaborated in detail below, different sub-layers of the base region of the HBT can be processed using specific processing conditions, which can be modulated depending on the implementation, in order to address one or more of the challenges set forth above. Additionally, the processing conditions set forth herein can be optimized such that the exemplary solutions herein can be advantageously configured to address the above challenges without adversely affecting production volume as some baseline techniques do. Specifically, some aspects of the exemplary solutions can involve modulating certain process conditions in order to reduce the total time period required to grow the base region of the HBT with a suitable dopant profile while avoiding the challenges mentioned herein. Although it is expected that such examples and their variations can increase the production volume of HBT-based IC devices in a foundry without a significant increase in cost, the requirements of the present disclosure are not specific results other than potentially reducing defects that could otherwise reduce the yield, reliability, or electrical performance of the product, unless explicitly recited in a particular technical solution.

[0033] Turning to the drawings, Figure 1 A cross-sectional view of an IC device 100 is depicted in accordance with some examples. In this example, the IC device 100 is a semiconductor device that is or includes a bipolar transistor, such as an HBT, and the structure of the bipolar transistor is generally shown to avoid obscuring the aspects described herein. Specifically, in some cases, multiple different dielectric layers or structures may be shown and described as a single layer or structure. It should be noted that, in such cases, multiple different dielectric layers or structures are covered in some examples. Additionally, intermediate or sacrificial mask layers (although not specifically shown in the figures) that can be used in a selective epitaxial process (e.g., SEG / SAE) are covered in some of the examples described herein.

[0034] The IC device 100 includes a semiconductor substrate 102, which can be a bulk semiconductor material, a semiconductor-on-insulator (SOI), or any other suitable semiconductor substrate. Depending on the application, the semiconductor material of the semiconductor substrate 102 can be or include silicon (Si), silicon germanium (SiGe), the like, or a combination thereof. In some examples, the semiconductor substrate 102 is a silicon substrate that can be singulated from a bulk silicon wafer at the end of semiconductor processing.

[0035] Isolation region 104 can be formed in semiconductor substrate 102, and each isolation region 104 can extend at least from the top portion of semiconductor substrate 102 (e.g., where devices are formed thereon and / or therein) to a certain depth in semiconductor substrate 102. Isolation region 104 can be formed by various isolation techniques, such as shallow trench isolation (STI), deep trench isolation (DTI), local oxidation of semiconductor (LOCOS), or the like. Depending on the implementation, isolation region 104 can comprise a suitable dielectric material, such as an oxide, a nitride, the like, or a combination thereof. In some arrangements, isolation region 104 can comprise a polysilicon-filled trench surrounded by a dielectric material. Generally, one or more isolation regions 104 can be provided to define active regions on semiconductor substrate 102 where semiconductor devices are to be formed thereon, above, and / or therein.

[0036] Collector region 106 can be formed on the active region of semiconductor substrate 102. In the illustrated example, collector region 106 is semiconductor material epitaxially grown on or above the active region of semiconductor substrate 102. In other examples, collector region 106 can be entirely disposed within semiconductor substrate 102 (e.g., without epitaxially grown material forming a part of collector region 106) or at least partially disposed within semiconductor substrate 102. In some arrangements, a heavily doped buried layer (e.g., a p-type buried layer or PBL not shown in this figure) can be provided as part of collector region 106. The semiconductor material of collector region 106 can include single-crystalline material and can comprise Si, SiGe, and the like, or a combination thereof. In some instances, collector region 106 can comprise silicon epitaxially grown by SEG on the active region of semiconductor substrate 102 using any suitable epitaxial technique, such as metalorganic vapor phase epitaxy (MOVPE), liquid phase epitaxy (LPE), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), and atomic layer epitaxy (ALE), etc., and can be appropriately doped (e.g., with a p-type dopant such as boron in a p-n-p HBT design).

[0037] Depending on the implementation, the epitaxial processes described herein may involve a variety of complex interactions of different materials, typically present in multiple phases (e.g., gas phase, liquid phase, and / or solid phase), which may occur in a dedicated chamber for growing epitaxial layers one layer at a time (e.g., atoms or molecules of a single layer, referred to as a monolayer) above a substrate. Epitaxial growth may result in the formation of facets on the sidewall surfaces of the epitaxial growth material. The formation of the facets may depend on the epitaxial growth conditions and the orientation of the crystalline surface on which the epitaxial growth material is grown. Broadly speaking, the epitaxial process may include the following steps and / or phenomena: transporting reactants to the substrate in the reaction chamber, transferring the reactants to the substrate surface, adsorbing the reactants on the substrate, surface processes such as reactions and kinetics, desorbing the products and / or by-products, transferring the products / by-products to the main transport medium (e.g., gas), and exhausting / removing the gas and other by-products from the reaction chamber.

[0038] As Figure 1 shown, isolation regions 108, 109 may be provided in the IC device 100 to facilitate laterally defining and / or forming suitable contact surfaces relative to the collector region 106. In some arrangements, the isolation region 108 may extend from the top surface 105 of the collector region 106 to a certain depth within the collector region 106. The isolation region 109 may be formed to laterally define the collector region 106 and may be disposed above the isolation region 104 in the semiconductor substrate 102. Depending on the implementation, the isolation regions 108, 109 may be STI, DTI, or the like. The isolation regions 108, 109 may each comprise a dielectric material, such as an oxide, a nitride, the like, or a combination thereof.

[0039] A first dielectric layer 110 may be formed over the isolation regions 108, 109 and the collector region 106. As described above, the first dielectric layer 110 may comprise a plurality of dielectric layers, such as an etch stop layer (e.g., including silicon nitride (SiN) or the like) and an interlayer dielectric disposed on the etch stop layer (e.g., including silicon dioxide (SiO2) or the like) ( Figure 1 not specifically shown in). The first dielectric layer 110 may be deposited by any suitable deposition process and may subsequently be planarized by using a planarization process, such as chemical mechanical polishing (CMP).

[0040] Regarding the formation of the remaining portions of the HBT, such as the base region and the emitter region covering the collector region 106, and regarding the formation of the external region in some embodiments for providing connectivity to the base region, a conductive layer 116 may first be deposited over the first dielectric layer 110. The conductive layer 116 may be formed by any suitable deposition process and may include a doped semiconductor material, such as an n-doped material in a p-n-p HBT, which may be doped polysilicon, doped amorphous silicon, or undoped polysilicon / undoped amorphous silicon, followed by an n-type ion implant. By using appropriate lithography and etching processes, with a patterned SiO2 / SiN layer as a mask (not shown in this figure), openings, also referred to as "emitter windows", may be created through the conductive layer 116 and the first dielectric region 110, where the openings are configured to facilitate the formation of the base region 112 over the collector region 106. At the same time, the patterning of the conductive layer 116 may also be configured to form one or more external regions 115, which are configured to provide electrical connectivity to the base region 112 to be formed over the collector region 106. Subsequent etching processes may be configured to remove the SiO2 layer while maintaining the patterned SiN layer to facilitate the formation of the base region, such as the base region 112, in the emitter window opening using SEG / SAE. As previously described, the base region 112 may include a multi-layer structure (not specifically shown in this figure), where the semiconductor material of each sub-layer may include Si, SiGe, and the like, or a combination thereof. As will be further elaborated in detail below, suitable epitaxial processes (e.g., SEG / SAE) and process recipes configured to minimize the spread of dopant concentrations without adversely affecting the processing time may be used to sequentially form the different layers / sub-layers of the base region 112 in the opening.

[0041] Dielectric spacers 118 may be disposed along the sidewalls of the openings through the external regions 115, where the dielectric spacers 118 may extend into the base region 112. The dielectric spacers 118 may be formed by conformally depositing one or more dielectric layers in the openings and etching the one or more dielectric layers (e.g., anisotropically etching) such that the dielectric spacers 118 remain along the sidewalls of the openings while a portion of the base region 112 remains exposed, over which the emitter region 120 may then be formed. Similar to the dielectric layers described previously, the dielectric spacers 118 formed in the openings may include any suitable dielectric material, such as SiN, SiO2, and / or a combination thereof, or the like.

[0042] A suitably doped material (e.g., a p-doped material) can form an emitter region 120 disposed in an opening defined by spacer 118 and above the exposed base region 112. In the illustrated example, emitter region 120 is a semiconductor material epitaxially grown on base region 112 after forming its various sub-layers in successive stages, which may include forming a silicon capping layer. The semiconductor material of emitter region 120 is crystalline (e.g., single crystal), and may include Si, SiGe, and / or combinations thereof that can be epitaxially grown (e.g., SEG / SAE), or the like.

[0043] A fill material 122 can be disposed on emitter region 120, which can initially fill the opening and then be patterned to form apertures configured to facilitate contact formation in subsequent stages. In some arrangements, fill material 122 can include a conductive material (such as a doped semiconductor material, e.g., doped polysilicon or doped amorphous silicon) or a dielectric material. Fill material 122 can be deposited using any suitable deposition process. In some arrangements, fill material 122 including polysilicon and emitter region 120 including single crystal silicon can be deposited together simultaneously.

[0044] A second dielectric layer 130 can be disposed above the patterned conductive layer 116, which includes the external region 115, dielectric spacer 118, fill material 122, and first dielectric layer 110. In some arrangements, second dielectric layer 130 can include multiple dielectric layers / sublayers and can function as a pre-metal dielectric (PMD) layer, which can be formed using any suitable process and then polished (e.g., by CMP). Suitable contact vias can be formed through first dielectric layer 110 and second dielectric layer 130 using photolithography and etching processes to provide openings to collector region 106, external region 115, and emitter region 120, which can be suitably silicided or covered by a metal silicide layer (e.g., cobalt silicide (CoSi)) before contact formation. Figure 1is not shown specifically. As shown, the collector contact 132 is disposed through the second dielectric layer 130 and the first dielectric layer 110 and contacts the silicided surface of the collector region 106. Similarly, the base contact 134 is disposed through the second dielectric layer 130 and contacts the silicided outer region 115 that is in electrical contact with the base region 112. The emitter contact 136 is disposed through the second dielectric layer 130 and contacts the silicided surface of the emitter region 120 and / or the fill material 122. In some arrangements where the fill material 122 is conductive, the emitter contact 136 can contact the fill material 122 without contacting the emitter region 120 and can be electrically connected to the emitter region 120. In the examples herein, the contacts 132, 134, 136 can include one or more barrier layers and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), and the like, or combinations thereof) conformally formed in contact via openings, which can be filled with a conductive fill material (e.g., a metal such as tungsten (W), copper (Cu), combinations thereof, or the like).

[0045] As described above, in some examples, the IC device 100 is or includes a bipolar transistor, and more specifically an HBT, which can be a stand-alone device or integrated with other microelectronic circuits depending on the level of integration. Without being limited to any particular technology node or product implementation, the following description sets forth various processes and materials for forming Figure 1 the multi-layer structure of the base region 112 shown in. Additionally, although the following examples relate to a p-n-p HBT structure, aspects described herein in other examples can also be used to implement an n-p-n HBT structure, with appropriate modifications applied as necessary.

[0046] Figure 2 A cross-sectional view of an IC device 200 is depicted in accordance with some examples, showing another arrangement of an HBT. Similar to Figure 1 , the IC device 200 is generally shown to avoid obscuring the aspects described herein. As previously mentioned, a semiconductor substrate 202 made of a suitable material can include various isolation regions 204, such as DTI, STI, or the like, which can be configured to define active regions on the semiconductor substrate 202 where semiconductor devices are to be formed thereon, above, and / or within. The collector region 206 is disposed on or above the active region of the semiconductor substrate 202. A multi-layer base region 212 is disposed between the collector region 206 and the emitter region 220, where the base region 212 can be formed in a non-selective epitaxial SiGe process. Different from Figure 1 the example shown in Figure 2The IC device 200 does not include an external region for providing connectivity relative to the base region 212. Instead, the base region 212 is shaped to directly support the contact 234. Although there is no external region covering the base region 212, a window or opening can be formed through the dielectric layer 214 covering the collector region 206 to facilitate the formation of the base region 212 above the collector region 206 using a SEG / SAE process similar to that shown for the formation of the base region 112 in Figure 1 The emitter region 220 formed on or above the base region 212 after the formation of the base region 212 can have a contact 236 thereto without an opening lined with a dielectric sidewall and / or filled with a conductive fill material, as is the case in the example of Figure 1 . The collector region 206 defined by the isolation regions 208, 210 can be in contact with the contact 232 formed through one or more dielectric layers 214, 230, which are formed similar to the dielectric layer arrangements 110, 130 shown in Figure 1 . Additionally, the isolation region 210 can be formed above an isolation region 204 similar to the isolation region 104 of the IC device 100 in Figure 1 . Except for the differences described above, the IC device 200 is substantially similar to the IC device 100 in Figure 1 , and the individual layers / sublayers of the multi-layer structure forming the base region 212 can be fabricated using similar process conditions as those used in fabricating the base region 112 according to the examples herein.

[0047] Figure 3A vertical architecture of a representative HBT 300 is shown, where a cross-sectional view of a multi-layer structure of the base region 312 is presented according to some examples. In one arrangement, a first base sub-layer 332 of the base region 312 is disposed on or above the collector region 306 of the representative HBT 300. A second base sub-layer 334 of the base region 312 is disposed on or above the first base sub-layer 332 in a vertical stack formation. In a similar manner, a third base sub-layer 336 of the base region 312 is disposed on or above the second base sub-layer 334. A fourth base sub-layer 338 of the base region 312 is disposed on or above the third base sub-layer 336. A fifth base sub-layer 340 of the base region 312 is disposed on or above the fourth base sub-layer 338. A top capping sub-layer 342 of the base region 312 is disposed on or above the fifth base sub-layer 340. The emitter region 320 is disposed on or above the top capping sub-layer 342. As will be seen below, each of the base sub-layers 332 to 340 and the top capping layer 342 (which, in some examples, can be considered as the sixth sub-layer of the base region 312) can be deposited, grown, or otherwise formed in corresponding stages of a process flow having a corresponding set of process conditions, and each process condition can be adjusted, modulated, tuned, and / or otherwise optimized to help achieve a narrow dopant profile in the base region 312 while minimizing the amount of time required to fabricate the base region 312 having a given total thickness.

[0048] According to some examples, Figure 3 the collector region 306, the base region 312, and the emitter region 320 of Figure 1 may appear to be respectively similar to the collector region 106, the base region 112, and the emitter region 120 of the IC device 100 depicted in Figure 3 In a similar manner, according to some examples, Figure 2 the collector region 306, the base region 312, and the emitter region 320 of

[0049] Depending on the application and processing conditions, the various sub-layers of the base region 312 can each have a corresponding thickness in a direction along the surface normal with respect to the main surface of the IC device containing the representative HBT 300 (e.g., the top surface of the semiconductor substrate, which is not specifically shown in this figure). In the case of measuring the thickness in a direction extending inward from the bottom surface of the emitter region 320 (e.g., towards the collector region 306), the thickness of the base sub-layer can be regarded as the corresponding depth of the respective base sub-layer, where the bottom surface of the emitter region 320 is the reference point of zero depth. Thus, the top capping layer / sublayer 342 can be regarded as the topmost / sublayer of the base region 312, e.g., closest to the emitter region 320, while the first base sub-layer 332 can be regarded as the deepest or bottommost / sublayer of the base region 312, e.g., closest to the collector region 306.

[0050] By way of illustration, the first base sub-layer 332 has a first thickness 352; the second base sub-layer 334 has a second thickness 354; the third base sub-layer 336 has a third thickness 356; the fourth base sub-layer 338 has a fourth thickness 358; the fifth base sub-layer 340 has a fifth thickness 360; and the top cover sub-layer (or sixth base sub-layer) 342 has a sixth thickness 362. Depending on the application, each of the various base sub-layers may have a corresponding thickness in the range of about a few nanometers (nm) to about several tens of nanometers.

[0051] In some instances, the thicknesses of some of the base sub-layers may be substantially equal. In some instances, the thicknesses 352, 356, 358 of the first base sub-layer 332, the third base sub-layer 336, and the fourth base sub-layer 338 may be in the range of about 2 nm to about 10 nm. In some instances, the thicknesses 354, 360 of the second base sub-layer 334 and the fifth base sub-layer 340 may be in the range of about 5 nm to about 40 nm. In some instances, the thickness 362 of the top cover sub-layer 342 may be in the range of about 10 nm to about 50 nm. Although the relationships between the various thicknesses and the thicknesses of the layers have been given as examples, any suitable thickness may be implemented for a given sub-layer.

[0052] The base sub-layers 332, 334, 336, 338, 340 and the top cap sub-layer 342 are each composed of a suitable semiconductor material having a crystalline structure (e.g., single crystal). The base sub-layers 332, 334, 336, 338, 340 may also be doped with a suitable dopant. The base sub-layers 332, 334, 336, 338, 340 are formed of at least one semiconductor species different from or not typically included in the collector region 306, the top cap sub-layer 342, and / or the emitter region 320 (e.g., epitaxially grown). Incorporating at least one different semiconductor species in different compositions and / or concentrations can result in the formation of a heteroepitaxial layer or a portion of the base region 312, which in turn can form a heterojunction relative to the top cap sub-layer 342 and / or the emitter region 320 as part of a representative HBT 300. In the example described in the context of the Si / SiGe system, the at least one different semiconductor species includes germanium. Thus, the following examples illustrate representative concentrations (e.g., in percentages), concentration gradients, and profile distributions in the context of germanium, which can also more generally apply to other semiconductor species (e.g., from Group IV), which can be used to form different types of compound semiconductor materials. Additionally, the base region 312 and the emitter region 320 are doped with dopants that can be configured to form a PN junction at or near the heterojunction. In the example described below in the context of a p-n-p HBT of the Si / SiGe system, the dopant for doping one or more of the base sub-layers 332, 334, 336, 338, 340 of the base region 312 includes an n-type dopant, and more specifically phosphorus as previously mentioned. In some additional and / or alternative arrangements, other n-type dopants such as As in the Si / SiGe system or other n-type dopants for other material systems can be used to dope the heterojunction base region, such as the base region 312. In other examples, a p-type dopant (e.g., having a conductivity type opposite to that of the n-type dopant) can be used in the context of an n-p-n HBT embodiment to dope the heterojunction base region, such as the base region 312.

[0053] As will be elaborated below, the concentration of germanium can vary in percentage between the various base sub-layers 332, 334, 336, 338, 340. On the other hand, the collector region 306, the top cap sub-layer 342, and the emitter region 320 are each composed of silicon (e.g., without different semiconductor species such as germanium). In some examples, the second base sub-layer 334, the third base sub-layer 336, the fourth base sub-layer 338, and the fifth base sub-layer 340 may each be doped with approximately or substantially equal percentages of carbon, e.g., in the range of 0.15% to 0.3%. In some examples, carbon can be omitted, e.g., in the case of implementing dopants other than phosphorus. In some examples, the SiGe compositions of the various base sub-layers 332, 334, 336, 338, 340 may include Si 1-x Gex a ratio range of the form, where 0 ≤ x ≤ 1. Additional details regarding the specific SiGe ratio of different base sub-layers (e.g., base sub-layers 332, 334, 336, 338, 340) of the HBT heterostructure can be found in U.S. Patent Application Publication No. 2023 / 0088544, which is incorporated herein by reference for all purposes.

[0054] Regarding optimizing the growth rate of different base sub-layers and thus the time required to fabricate a base region with a specific total thickness while ensuring that the profile of the n-type dopant remains within a narrow width (e.g., having a steep or narrow peak), the inventors of the present disclosure have found that a combined flow involving different silicon precursors can be particularly advantageous in balancing various competing process constraints. Although using a Si precursor such as DCS can generally provide better etch selectivity required for SEG / SAE processing over regions defined by patterned SiO2 / SiN layers (e.g., in emitter window openings), DCS-based processing requires higher temperatures to support a growth rate sufficient to maintain a cost-effective process flow for manufacturability. However, the higher temperatures used in DCS-based epitaxial processing can have a negative impact on the phosphorus profile, resulting in a wider peak within the base region. Thus, the examples herein provide a process flow where the DCS-based epitaxial process can be replaced during certain selective stages of base region formation (e.g., stages involving doping with an n-type dopant species) by an epitaxial process based on another Si precursor such as silane (SiH4) that provides sufficient growth rate at a lower temperature and thus does not have a negative impact on the dopant profile in the base region. To maintain the selectivity of the epitaxial process, a co-etchant (e.g., hydrogen chloride (HCl)) can be used and / or adjusted accordingly during the selective stages according to some examples herein.

[0055] Figure 4A and 4B A flowchart depicting a method of IC manufacturing, where according to some examples, the base region of an HBT can be formed using a combined flow of different Si precursors and process conditions relative to different portions of the base region. Figure 4AThe example method 400A shown in FIG. 0 represents an overall process for forming a heterojunction base region having at least three parts, which can be fabricated in successive stages in a suitable epitaxial flow (e.g., SEG / SAE) with corresponding process conditions. At block 402, a first part of the base region of the HBT can be formed, for example, above the collector region at a first temperature and / or using a first type of Si precursor including DCS. As previously elaborated, DCS can be used to provide better selectivity while supporting a higher growth rate at high temperatures during the formation of the first base part that does not involve doping with n-type species. At block 404, a second part of the base region can be formed above the first base part at a second temperature lower than the first temperature and / or using a second type of Si precursor and a suitable n-dopant precursor. In some examples, the second type of Si precursor includes silane, and the n-type dopant precursor includes phosphine (PH3) that can be applied during at least a sub-part of the formation of the second part. Since a lower temperature is used in the growth process involving dopants, the dispersion of the dopant profile can be minimized, which can help limit the profile to a narrow width during subsequent manufacturing stages. At block 406, a third part of the base region can be formed above the second base part, where a higher temperature can be applied and / or the supply of the first type of Si precursor can be resumed while terminating the supply of the n-dopant precursor. Thus, while the growth rate is not negatively affected during the formation of the various base region parts, the temperature state control is selectively applied to facilitate limiting the profile of the n-dopant to a narrow region within the base region. Additionally, since the silane-based phase used for forming the second base part can be advantageously modulated to achieve a growth rate greater than the growth rate in some baseline technologies, the throughput of the HBT process flow can be advantageously improved in some examples herein. As will be further seen below, depending on the specific multi-layer architecture of the base region, other processing conditions can also be appropriately changed layer by layer during the formation of the various base region parts. Specifically, in the case of including a co-etchant to facilitate SEG / SAE processing, the flow rate of the co-etchant can also be appropriately adjusted when using silane.

[0056] Figure 4BThe example method 400B represents a process for fabricating the base region of a multi-layer HBT on a layer-by-layer basis, where a first subset of the layers may form a first base portion, a second subset of the layers may form a second base portion, and a third subset of the layers may form a third base portion, and the base portions may correspond to the base portions described above. At block 420, a first base sub-layer of the base region may be formed epitaxially on or above the collector region, where the epitaxial process may be performed using a first type of Si precursor (e.g., DCS) at a first temperature to produce a first base sub-layer having a first thickness. At block 422, a second base sub-layer of the base region may be formed epitaxially on or above the first base sub-layer, where the epitaxial process is performed using the first type of Si precursor at the first temperature to produce a second base sub-layer having a second thickness. At block 424, a third base sub-layer of the base region may be formed epitaxially on or above the second base sub-layer, the third base sub-layer having a third thickness, where the epitaxial process is performed using a second type of Si precursor (e.g., silane) and a supply of an n-dopant precursor (e.g., PH3) at a second temperature lower than the first temperature. At block 426, a fourth base sub-layer of the base region may be formed epitaxially on or above the third base sub-layer, the fourth base sub-layer having a fourth thickness, where the epitaxial process is performed using the first type of Si precursor while terminating the supply of the n-dopant precursor at the second temperature. At block 428, a fifth base sub-layer of the base region may be formed epitaxially on or above the fourth base sub-layer, where the epitaxial process is performed using the first type of Si precursor at the first temperature to produce a fifth base sub-layer having a fifth thickness. At block 430, a cap layer may be formed epitaxially on or above the fifth base sub-layer (e.g., as a sixth base sub-layer of the base region), the cap layer having a sixth thickness, where the epitaxial process is performed at a third temperature higher than the first temperature and using the first type of Si precursor.

[0057] Depending on the implementation, in some instances, the epitaxial growth process described above may include SEG / SAE processing. As previously described, a variety of techniques may be used to implement epitaxial growth, where appropriate process conditions, precursor gases (or other sources), carrier gases, or other delivery media, etc., may be used during epitaxial growth to achieve the target thicknesses of the specific HBT implementation (e.g., sub-layers 332 to 342) and the target concentrations of the species in sub-layers 332 to 342.

[0058] Continuing with the example where base sub-layers 332 to 340 are composed of SiGe materials as described above, in some arrangements, the SEG process for epitaxially growing base sub-layers 332 to 340 may include a silicon-containing precursor gas, a germanium-containing precursor gas, and an etchant gas. The base sub-layer 342, which includes single-crystalline silicon, does not contain germanium, as previously mentioned. Figure 5Table 500 depicts various processing conditions for fabricating a laminated base region that is part of an HBT. As shown, six columns 502 to 512 are presented, each specifying a set of exemplary process conditions, target thicknesses, durations, etc. respectively corresponding to the six base sub-layers 332 to 342 discussed above.

[0059] In some examples, the recipe for selectively growing a representative base sub-layer may include using DCS as a silicon-containing precursor gas (and also potentially as a co-etchant gas) at a higher temperature range (e.g., about 650 °C) during some stages or steps, which may be replaced with silane during certain other stages or steps involving a lower temperature range (e.g., about 570 °C). A dopant-containing gas (e.g., an n-type dopant precursor gas) may be implemented during the epitaxial growth of a given layer to in-situ dope the layer. According to examples herein, n-type in-situ doping may be implemented during a silane-based growth stage rather than a DCS-based growth stage. Although HCl and DCS may be implemented as co-etchants during a DCS-based stage, only HCl is implemented as an etchant during a silane-based growth stage to maintain the SEG / SAE process. Additionally, because an n-type in-situ doped layer that is roughly centered within the base region of the HBT is desired, a silane-based stage and corresponding n-type in-situ doping may be implemented for fabricating a base sub-layer that is roughly in the middle of a base region of a given thickness, which may correspond to a pre-configured target depth from the emitter region (or, conversely, the height from the collector region). Thus, in some examples, phosphine (PH3) may be used as an n-type dopant precursor during the epitaxial growth of the third base sub-layer 336 to in-situ dope the third base sub-layer 336 with phosphorus, where the growth stage is based on silane implemented at a temperature lower than that for a DCS-based growth stage. In some examples, a germanium-containing precursor (e.g., germane (GeH4)) may be applied at different rates during the fabrication of base sub-layers 332 to 340. In some examples, a carbon-containing gas, such as monomethylsilane (MMS) (CSiH6), dimethylsilane (DMS) (C2H8Si), or trimethylsilane (TMS) (C3H 10 Si), may be used during the epitaxial growth of a selective subset of base sub-layers (e.g., the second base sub-layer 334, the third base sub-layer 336, the fourth base sub-layer 338, and the fifth base sub-layer 340) to in-situ dope the corresponding sub-layers with carbon.

[0060] In some instances, the base sub-layer 332 can be fabricated during a growth stage (Stage A) having the processing conditions and target markers set forth in column 502 of Table 500. According to one embodiment, Stage A can involve epitaxial growth by using DCS at a flow rate of about 40 standard cubic centimeters per minute (sccm) in a temperature range of about 650 °C and supplying a germane precursor (e.g., 6% germane in hydrogen (H2)) in a carrier gas at about 10 sccm under other processing conditions to achieve a target thickness of about 5 nm to 10 nm above the collector region.

[0061] In some instances, the base sub-layer 334 can be fabricated during a growth stage (Stage B) having the processing conditions and target markers set forth in column 504 of Table 500. According to one embodiment, Stage B can also involve epitaxial growth by using DCS at a flow rate of about 40 sccm in a temperature range of about 650 °C and supplying a germane precursor (e.g., 6% germane in H2) at about 17 sccm under other processing conditions to achieve a target thickness of about 15 nm to 25 nm above the base sub-layer 332.

[0062] In some instances, the base sub-layer 336 can be fabricated during a growth stage (Stage C) having the processing conditions and target markers set forth in column 506 of Table 500. According to one embodiment, Stage C can involve epitaxial growth by using silane at a flow rate of about 57 sccm in a lower temperature range of about 570 °C and supplying a germane precursor (e.g., 6% germane in H2) and phosphole in a carrier gas at about 18 sccm to achieve a desired dopant concentration profile depending on the application. In an exemplary arrangement, Stage C can be implemented to achieve a narrow target thickness of the base sub-layer 336 formed above the base sub-layer 334, e.g., about 2 nm to 10 nm. According to the examples herein, the base sub-layer 336 can be configured as a layer centered about the middle of the base region as described above to obtain a substantially normal (or Gaussian) distribution of the dopant profile having a peak concentration within the third base sub-layer 336. In one arrangement, the n-doped base sub-layer 336 can be formed as a narrow band having a thickness of about one-tenth of the thickness of the heteroepitaxial portion of the base region 312.

[0063] In some instances, the base sub-layer 338 may be fabricated in a growth stage (Stage D) having the processing conditions and target markers set forth in column 508 of Table 500. According to one embodiment, Stage D may involve epitaxial growth by using silane at a flow rate of about 57 sccm in a lower temperature range of about 570 °C and supplying a germane precursor (e.g., 6% germane in H2) at about 28 sccm in other processing conditions to achieve a target thickness of about 5 nm to 10 nm above the base sub-layer 336. According to the examples herein, the supply of phosphole may be terminated in Stage D and subsequent growth stages.

[0064] In some instances, the base sub-layer 340 may be fabricated in a growth stage (Stage E) having the processing conditions and target markers set forth in column 510 of Table 500. According to one embodiment, Stage E may involve epitaxial growth by using DCS at a flow rate of about 40 sccm in a higher temperature range of about 650 °C and supplying a germane precursor (e.g., 6% germane in H2) at about 10 sccm in other processing conditions to achieve a target thickness of about 5 nm to 15 nm above the base sub-layer 338.

[0065] In some instances, the base sub-layer 342 may be fabricated in a growth stage (Stage F) having the processing conditions and target markers set forth in column 512 of Table 500. According to one embodiment, Stage F may involve epitaxial growth by using DCS at a flow rate of about 40 sccm in a higher temperature range of about 750 °C in other processing conditions. Since the base sub-layer 342 may operate as a capping layer of the base region that interfaces with the emitter region, where the capping layer includes elemental Si material, the supply of germane may be terminated during the Stage F process. In some arrangements, according to the examples herein, the process conditions of Stage F may be adjusted to achieve a target thickness of about 20 nm to 50 nm above the base sub-layer 340.

[0066] As Figure 5 set forth in Table 500, HCl may be used as an etchant or co-etchant in the entire epitaxial flow to promote the selectivity of growth in the patterned regions, such as the regions above the collector region 306 defined for fabricating the heterojunction base region 312, while DCS is used as a precursor and etchant in the stages involving high temperature ranges. Using a combination of silane and HCl in a lower temperature range during Stage C instead of using DCS and HCl in a higher temperature range provides a process condition mix that enables the in-situ doped dopant species to have a peak substantially confined near the middle portion of the base region 312 while minimizing the potential broadening or widening of the peak during high temperature processing.

[0067] Figure 6 To depict for use according to some embodimentsFigure 5 fabricated under the processing conditions respectively Figure 3 FIG. 600 of the approximate base epitaxial target concentration gradients of germanium, phosphorus, and carbon in different growth stages of the base sub-layers 332 to 342 of the layered structure of Figure 3 (e.g., prior to subsequent diffusion). As shown, the depth continuum region shown along the X-axis 699 can be divided into three regions, e.g., the p-doped emitter region 320, the n-doped base region 312, and the p-doped collector region 306, where the p-doped collector region 306 forms the deepest region of the HBT fabricated in or above the semiconductor substrate, e.g., the HBT shown in Figure 1 the HBT shown in Figure 2 the HBT shown in Figure 6 It should be noted that

[0068] It should be noted that Figure 6 the concentration gradients of the species shown represent the target concentrations after depositing the base sub-layers 332 to 342 and without significant additional processing (e.g., without any high-temperature processing that would otherwise cause diffusion of the dopant species). The target germanium concentration gradient 620 increases from the interface between the first base sub-layer 332 and the collector region 306 to a first target concentration of approximately 18% in the first base sub-layer 332 (in the stage A processing), and then increases to a target concentration of approximately 23% in the second base sub-layer 334 (in the stage B processing). Thereafter, the target germanium concentration gradient 620 decreases to a lower concentration of approximately 18%, thereby creating a "valley" in the concentration profile of the third base sub-layer 336 in the stage C processing. Based on the valley concentration of approximately 18%, the target germanium concentration gradient 620 increases to a higher target concentration value (e.g., approximately 23%) in the fourth base sub-layer 338 (in the stage D processing), and then decreases to a lower concentration value (e.g., approximately 18%) in the fifth base sub-layer 340 (in the stage E processing). Thereafter, during the formation of the sixth base sub-layer 612 formed as a silicon cap layer in the stage F processing as described above, the target germanium concentration gradient 620 decreases to zero.

[0069] In some instances, the collector region 306 does not contain a significant amount of germanium prior to depositing, for example, the first base sub-layer 332 because the collector region 306 (which has been doped with a p-type dopant species) may not have been directly exposed to a germanium-containing precursor or material. It is contemplated that prior to depositing the first base sub-layer 332, the collector region 306 may have a trace or non-substantial amount of germanium due to, for example, indirect or non-substantive exposure to germanium. Upon further consideration, after depositing the first base sub-layer 332, an amount of germanium may diffuse from the first base sub-layer 332 into the collector region 306 (e.g., due to Ge diffusion caused by heat treatment).

[0070] The goal of the phosphorus concentration gradient 622 is to have a peak in the third base sub-layer 336 formed during the stage C process, which is expected to approximate a Gaussian or quasi-Gaussian distribution (e.g., with some skew) after processing and subsequent annealing. As shown, the phosphorus doped in the third base sub-layer 336 is set between two interfaces, where the germanium concentration in the third base sub-layer 336 is lower (e.g., has a valley concentration) relative to the germanium concentration in adjacent sub-layers (e.g., the second base sub-layer 334 and the fourth base sub-layer 338). Additionally, it can be seen that the adjacent second base sub-layer 334 and fourth base sub-layer 338 have the highest target concentration of germanium. By having the phosphorus set between two interfaces or regions where the germanium concentration increases, such that the phosphorus profile overlaps or is overlapped by the valley concentration of germanium, the effect of segregation diffusion can be better incorporated within the base sub-layers 332 to 340 that form the heteroepitaxial structure for the base region 312 described herein, which can help prevent the peak concentration of phosphorus from occurring or repositioning outside of the base sub-layers 332 to 340.

[0071] In a similar manner, it can be seen that the carbon concentration gradient 624 overlaps with the third base sub-layer 336 that contains in-situ doped phosphorus. The presence of carbon can reduce the thermal diffusivity mobility of phosphorus, for example, during a period of thermal stress. Thus, by having the sub-layer doped with phosphorus overlapped and / or surrounded by a sub-layer doped with carbon, the diffusion effect can be reduced, especially when it occurs during thermal stress, such that more phosphorus remains within the third base sub-layer 336. Therefore, it is expected that the carbon doping described in the examples herein can further help prevent the peak concentration of phosphorus from occurring or repositioning outside of the base sub-layers 332 to 340.

[0072] After depositing sub - layers 332 to 342 of the base region 312, additional processing may be performed relative to the remaining IC manufacturing steps. For example, high - temperature processing may be performed on a semiconductor wafer containing an HBT formed according to the examples herein. Specifically, in some embodiments, an annealing process such as rapid thermal annealing (RTA) may be performed to activate dopants such as CMOS components and emitter drive - in dopants. An exemplary annealing process may include a nitrogen (N2) spike RTA at a peak temperature of 1,080 °C for CMOS source / drain activation and emitter drive - in. Additionally, due to the co - integration of other devices in the CBiCMOS design, the base region 312 may experience multiple thermal stresses after the base region 312 is formed, which may cause further diffusion of species in the base region 312.

[0073] Figure 7 FIG. 700 is a diagram depicting dopant profiles in an HBT according to some examples. As shown, FIG. 700 includes three dynamic secondary ion mass spectrometry (DSIMS) traces respectively representing a phosphorus concentration profile 702, a germanium concentration profile 704, and a carbon concentration profile 706, where the dopant profiles may include or exhibit diffusion effects and other artifacts. In some arrangements, the exemplary FIG. 700 may represent the dopant concentration profile grown after forming the base region of the HBT (e.g., before completion of the heat treatment). Similar to FIG. 600 described above, a depth continuum is shown along the X - axis 799, which indicates that the total thickness of the base region is approximately 70 nm to 80 nm. The percentage concentration of germanium is shown on the first Y - axis 797 on a linear scale, while the phosphorus concentration (atoms / cm³) is shown on the second Y - axis 795 on a logarithmic scale. Although Figure 7 the DSIMS traces 702, 704, 706 in 19 may include signal noise and possible self - doping and / or indirect doping effects, etc., it can be seen that the exemplary phosphorus concentration profile 702 exhibits a substantially normal (Gaussian) distribution, with a narrow peak centered at 45 nm to 47.5 nm within the base region. In some examples, the concentration of the phosphorus peak may be in the range of about 1×10 19 atoms / cm³ to 5×10 18 atoms / cm³, but is not limited thereto. In some examples, depending on the embodiment, the peak concentration may exhibit an order - of - magnitude range, such as about 5×10 19 atoms / cm³ to 5×10

[0074] Although various examples of the present disclosure have been described above, the examples have been presented by way of example only and not limitation. Many changes may be made to the disclosed examples in light of the disclosure herein without departing from the spirit or scope of the present disclosure. Accordingly, the breadth and scope of the present disclosure should not be limited by any of the examples described above. Indeed, the scope of the present disclosure should be defined in accordance with the appended claims and their equivalents.

[0075] Additionally, in at least some additional or alternative embodiments, the functions / actions described in the blocks may not occur in the order shown in the flowcharts. For example, depending on the functionality / action involved, two blocks shown in succession may in fact be performed substantially concurrently or the blocks may sometimes be performed in the reverse order. Further, the functionality of a given block of a flowchart and / or block diagram may be split into multiple blocks, and / or the functionality of two or more blocks of a flowchart and / or block diagram may be at least partially integrated. Also, some blocks in the flowcharts may optionally be omitted. Additionally, although some of the figures contain arrows on communication paths to show the primary direction of communication, it should be understood that communication may occur in the direction opposite to the depicted arrows. Finally, other blocks may be added / inserted between the shown blocks.

[0076] The order or sequence of actions, steps, functions, components, or blocks shown in any of the flowcharts and / or block diagrams depicted in the figures of the present disclosure may be modified, changed, replaced, customized, or otherwise rearranged within a particular flowchart or block diagram, including deletion or omission of a particular action, step, function, component, or block. Additionally, the actions, steps, functions, components, or blocks shown in a particular flowchart may be intermixed with or otherwise arranged or rearranged with the actions, steps, functions, components, or blocks shown in another flowchart so as to effect additional changes, modifications, and configurations relative to one or more processes for the purpose of practicing the teachings of the present disclosure. Similarly, although various examples have been set forth herein, not all features of a particular example are necessarily limited thereto and / or required therefor.

[0077] At least some of the foregoing descriptions may include certain directional terms such as "upper", "lower", "top", "bottom", "left", "right", "front", "back", "vertical", "horizontal", etc., which may be used with reference to the orientation of some of the described figures or their illustrative elements. Since the components of some examples may be positioned in a number of different orientations, the directional terms are used for illustrative purposes and are in no way limiting. Similarly, references to features referred to as "first", "second", etc. do not denote any particular order, importance, etc., and such references may be interchanged depending on the context, embodiment, etc. Additionally, unless otherwise specifically noted, the features of the examples described herein may be combined with each other.

[0078] Although various embodiments have been shown and described in detail, the claims are not limited to any particular embodiment or example. The above detailed description should not be taken to imply that any particular component, element, step, action, or function is essential such that it must be included within the scope of the claims. In the case of reciting or describing a phrase such as "at least one of A and B" or a phrase of similar import, such a phrase should be understood to mean "only A, only B, or both A and B". References to singular elements are not intended to mean "one and only one" unless explicitly stated, but rather "one or more". In a similar manner, depending on the context, phrases such as "a plurality" or "multiple" may mean "one or more" or "at least one". All structural and functional equivalents of the elements of the embodiments described above are expressly incorporated herein by reference and are intended to be covered by the appended claims.

Claims

1. A method for manufacturing an integrated circuit IC, comprising: forming a first portion of a base region above a collector region of a heterojunction bipolar transistor HBT, the first portion being formed epitaxially at a first temperature; forming a second portion of the base region over the first portion, the second portion being epitaxially formed at a lower second temperature; and A third portion of the base region is formed over the second portion, the third portion being epitaxially formed at the first temperature. 2 . The method of claim 1 , further comprising forming the first portion and the third portion using a first type of silicon precursor and forming the second portion using a second, different type of silicon precursor.

3. The method of claim 2, wherein the first type of silicon precursor comprises dichlorosilane (DCS, SiCl2H2), and the second type of silicon precursor includes silane (SiH4).

4. The method of claim 1, further comprising applying hydrogen chloride (HCl) at a first flow rate while forming the second portion, and applying the HCl at one or more second flow rates higher than the first flow rate while forming the first portion and the third portion.

5. The method of claim 1, further comprising applying phosphine (PH3) as an n-type dopant precursor while forming the sub-portion of the second portion, the n-type dopant precursor being used to form the sub-portion at about 5×10 18 atoms / cm3 to 5×10 19 The sub-portion is in-situ doped at a peak concentration range of about 100 atoms / cm3.

6. The method of claim 1, further comprising applying germane (GeH4) as a germanium precursor while forming the first portion, the second portion, and the third portion of the base region.

7. The method of claim 1, wherein the third portion comprises a compound semiconductor, and the method further comprises: forming a top cap layer of the base region over the third portion, the top cap layer comprising an elemental semiconductor; and An emitter region is formed above the top cap layer.

8. The method of claim 1, further comprising doping the third portion, the second portion, and a sub-portion of the first portion immediately below the second portion, each with a substantially equal concentration of carbon.

9. An integrated circuit IC, comprising: Semiconductor substrate; and A heterojunction bipolar transistor comprises a collector region, a base region and an emitter region, wherein the collector region is formed in or above the semiconductor substrate, the base region is disposed between the collector region and the emitter region, the base region comprises a heteroepitaxial portion, the heteroepitaxial portion comprises a narrow band of an n-dopant region, the thickness of the narrow band being approximately one tenth of the thickness of the heteroepitaxial portion.

10. The IC of claim 9, wherein the heteroepitaxial portion comprises silicon germanium (SiGe), and the n-dopant region is doped with a peak concentration in the range of about 5×10 18 atoms / cm3 to 5×10 19 atoms / cubic centimeter of phosphorus.

11. The IC of claim 9, wherein the narrow band overlaps a valley of a germanium distribution profile in the heteroepitaxial portion.

12. The IC of claim 9, wherein the base region further comprises a top cap layer overlying the heteroepitaxial portion and beneath the emitter region, the top cap layer comprising an elemental semiconductor.

13. The IC of claim 12, wherein the top cap layer has a thickness of about 30 nanometers (nm).

14. The IC of claim 9, wherein the narrow strip has a thickness of about 5 nm.

15. A method for manufacturing an integrated circuit IC, comprising: forming a first portion of a base region over a collector region of a heterojunction bipolar transistor HBT, the first portion being epitaxially formed using a first type of silicon precursor; forming a second portion of the base region over the first portion, the second portion being epitaxially formed using a second, different type of silicon precursor; and A third portion of the base region is formed over the second portion, the third portion being epitaxially formed using a silicon precursor of the first type.

16. The method of claim 15, wherein the first portion and the third portion are formed at a first temperature, and the second portion is formed at a lower second temperature.

17. The method of claim 15, wherein the first type of silicon precursor comprises dichlorosilane (DCS, SiCl2H2), and the second type of silicon precursor includes silane (SiH4).

18. The method of claim 15, further comprising applying hydrogen chloride (HCl) at a first flow rate while forming the second portion, and applying the HCl at one or more second flow rates higher than the first flow rate while forming the first portion and the third portion.

19. The method of claim 15, further comprising applying phosphine (PH3) as an n-type dopant precursor while forming the sub-portion of the second portion, the n-type dopant precursor being used to form the sub-portion at about 5×10 18 atoms / cm3 to 5×10 19 The sub-portion is in-situ doped at a peak concentration range of about 100 atoms / cm3.

20. The method of claim 15, further comprising applying germane (GeH4) as a germanium precursor while forming the first portion, the second portion, and the third portion of the base region.

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