Electrostatic device

Abstract

The present disclosure relates to semiconductor structures, and more particularly to electrostatic devices and methods of manufacture. The structure includes a device having a collector region, an emitter region, and a base region; an oxidation structure in the base region; and an isolation structure adjoining the oxidized structure and extending between the base region and the emitter region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor structures, and more particularly to electrostatic devices and manufacturing methods. BACKGROUND OF THE DISCLOSURE

[0002] To more efficiently deliver power in electrical systems such as electric vehicles, the operating voltage has become increasingly high. Also, as the size of integrated circuits continues to shrink, they become more sensitive to electrostatic discharge. This use of high voltages and the continued scaling of devices require electrostatic discharge (ESD) protection devices to be able to withstand such high voltages and have sufficient robustness in a small footprint.

[0003] Traditionally, a method of stacking low-voltage ESD devices has been used to achieve high-voltage operating capabilities. However, this stacking method increases the footprint of the ESD device by the number of stacks. In addition, using multiple ESD devices results in an increase in on-resistance. SUMMARY OF THE DISCLOSURE

[0004] In one aspect of the present disclosure, a structure includes: a device having a collector region, an emitter region, and a base region; an oxidation structure within the base region; and an isolation structure adjacent to the oxidation structure and extending between the base region and the emitter region.

[0005] In one aspect of the present disclosure, a structure includes: a collector region including a P-drift region in a semiconductor substrate; an emitter region including a P+ diffusion region in an N-well and a shallow trench isolation structure adjacent to the P+ diffusion region; a base region located within an N-drift region in the semiconductor substrate; and a local oxidation within the base region that extends from the P-drift region and contacts the shallow trench isolation structure.

[0006] In one aspect of the present disclosure, a method includes: forming a device having a collector region, an emitter region, and a base region; forming an oxidation structure within the base region; and forming an isolation structure adjacent to the oxidation structure and extending between the base region and the emitter region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In the following detailed description, reference is made to the numerous drawings, which are described in a non-limiting example of an exemplary embodiment of the present disclosure.

[0008] Figure 1 Structures and corresponding manufacturing processes in accordance with aspects of the present disclosure are shown.

[0009] Figures 2-5 Additional structures and corresponding manufacturing processes in accordance with aspects of the present disclosure are shown.

[0010] Figure 6shows a process flow representing a manufacturing process for manufacturing Figures 1-5 the device. DETAILED DESCRIPTION

[0011] The present disclosure relates to semiconductor structures, and more particularly to electrostatic devices and manufacturing methods. More specifically, the present disclosure relates to high-voltage electrostatic discharge (ESD) protection devices. In an embodiment, the high-voltage ESD protection device includes a high-voltage PNP bipolar transistor having a shallow trench isolation structure adjacent to a raised oxide structure (i.e., a LOCOS structure) inside the base region. Advantageously, the high-voltage ESD protection device exhibits a small footprint, which can maintain high-voltage operation, and also exhibits a small on-resistance and an increased breakdown voltage at higher temperatures.

[0012] The electrostatic devices of the present disclosure can be manufactured in a variety of different ways using a variety of different tools. However, generally, methods and tools are used to form structures having micron and nanometer scale dimensions. Methods (i.e., techniques) for manufacturing the electrostatic devices of the present disclosure have been adopted in accordance with integrated circuit (IC) technology. For example, these structures are built on a wafer and realized in a material film patterned on top of the wafer by a photolithography process. Specifically, the manufacturing of the electrostatic devices uses three basic building blocks: (i) depositing a thin film of material on a substrate; (ii) applying a patterned mask on top of the film by photolithographic imaging; and (iii) selectively etching the film with respect to the mask. In addition, as is known in the art, a pre-cleaning process can be used to clean any contaminants on the etched surface. In addition, as is known in the art, a rapid thermal annealing process can be used to drive in dopants or material layers when necessary.

[0013] Figure 1 shows a structure and a corresponding manufacturing process according to aspects of the present disclosure. In an embodiment, the structure 10 can be a high-voltage PNP device having a local oxidation (LOCOS) 12 in the base region 14 adjacent to the shallow trench isolation structure 16. The shallow trench isolation structure is located between the base region 14 and the diffusion regions in the emitter region 18. In an embodiment, the PNP device can be a lateral device including an emitter region 18, a base region 14, and a collector region 20. Those skilled in the art should also understand that the structure 10 can be an NPN device by simply changing the N region and the P region to the P region and the N region, respectively.

[0014] More specifically, structure 10 includes a semiconductor substrate 22. In an embodiment, the semiconductor substrate 22 can be an epitaxially grown N-type semiconductor substrate. The semiconductor substrate 22 can be composed of any suitable material, including but not limited to Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. In an embodiment, the semiconductor substrate 22 can include any suitable crystal orientation (e.g., <100>, <110>, <111>, or <001> crystal orientation).

[0015] A buried isolation layer 24 can be formed in the semiconductor substrate 22. A drift region 26 can be formed in the semiconductor substrate 22, which extends to and contacts the buried isolation layer 24. The buried isolation layer 24 can be a P+ region, and the drift region 26 can be a P-type drift region. In an embodiment, the combination of the buried isolation layer 24 and the drift region 26 can be used to isolate, for example, the N+ drift regions 14a in the base region 14, the emitter 18, and the collector 20.

[0016] Figure 1 Also shown are a P well 28 formed in the P drift region 26 and a P+ region 30 (e.g., contact) formed in the P well 28. An N well 32 having an N+ region (e.g., contact) 34 can also be formed in the semiconductor substrate 22. In an embodiment, the N well 32 having the N+ region 34 can be isolated from the P drift region 26, the P well 28, and the P+ region 30 (e.g., contact) by a shallow trench isolation structure 36 formed in the semiconductor substrate 22. A P+ region (e.g., contact) 18a can be formed in the N well 38 within the drift region 14a. The shallow trench isolation structure 16 directly abuts (e.g., physically contacts) the LOCOS 12. The shallow trench isolation structure 16 can also isolate the P+ region (e.g., contact) 18a. In an embodiment, the shallow trench isolation structure 16 is located between the P+ diffusion region 18a in the emitter region 18 and the base region 14.

[0017] Polysilicon material 40 can be formed on the LOCOS 12. The polysilicon material 40 can be a p-type polysilicon material. In an embodiment, the polysilicon material is located in the collector region 20 and is electrically connected to the P+ region 30.

[0018] Those skilled in the art should understand that the emitter region 18 can include a P+ region 18a having a shallow trench isolation structure 16. Additionally, the base region 14 can include an N+ drift region 14a and an N well 30. The collector region 20 can include a polysilicon material 40, a P drift region 26, a P well 28, and a P+ region 30. In this way, the emitter region 18, the base region 14, and the collector region 20 form a PNP bipolar junction transistor.

[0019] The buried isolation layer 24, P drift region 26, P well 28, P+ regions (contacts) 18a, 30, drift region 14a, N well 32, N+ region (contact) 34, and N well 38 can be formed by a conventional ion implantation process. In a conventional ion implantation process, a dopant of a certain conductivity type at a certain concentration can be introduced into the semiconductor substrate 22.

[0020] For example, in a conventional ion implantation process, a corresponding patterned implantation mask can be used to define the selected regions to be exposed for implantation. The implantation mask for selecting the exposed regions for forming the p-type structure is stripped after implantation and before the implantation mask for forming the n-type structure of a different conductivity type (and vice versa). The implantation mask can include a photosensitive material layer, such as an organic photoresist layer, which is applied by a spin coating process, pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer. Each implantation mask has a thickness and a blocking ability sufficient to prevent the masked regions from receiving a certain dose of implanted ions. The p-type features, such as the buried isolation layer 24, P drift region 26, P well 28, and P+ regions 18a, 30 can be doped with a p-type dopant, such as boron (B); while the drift region 14a, N well 32, N+ region (contact) 34, and N well 38 can be doped with an n-type dopant, such as arsenic (As), phosphorus (P), and antimony (Sb), and other suitable examples.

[0021] The shallow trench isolation structures 16, 36 can be formed by conventional lithography, etching, and deposition methods known to those skilled in the art. For example, a resist formed over the semiconductor substrate 22 is exposed to energy (light) and developed with a conventional resist developer to form a pattern (opening). A pattern transfer to the semiconductor substrate 22 using an etching process with selective chemical action (e.g., reactive ion etching (RIE)) is performed to form one or more trenches in the semiconductor substrate 22. After removing the resist by a conventional oxygen ashing process or other known strippers, an insulator material (e.g., SiO2) can be deposited by any conventional deposition process (e.g., chemical vapor deposition (CVD) process). Any residual material on the surface of the semiconductor substrate 22 can be removed by a conventional chemical mechanical polishing (CMP) process.

[0022] The wiring structure 42 can be disposed to the emitter region 18, base region 14, and collector region 20. The wiring structure 42 can be formed by conventional lithography, etching, and deposition methods known in the art, and thus the present disclosure can be fully understood without further explanation. Those skilled in the art should also understand that the wiring structure 42 can be formed in an interlayer dielectric material (e.g., an oxide, a nitride, or a combination thereof).

[0023] Before forming the wiring structure 42, a silicide process may be performed to form silicide contacts on the polysilicon material 40, the N+ regions (e.g., contacts) 34, and the P+ regions (e.g., contacts) 18a, 30. The reference numerals depicting the polysilicon material 40, the N+ regions (e.g., contacts) 34, and the P+ regions 18a, 30 may also be used to identify the silicide contacts.

[0024] Those skilled in the art will understand that the silicide process begins with depositing a thin transition metal layer (e.g., nickel, cobalt, or titanium) over a fully formed semiconductor device (e.g., doped or ion implanted regions and polysilicon material 40). After depositing the material, the structure is heated to cause the transition metal to react with the exposed silicon (or other semiconductor materials as described herein) in the active regions of the semiconductor device (e.g., doped or ion implanted regions and polysilicon material 40) to form a low-resistance transition metal silicide. After the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device.

[0025] Figure 2 A structure according to another aspect of the present disclosure is shown. More specifically, Figure 2 Structure 10a shows Figure 1 on a p-type semiconductor substrate 44. The p-type semiconductor substrate 44 may be isolated from the semiconductor substrate 22 by a buried isolation layer 46. In an embodiment, the buried isolation layer 46 may be an N+ buried isolation layer. The buried isolation layer 46 may be formed by an ion implantation process or an in-situ doped epitaxial growth process. For the former configuration, the buried isolation layer 46 may be formed into the semiconductor substrate 44 by an ion implantation process. For the latter configuration, an epitaxial growth process may be used to grow both the buried isolation layer 46 and the semiconductor substrate 22 using the same semiconductor material, where the n-type dopant concentration of the buried isolation layer 46 is greater. The remaining features of structure 10a are similar to Figure 1 structure 10.

[0026] Examples of various epitaxial growth processes that may be employed in the present disclosure include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). The epitaxial growth process may be carried out using any known precursor gas or gas mixture (e.g., hydrogen, nitrogen, helium, and argon). Dopants (such as the n-type described herein) are typically added to the precursor gas or gas mixture. An annealing process may be performed to drive the dopants into the semiconductor substrate 22.

[0027] The p-type semiconductor substrate 44 can be a bulk processed substrate or a semiconductor-on-insulator (SOI) technology. In SOI technology, from top to bottom, a top semiconductor layer is disposed above a buried insulator layer, and the buried insulator layer is disposed above a processed substrate. The processed substrate and the top semiconductor layer can be semiconductor materials, such as Si, Ge, SiGe, SiC, SiGeC, group III-V compound semiconductors, group II-VI compound semiconductors, or any combination thereof. Generally, the processed substrate and the top semiconductor layer include single crystal semiconductor materials, such as single crystal silicon having any suitable crystal orientation (e.g., <100>, <110>, <111>, or <001> crystal orientation). The buried insulator layer can include dielectric materials, such as silicon dioxide, silicon nitride, silicon oxynitride, boron nitride, or a combination thereof. In one embodiment, the buried insulator layer can be a buried oxide layer (BOX).

[0028] Figure 3 A structure according to another aspect of the present disclosure is shown. More specifically, Figure 3 Structure 10b of shows a Figure 2 Structure 10a having a resistive element in the emitter region 18. More specifically, the resistive element includes an N+ region 48 in the N-well 38, and the N+ region 48 is separated from the P+ region 18a by an additional shallow trench isolation structure 16a. The N+ region 48 and the P+ region 18a in the N-well 38 are electrically connected together by a wiring structure 42. The remaining features of structure 10b are similar to those of Figure 2 Structure 10a in, and thus the present disclosure can be fully understood without further explanation.

[0029] Figure 4 Another structure according to another aspect of the present disclosure is shown. Figure 4 Structure 10c of includes a deep trench structure 50 and a deep trench isolation structure 52. The deep trench structure 50 and the deep trench isolation structure 52 can be formed by conventional lithography, etching, and deposition methods described herein, and thus the present disclosure can be fully understood without further explanation. In Figure 4 Structure 10c of, the N-well 32 and the N+ region 34 can be eliminated.

[0030] Both the deep trench structure 50 and the deep trench isolation structure 52 extend to the underlying p-type semiconductor substrate 44. In addition, the deep trench isolation structure 52 extends through the shallow trench isolation structure 36, adjacent to the p-type drift region 26 and in an embodiment contacts the p-type drift region 26. Thus, the buried isolation layer 24 and the deep trench isolation structure 52 can be used to isolate the emitter region 18, the collector region 20, and the base region 14.

[0031] In an embodiment, a deep trench structure 50 provides contact to a subset electrode region of a device. The deep trench structure 50 includes a sidewall liner 50a (e.g., SiO2) containing an insulator material that extends into the p-type semiconductor substrate 44 and a polysilicon material 50b (e.g., p-type polysilicon). The wiring structure 42 can be connected to the polysilicon material 50b (e.g., p-type polysilicon). The deep trench isolation structure 52 includes an insulator material (e.g., SiO2). The remaining features of the structure 10c are similar to Figure 3 the structure 10b, and thus the present disclosure can be fully understood without further explanation.

[0032] Figure 5 Another structure according to aspects of the present disclosure is shown. Figure 5 The structure 10d of includes a separate drift region 14a located in the base region 14. The drift region 14a is isolated using a separate buried isolation layer 24 (e.g., P+ buried isolation layer). The remaining features of the structure 10d are similar to Figure 4 the structure 10c, and thus the present disclosure can be fully understood without further explanation.

[0033] Figure 6 A process flow representing a manufacturing process for fabricating Figures 1-5 the device is shown. It should be understood that the steps of the process flow can be provided in an order different from the order provided herein, depending on the available tools and other design and process flow variables known in the art.

[0034] In step 100, a buried isolation layer 46 can be formed in the semiconductor substrate 44. In an embodiment, the buried isolation layer 46 can be formed by an ion implantation process, as already described for Figure 2 the same.

[0035] In step 105, semiconductor material 22 can be epitaxially grown on the semiconductor substrate 44 above the buried isolation layer 46. In an embodiment, the epitaxial growth of the semiconductor material 22 can include in-situ doping with an N-type dopant (e.g., arsenic).

[0036] In step 110, a buried isolation layer, diffusion regions, drift regions, and implantation regions 18a, 24, 26, 28, 30, 32, 34, 38, 48 can be formed using separate ion implantation processes and different masks, as described herein and known in the art, and thus the present disclosure can be fully understood without further explanation. In these processes, corresponding patterned implantation masks can be used to define the selected regions to be exposed for implantation. The implantation mask used to select the exposed region for forming a single feature is stripped after implantation and before the implantation mask for forming another feature, as known in the art.

[0037] In step 120, isolation structures 16, 16a, 36 are formed in semiconductor material 22. In an embodiment, the isolation structures 16, 16a, 36 can be shallow trench isolation structures formed by conventional lithography, etching, and deposition methods, as described hereinbefore.

[0038] In step 125, optional deep trench structures 50, 52 extending into semiconductor material 44 can be formed through semiconductor material 22. The deep trench structures 50, 52 can be formed by conventional lithography and etching processes and subsequent deposition of insulator material and polysilicon material using a conventional deposition process (e.g., CVD). The deep trench isolation structure 50 can include a step of lining the structure with oxide material 50a and subsequent anisotropic etching process to remove the insulator from the bottom of the trench. The remaining portion of the deep trench isolation structure can be filled with p-doped polysilicon material 50b using a conventional deposition method (e.g., CVD).

[0039] In step 130, a LOCOS 12 adjacent to and in direct contact with the shallow trench isolation structure 16 can be formed. In the LOCOS process, for example, a silicon oxide insulating structure penetrates beneath the surface of semiconductor substrate 22 such that the Si - SiO2 interface appears at a lower position than the rest of the silicon surface. The LOCOS process includes a thermal oxidation process at selected regions. In this process, oxygen penetrates deep into semiconductor substrate 22, reacts with silicon (or other semiconductor material) and converts it to, for example, silicon oxide. The LOCOS will extend partially beneath the surface and into semiconductor substrate 22 and partially above the surface of semiconductor substrate 22.

[0040] In step 135, polysilicon material 40 can be deposited on the LOCOS 12. The polysilicon material 40 can be epitaxially grown or deposited using a conventional deposition method (e.g., CVD process), followed by a conventional patterning process.

[0041] In step 140, a silicide contact can be formed using the conventional silicide process described herein. The silicide can be formed on any active region, e.g., diffusion regions and polysilicon materials.

[0042] In step 145, a wiring structure (e.g., a metal contact) 42 can be formed using conventional lithography, etching, and deposition processes. For example, as known in the art, the wiring structure 42 can be fabricated by forming vias in the interlayer dielectric material, then depositing a metal material (e.g., tungsten, aluminum, copper, etc.), and then performing a chemical mechanical polishing (CMP) process, so that the present disclosure can be fully understood without further explanation herein.

[0043] The structures described herein can be used in System-on-Chip (SOC) technology. An SoC is an integrated circuit (also referred to as a "chip") that integrates all components of an electronic system on a single chip or substrate. Since the components are integrated on a single substrate, an SoC consumes much less power and occupies much less area compared to a multi-chip design with equivalent functionality. Thus, SoCs are becoming a dominant force in mobile computing (e.g., in smartphones) and the edge computing market. SoCs are also used in embedded systems and the Internet of Things.

[0044] The above method is used for the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare die, or in packaged form. In the latter case, the chips are mounted in the form of single-chip packages (e.g., plastic carriers with leads fixed to a motherboard or other higher-level carrier) or multi-chip packages (e.g., ceramic carriers with one or both of surface interconnects or buried interconnects). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to high-end computer products with a display, keyboard, or other input device and a central processor.

[0045] The description of the various embodiments of the present disclosure has been given for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to a person of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, the practical application, or the technical improvement of technologies found in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: A device including a collector region, an emitter region and a base region; an oxide structure in the base region; as well as An isolation structure is adjacent to the oxide structure and extends between the base region and the emitter region.

2. The structure according to claim 1, wherein: The oxide structure includes a local oxidation (LOCOS) in the semiconductor substrate in the base region.

3. The structure according to claim 2, wherein: The oxide structure is a raised isolation structure located above a surface of the semiconductor substrate and extending below the surface of the semiconductor substrate.

4. The structure of claim 2, further comprising a polysilicon material located on the oxide structure.

5. The structure according to claim 4, wherein: The polysilicon material is electrically connected to a diffusion region in the collector region.

6. The structure according to claim 1, wherein: The oxide structure extends between diffusion regions in the collector region and contacts the isolation structure.

7. The structure according to claim 6, wherein: The diffusion region includes p-type dopants located in the P-well and P-drift regions.

8. The structure of claim 7, further comprising a P+ buried isolation layer in the semiconductor substrate, wherein The P drift region and the P+ buried isolation layer isolate the N+ drift region of the base region.

9. The structure according to claim 2, wherein: The isolation structure includes a shallow trench isolation structure extending within a first well of a first conductivity type and adjacent to a diffusion region of a second conductivity type within the first well.

10. The structure according to claim 9, wherein: The first conductivity type includes an n-type dopant, and the second conductivity type includes a p-type dopant.

11. The structure of claim 9 further comprising a resistive element comprising a diffusion region of the first conductivity type between the diffusion regions of the second conductivity type within the first well.

12. The structure according to claim 11, wherein: The diffusion region of the first conductivity type is isolated from the diffusion region of the second conductivity type by a shallow trench isolation structure.

13. The structure of claim 1 further comprising a deep trench isolation structure and a second deep trench isolation structure, wherein: The deep trench isolation structure includes an insulator liner material and a filled polysilicon material, the second deep trench isolation structure includes an insulator material, and the second deep trench isolation structure isolates the emitter region, the collector region, and the base region.

14. The structure according to claim 13, wherein: The polysilicon material includes P-doped polysilicon and extends to an underlying semiconductor substrate below the N+ buried layer.

15. A structure comprising: a collector region including a P drift region in a semiconductor substrate; an emitter region, comprising a P+ diffusion region in the N-well and a shallow trench isolation structure adjacent to the P+ diffusion region; A base region located in an N drift region in the semiconductor substrate; as well as A local oxidation in the base region extends from the P drift region and contacts the shallow trench isolation structure.

16. The structure according to claim 15, wherein: The local oxidation in the base region protrudes above a top surface of the semiconductor substrate and extends below the top surface of the semiconductor substrate.

17. The structure of claim 15, further comprising: P-doped polysilicon is located on the local oxidation and is electrically connected to a P+ diffusion region in the P drift region.

18. The structure of claim 15, further comprising: a first deep trench isolation structure that touches the P drift region and extends into an underlying substrate below a buried isolation layer; as well as A second deep trench isolation structure extends into the underlying substrate below the buried isolation layer, wherein the second deep trench isolation structure comprises an insulator liner and polysilicon material.

19. The structure of claim 15, further comprising: The resistor element includes an N+ diffusion region located in the N well and isolated from the P+ diffusion region by a shallow trench isolation structure in the N well.

20. A method comprising: forming a device including a collector region, an emitter region, and a base region; forming an oxide structure in the base region; as well as An isolation structure is formed adjacent to the oxide structure and extending between the base region and the emitter region.

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