Epitaxial structure, semiconductor device and manufacturing method thereof

Abstract

The invention provides an epitaxial structure, a semiconductor device and a manufacturing method thereof, and the epitaxial structure comprises a Ga2O3 substrate; the epitaxial laminated layer is arranged on the Ga2O3 substrate, the epitaxial laminated layer at least comprises a first insulating isolation layer, a GaN channel layer, a barrier layer, a second insulating isolation layer, an N-type semiconductor layer, an active region and a P-type semiconductor layer which are sequentially laminated on the Ga2O3 substrate from bottom to top, and the epitaxial structure is integrated with various wide bandgap semiconductor materials in a monolithic manner, the Ga2O3 substrate can be used for forming an optical detector, the GaN channel layer and the barrier layer can be used for forming a transistor, and the N-type semiconductor layer, the active region and the P-type semiconductor layer can be used for forming a light emitting diode so as to be used for manufacturing a semiconductor device capable of visually monitoring ultraviolet light in real time, and detection information can be fed back without an additional electric signal processing system. And the miniaturization requirement of the solar blind ultraviolet detector can be met.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device fabrication, and more specifically, relates to an epitaxial structure, a semiconductor device, and a method for fabricating the same. Background Art

[0002] The solar-blind ultraviolet detector (UV-PD) has the advantages of high signal-to-noise ratio and low false alarm rate, and has currently been widely used in civil and defense fields such as fire warning, ozone monitoring, high-voltage corona detection, missile identification and tracking, shipborne communication, and deep space exploration for the requirements of ultra-long distance and ultra-high precision. Commercial UV-PDs mainly include silicon (Si)-based charge-coupled devices (CCDs), complementary metal-oxide-semiconductor (CMOS) devices, and photomultiplier tubes (PMTs). Such devices require a filter to exclude visible light interference during operation, and the PMT requires a voltage of up to several kilovolts to obtain high gain, thereby increasing the volume and energy consumption of the detection system. The ultra-wide bandgap semiconductor gallium oxide (Ga2O3) material, with a bandgap as high as 4.9 eV and an extremely high optical absorption coefficient, is a very promising candidate for fabricating high-sensitivity and high-quantum-efficiency UV-PDs. Currently, Ga2O3 UV-PDs have demonstrated excellent imaging capabilities and will be applied in fields such as medical drug imaging, cosmic celestial body observation, and daily ultraviolet protection.

[0003] However, the existing Ga2O3 solar-blind ultraviolet detectors consist of a PD chip and an electrical signal processing system. The current generated by the PD chip after detecting ultraviolet light needs to pass through the electrical signal processing module to feedback the detection information, which is not suitable for intuitive real-time monitoring scenarios and the miniaturization requirements of detectors. Summary of the Invention

[0004] In view of this, the present invention provides an epitaxial structure, a semiconductor device, and a method for fabricating the same to solve the problem that the existing gallium oxide solar-blind ultraviolet detector needs to be equipped with an electrical signal processing system to feedback the detection information, which is not suitable for intuitive real-time monitoring scenarios and the miniaturization requirements of detectors.

[0005] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0006] An epitaxial structure, characterized in that the epitaxial structure includes:

[0007] A Ga2O3 substrate;

[0008] An epitaxial stack disposed on the Ga2O3 substrate, the epitaxial stack at least including: a first insulating isolation layer, a GaN channel layer, a barrier layer, a second insulating isolation layer, an N-type semiconductor layer, an active region, and a P-type semiconductor layer that are sequentially stacked on the Ga2O3 substrate from bottom to top.

[0009] Preferably, the epitaxial stack is obtained by a single epitaxy on the Ga2O3 substrate, and the lattice constant of the first insulating isolation layer is between the lattice constants of the Ga2O3 substrate and the GaN channel layer.

[0010] Preferably, the lattice constant of the second insulating isolation layer is between the lattice constants of the barrier layer and the N-type semiconductor layer.

[0011] Preferably, both the first insulating isolation layer and the second insulating isolation layer include nitride high-resistance materials.

[0012] Preferably, the epitaxial stack further includes a nucleation layer and a buffer layer that are located between the Ga2O3 substrate and the first insulating isolation layer and are sequentially stacked in the direction toward the first insulating isolation layer.

[0013] The present invention also provides a semiconductor device, which includes:

[0014] The epitaxial structure described in any one of the above;

[0015] Wherein, one side of the Ga2O3 substrate facing the epitaxial stack has an exposed first mesa, one side of the barrier layer facing away from the GaN channel layer has an exposed second mesa, one side of the N-type semiconductor layer facing away from the second insulating isolation layer has an exposed third mesa, and one side of the P-type semiconductor layer facing away from the active region is a fourth mesa;

[0016] A first group of electrode structures, which are located on the first mesa and form a photodetector with the Ga2O3 substrate;

[0017] A second group of electrode structures, which are located on the second mesa and form a transistor with the GaN channel layer and the barrier layer;

[0018] A third group of electrode structures, which are located on the third mesa and the fourth mesa and form a light-emitting diode with the N-type semiconductor layer, the active region, and the P-type semiconductor layer;

[0019] Wherein, the photodetector, the transistor, and the light-emitting diode are sequentially connected in series, and the first group of electrode structures, the second group of electrode structures, and the third group of electrode structures are all insulated from the sidewalls of the epitaxial stack.

[0020] Preferably, the first group of electrode structures is a PD electrode;

[0021] The second group of electrode structures includes: a drain electrode, a source electrode, and a gate electrode. The drain electrode and the source electrode both form ohmic contacts with the barrier layer, and the gate electrode forms a Schottky contact with the barrier layer;

[0022] The third group of electrode structures includes: an N electrode located on the third mesa and a P electrode located on the fourth mesa.

[0023] Preferably, the semiconductor device further includes a passivation layer that covers the exposed surface of the epitaxial stack.

[0024] Preferably, the passivation layer also covers the exposed surfaces of the second group of electrode structures and the third group of electrode structures, and exposes the first group of electrode structures. The passivation layer includes a first via hole, a second via hole, a third via hole, a fourth via hole, and a fifth via hole that penetrate through the passivation layer;

[0025] Moreover, the semiconductor device further includes: a first pad, a second pad, a third pad, a fourth pad, a fifth pad, and a sixth pad located on a side of the passivation layer away from the Ga2O3 substrate;

[0026] Wherein, the first pad is connected to the drain by being embedded in the first via hole; the second pad is connected to the P electrode by being embedded in the second via hole; the third pad is connected to the N electrode by being embedded in the third via hole; the fourth pad is connected to the gate by being embedded in the fourth via hole; the fifth pad is connected to the source by being embedded in the fifth via hole; the sixth pad is connected to the PD electrode by extending to the sidewall of the passivation layer.

[0027] The present invention also provides a method for manufacturing a semiconductor device, including:

[0028] Step 1, manufacturing an epitaxial structure;

[0029] Specifically, providing a Ga2O3 substrate, and forming an epitaxial stack on the Ga2O3 substrate through a single epitaxial process. The epitaxial stack at least includes a first insulating isolation layer, a GaN channel layer, a barrier layer, a second insulating isolation layer, an N-type semiconductor layer, an active region, and a P-type semiconductor layer that are sequentially stacked along the growth direction;

[0030] Step 2, etching the epitaxial stack and preparing a first group of electrode structures, a second group of electrode structures, and a third group of electrodes to form a semiconductor device;

[0031] Specifically, through an etching process, a bare first mesa is formed on the side of the Ga2O3 substrate facing the epitaxial stack, a bare second mesa is formed on the side of the barrier layer facing away from the GaN channel layer, a bare third mesa is formed on the side of the N-type semiconductor layer facing away from the second insulating isolation layer, and the side of the P-type semiconductor layer facing away from the active region is a fourth mesa; and a first set of electrode structures is fabricated on the first mesa, which forms a photodetector with the Ga2O3 substrate; a second set of electrode structures is fabricated on the second mesa, which forms a transistor with the GaN channel layer and the barrier layer; a third set of electrode structures is fabricated on the third mesa and the fourth mesa, which forms a light-emitting diode with the N-type semiconductor layer, the active region, and the P-type semiconductor layer;

[0032] Wherein, the photodetector, the transistor, and the light-emitting diode are electrically connected in series in sequence, and the first set of electrode structures, the second set of electrode structures, and the third set of electrode structures are all insulated from the sidewalls of the epitaxial stack.

[0033] Through the above technical solution, the following effects can be achieved:

[0034] An epitaxial structure provided by the present invention includes: a Ga2O3 substrate; an epitaxial stack disposed on the Ga2O3 substrate, and the epitaxial stack at least includes: a first insulating isolation layer, a GaN channel layer, a barrier layer, a second insulating isolation layer, an N-type semiconductor layer, an active region, and a P-type semiconductor layer that are sequentially stacked from bottom to top on the Ga2O3 substrate. This epitaxial structure monolithically integrates multiple wide-bandgap semiconductor materials. Among them, the Ga2O3 substrate can be used to form a photodetector, the GaN channel layer and the barrier layer can be used to form a transistor, and the N-type semiconductor layer, the active region, and the P-type semiconductor layer can be used to form a light-emitting diode, so as to be used to fabricate a semiconductor device that realizes the function of visually and real-time monitoring ultraviolet light, can feedback detection information without equipping an additional electrical signal processing system, and can meet the miniaturization requirements of a solar-blind ultraviolet detector.

[0035] Furthermore, an epitaxial stack can be obtained by a single epitaxy on a Ga2O3 substrate. The Ga2O3 semiconductor material has a wide bandgap characteristic (bandgap width ~ 4.8 eV), excellent thermal stability, and chemical inertness, making it suitable for high-temperature epitaxial growth environments. A first insulating isolation layer is formed on the Ga2O3 substrate. The first insulating isolation layer uses its high insulation and thermal matching with the Ga2O3 substrate to isolate the Ga2O3 substrate from subsequent functional layers, reducing leakage current. Moreover, the lattice constant of the first insulating isolation layer is between the lattice constants of the Ga2O3 substrate and the GaN channel layer, enabling the first insulating isolation layer to effectively alleviate the lattice mismatch between the Ga2O3 substrate and the GaN channel layer, reducing the dislocation density and providing a high-quality template for subsequent multi-layer growth. By utilizing the lattice adaptation and thermal matching characteristics of the Ga2O3 substrate and the epitaxial functional layers, an epitaxial stack can be directly obtained by a single epitaxy. Also, integrating multiple wide-bandgap semiconductor materials by a single epitaxy method can simplify the material preparation process and lay a foundation for the monolithic integration of different wide-bandgap semiconductor devices.

[0036] Furthermore, the lattice constant of the second insulating isolation layer is set to be between the lattice constants of the barrier layer and the N-type semiconductor layer. The second insulating isolation layer can effectively alleviate the lattice mismatch between the barrier layer and the N-type semiconductor layer, thereby improving the crystal quality of the epitaxial stack.

[0037] Furthermore, both the first insulating isolation layer and the second insulating isolation layer are set to include a nitride high-resistance material. The nitride high-resistance material has high lattice matching flexibility, making it more convenient to adjust the lattice constant of the nitride high-resistance material to achieve lattice transition and reduce mismatch. Moreover, the thermal expansion coefficient of the nitride high-resistance material is close to that of III-V (wide-bandgap) materials, which can reduce cracks caused by thermal stress. Additionally, the nitride high-resistance material has high chemical stability, and at high temperatures, the nitride can inhibit the diffusion reaction between the functional layers on both sides of the nitride high-resistance material.

[0038] A semiconductor device provided by the present invention adopts the epitaxial structure of any one of the above, wherein the first group of electrode structures and the Ga2O3 substrate form a photodetector, the second group of electrode structures and the GaN channel layer and the barrier layer form a transistor, and the third group of electrode structures and the N-type semiconductor layer, the active region and the P-type semiconductor layer form a light-emitting diode. The photodetector, the transistor and the light-emitting diode are sequentially connected in series. The semiconductor device integrates the photodetector, the transistor and the light-emitting diode in the same module in a vertically stacked manner in sequence, which can meet the miniaturization requirement of the solar-blind ultraviolet detector. Moreover, the wide bandgap of the Ga2O3 substrate corresponds to the absorption of the solar-blind ultraviolet band (240-280nm) so that the photodetector can receive ultraviolet light signals; the GaN channel layer and the barrier layer are used as the core structure of the transistor. At the heterojunction interface between the GaN channel layer and the barrier layer, due to the polarization effect and the band offset, electrons are confined in the nanoscale thin layer to form a two-dimensional electron gas (2DEG) with high concentration and high mobility to achieve photocurrent amplification; the N-type semiconductor layer and the P-type semiconductor layer respectively realize carrier regulation through N-type doping and P-type doping, and recombination luminescence occurs in the active region to make the light-emitting diode emit visible light. After the semiconductor device is connected to the working power supply, after the photodetector receives the ultraviolet light signal, the photodetector exerts the advantages of the Ga2O3 material in ultraviolet detection to receive ultraviolet light and generate a photocurrent. Under the action of the electric field, the photocurrent flows from the photodetector into the transistor. After the transistor amplifies the photocurrent, it drives the light-emitting diode to emit visible light, realizing the function of intuitively and real-time monitoring ultraviolet light, and has broad application prospects in monitoring corona, fire occurrence, and full-duplex indoor optical communication scenarios.

[0039] In addition, the GaN channel layer and the barrier layer are arranged between the first insulating isolation layer and the second insulating isolation layer. This structural design can effectively suppress the hot electron emission effect of the transistor, significantly reduce the generation of leakage current, and will not cause adverse effects on the photodetector and the light-emitting diode; at the same time, this design enhances the breakdown voltage performance of the device under high voltage and reduces the breakdown risk.

[0040] In addition, the setting of the first insulating isolation layer can improve the crystal quality of the transistor, and the setting of the second insulating isolation layer can improve the crystal quality of the light-emitting diode, thereby improving the overall performance of the semiconductor device.

[0041] A manufacturing method of a semiconductor device provided by the present invention, while achieving the beneficial effects of the above semiconductor device, adopts an epitaxial method to integrate a variety of wide bandgap semiconductor materials, simplifies the material preparation process to realize the monolithic integration preparation of different wide bandgap semiconductor devices on the same substrate. The preparation method is applicable to the device preparation process of traditional integrated circuits, is simple and convenient to manufacture, is convenient for industrial production, and does not increase the additional device preparation cost. Description of the Drawings

[0042] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0043] Figure 1 Schematic structural diagram of an epitaxial structure provided by an embodiment of the present invention;

[0044] Figure 2 Schematic structural diagram of another epitaxial structure provided by an embodiment of the present invention;

[0045] Figure 3 Schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0046] Figure 4 Schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0047] Figure 5 Schematic structural diagram of yet another semiconductor device provided by an embodiment of the present invention;

[0048] Figure 6 Schematic structural diagram of still another semiconductor device provided by an embodiment of the present invention;

[0049] Figure 7 For Figure 6 Top view schematic diagram;

[0050] Figure 8 Schematic structural diagram of still another semiconductor device provided by an embodiment of the present invention;

[0051] Figure 9 Flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention;

[0052] Figures 10 to 15 For Figure 9 Process cross-sectional diagrams corresponding to the steps of the manufacturing method shown.

[0053] Symbol description in the figure:

[0054] A, first group of electrode structures; B, second group of electrode structures; C, third group of electrode structures; P6, sixth pad; P7, first integrated pad; P8, second integrated pad; K1, first via; K2, second via; K3, third via; K4, fourth via; K5, fifth via; M1, first mesa; M2, second mesa; M3, third mesa; M4, fourth mesa; P1, first pad; P2, second pad; P3, third pad; P4, fourth pad; P5, fifth pad;

[0055] 1. Ga2O3 substrate; 2. First insulating isolation layer; 3. GaN channel layer; 4. Barrier layer; 5. Second insulating isolation layer; 6. N-type semiconductor; 7. Active region; 8. P-type semiconductor; 9. PD electrode; 10. Drain electrode; 11. Source electrode; 12. Gate electrode; 13. N electrode; 14. P electrode; 15. Nucleation layer; 16. Buffer layer; 17. Passivation layer; 18. Metal reflection layer; 20. First external metal connection line; 21. Second external metal connection line; 30. First internal metal connection line; 31. Second internal metal connection line. Detailed implementation manners

[0056] For a clearer understanding of the content of the present invention, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.

[0057] In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application may be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the connotation of the present application. Therefore, the present application is not limited by the specific embodiments disclosed below.

[0058] Secondly, the present application will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present application in detail, for the convenience of explanation, the cross-sectional views showing the device structure will be enlarged locally out of the general scale, and the schematic diagrams are only examples and should not limit the protection scope of the present application herein. In addition, in actual production, three-dimensional spatial dimensions including length, width, and depth should be included.

[0059] In view of this, an epitaxial structure provided by an embodiment of the present application is as Figure 1 shown, and the epitaxial structure includes:

[0060] Ga2O3 substrate 1;

[0061] An epitaxial stack disposed on the Ga2O3 substrate 1, and the epitaxial stack at least includes: a first insulating isolation layer 2, a GaN channel layer 3, a barrier layer 4, a second insulating isolation layer 5, an N-type semiconductor 6 layer, an active region 7, and a P-type semiconductor 8 layer that are sequentially stacked on the Ga2O3 substrate 1 from bottom to top.

[0062] Optionally, in some embodiments, the Ga2O3 substrate 1 includes a β-Ga2O3 substrate.

[0063] Optionally, in some embodiments, an epitaxial stack is obtained by a single epitaxy on the Ga2O3 substrate 1, and the lattice constant of the first insulating isolation layer 2 is between the lattice constants of the Ga2O3 substrate 1 and the GaN channel layer 3.

[0064] Optionally, in some embodiments, the lattice constant of the second insulating isolation layer 5 is between the lattice constants of the barrier layer 4 and the N-type semiconductor layer 6.

[0065] Optionally, in some embodiments, both the first insulating isolation layer 2 and the second insulating isolation layer 6 include nitride high-resistance materials.

[0066] Optionally, in some embodiments, both the first insulating isolation layer 2 and the second insulating isolation layer 5 include, but are not limited to, a single nitride layer, or different combined structures of multiple nitride layers.

[0067] Optionally, in some embodiments, both the first insulating isolation layer 2 and the second insulating isolation layer 5 include, but are not limited to, a single AlN layer, a single C-doped GaN layer, a single Fe-doped InGaN layer, an AlN / GaN superlattice structure, an AlN / AlGaN superlattice structure, or multiple AlGaN layers with different Al components.

[0068] Optionally, in some embodiments, the thickness ranges of both the first insulating isolation layer 2 and the second insulating isolation layer 5 are 0.02 μm - 3 μm, including the end values. Exemplarily, the thickness of the first insulating isolation layer 2 is 0.02 μm or 1 μm or 2 μm or 3 μm, and the thickness of the second insulating isolation layer 5 is 0.02 μm or 1 μm or 2 μm or 3 μm.

[0069] It should be noted that the specific materials and thicknesses of the first insulating isolation layer 2 and the second insulating isolation layer 5 are not limited in this embodiment. The materials and thicknesses of the first insulating isolation layer 2 and the second insulating isolation layer 5 can be the same or different. In an optional embodiment of the present application, the first insulating isolation layer 2 can be a C-doped GaN high-resistance layer, and the thickness of the C-doped GaN high-resistance layer can be 2 μm. The second insulating isolation layer 5 can be an Fe-doped GaN high-resistance layer, and the thickness of the Fe-doped GaN high-resistance layer can be 1 μm.

[0070] Optionally, in some embodiments, the thickness range of the GaN channel layer 3 is 10 nm - 1500 nm, including the end values. Exemplarily, the thickness of the GaN channel layer 3 is 10 nm or 100 nm or 200 nm or 300 nm or 1500 nm.

[0071] Optionally, in some embodiments, the barrier layer 4 includes, but is not limited to, one or more of an AlN layer, an AlGaN layer, an InAlGaN layer, an InAlN layer, and an AlN / GaN superlattice structure.

[0072] Optionally, in some embodiments, the thickness of the barrier layer 4 ranges from 2 nm to 40 nm, including the end values. Exemplarily, the thickness of the barrier layer 4 is 2 nm or 20 nm or 40 nm.

[0073] Optionally, in some embodiments, the thickness of the N-type semiconductor 6 layer ranges from 0.5 μm to 4 μm, including the end values. Exemplarily, the thickness of the N-type semiconductor 6 layer is 0.5 μm or 2 μm or 4 μm.

[0074] Optionally, in some embodiments, the thickness of the P-type semiconductor 8 layer ranges from 20 nm to 300 nm, including the end values. Exemplarily, the thickness of the P-type semiconductor 8 layer is 20 nm or 50 nm or 100 nm or 200 nm or 300 nm.

[0075] Optionally, in some embodiments, the active region 7 is a periodic structure composed of well layers and barrier layers. The thickness of the active region 7 ranges from 10 nm to 200 nm, including the end values. Exemplarily, the thickness of the active region 7 is 10 nm or 50 nm or 100 nm or 200 nm.

[0076] It should be noted that the specific materials of the N-type semiconductor 6 layer and the P-type semiconductor 8 layer are not limited in this embodiment. In an alternative embodiment of the present application, the N-type semiconductor 6 layer can be an N-type GaN layer, the P-type semiconductor 8 layer can be a P-type GaN layer, and the active region 7 can be an InGaN / GaN multi-quantum well layer.

[0077] Optionally, in some embodiments, as Figure 2 shown, the epitaxial stack further includes a nucleation layer 15 and a buffer layer 16 that are located between the Ga2O3 substrate 1 and the first insulating isolation layer 2 and are stacked in sequence toward the first insulating isolation layer 2, for lattice transition and effective stress reduction, which can further improve the crystal quality of the epitaxial stack.

[0078] Optionally, in some embodiments, the nucleation layer 15 includes, but is not limited to, one or more of an AlN layer, a GaN layer, and an AlGaN layer.

[0079] Optionally, in some embodiments, the thickness of the nucleation layer 15 ranges from 5 nm to 500 nm, including the end values. Exemplarily, the thickness of the nucleation layer 15 is 5 nm or 200 nm or 500 nm.

[0080] The embodiments of the present application provide a semiconductor device, as Figure 3As shown, the semiconductor device includes:

[0081] An epitaxial structure according to any one of the above;

[0082] Wherein, one side of the Ga2O3 substrate 1 facing the epitaxial stack has an exposed first mesa M1, one side of the barrier layer 4 facing away from the GaN channel layer 3 has an exposed second mesa M2, one side of the N-type semiconductor 6 layer facing away from the second insulating isolation layer 5 has an exposed third mesa M3, and one side of the P-type semiconductor 8 layer facing away from the active region 7 is a fourth mesa M4;

[0083] A first group of electrode structures A, which is located on the first mesa M1 and forms a photodetector with the Ga2O3 substrate 1;

[0084] A second group of electrode structures B, which is located on the second mesa M2 and forms a transistor with the GaN channel layer 3 and the barrier layer 4;

[0085] A third group of electrode structures C, which is located on the third mesa M3 and the fourth mesa M4 and forms a light-emitting diode with the N-type semiconductor 6 layer, the active region 7 and the P-type semiconductor 8 layer;

[0086] Wherein, the photodetector, the transistor and the light-emitting diode are sequentially connected in series electrically, and the first group of electrode structures A, the second group of electrode structures B and the third group of electrode structures C are all insulated from the side walls of the epitaxial stack.

[0087] Optionally, in some embodiments, the transistor includes a high electron mobility transistor (HEMT).

[0088] Optionally, in some embodiments, the first group of electrode structures A is a PD electrode 9;

[0089] The second group of electrode structures B includes: a drain 10, a source 11 and a gate 12. The drain 10 and the source 11 both form ohmic contacts with the barrier layer 4, and the gate 12 forms a Schottky contact with the barrier layer 4;

[0090] The third group of electrode structures C includes: an N electrode 13 located on the third mesa M3 and a P electrode 14 located on the fourth mesa M4.

[0091] It should be noted that after the semiconductor device in this embodiment is connected to the working power supply, the photocurrent flows into the source 11 of the transistor from the PD electrode 9 of the photodetector, then flows out from the drain 10 of the transistor, and then flows into the P electrode 14 of the light-emitting diode, and then flows out from the N electrode 13 of the light-emitting diode.

[0092] It should also be noted that the drain 10, the source 11 and the gate 12 are spaced apart from each other; the N electrode 13 and the P electrode 14 are spaced apart from each other.

[0093] Optionally, in this embodiment, the PD electrode 9 includes, but is not limited to, an interdigital electrode, which is composed of alternately arranged finger-shaped metal electrodes, forming a dense electrode pair, which can improve the carrier collection efficiency. A parallel electric field is formed between adjacent finger-shaped electrodes, making the electric field distribution more uniform, thereby improving the performance of the photodetector.

[0094] Optionally, in this embodiment, the drain 10 and the source 11 are located on both sides of the gate 12, and the gate 12 is used to control the current to achieve field effect modulation.

[0095] Optionally, in some embodiments, the drain 10 is arranged on the side close to the P electrode to facilitate the subsequent connection between the drain 10 and the P electrode.

[0096] Optionally, in some embodiments, the second insulating isolation layer 5 and the light-emitting diode can be located between the source 11 and the gate 12 (not shown in the figure). The second insulating isolation layer 5 can improve the dielectric withstand ability between the source 11 and the gate 12, thereby improving the breakdown voltage withstand ability of the HEMT.

[0097] Optionally, in some embodiments, refer to Figure 3 As shown, the second insulating isolation layer 5 and the light-emitting diode can be located between the drain 10 and the gate 12. The second insulating isolation layer 5 can improve the dielectric withstand ability between the drain 10 and the gate 12, thereby improving the breakdown voltage withstand ability of the HEMT. Moreover, the gate 12 is arranged close to the source 11 to reduce the field effect modulation delay.

[0098] Optionally, in some embodiments, the epitaxial structure adopted by the semiconductor device includes: an epitaxial stack obtained by a single epitaxy on the Ga2O3 substrate 1. The epitaxial stack obtained by a single epitaxy can integrate the photodetector, the transistor, and the light-emitting diode in a vertically stacked manner in the same module by epitaxy.

[0099] Optionally, in some embodiments, the PD electrode 9 includes one or more metal stacks of, but is not limited to, a Ti layer and an Au layer. Among them, the thickness of the Ti layer can be 20 nm, and the thickness of the Au layer can be 120 nm.

[0100] Optionally, in some embodiments, the gate 12 includes one or more metal stacks of, but is not limited to, a Ni layer and an Au layer. Among them, the thickness of the Ni layer can be 60 nm, and the thickness of the Au layer can be 100 nm.

[0101] Optionally, in some embodiments, the source 11 includes one or more metal stacks of, but is not limited to, a Ti layer, an Al layer, a Ni layer, and an Au layer. Among them, the thickness of the Ti layer can be 20 nm, the thickness of the Al layer can be 120 nm, the thickness of the Ni layer can be 40 nm, and the thickness of the Au layer can be 50 nm.

[0102] Optionally, in some embodiments, the drain 10 includes, but is not limited to, one or more metal stacks of a Ti layer, an Al layer, a Ni layer, and an Au layer. Among them, the thickness of the Ti layer can be 20 nm, the thickness of the Al layer can be 120 nm, the thickness of the Ni layer can be 40 nm, and the thickness of the Au layer can be 50 nm.

[0103] Optionally, in some embodiments, electrical connection can be achieved between the photodetector and the transistor, and between the transistor and the light-emitting diode, by means of external bonding wires.

[0104] Specifically, referring to Figure 3 As shown, the PD electrode 9 of the photodetector can be electrically connected to the source 11 of the transistor through the first external metal connection line 20, and the drain 10 of the transistor can be electrically connected to the P electrode 14 of the light-emitting diode through the second external metal connection line 21.

[0105] Optionally, in some embodiments, as Figure 4 shown, the semiconductor device further includes a passivation layer 17 that covers the exposed surface of the epitaxial stack.

[0106] It should be noted that in this embodiment, the first group of electrode structures A, the second group of electrode structures B, and the third group of electrode structures C are insulated from the sidewalls of the epitaxial stack by the passivation layer 17, and the material of the passivation layer 17 can be silicon oxide, silicon nitride, or other materials with a passivation effect, which is not limited in the embodiments of the present application.

[0107] Optionally, in some embodiments, between the photodetector and the transistor, and between the transistor and the light-emitting diode, metal connection lines can also be directly provided on the semiconductor device by means of an intervening passivation layer to achieve electrical connection without the need to additionally increase external bonding wires.

[0108] Specifically, referring to Figure 4 As shown, the PD electrode 9 of the photodetector can be electrically connected to the source 11 of the transistor through the first internal metal connection line 30, and the drain 10 of the transistor can be electrically connected to the P electrode 14 of the light-emitting diode through the second internal metal connection line 31.

[0109] Optionally, in some embodiments, as Figure 5 shown, the passivation layer 17 also covers the exposed surfaces of the second group of electrode structures B and the third group of electrode structures C, and exposes the first group of electrode structures A. The passivation layer 17 includes a first through-hole K1, a second through-hole K2, a third through-hole K3, a fourth through-hole K4, and a fifth through-hole K5 (not shown in the figure) that penetrate the passivation layer 17;

[0110] Moreover, the semiconductor device further includes: a first pad P1, a second pad P2, a third pad P3, a fourth pad P4, a fifth pad P5, and a sixth pad P6 located on the side of the passivation layer 17 away from the Ga2O3 substrate 1;

[0111] Wherein, the first pad P1 is connected to the drain 10 by being embedded in the first through hole K1; the second pad P2 is connected to the P electrode 14 by being embedded in the second through hole K2; the third pad P3 is connected to the N electrode 13 by being embedded in the third through hole K3; the fourth pad P4 is connected to the gate 12 by being embedded in the fourth through hole K4; the fifth pad P5 is connected to the source 11 by being embedded in the fifth through hole K5; the sixth pad P6 is connected to the PD electrode 9 by extending to the side wall of the passivation layer 17.

[0112] It should be noted that in this embodiment, the first group of electrode structures A is exposed to avoid the influence of the existence of the passivation layer 17 on the photoelectric reception of the photodetector.

[0113] It should also be noted that the materials of the first pad P1, the second pad P2, the third pad P3, the fourth pad P4, the fifth pad P5, and the sixth pad P6 include but are not limited to one or more metal stacks of Al, Cu, Au, TiN, Ti, Pt, Cr, Ni, Pd, which are not limited in the embodiments of the present application. In an alternative embodiment of the present application, the materials of the first pad P1, the second pad P2, the third pad P3, the fourth pad P4, the fifth pad P5, and the sixth pad P6 can be Al. The specific thickness of the passivation layer 17 is not limited in this embodiment. In an alternative embodiment of the present application, the thickness of the passivation layer 17 can be 2 μm.

[0114] Optionally, in some embodiments, the surfaces of the first pad P1, the second pad P2, the third pad P3, the fourth pad P4, the fifth pad P5, and the sixth pad P6 away from the passivation layer 17 are all at the same horizontal height, which can reduce welding defects and avoid device tilting or suspension, so as to improve the device stability.

[0115] Optionally, in some embodiments, as Figure 6 and Figure 7 shown, the first pad P1 and the second pad P2 are an integrally formed first integrated pad P7; the fifth pad P5 and the sixth pad P6 are an integrally formed second integrated pad P8.

[0116] It should be noted that in this embodiment, the photodetector and the transistor are electrically connected through the integrally formed first integrated pad P7, and the transistor and the light-emitting diode are electrically connected through the integrally formed second integrated pad P8, which can reduce the number of pads, so as to reduce the process cost, wiring complexity, and risk of welding defects, improve the connection reliability, and can also save layout space to meet the requirements of device miniaturization.

[0117] Optionally, in some embodiments, referring to Figure 6 as shown, an epitaxial stack having a nucleation layer 15 and a buffer layer 16 can be adopted to further improve the overall performance of the semiconductor device.

[0118] To improve the light extraction efficiency of the semiconductor device to be applicable to scenarios with high brightness requirements, in an optional embodiment of the present application, referring to Figure 4 or Figure 5 or Figure 6 as shown, the passivation layer 17 can include an insulating reflection structure so that the light emitted by the light-emitting diode can exit from the Ga2O3 substrate 1.

[0119] It should be noted that the Ga2O3 substrate 1 in this embodiment is a transparent substrate, and the light emitted by the light-emitting diode can exit from the Ga2O3 substrate 1.

[0120] Alternatively, to improve the light extraction efficiency of the semiconductor device to be applicable to scenarios with high brightness requirements, as Figure 8 shown, in another optional embodiment of the present application, a metal reflection layer 18 is provided on the surface of the Ga2O3 substrate 1 facing away from the epitaxial stack so that the light emitted by the light-emitting diode can exit from the side of the light-emitting diode.

[0121] It should be noted that the passivation layer 17 in this embodiment does not have a reflection effect.

[0122] The embodiment of the present application provides a manufacturing method of a semiconductor device, as Figure 9 shown, the manufacturing method includes:

[0123] Step 1, manufacturing an epitaxial structure;

[0124] Specifically, referring to Figure 1 as shown, a Ga2O3 substrate 1 is provided, and an epitaxial stack is formed on the Ga2O3 substrate 1 through a single epitaxial process. The epitaxial stack at least includes a first insulating isolation layer 2, a GaN channel layer 3, a barrier layer 4, a second insulating isolation layer 5, an N-type semiconductor 6 layer, an active region 7, and a P-type semiconductor 8 layer stacked in sequence along the growth direction;

[0125] It should be noted that by forming the epitaxial stack through a single epitaxial process and integrating multiple wide-bandgap semiconductor materials in a single epitaxial manner, the material preparation process can be simplified, laying a foundation for the monolithic integration of different wide-bandgap semiconductor devices.

[0126] In an optional embodiment of the present application, Step 1 can include the following processes:

[0127] Step A01, providing a Ga2O3 substrate 1;

[0128] Step A02: Use an MOCVD device, set the growth pressure inside the reaction chamber to 100 - 200 Torr, the growth temperature to 900 - 1100 °C, continuously introduce ammonia and an aluminum source, or ammonia and a gallium source, or ammonia, a gallium source and an indium source, or ammonia, a gallium source and an aluminum source into the reaction chamber for a duration of 1 - 1000 s, and grow a first insulating isolation layer 2 on the Ga2O3 substrate 1;

[0129] Step A03: Set the growth pressure inside the reaction chamber to 100 - 200 Torr, the growth temperature to 1000 - 1100 °C, continuously introduce a gallium source and ammonia into the reaction chamber for a duration of 1 - 1500 s, and grow a GaN channel layer on the first insulating isolation layer 2;

[0130] Step A04: Set the growth pressure inside the reaction chamber to 100 - 200 Torr, the growth temperature to 1000 - 1100 °C, continuously introduce ammonia and an aluminum source, or ammonia, a gallium source and an aluminum source, or ammonia, a gallium source and an indium source, or ammonia, a gallium source, an aluminum source and an indium source into the reaction chamber for a duration of 1 - 100 s, and grow a barrier layer 4 on the GaN channel layer;

[0131] Step A05: Set the growth pressure inside the reaction chamber to 100 - 200 Torr, the growth temperature to 900 - 1100 °C, continuously introduce ammonia and an aluminum source, or ammonia and a gallium source, or ammonia, a gallium source and an indium source, or ammonia, a gallium source and an aluminum source into the reaction chamber for a duration of 1 - 1000 s, and grow a second insulating isolation layer 5 on the barrier layer 4;

[0132] Step A06: Set the growth pressure inside the reaction chamber to 100 - 500 Torr, the growth temperature to 1000 - 1100 °C, continuously introduce ammonia and a gallium source into the reaction chamber, and through N-type doping, grow an N-type semiconductor 6 layer on the second insulating isolation layer 5. Exemplarily, the doping source for N-type doping can be Si;

[0133] Step A07: Set the growth pressure inside the reaction chamber to 100 - 500 Torr, the growth temperature to 700 - 900 °C, continuously introduce a gallium source, ammonia and an indium source into the reaction chamber to form a well layer, stop introducing the indium source into the reaction chamber to form a barrier layer, and repeat the alternating growth of the well layer and the barrier layer to form an active region 7;

[0134] Step A08: Set the growth pressure inside the reaction chamber to 100 - 500 Torr, the growth temperature to 900 - 1100 °C, continuously introduce a gallium source and ammonia into the reaction chamber, and through P-type doping, grow a P-type semiconductor 8 layer on the active region 7. Exemplarily, the doping source for P-type doping can be Mg.

[0135] It should be noted that, in this embodiment, high-purity H2 (hydrogen) or high-purity N2 (nitrogen) or a mixed gas of high-purity H2 and high-purity N2 is used as the carrier gas, trimethylgallium (TMGa) and triethylgallium (TEGa) are used as the gallium sources, trimethylindium (TMIn) is used as the indium source, trimethylaluminum (TMAl) is used as the aluminum source, and ammonia (NH3) is used as the nitrogen source. MOCVD refers to Metal-Organic Chemical Vapor Deposition.

[0136] Step 2: Etch the epitaxial stack and fabricate the first group of electrode structures A, the second group of electrode structures A, and the third group of electrodes A to form a semiconductor device;

[0137] Specifically, referring to Figure 3 As shown, through an etching process, the side of the Ga2O3 substrate 1 facing the epitaxial stack has an exposed first mesa M1, the side of the barrier layer 4 facing away from the GaN channel layer 3 has an exposed second mesa M2, the side of the N-type semiconductor 6 layer facing away from the second insulating isolation layer 5 has an exposed third mesa M3, and the side of the P-type semiconductor 8 layer facing away from the active region 7 is the fourth mesa M4; and the first group of electrode structures A is fabricated on the first mesa M1, which forms a photodetector with the Ga2O3 substrate 1; the second group of electrode structures B is fabricated on the second mesa M2, which forms a transistor with the GaN channel layer 3 and the barrier layer 4; the third group of electrode structures C is fabricated on the third mesa M3 and the fourth mesa M4, which forms a light-emitting diode with the N-type semiconductor 6 layer, the active region 7, and the P-type semiconductor 8 layer;

[0138] Among them, the photodetector, the transistor, and the light-emitting diode are connected in series electrically, and the first group of electrode structures A, the second group of electrode structures B, and the third group of electrode structures C are all insulated from the sidewalls of the epitaxial stack.

[0139] It should be noted that, in this embodiment, the photodetector, the transistor, and the light-emitting diode are integrated in the same module in a vertically stacked manner in sequence through epitaxy. The photodetector, the transistor, and the light-emitting diode are connected in series electrically. After the semiconductor device is connected to the working power supply, after the photodetector receives the ultraviolet light signal, the Ga2O3 material absorbs the ultraviolet light and generates a photocurrent. Under the action of the electric field, the photocurrent flows from the photodetector into the transistor, and the transistor amplifies the photocurrent and then drives the light-emitting diode to emit visible light, realizing the function of intuitively and real-time monitoring ultraviolet light.

[0140] In an alternative embodiment of the present application, Step 2 may include the following processes:

[0141] Step B01: As Figure 10 shown, use the first photolithography to etch the epitaxial stack to form the first mesa M1;

[0142] Specifically, a first mesa preset area is defined on the surface of the epitaxial stack, and etching is performed along the first mesa preset area to expose the Ga2O3 substrate 1, forming a first mesa M1;

[0143] Step B02: As Figure 11 shown, a first set of electrode structures A is fabricated on the first mesa M1;

[0144] Step B03: As Figure 12 shown, a second photolithography is used to etch the epitaxial stack, simultaneously forming a second mesa M2, a third mesa M3, and a fourth mesa M4;

[0145] Specifically, a second mesa preset area and a third mesa preset area are defined on the upper surface of the epitaxial stack. Etching is performed along the second mesa preset area to expose the barrier layer 4, forming the second mesa M2; simultaneously, etching is performed along the third mesa preset area to expose the N-type semiconductor 6 layer, forming the third mesa M3; and the surface of the P-type semiconductor 8 layer facing away from the active region 7 is the fourth mesa M4;

[0146] Step B04: As Figure 13 shown, a third set of electrode structures C is fabricated on the third mesa M3 and the fourth mesa M4;

[0147] Step B05: Referring to Figure 3 shown, a second set of electrode structures B is fabricated on the second mesa M2.

[0148] In another optional embodiment of the present application, step two may include the following processes:

[0149] Step C01: As Figure 14 shown, through a single photolithography, etching is performed along a partial surface of the epitaxial stack, simultaneously forming a first mesa M1, a second mesa M2, a third mesa M3, and a fourth mesa M4;

[0150] Specifically, a first mesa preset area, a second mesa preset area, and a third mesa preset area are defined on the upper surface of the epitaxial stack. Etching is performed along the first mesa preset area to expose the Ga2O3 substrate 1, forming the first mesa M1; etching is performed along the second mesa preset area to expose the barrier layer 4, forming the second mesa M2; simultaneously, etching is performed along the third mesa preset area to expose the N-type semiconductor 6 layer, forming the third mesa M3; and the surface of the P-type semiconductor 8 layer facing away from the active region 7 is the fourth mesa M4;

[0151] Step C02: Referring to Figure 12 shown, a first set of electrode structures A is fabricated on the first mesa M1;

[0152] Step C03: Referring to Figure 13 shown, a third set of electrode structures C is fabricated on the third mesa M3 and the fourth mesa M4;

[0153] Step C04, refer to Figure 3 As shown, fabricate the second set of electrode structures B on the second tabletop M2.

[0154] It should be noted that in this embodiment, through one lithography process, the first tabletop M1, the second tabletop M2, the third tabletop M3, and the fourth tabletop M4 can be formed simultaneously to save process steps.

[0155] Optionally, in some embodiments, the Ga2O3 substrate 1 includes a β-Ga2O3 substrate.

[0156] Optionally, in some embodiments, the lattice constant of the first insulating isolation layer 2 is between the lattice constants of the Ga2O3 substrate 1 and the GaN channel layer 3.

[0157] Optionally, in some embodiments, the lattice constant of the second insulating isolation layer 5 is between the lattice constants of the barrier layer 4 and the N-type semiconductor layer 6.

[0158] Optionally, in some embodiments, both the first insulating isolation layer 2 and the second insulating isolation layer 5 include nitride high-resistance materials.

[0159] Optionally, in some embodiments, both the first insulating isolation layer 2 and the second insulating isolation layer 5 include, but are not limited to, a single-layer nitride layer, or different combined structures of multiple nitride layers.

[0160] Optionally, in some embodiments, both the first insulating isolation layer 2 and the second insulating isolation layer 5 include, but are not limited to, a single-layer AlN layer, a single-layer C-doped GaN layer, a single-layer Fe-doped InGaN layer, an AlN / GaN superlattice structure, an AlN / AlGaN superlattice structure, or multiple AlGaN layers with different Al components.

[0161] Optionally, in some embodiments, the thickness ranges of both the first insulating isolation layer 2 and the second insulating isolation layer 5 are 0.02 μm - 3 μm, including the end values. Exemplarily, the thickness of the first insulating isolation layer 2 is 0.02 μm or 1 μm or 2 μm or 3 μm, and the thickness of the second insulating isolation layer 5 is 0.02 μm or 1 μm or 2 μm or 3 μm.

[0162] It should be noted that the specific materials and thicknesses of the first insulating isolation layer 2 and the second insulating isolation layer 5 are not limited in this embodiment. The materials and thicknesses of the first insulating isolation layer 2 and the second insulating isolation layer 5 can be the same or different. In an optional embodiment of this application, the first insulating isolation layer 2 can be a C-doped GaN high-resistance layer, and the thickness of the C-doped GaN high-resistance layer can be 2 μm. The second insulating isolation layer 5 can be an Fe-doped GaN high-resistance layer, and the thickness of the Fe-doped GaN high-resistance layer can be 1 μm.

[0163] Optionally, in some embodiments, the thickness of the GaN channel layer 3 ranges from 10 nm to 1500 nm, including the end values. Exemplarily, the thickness of the GaN channel layer 3 is 10 nm or 100 nm or 200 nm or 300 nm or 1500 nm.

[0164] Optionally, in some embodiments, the barrier layer 4 includes, but is not limited to, one or more of an AlN layer, an AlGaN layer, an InAlGaN layer, an InAlN layer, and an AlN / GaN superlattice structure.

[0165] Optionally, in some embodiments, the thickness of the barrier layer 4 ranges from 2 nm to 40 nm, including the end values. Exemplarily, the thickness of the barrier layer 4 is 2 nm or 20 nm or 40 nm.

[0166] Optionally, in some embodiments, the thickness of the N-type semiconductor 6 layer ranges from 0.5 μm to 4 μm, including the end values. Exemplarily, the thickness of the N-type semiconductor 6 layer is 0.5 μm or 2 μm or 4 μm.

[0167] Optionally, in some embodiments, the thickness of the P-type semiconductor 8 layer ranges from 20 nm to 300 nm, including the end values. Exemplarily, the thickness of the P-type semiconductor 8 layer is 20 nm or 50 nm or 100 nm or 200 nm or 300 nm.

[0168] Optionally, in some embodiments, the active region 7 is a periodic structure composed of well layers and barrier layers. The thickness of the active region 7 ranges from 10 nm to 200 nm, including the end values. Exemplarily, the thickness of the active region 7 is 10 nm or 50 nm or 100 nm or 200 nm.

[0169] It should be noted that the specific materials of the N-type semiconductor 6 layer and the P-type semiconductor 8 layer are not limited in this embodiment. In an alternative embodiment of the present application, the N-type semiconductor 6 layer can be an N-type GaN layer, the P-type semiconductor 8 layer can be a P-type GaN layer, and the active region 7 can be an InGaN / GaN multi-quantum well layer.

[0170] Optionally, in some embodiments, referring to Figure 2 As shown, the epitaxial stack further includes a nucleation layer 15 and a buffer layer 16 that are located between the Ga2O3 substrate 1 and the first insulating isolation layer 2 and are sequentially stacked in the direction of the first insulating isolation layer 2, for lattice transition and effective stress reduction, which can further improve the crystal quality of the epitaxial stack.

[0171] Optionally, in some embodiments, the nucleation layer 15 includes, but is not limited to, one or more of an AlN layer, a GaN layer, and an AlGaN layer.

[0172] Optionally, in some embodiments, the thickness of the nucleation layer 15 ranges from 5 nm to 500 nm, including the end values. Exemplarily, the thickness of the nucleation layer 15 is 5 nm or 200 nm or 500 nm.

[0173] Optionally, in some embodiments, the first set of electrode structures A is the PD electrode 9;

[0174] The second set of electrode structures B includes: a drain electrode 10, a source electrode 11, and a gate electrode 12. Both the drain electrode 10 and the source electrode 11 form ohmic contacts with the barrier layer 4, and the gate electrode 12 forms a Schottky contact with the barrier layer 4;

[0175] The third set of electrode structures C includes: an N electrode 13 located on the third mesa M3 and a P electrode 14 located on the fourth mesa M4.

[0176] It should be noted that after the semiconductor device in this embodiment is connected to the working power supply, the photocurrent flows into the source electrode 11 of the transistor from the PD electrode 9 of the photodetector, then flows out from the drain electrode 10 of the transistor, and then flows into the P electrode 14 of the light-emitting diode, and then flows out from the N electrode 13 of the light-emitting diode.

[0177] It should also be noted that the drain electrode 10, the source electrode 11, and the gate electrode 12 are spaced apart from each other; the N electrode 13 and the P electrode 14 are spaced far apart from each other.

[0178] Optionally, in this embodiment, the PD electrode 9 includes, but is not limited to, an interdigital electrode. The interdigital electrode is composed of alternately arranged finger-shaped metal electrodes, forming a dense electrode pair, which can improve the carrier collection efficiency. A parallel electric field is formed between adjacent finger-shaped electrodes, making the electric field distribution more uniform, thereby improving the performance of the photodetector.

[0179] Optionally, in this embodiment, the drain electrode 10 and the source electrode 11 are located on both sides of the gate electrode 12, and the gate electrode 12 is used to control the current to achieve field effect modulation.

[0180] Optionally, in some embodiments, the drain electrode 10 is arranged on the side close to the P electrode to facilitate the subsequent connection between the drain electrode 10 and the P electrode.

[0181] Optionally, in some embodiments, the second insulating isolation layer 5 and the light-emitting diode can be located between the source electrode 11 and the gate electrode 12 (not shown in the figure). The second insulating isolation layer 5 can improve the dielectric withstand ability between the source electrode 11 and the gate electrode 12, thereby improving the breakdown voltage resistance of the HEMT.

[0182] Optionally, in some embodiments, refer to Figure 3As shown, the second insulating isolation layer 5 and the light-emitting diode can be located between the drain 10 and the gate 12. The second insulating isolation layer 5 can improve the dielectric withstand ability between the drain 10 and the gate 12, thereby enhancing the breakdown voltage withstand ability of the HEMT. Moreover, the gate 12 is arranged close to the source 11 to reduce the field effect modulation delay.

[0183] Optionally, in some embodiments, forming the drain 10, the source 11, and the gate 12 may include the following processes:

[0184] Form the drain 10 and the source 11 on the second mesa M2 by metal deposition, and then perform a laser annealing process so that both the drain 10 and the source 11 form ohmic contacts with the barrier layer 4. In an optional embodiment of the present application, the time of laser annealing can be 1 minute;

[0185] Form the gate 12 on the second mesa M2 by metal deposition.

[0186] Optionally, in some embodiments, the PD electrode 9 includes, but is not limited to, one or more stacks of a Ti layer and an Au layer. Among them, the thickness of the Ti layer can be 20 nm, and the thickness of the Au layer can be 120 nm.

[0187] Optionally, in some embodiments, the gate 12 includes, but is not limited to, one or more stacks of a Ni layer and an Au layer. Among them, the thickness of the Ni layer can be 60 nm, and the thickness of the Au layer can be 100 nm.

[0188] Optionally, in some embodiments, the source 11 includes, but is not limited to, one or more stacks of a Ti layer, an Al layer, a Ni layer, and an Au layer. Among them, the thickness of the Ti layer can be 20 nm, the thickness of the Al layer can be 120 nm, the thickness of the Ni layer can be 40 nm, and the thickness of the Au layer can be 50 nm.

[0189] Optionally, in some embodiments, the drain 10 includes, but is not limited to, one or more stacks of a Ti layer, an Al layer, a Ni layer, and an Au layer. Among them, the thickness of the Ti layer can be 20 nm, the thickness of the Al layer can be 120 nm, the thickness of the Ni layer can be 40 nm, and the thickness of the Au layer can be 50 nm.

[0190] Optionally, in some embodiments, the photodetector and the transistor, and between the transistor and the light-emitting diode can be electrically connected by means of external bonding wires.

[0191] Specifically, referring to Figure 3 As shown, the PD electrode 9 of the photodetector can be electrically connected to the source 11 of the transistor through the first external metal connection line 20, and the drain 10 of the transistor can be electrically connected to the P electrode 14 of the light-emitting diode through the second external metal connection line 21.

[0192] Optionally, in some embodiments, with reference to Figure 4 as shown, the semiconductor device further includes a passivation layer 17 that covers the exposed surface of the epitaxial stack.

[0193] It should be noted that in this embodiment, the first group of electrode structures A, the second group of electrode structures B, and the third group of electrode structures C are insulated from the sidewalls of the epitaxial stack through the passivation layer 17, and the material of the passivation layer 17 can be silicon oxide, silicon nitride, or other materials with a passivation effect, which is not limited in the embodiments of the present application.

[0194] Optionally, in some embodiments, the passivation layer 17 can be formed by a chemical vapor deposition process.

[0195] Optionally, in some embodiments, between the photodetector and the transistor, and between the transistor and the light-emitting diode, metal connection lines can also be directly provided on the semiconductor device by means of an intervening passivation layer to achieve electrical connection without the need to additionally add external bonding wires.

[0196] Specifically, with reference to Figure 4 as shown, the PD electrode 9 of the photodetector can be electrically connected to the source electrode 11 of the transistor through a first internal metal connection line 30, and the drain electrode 10 of the transistor can be electrically connected to the P electrode 14 of the light-emitting diode through a second internal metal connection line 31.

[0197] Optionally, in some embodiments, with reference to Figure 5 as shown, the passivation layer 17 also covers the exposed surfaces of the second group of electrode structures B and the third group of electrode structures C and exposes the first group of electrode structures A. As Figure 15 shown, the passivation layer 17 includes a first through hole K1, a second through hole K2, a third through hole K3, a fourth through hole K4, and a fifth through hole K5 that penetrate the passivation layer 17;

[0198] Moreover, the semiconductor device further includes: a first pad P1, a second pad P2, a third pad P3, a fourth pad P4, a fifth pad P5, and a sixth pad P6 located on the side of the passivation layer 17 away from the Ga2O3 substrate 1;

[0199] wherein, the first pad P1 is connected to the drain electrode 10 by being embedded in the first through hole K1; the second pad P2 is connected to the P electrode 14 by being embedded in the second through hole K2; the third pad P3 is connected to the N electrode 13 by being embedded in the third through hole K3; the fourth pad P4 is connected to the gate electrode 12 by being embedded in the fourth through hole K4; the fifth pad P5 is connected to the source electrode 11 by being embedded in the fifth through hole K5; and the sixth pad P6 is connected to the PD electrode 9 by extending to the sidewall of the passivation layer 17.

[0200] Optionally, in this embodiment, a deep hole etching process may be employed to form the first through hole K1, the second through hole K2, the third through hole K3, the fourth through hole K4, and the fifth through hole K5.

[0201] It should be noted that in this embodiment, the first group of electrode structures A is exposed to avoid the influence of the presence of the passivation layer 17 on the photoelectric reception of the photodetector.

[0202] It should also be noted that the materials of the first pad P1, the second pad P2, the third pad P3, the fourth pad P4, the fifth pad P5, and the sixth pad P6 include, but are not limited to, one or more metal stacks of Al, Cu, Au, TiN, Ti, Pt, Cr, Ni, Pd, which are not limited in the embodiments of the present application. In an alternative embodiment of the present application, the materials of the first pad P1, the second pad P2, the third pad P3, the fourth pad P4, the fifth pad P5, and the sixth pad P6 may be Al. The specific thickness of the passivation layer 17 is not limited in this embodiment. In an alternative embodiment of the present application, the thickness of the passivation layer 17 may be 2 μm.

[0203] Optionally, in some embodiments, the surfaces of the first pad P1, the second pad P2, the third pad P3, the fourth pad P4, the fifth pad P5, and the sixth pad P6 facing away from the passivation layer 17 are all at the same horizontal height, which can reduce welding defects and avoid device tilting or suspension, so as to improve the device stability.

[0204] Optionally, in some embodiments, referring to Figure 6 and Figure 7 as shown, the first pad P1 and the second pad P2 are an integrally formed first integrated pad P7; the fifth pad P5 and the sixth pad P6 are an integrally formed second integrated pad P8.

[0205] It should be noted that the photodetector and the transistor in this embodiment are electrically connected through the integrally formed first integrated pad P7, and the transistor and the light-emitting diode are electrically connected through the integrally formed second integrated pad P8, which can reduce the number of pads, so as to reduce the process cost, wiring complexity, and risk of welding defects, improve the connection reliability, and can also save layout space to meet the requirements of device miniaturization.

[0206] Optionally, in some embodiments, referring to Figure 6 as shown, an epitaxial structure with a nucleation layer 15 and a buffer layer 16 may be employed to further improve the overall performance of the semiconductor device.

[0207] To improve the light extraction efficiency of the semiconductor device to be applicable to scenarios with higher brightness requirements, in an alternative embodiment of the present application, referring to Figure 4 or Figure 5 or Figure 6As shown, the passivation layer 17 may include an insulating reflection structure so that the light emitted by the light-emitting diode can exit from the Ga2O3 substrate 1.

[0208] It should be noted that the Ga2O3 substrate 1 in this embodiment is a transparent substrate, and the light emitted by the light-emitting diode can exit from the Ga2O3 substrate 1.

[0209] Alternatively, to improve the light extraction efficiency of the semiconductor device to be applicable to scenarios with high brightness requirements, refer to Figure 8 As shown, in another alternative embodiment of the present application, a metal reflection layer 18 is provided on the surface of the Ga2O3 substrate 1 facing away from the epitaxial stack so that the light emitted by the light-emitting diode can exit from the side of the light-emitting diode.

[0210] It should be noted that the passivation layer 17 in this embodiment does not have a reflection effect.

[0211] In summary, through the above technical solutions, the following effects can be achieved:

[0212] An epitaxial structure provided in this embodiment, the epitaxial structure includes: a Ga2O3 substrate; an epitaxial stack provided on the Ga2O3 substrate, the epitaxial stack at least includes: a first insulating isolation layer, a GaN channel layer, a barrier layer, a second insulating isolation layer, an N-type semiconductor layer, an active region, and a P-type semiconductor layer sequentially stacked from bottom to top on the Ga2O3 substrate. This epitaxial structure monolithically integrates multiple wide-bandgap semiconductor materials. Among them, the Ga2O3 substrate can be used to form a photodetector, the GaN channel layer and the barrier layer can be used to form a transistor, and the N-type semiconductor layer, the active region, and the P-type semiconductor layer can be used to form a light-emitting diode, so as to be used to manufacture a semiconductor device that realizes the function of intuitively and real-time monitoring ultraviolet light. It can feedback detection information without equipping an additional electrical signal processing system, and can meet the miniaturization requirements of the solar-blind ultraviolet detector.

[0213] Furthermore, an epitaxial stack can be obtained by single-step epitaxy on a Ga2O3 substrate. The Ga2O3 semiconductor material has a wide bandgap characteristic (bandgap width ~ 4.8 eV), excellent thermal stability, and chemical inertness, making it suitable for high-temperature epitaxial growth environments. A first insulating isolation layer is formed on the Ga2O3 substrate. The first insulating isolation layer uses its high insulation and thermal matching with the Ga2O3 substrate to isolate the Ga2O3 substrate from subsequent functional layers, reducing leakage current. Moreover, the lattice constant of the first insulating isolation layer is between that of the Ga2O3 substrate and the GaN channel layer, enabling the first insulating isolation layer to effectively relieve the lattice mismatch between the Ga2O3 substrate and the GaN channel layer, reducing the dislocation density and providing a high-quality template for subsequent multi-layer growth. By utilizing the lattice adaptation and thermal matching characteristics of the Ga2O3 substrate and the epitaxial functional layers, an epitaxial stack can thus be directly obtained by single-step epitaxy. Also, integrating multiple wide-bandgap semiconductor materials by single-step epitaxy can simplify the material preparation process and lay the foundation for the monolithic integration of different wide-bandgap semiconductor devices.

[0214] Furthermore, the lattice constant of the second insulating isolation layer is set to be between that of the barrier layer and the N-type semiconductor layer. The second insulating isolation layer can effectively relieve the lattice mismatch between the barrier layer and the N-type semiconductor layer, thereby improving the crystal quality of the epitaxial stack.

[0215] Furthermore, both the first insulating isolation layer and the second insulating isolation layer are set to include a nitride high-resistance material. The nitride high-resistance material has high lattice matching flexibility, making it more convenient to adjust the lattice constant of the nitride high-resistance material to achieve lattice transition and reduce mismatch. Moreover, the thermal expansion coefficient of the nitride high-resistance material is close to that of III-V (wide-bandgap) materials, which can reduce cracks caused by thermal stress. Additionally, the nitride high-resistance material has high chemical stability, and at high temperatures, the nitride can inhibit the diffusion reaction between the functional layers on both sides of the nitride high-resistance material.

[0216] A semiconductor device provided in this embodiment adopts the epitaxial structure of any one of the above, wherein the first group of electrode structures and the Ga2O3 substrate form a photodetector, the second group of electrode structures and the GaN channel layer and the barrier layer form a transistor, and the third group of electrode structures and the N-type semiconductor layer, the active region and the P-type semiconductor layer form a light-emitting diode. The photodetector, the transistor and the light-emitting diode are sequentially connected in series. The semiconductor device integrates the photodetector, the transistor and the light-emitting diode in the same module in a vertically stacked manner in sequence, which can meet the miniaturization requirements of the solar-blind ultraviolet detector. Moreover, the wide bandgap of the Ga2O3 substrate corresponds to the absorption of the solar-blind ultraviolet band (240-280 nm), so that the photodetector can receive ultraviolet light signals; the GaN channel layer and the barrier layer are used as the core structure of the transistor. At the heterojunction interface between the GaN channel layer and the barrier layer, due to the polarization effect and the band offset, electrons are confined in a nanoscale thin layer to form a two-dimensional electron gas (2DEG) with high concentration and high mobility to achieve photocurrent amplification; the N-type semiconductor layer and the P-type semiconductor layer respectively achieve carrier regulation through N-type doping and P-type doping, and recombination luminescence occurs in the active region to enable the light-emitting diode to emit visible light. After the semiconductor device is connected to the working power supply, after the photodetector receives the ultraviolet light signal, the photodetector utilizes the advantages of the Ga2O3 material in ultraviolet detection to receive ultraviolet light and generate a photocurrent. Under the action of the electric field, the photocurrent flows from the photodetector into the transistor. The transistor amplifies the photocurrent and then drives the light-emitting diode to emit visible light, realizing the function of intuitively and real-time monitoring ultraviolet light, and has broad application prospects in monitoring corona, fire occurrence, and full-duplex indoor optical communication scenarios.

[0217] In addition, the GaN channel layer and the barrier layer are arranged between the first insulating isolation layer and the second insulating isolation layer. This structural design can effectively suppress the hot electron emission effect of the transistor, significantly reduce the generation of leakage current, and will not cause adverse effects on the photodetector and the light-emitting diode; at the same time, this design enhances the breakdown voltage resistance of the device under high voltage and reduces the breakdown risk.

[0218] In addition, the setting of the first insulating isolation layer can improve the crystal quality of the transistor, and the setting of the second insulating isolation layer can improve the crystal quality of the light-emitting diode, thereby improving the overall performance of the semiconductor device.

[0219] A manufacturing method of a semiconductor device provided in this embodiment, while achieving the beneficial effects of the above semiconductor device, adopts an epitaxial method to integrate a variety of wide bandgap semiconductor materials, simplifies the material preparation process, and realizes the monolithic integration preparation of different wide bandgap semiconductor devices on the same substrate. The preparation method is applicable to the device preparation process of traditional integrated circuits, is simple and convenient to manufacture, is convenient for industrial production, and does not increase the additional device preparation cost.

[0220] Those skilled in the art should understand that in the disclosure of the present invention, the orientation or positional relationship indicated by terms such as "lateral", "longitudinal", "upper", "lower", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting the present invention.

[0221] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other.

[0222] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An epitaxial structure, characterized in that: The epitaxial structure comprises: Ga2O3 substrate; An epitaxial stack is arranged on the Ga2O3 substrate, and the epitaxial stack at least includes: a first insulating isolation layer, a GaN channel layer, a barrier layer, a second insulating isolation layer, an N-type semiconductor layer, an active region and a P-type semiconductor layer stacked sequentially from bottom to top on the Ga2O3 substrate.

2. The epitaxial structure according to claim 1, characterized in that: The epitaxial stack is obtained by single epitaxy on the Ga2O3 substrate, and the lattice constant of the first insulating isolation layer is between the lattice constants of the Ga2O3 substrate and the GaN channel layer.

3. The epitaxial structure according to claim 1, characterized in that: The lattice constant of the second insulating isolation layer is between the lattice constants of the barrier layer and the N-type semiconductor layer.

4. The epitaxial structure according to claim 1, characterized in that: The first insulating isolation layer and the second insulating isolation layer both include nitride high-resistance material.

5. The epitaxial structure according to claim 1, characterized in that: The epitaxial stack further includes a nucleation layer and a buffer layer which are located between the Ga2O3 substrate and the first insulating isolation layer and are sequentially stacked toward the first insulating isolation layer.

6. A semiconductor device, characterized in that: The semiconductor device comprises: Adopting the epitaxial structure according to any one of claims 1 to 5; The Ga2O3 substrate has an exposed first mesa on a side facing the epitaxial stack, the barrier layer has an exposed second mesa on a side facing away from the GaN channel layer, the N-type semiconductor layer has an exposed third mesa on a side facing away from the second insulating isolation layer, and the P-type semiconductor layer has a fourth mesa on a side facing away from the active region; A first set of electrode structures, which are located on the first table and form a photodetector with the Ga2O3 substrate; A second set of electrode structures, which are located on the second terrace and form a transistor with the GaN channel layer and the barrier layer; A third set of electrode structures, which are located on the third mesa and the fourth mesa and form a light emitting diode with the N-type semiconductor layer, the active region and the P-type semiconductor layer; The photodetector, the transistor and the light emitting diode are electrically connected in series in sequence, and the first electrode structure, the second electrode structure and the third electrode structure are all insulated from the sidewall of the epitaxial stack.

7. The semiconductor device according to claim 6, wherein: The first group of electrode structures are PD electrodes; The second group of electrode structures includes: a drain, a source and a gate, the drain and the source both form an ohmic contact with the barrier layer, and the gate forms a Schottky contact with the barrier layer; The third group of electrode structures includes: an N electrode located on the third mesa and a P electrode located on the fourth mesa.

8. The semiconductor device according to claim 7, wherein: The semiconductor device further comprises a passivation layer, wherein the passivation layer covers an exposed surface of the epitaxial stack.

9. The semiconductor device according to claim 8, characterized in that: The passivation layer also covers the exposed surfaces of the second group of electrode structures and the third group of electrode structures, and exposes the first group of electrode structures, and the passivation layer includes a first through hole, a second through hole, a third through hole, a fourth through hole and a fifth through hole penetrating the passivation layer; Furthermore, the semiconductor device further comprises: a first pad, a second pad, a third pad, a fourth pad, a fifth pad, and a sixth pad located on a side of the passivation layer away from the Ga2O3 substrate; Among them, the first pad is connected to the drain by being embedded in the first through hole; the second pad is connected to the P electrode by being embedded in the second through hole; the third pad is connected to the N electrode by being embedded in the third through hole; the fourth pad is connected to the gate by being embedded in the fourth through hole; the fifth pad is connected to the source by being embedded in the fifth through hole; and the sixth pad is connected to the PD electrode by extending to the side wall of the passivation layer.

10. A method for manufacturing a semiconductor device, characterized in that: include: Step 1: making an epitaxial structure; Specifically, a Ga2O3 substrate is provided, and an epitaxial stack is formed on the Ga2O3 substrate by a single epitaxial process, wherein the epitaxial stack at least includes a first insulating isolation layer, a GaN channel layer, a barrier layer, a second insulating isolation layer, an N-type semiconductor layer, an active region, and a P-type semiconductor layer sequentially stacked along a growth direction; Step 2: etching the epitaxial stack and preparing a first electrode structure, a second electrode structure and a third electrode structure to form a semiconductor device; Specifically, an etching process is performed so that the side of the Ga2O3 substrate facing the epitaxial stack has an exposed first mesa, the side of the barrier layer facing away from the GaN channel layer has an exposed second mesa, the side of the N-type semiconductor layer facing away from the second insulating isolation layer has an exposed third mesa, and the side of the P-type semiconductor layer facing away from the active region is a fourth mesa; and a first group of electrode structures are made on the first mesa, which together with the Ga2O3 substrate constitute a light detector; a second group of electrode structures are made on the second mesa, which together with the GaN channel layer and the barrier layer constitute a transistor; and a third group of electrode structures are made on the third mesa and the fourth mesa, which together with the N-type semiconductor layer, the active region and the P-type semiconductor layer constitute a light-emitting diode; The photodetector, the transistor and the light emitting diode are electrically connected in series in sequence, and the first electrode structure, the second electrode structure and the third electrode structure are all insulated from the sidewall of the epitaxial stack.

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