Manufacturing method of solar cell, solar cell and cell string

Abstract

The invention discloses a manufacturing method of a solar cell, the solar cell and a cell string, relates to the technical field of solar cells, and aims to solve the problems that a main grid is in contact with a silicon substrate, a passivation layer is damaged, the open-circuit voltage is reduced, and the photoelectric conversion efficiency is influenced. The manufacturing method of the solar cell comprises the steps that an emitter layer is formed on one face of a semiconductor substrate, the conduction type of the semiconductor substrate is opposite to that of the emitter layer, and the emitter layer and the semiconductor substrate jointly form a PN junction. A passivation layer is formed on the emitter layer, and an insulating layer is formed on the passivation layer. And forming main grids which extend along a first direction and are distributed at intervals along a second direction on the insulating layer, wherein the first direction is different from the second direction. And forming fine grids which extend along the second direction and are distributed at intervals along the first direction on the insulating layer. Wherein the main grid extends towards the emitter layer, the depth of the main grid extending into the insulating layer exceeds 20% of the thickness of the insulating layer, and the depth of the main grid extending into the passivation layer does not exceed 90% of the thickness of the passivation layer.

Description

[0001] This application is a divisional application of the patent application with the application number 202311296304.2 and the invention title "A Manufacturing Method of Solar Cells, Solar Cells and Battery Strings". The filing date of the patent application with the application number 202311296304.2 is October 8, 2023. Technical Field

[0002] The present invention relates to the technical field of solar cells, and particularly to a manufacturing method of solar cells, solar cells and battery strings. Background Art

[0003] A solar cell is a semiconductor device that can convert light energy into electrical energy. Specifically, when the solar cell is irradiated with light, the semiconductor substrate included in the solar cell absorbs photons and generates electron-hole pairs. Under the action of the built-in electric field of the PN junction, the electron-hole pairs are separated and are respectively led out through the emitter and the back field of the solar cell, and finally are collected by the electrode structure disposed on the semiconductor substrate.

[0004] The above-mentioned electrode structure generally includes a main grid and fine grids formed by integral printing. During the sintering process, as the corrosion proceeds synchronously, both the main grid and the fine grids are in contact with the silicon substrate.

[0005] However, during the contact between the main grid and the silicon substrate, the passivation layer will be severely damaged. At this time, the open-circuit voltage (Uoc) will decrease, thereby affecting the photoelectric conversion efficiency. Summary of the Invention

[0006] The purpose of the present invention is to provide a manufacturing method of solar cells, solar cells and battery strings, which is used to reduce or eliminate the damage to the passivation layer and improve the open-circuit voltage, so as to reduce the influence on the photoelectric conversion efficiency.

[0007] To achieve the above purpose, in the first aspect, the present invention provides a manufacturing method of solar cells. The manufacturing method of the solar cell includes:

[0008] First, a semiconductor substrate is provided. Next, an emitter layer is formed on one side of the semiconductor substrate. The conductive types of the semiconductor substrate and the emitter layer are opposite, and the emitter layer and the semiconductor substrate together form a PN junction. Next, a passivation layer is formed on the emitter layer. Next, an insulating layer is formed on the passivation layer. Next, a main gate is formed on the insulating layer. The main gate extends in a first direction and is spaced apart in a second direction, where the first direction is different from the second direction. Next, a fine gate is formed on the insulating layer. The fine gate extends in the second direction and is spaced apart in the first direction. Each main gate intersects with multiple fine gates. The fine gates pass through the passivation layer and the insulating layer and are connected to the emitter layer. Among them, the main gate extends towards the emitter layer. The depth that the main gate extends into the insulating layer exceeds 20% of the thickness of the insulating layer, and the depth that the main gate extends into the passivation layer does not exceed 90% of the thickness of the passivation layer. The depth direction, the thickness direction of the passivation layer, and the thickness direction of the insulating layer are all consistent with the direction towards the semiconductor substrate.

[0009] In the manufacturing method of the solar cell provided by the present invention, since the main gate is formed on the insulating layer and the main gate extends towards the emitter layer, the depth that the main gate extends into the insulating layer exceeds 20% of the thickness of the insulating layer, and the depth that the main gate extends into the passivation layer does not exceed 90% of the thickness of the passivation layer. At this time, some extended main gates (i.e., some regions of the main gate) may be only located within the insulating layer; they may also be located within both the insulating layer and the passivation layer at the same time, but the depth that the main gate extends into the passivation layer does not exceed 90% of the thickness of the passivation layer.

[0010] When some extended main gates are only located within the insulating layer, the main gate does not damage the passivation layer, ensuring the passivation effect of the passivation layer. Based on this, the open-circuit voltage can be increased to reduce or avoid the impact on the photoelectric conversion efficiency.

[0011] When some extended main gates are located within both the insulating layer and the passivation layer at the same time, but the depth that the main gate extends into the passivation layer does not exceed 90% of the thickness of the passivation layer, compared with the situation in the prior art where the main gate passes through the passivation layer and is connected to the silicon substrate, the degree of damage of the main gate to the passivation layer is reduced, ensuring the passivation effect of the passivation layer. Based on this, the open-circuit voltage can be increased, thereby reducing the impact on the photoelectric conversion efficiency. Further, the above main gate is connected to both the insulating layer and the passivation layer at the same time. At this time, the mechanical properties of the main gate can be ensured, and the tensile characteristics of the main gate can be improved. Based on this, the probability of the main gate detaching from the solar cell can be reduced or eliminated to ensure the quality and performance of the solar cell.

[0012] In one implementation, the metal solid content in the raw material for forming the main gate is less than the metal solid content in the raw material for forming the fine gate.

[0013] In the case of adopting the above technical solution, the depth of the main grid extending towards the emitter layer is less than the depth of the fine grid extending towards the emitter layer. At this time, the damage degree of the main grid to the passivation layer can be reduced to ensure the passivation effect of the passivation layer. Further, when the metal solid content in the fine grid raw material remains unchanged, compared with the case where the metal solid content in the main grid raw material and the fine grid raw material is the same in the prior art, not only can the cost of the main grid raw material be reduced to reduce the manufacturing cost of the solar cell. At the same time, it can also ensure that the depth of the fine grid extending towards the emitter layer in the present invention is basically the same as or the same as the depth of the fine grid extending towards the emitter layer in the prior art to ensure that the performance of the fine grid remains unchanged.

[0014] In a second aspect, the present invention also provides a solar cell. The solar cell includes: a semiconductor substrate, an emitter layer, a passivation layer, an insulating layer, a main grid, and a fine grid. The emitter layer is located on one side of the semiconductor substrate. The conductive types of the semiconductor substrate and the emitter layer are opposite, and the emitter layer and the semiconductor substrate together form a PN junction. The passivation layer is located on the emitter layer, and the insulating layer is located on the passivation layer. The main grid is located on the insulating layer. The main grid extends along a first direction and is spaced apart along a second direction. The first direction is different from the second direction. The fine grid is located on the insulating layer. The fine grid extends along the second direction and is spaced apart along the first direction. Each main grid intersects with multiple fine grids. The fine grid passes through the passivation layer and the insulating layer and is connected to the emitter layer. Among them, the main grid extends towards the emitter layer. The depth of the main grid extending into the insulating layer exceeds 20% of the thickness of the insulating layer, and the depth of the main grid extending into the passivation layer does not exceed 90% of the thickness of the passivation layer. The depth direction, the thickness direction of the passivation layer, and the thickness direction of the insulating layer are all consistent with the direction towards the semiconductor substrate.

[0015] In the solar cell provided by the present invention, since the main grid is formed on the insulating layer and the main grid extends towards the emitter layer, the depth of the main grid extending into the insulating layer exceeds 20% of the thickness of the insulating layer, and the depth of the main grid extending into the passivation layer does not exceed 90% of the thickness of the passivation layer. At this time, a part of the extended main grid (i.e., a partial area of the main grid) may be only located in the insulating layer; it may also be located in both the insulating layer and the passivation layer at the same time, but the depth of the main grid extending into the passivation layer does not exceed 90% of the thickness of the passivation layer.

[0016] When a part of the extended main grid is only located in the insulating layer, the main grid does not damage the passivation layer, ensuring the passivation effect of the passivation layer. Based on this, the open-circuit voltage can be increased to reduce or avoid the influence on the photoelectric conversion efficiency.

[0017] When the extended partial main grid is located within both the insulating layer and the passivation layer simultaneously, but the depth to which the main grid extends into the passivation layer does not exceed 90% of the thickness of the passivation layer, compared with the situation in the prior art where the main grid passes through the passivation layer and is connected to the silicon substrate, the degree of damage to the passivation layer by the main grid is reduced, ensuring the passivation effect of the passivation layer. Based on this, the open-circuit voltage can be increased, thereby reducing the impact on the photoelectric conversion efficiency. Further, the above-mentioned main grid is connected to both the insulating layer and the passivation layer simultaneously. At this time, the mechanical properties of the main grid can be guaranteed, and the tensile characteristics of the main grid can be improved. Based on this, the probability of the main grid detaching from the solar cell can be reduced or eliminated to ensure the quality and performance of the solar cell.

[0018] In one implementation, the ratio of the depth to which the above-mentioned main grid extends into the passivation layer to the thickness of the passivation layer is greater than or equal to 20%.

[0019] In the case of adopting the above technical solution, the main grid is connected to both the insulating layer and the passivation layer simultaneously. At this time, the mechanical properties of the main grid can be guaranteed, and the tensile characteristics of the main grid can be improved to reduce or eliminate the probability of the main grid detaching from the solar cell, thereby ensuring the quality and performance of the solar cell.

[0020] In one implementation, the depth to which the above-mentioned main grid extends into the passivation layer is 0.

[0021] In the case of adopting the above technical solution, the main grid can be prevented from damaging the passivation layer to ensure the passivation effect of the passivation layer. Based on this, the open-circuit voltage can be increased, avoiding the impact on the photoelectric conversion efficiency.

[0022] In one implementation, when the thickness of the above-mentioned passivation layer is greater than or equal to 5 nm and less than or equal to 20 nm, the depth to which the main grid extends into the passivation layer is greater than or equal to 1 nm and less than or equal to 18 nm.

[0023] In the case of adopting the above technical solution, since the depth is greater than or equal to 1 nm, at this time, it can be ensured that the main grid is connected to both the insulating layer and the passivation layer simultaneously. Based on this, the mechanical properties of the main grid can be guaranteed, and the tensile characteristics of the main grid can be improved to reduce or eliminate the probability of the main grid detaching from the solar cell, thereby ensuring the quality and performance of the solar cell. Further, since the depth is less than or equal to 18 nm, at this time, the degree of damage to the passivation layer by the main grid can be reduced, ensuring the passivation effect of the passivation layer to increase the open-circuit voltage and reduce the impact on the photoelectric conversion efficiency.

[0024] In one implementation, each main grid includes: a main grid connection line and a pad. A plurality of pads are arranged at intervals along a first direction on the main grid connection line. The width of the pad is greater than the width of the main grid connection line. The width direction of the pad and the width direction of the main grid connection line are both consistent with a second direction.

[0025] In the case of adopting the above technical solution, when the number of main grid connection lines is the same, compared with the case where the width of the main grid connection line is equal to the width of the pad, it is possible to reduce the amount of raw materials used for manufacturing the main grid connection line and save the raw material cost while ensuring that the current collection ability of the main grid connection line meets the actual needs. At the same time, it is also possible to reduce the shielding of the semiconductor substrate by the main grid connection line, increase the light-receiving area of the semiconductor substrate, and improve the photoelectric conversion efficiency of the solar cell. Further, when manufacturing the battery string in the later stage, the solder ribbon needs to be connected to the pad. At this time, compared with the case where the width of the main grid connection line is equal to the width of the pad, the solder ribbon is more easily connected to the pad, reducing the manufacturing difficulty and improving the manufacturing efficiency.

[0026] In one implementation, the number of the above-mentioned main grids is greater than or equal to 8 and less than or equal to 25; and / or, the width of the main grid connection line is greater than or equal to 35 microns and less than or equal to 60 microns. The width of the pad is greater than or equal to 0.6 mm and less than or equal to 1.3 mm.

[0027] In the case of adopting the above technical solution, by controlling the number of main grids, the width of the main grid connection line, and the width of the pad, the shielding area of the main grid on the semiconductor substrate can be controlled. At this time, the amount of light injected into the semiconductor substrate can be increased, and the light-receiving area of the semiconductor substrate can be increased to improve the battery efficiency of the solar cell.

[0028] In one implementation, the number of the above-mentioned fine grids is greater than or equal to 100 and less than or equal to 200. The width of the fine grid is greater than or equal to 20 microns and less than or equal to 45 microns, and the width direction of the fine grid is the same as the first direction.

[0029] In the case of adopting the above technical solution, the current collection ability of the fine grid can be improved to improve the battery efficiency of the solar cell.

[0030] In a third aspect, the present invention further provides a battery string. The battery string includes a plurality of solder ribbons and a plurality of solar cells arranged at intervals as described in the above technical solution, and the solder ribbons are correspondingly connected to the main grids.

[0031] Compared with the prior art, the beneficial effects of the battery string provided by the present invention are the same as those of the solar cell described in the above technical solution, and will not be elaborated here.

[0032] In one implementation, when the above-mentioned main grid includes a main grid connection line and a pad, the solder ribbon is arranged on the pad along the first direction and covers the main grid connection line. The maximum width of the solder ribbon is less than or equal to the width of the pad, and the width directions of the solder ribbon and the pad are both the same as the second direction.

[0033] In the case of adopting the above technical solution, the shielding of the semiconductor substrate by the solder tape can be reduced, the light-receiving area of the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0034] In one implementation, the width of the above solder tape is less than or equal to the width of the main grid connection line, and the width directions of both the solder tape and the main grid connection line are the same as the second direction.

[0035] In the case of adopting the above technical solution, the shielding of the semiconductor substrate by the solder tape can be reduced, the light-receiving area of the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0036] In one implementation, the ratio of the width of the above solder tape to the width of the main grid connection line is greater than or equal to 50% and less than or equal to 90%.

[0037] In the case of adopting the above technical solution, since the solder tape includes a core layer made of a metal material and a solder layer located on the outer surface of the core layer. During the actual welding process of the solder tape and the pad, the solder layer melts and has a certain fluidity. Since the above ratio is greater than or equal to 50% and less than or equal to 90%, the flowing solder can be distributed at the interface between the solder tape and the main grid connection line, giving it sufficient flow space. At this time, the solder can be prevented from flowing onto the semiconductor substrate to avoid solder contamination and shielding of the semiconductor substrate, thereby ensuring the quality and performance of the solar cell. Description of the Drawings

[0038] The drawings described herein are used to provide a further understanding of the present invention, and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0039] Figure 1 is a schematic structural diagram of a solar cell in the prior art;

[0040] Figure 2 is a schematic structure of the solar cell in the embodiment of the present invention Figure 1 ;

[0041] Figure 3 is a schematic structure of the solar cell in the embodiment of the present invention Figure 2 .

[0042] Reference Signs:

[0043] 1 - semiconductor substrate, 2 - emitter layer, 3 - passivation layer,

[0044] 4 - insulating layer, 5 - main grid, 50 - main grid connection line,

[0045] 51 - pad, 6 - fine grid. Detailed implementation manners

[0046] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0047] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0048] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined. The meaning of "several" is one or more unless otherwise specifically defined.

[0049] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present invention.

[0050] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0051] Screen printing is the core of process management in the manufacturing process of solar cells. Screen printing is mainly used for electrode formation of solar cells. Specifically, printing is performed based on the basic principle that the mesh holes of the graphic part of the screen are permeable to the slurry, while the mesh holes of the non-graphic part are not permeable to the slurry. When printing, pour the slurry at one end of the screen, and use a scraper to apply a certain pressure to the slurry part of the screen while moving toward the other end of the screen. During the movement, the slurry is squeezed from the mesh holes of the graphic part to the substrate by the scraper to form the required pattern. Conventional solar cell screen printing adopts the mainstream SP (Single Print) mode, that is, the main and fine grid integrated printing mode. The main grid and fine grid are taken into consideration at the same time in the screen design, and the main and fine grid lines are overlapped after a single printing of the slurry. After printing, the slurry contacts the insulating layer (such as SiNx). The phosphate glass component contained in the slurry is corrosive to a certain extent, and will corrode the SiNx and the underlying passivation layer (such as AlOx) on the contact surface, causing the Ag and Si in the slurry to form a silver-silicon alloy, thereby forming a better ohmic contact.

[0052] Specifically, in the existing screen printing electrode manufacturing process, the battery that has completed a single integrated slurry printing enters the sintering furnace. The first stage of sintering is carried out in the temperature range of 200℃ to 400℃. At this stage, organic binders such as ethyl cellulose and polyvinyl alcohol will be burned. The second stage is carried out at 600℃ to 900℃. This stage is an important step in forming the electrode. At this stage, the phosphate glass material changes from a solid state to a molten state at high temperature, which can corrode the polysilicon layer (such as the emitter layer), play a role in widening the window, and carry the metal conductive phase silver particles forward, melt and corrode the lower dielectric film (such as the emitter layer). The silver particles are melted or reacted by calcination, and further contact is formed with the lower film layer. In this process, the main grid formed by SP integrated printing also corrodes the lower layer, penetrates the insulating layer and the passivation layer (the thickness of the passivation layer is generally greater than or equal to 5nm and less than or equal to 20nm), and the final stay depth is consistent with the fine grid. That is, during the sintering process, as the corrosion proceeds simultaneously, the main gate and the fine gate are in contact with the silicon substrate. However, the main gate will seriously damage the passivation layer during the contact with the silicon substrate. At this time, the open circuit voltage (Uoc) will be reduced, which will affect the photoelectric conversion efficiency. Figure 1 , the main gate 5 contacts the emitter layer 2 on the silicon substrate (i.e., the semiconductor substrate 1), which will also cause the open circuit voltage (Uoc) to decrease, thereby affecting the photoelectric conversion efficiency. It should be noted that the emitter layer 2 can be formed by doping in the original structure of the single crystal silicon semiconductor substrate, such as by diffusion or ion implantation, or it can be an additional layer formed on the surface of the original single crystal silicon semiconductor substrate by deposition or other processes.

[0053] To solve the above technical problems, in a first aspect, an embodiment of the present invention provides a method for manufacturing a solar cell. The method for manufacturing the solar cell includes the following steps:

[0054] Referring to Figure 2 and Figure 3 , first, provide a semiconductor substrate 1.

[0055] In actual application, the specific structure of the above semiconductor substrate can be determined according to the actual application scenario, and no specific limitation is made here. For example: the above semiconductor substrate can be only a semiconductor substrate. Exemplarily, the above semiconductor substrate can be a substrate of semiconductor materials such as a single crystal silicon substrate, a polycrystalline silicon substrate, or an amorphous silicon substrate. In terms of the conduction type, the semiconductor substrate can be an N-type conductive substrate or a P-type conductive substrate. In terms of the structure, the first surface of the semiconductor substrate can be a textured surface to improve the light trapping effect of the light-facing surface of the solar cell, thereby improving the utilization rate of light by the solar cell. Of course, the first surface of the semiconductor substrate can also be a flat surface. As for the second surface of the semiconductor substrate, it can be a polished surface or a textured surface, and no specific limitation is made here. Further, the size of the above semiconductor substrate can be 182, 210, or other semiconductor substrates such as rectangles. The thickness of the semiconductor substrate is generally greater than or equal to 100 microns and less than or equal to 180 microns.

[0056] Next, form an emitter layer 2 on one surface of the semiconductor substrate 1. The conduction types of the semiconductor substrate 1 and the emitter layer 2 are opposite, and the emitter layer 2 and the semiconductor substrate 1 together form a PN junction.

[0057] Exemplarily, the emitter layer is a region doped with impurities of a second conduction type (e.g., N-type) opposite to the first conduction type (e.g., P-type) of the semiconductor substrate. Further, the above emitter layer can be formed by doping in the original structure of the single crystal silicon semiconductor substrate, such as by using common industry means such as diffusion or ion implantation, or can be an additional layer formed on the surface of the original single crystal silicon semiconductor substrate by processes such as deposition. Still further, the above emitter layer is located on the light-receiving surface of the semiconductor substrate. In addition, other descriptions of the emitter layer can refer to the prior art, and no specific limitation is made here.

[0058] Next, form a passivation layer 3 on the emitter layer 2.

[0059] Exemplarily, the material of the above passivation layer 3 can include one or more of aluminum oxide, zinc oxide, and silicon nitride.

[0060] Next, form an insulating layer 4 on the passivation layer 3.

[0061] Exemplarily, the material of the above-mentioned insulating layer 4 may include one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0062] Next, a main gate 5 is formed on the insulating layer 4. The main gate 5 extends along a first direction and is spaced apart along a second direction, and the first direction is different from the second direction.

[0063] Exemplarily, for the above-mentioned first direction and second direction, the two may be any two directions parallel to the surface of the semiconductor substrate and different from each other. Preferably, referring to Figure 3 , the above-mentioned first direction A and second direction B are orthogonal.

[0064] Next, a fine gate 6 is formed on the insulating layer 4. The fine gate 6 extends along the second direction and is spaced apart along the first direction. Each main gate 5 intersects with a plurality of fine gates 6, and the fine gate 6 passes through the passivation layer 3 and the insulating layer 4 and is connected to the emitter layer 2.

[0065] Exemplarily, in the direction towards the semiconductor substrate 1, the above-mentioned fine gate may be connected to the emitter layer through an opening in the passivation layer and the insulating layer, or through a through hole in the passivation layer and the insulating layer, or in other ways. It should be understood that as long as the connection between the fine gate and the emitter layer can be achieved, the connection method is not limited to the above description.

[0066] Among them, the main gate 5 extends in the direction C towards the emitter layer 2. The depth that the main gate 5 extends into the insulating layer 4 exceeds 20% of the thickness D3 of the insulating layer 4, and the depth that the main gate 5 extends into the passivation layer 3 does not exceed 90% of the thickness D2 of the passivation layer 3; the depth direction, the thickness direction of the passivation layer 3, and the thickness direction of the insulating layer 4 are all consistent with the direction towards the semiconductor substrate 1. Exemplarily, the depth D1 that the main gate 5 extends does not exceed 90% of the thickness D2 of the passivation layer 3 and exceeds 20% of the thickness D3 of the insulating layer 4. The depth that the main gate 5 extends into the passivation layer 3 can be 0%, 10%, 15%, 30%, 50%, 80%, or 90% etc. of the thickness of the passivation layer 3.

[0067] In the manufacturing method of the solar cell provided by the embodiment of the present invention, since the main gate 5 is formed on the insulating layer 4 and the main gate 5 extends in the direction towards the emitter layer 2, the depth that the main gate extends into the insulating layer exceeds 20% of the thickness of the insulating layer, and the depth that the main gate extends into the passivation layer does not exceed 90% of the thickness of the passivation layer. At this time, a part of the extended main gate 5 (i.e., a partial region of the main gate) may be only located in the insulating layer 4; it may also be located in both the insulating layer 4 and the passivation layer 3 at the same time, but the depth that the main gate extends into the passivation layer does not exceed 90% of the thickness D2 of the passivation layer 3.

[0068] When the extended partial main grid 5 is only located within the insulating layer 4, the main grid 5 does not damage the passivation layer 3, ensuring the passivation effect of the passivation layer 3. Based on this, the open-circuit voltage can be increased to reduce or avoid the impact on the photoelectric conversion efficiency.

[0069] When the extended partial main grid 5 is located within both the insulating layer 4 and the passivation layer 3, but the depth of the main grid extending into the passivation layer does not exceed 90% of the thickness of the passivation layer 3, compared with the situation in the prior art where the main grid 5 passes through the passivation layer 3 and is connected to the silicon substrate, the degree of damage of the main grid 5 to the passivation layer 3 is reduced, ensuring the passivation effect of the passivation layer 3. Based on this, the open-circuit voltage can be increased, thereby reducing the impact on the photoelectric conversion efficiency. Further, when establishing an electrical connection during the later production of the battery string, the solder tape will cover the main grid 5. Due to the mechanical effects brought by the solder tape (including but not limited to stress, mismatch of expansion coefficients, etc.), it will have an adverse effect on the main grid 5 (for example, the main grid 5 may be peeled off from the solar cell). When the extended partial main grid 5 is located within both the insulating layer 4 and the passivation layer 3, but the depth of the main grid extending into the passivation layer does not exceed 90% of the thickness of the passivation layer 3, the above-mentioned main grid 5 is connected to both the insulating layer 4 and the passivation layer 3 at the same time. At this time, the mechanical properties of the main grid 5 can be ensured, and the tensile characteristics of the main grid 5 can be improved. Based on this, the probability of the main grid 5 detaching from the solar cell can be reduced or eliminated to ensure the quality and performance of the solar cell.

[0070] In an alternative manner, the above-mentioned solar cell can be a back-contact cell.

[0071] As a possible implementation, refer to Figure 2 The ratio of the depth of the main grid 5 extending into the passivation layer 3 to the thickness of the passivation layer 3 is greater than or equal to 20%. Exemplarily, the ratio can be 20%, 30%, 35%, 46%, 50%, etc. At this time, the main grid 5 is connected to both the insulating layer 4 and the passivation layer 3 at the same time. Based on this, the mechanical properties of the main grid 5 can be ensured, and the tensile characteristics of the main grid 5 can be improved to reduce or eliminate the probability of the main grid 5 detaching from the solar cell, thereby ensuring the quality and performance of the solar cell.

[0072] Combined with the previous description, when the main grid 5 extends into the passivation layer 3, the ratio of the depth of the main grid 5 extending into the passivation layer 3 to the thickness of the passivation layer 3 is greater than or equal to 20% and less than or equal to 90%.

[0073] As a possible implementation, the depth of the main grid 5 extending into the passivation layer 3 is 0. That is, the main grid 5 is only located within the insulating layer 4. Specifically, the main grid 5 is only located inside the insulating layer 4, or the main grid 5 is located at the junction of the insulating layer 4 and the passivation layer 3. At this time, the main grid 5 can be prevented from damaging the passivation layer 3 to ensure the passivation effect of the passivation layer 3. Based on this, the open-circuit voltage can be increased to avoid the impact on the photoelectric conversion efficiency.

[0074] As a possible implementation, when the thickness of the above passivation layer is greater than or equal to 5 nm and less than or equal to 20 nm, the depth that the main grid extends into the passivation layer is greater than or equal to 1 nm and less than or equal to 18 nm. For example, the depth that the main grid extends into the passivation layer can be 1 nm, 5 nm, 9 nm, 13 nm, 15 nm, 18 nm, etc.

[0075] Since the depth is greater than or equal to 1 nm, at this time, it can be ensured that the main grid is connected to both the insulating layer and the passivation layer. Based on this, the mechanical properties of the main grid can be guaranteed, the tensile characteristics of the main grid can be improved, so as to reduce or eliminate the probability of the main grid detaching from the solar cell, and further ensure the quality and performance of the solar cell. Further, since the depth is less than or equal to 18 nm, at this time, the damage degree of the main grid to the passivation layer can be reduced, the passivation effect of the passivation layer can be ensured, so as to increase the open-circuit voltage and reduce the influence on the photoelectric conversion efficiency. In addition, it can be ensured that the thickness of more than 2 nm of the passivation layer is not damaged.

[0076] As a possible implementation, the above emitter layer includes a heavily doped region and a lightly doped region. The fine grid is connected to the heavily doped region and forms an alloy region. The depth that the alloy region extends into the emitter layer is less than the junction depth of the emitter of the emitter layer, and both the depth direction and the junction depth direction of the emitter are consistent with the direction towards the semiconductor substrate.

[0077] In an alternative embodiment, when the junction depth of the above emitter is greater than or equal to 300 nm and less than or equal to 1200 nm, the depth that the alloy region extends into the emitter is greater than or equal to 50 nm and less than or equal to 1000 nm. For example, the depth that the alloy region extends into the emitter can be 50 nm, 80 nm, 100 nm, 260 nm, 390 nm, 550 nm, 1000 nm, etc. Since the depth is greater than or equal to 50 nm, at this time, the fine grid can be alloyed with the semiconductor substrate to form a good ohmic contact.

[0078] Preferably, when the junction depth of the emitter is greater than or equal to 300 nm and less than or equal to 1200 nm, the depth that the alloy region extends into the emitter is greater than or equal to 50 nm and less than or equal to 100 nm.

[0079] As a possible implementation, the thickness of the above insulating layer is greater than or equal to 40 nm and less than or equal to 100 nm. For example, the thickness of the insulating layer can be 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc.

[0080] As a possible implementation, see Figure 3, each main grid 5 includes: a main grid connection line 50 and a pad 51. A plurality of pads 51 are arranged at intervals along a first direction on the main grid connection line 50. The width of the pad 51 is greater than the width of the main grid connection line 50. The width directions of both the pad 51 and the main grid connection line 50 are the same as the second direction.

[0081] See Figure 2 and Figure 3 , when the number of the main grid connection lines 50 is the same, compared with the case where the width of the main grid connection line 50 is equal to the width of the pad 51, while ensuring that the current collection ability of the main grid connection line 50 meets the actual requirements, the amount of raw materials used to make the main grid connection line 50 can be reduced, saving raw material costs. At the same time, the shielding of the semiconductor substrate 1 by the main grid connection line 50 can also be reduced, increasing the light-receiving area of the semiconductor substrate 1 and improving the photoelectric conversion efficiency of the solar cell. Further, when making a battery string in the later stage, the solder tape needs to be connected to the pad 51. At this time, compared with the case where the width of the main grid connection line 50 is equal to the width of the pad 51, the solder tape is more easily connected to the pad 51, reducing the manufacturing difficulty and improving the manufacturing efficiency. It should be understood that the specific structures, manufacturing materials, etc. of the above-mentioned main grid connection line 50 and pad 51 can refer to the prior art and are not specifically limited herein.

[0082] In an alternative embodiment, see Figure 3 , the number of the above-mentioned main grids 5 is greater than or equal to 8 and less than or equal to 25. For example, the number of the main grids 5 can be 8, 10, 12, 15, 18, 20, 22 or 25, etc. And / or, the width of the main grid connection line 50 is greater than or equal to 35 microns and less than or equal to 60 microns. For example, the width of the main grid connection line 50 can be 35 microns, 40 microns, 45 microns, 52 microns, 55 microns or 60 microns, etc. The width of the pad 51 is greater than or equal to 0.6 mm and less than or equal to 1.3 mm. For example, the width of the pad 51 can be 0.6 mm, 0.8 mm, 1.0 mm, 1.16 mm, 1.23 mm or 1.3 mm, etc.

[0083] By controlling the number of the main grids 5, the width of the main grid connection line, and the width of the pad, the shielding area of the main grid 5 on the semiconductor substrate 1 can be controlled. At this time, the amount of light injected into the semiconductor substrate 1 can be increased, and the light-receiving area of the semiconductor substrate 1 can be increased to improve the cell efficiency of the solar cell.

[0084] As a possible implementation, see Figure 3, the number of the above-mentioned fine grids 6 is greater than or equal to 100 and less than or equal to 200. For example, the number of the fine grids 6 can be 100, 120, 150, 180, 195, 200, etc. The width of the fine grid 6 is greater than or equal to 20 microns and less than or equal to 45 microns, and the width direction of the fine grid 6 is consistent with the first direction. For example, the width of the fine grid 6 can be 20 microns, 26 microns, 30 microns, 36 microns, 40 microns, 45 microns, etc. At this time, the current collection ability of the fine grid 6 can be improved to improve the cell efficiency of the solar cell.

[0085] As a possible implementation, forming the main grid on the insulating layer includes:

[0086] First, print the main grid raw material on the insulating layer to form an initial main grid.

[0087] Exemplarily, the above-mentioned main grid raw material contains frit and metal. For example, the above-mentioned frit includes one or more of PbO, B2O3, Na2O, Li2O, Bi2O3, WO3, TeO2, Te / W, and the specific ratio can refer to the prior art and will not be specifically limited here. The above-mentioned metal includes but is not limited to silver. Further, the method of printing the main grid raw material can be screen printing, and the specific printing process can refer to the prior art and will not be specifically limited here.

[0088] Next, process the initial main grid to form the main grid.

[0089] Wherein, the ratio of the width of the main grid to the width of the initial main grid is greater than 1 and less than or equal to 1.1, and the width directions of the main grid and the initial main grid are both consistent with the second direction. For example, the ratio can be 1.01, 1.02, 1.04, 1.05, 1.08, 1.09, 1.1, etc.

[0090] In the actual process of manufacturing the main grid, the main grid will not only extend in the direction of the emitter layer, but also extend in the second direction. Therefore, by controlling the size of the finally formed main grid extending in the second direction, not only can the adverse effects on the insulating layer and / or the passivation layer be reduced, and further the adverse effects on the antireflection effect and / or the passivation effect of the solar cell be reduced. At the same time, the shielding of the semiconductor substrate by the main grid can also be reduced, the light-receiving area of the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0091] In addition, the above-mentioned main grid does not extend into the semiconductor substrate. It should be noted that not extending into the semiconductor substrate here means that the metal component (such as silver) in the main grid raw material will not enter the interface of the semiconductor substrate, or the metal component (such as silver) in the main grid raw material will not form an alloy (such as silver-silicon alloy) with the semiconductor material in the semiconductor substrate.

[0092] Preferably, the ratio of the width of the main grid to the width of the initial main grid is greater than 1 and less than or equal to 1.05. For example, the ratio can be 1.01, 1.02, 1.03, 1.04, 1.05, etc.

[0093] As a possible implementation, forming the fine grid on the insulating layer includes:

[0094] First, print the fine grid raw material on the insulating layer to form an initial fine grid.

[0095] Exemplarily, the above fine grid raw material contains frit and metal. For example, the above frit includes one or more of PbO, B2O3, Na2O, Li2O, Bi2O3, WO3, TeO2, Te / W, and the specific ratio can refer to the prior art and will not be specifically limited here. The above metal includes but is not limited to silver. Further, the method of printing the fine grid raw material can be screen printing, and the specific printing process can refer to the prior art and will not be specifically limited here.

[0096] Next, process the initial fine grid to form a fine grid.

[0097] Wherein, the ratio of the width of the fine grid to the width of the initial fine grid is greater than 1 and less than or equal to 1.2, and the width directions of both the fine grid and the initial fine grid are consistent with the first direction. For example, the ratio can be 1.01, 1.02, 1.04, 1.05, 1.08, 1.09, 1.1, 1.2, etc.

[0098] In the actual process of manufacturing the fine grid, the fine grid extends in the second direction, and the corrosiveness of the fine grid raw material is greater than that of the main grid raw material. Therefore, by controlling the size of the finally formed fine grid extending in the second direction, not only can the adverse effects on the insulating layer and / or the passivation layer be reduced, thereby reducing the adverse effects on the antireflection effect and / or the passivation effect of the solar cell. At the same time, it can also reduce the occlusion of the semiconductor substrate by the fine grid, increase the light-receiving area of the semiconductor substrate, and improve the photoelectric conversion efficiency of the solar cell.

[0099] Further, the above fine grid extends to the emitter layer. Under the window opening effect of the phosphoric acid glass, the metal component in the fine grid raw material enters the emitter layer and forms an alloy with the semiconductor component (such as silver-silicon alloy). The silver-silicon alloy formation region greatly improves the contact performance, and the silver-silicon alloy distribution region is within the region covered by the fine grid. The silver-silicon alloy distribution region can be continuous, but due to the migration of silver particles, the distribution of the silver-silicon alloy can be in a discrete and discontinuous form, or both forms coexist. The depth of the silver-silicon alloy distribution region can be adjusted according to the process and the composition of the fine grid raw material. Generally speaking, the higher the frit content, the stronger the extension performance of the fine grid.

[0100] Furthermore, the above-mentioned heavily doped region is generally located under the fine grid, but the heavily doped region can also be located under the main grid. In the embodiment of the present invention, it is preferred that the heavily doped region is located under the fine grid, and no heavily doped region is provided under the main grid. The silver-silicon alloy is distributed in the heavily doped region. However, sometimes the silver-silicon alloy will also migrate laterally beyond the heavily doped region and enter the adjacent lightly doped region. However, the content of the excess part is small and is generally discrete. The total amount of the silver-silicon alloy entering the adjacent lightly doped region does not exceed 10% of the total silver-silicon alloy, and even 5% or less than 2%. The silver-silicon alloy gradually entering the adjacent lightly doped region will have an adverse effect.

[0101] Preferably, the ratio of the width of the fine grid to the width of the initial fine grid is greater than 1 and less than or equal to 1.08. For example, the ratio can be 1.01, 1.02, 1.03, 1.04, 1.05, 1.06, 1.07 or 1.08, etc.

[0102] In an alternative manner, the metal solid content in the raw material for forming the main grid is less than the metal solid content in the raw material for forming the fine grid. That is, the metal solid content in the main grid raw material is less than the metal solid content in the fine grid raw material. Exemplarily, the silver solid content in the above-mentioned main grid raw material is less than the silver solid content in the fine grid raw material.

[0103] At this time, the depth of the main grid extending towards the emitter layer is less than the depth of the fine grid extending towards the emitter layer. Based on this, the damage degree of the main grid to the passivation layer can be reduced to ensure the passivation effect of the passivation layer. Further, when the metal solid content in the fine grid raw material remains unchanged, compared with the situation where the metal solid contents in the main grid raw material and the fine grid raw material are the same in the prior art, not only can the cost of the main grid raw material be reduced to reduce the manufacturing cost of the solar cell. At the same time, it can also ensure that the depth of the fine grid extending towards the emitter layer in the embodiment of the present invention is basically the same as or the same as the depth of the fine grid extending towards the emitter layer in the prior art to ensure that the performance of the fine grid remains unchanged.

[0104] In addition, when adjusting the extension depths of the main grid and the fine grid, it can be achieved by controlling the specific components of the main grid raw material and the fine grid raw material. For example, it can be adjusted by increasing the frit content or metal content in the main grid raw material and the fine grid raw material.

[0105] In a second aspect, the embodiment of the present invention also provides a solar cell. See Figure 2 and Figure 3, the solar cell includes: a semiconductor substrate 1, an emitter layer 2, a passivation layer 3, an insulating layer 4, a main grid 5, and a fine grid 6. The emitter layer 2 is located on one side of the semiconductor substrate 1. The semiconductor substrate 1 and the emitter layer 2 have opposite conductivity types, and the emitter layer 2 and the semiconductor substrate 1 together form a PN junction. The passivation layer 3 is located on the emitter layer 2, and the insulating layer 4 is located on the passivation layer 3. The main grid 5 is located on the insulating layer 4. The main grid 5 extends in a first direction and is spaced apart in a second direction. The first direction is different from the second direction. The fine grid 6 is located on the insulating layer 4. The fine grid 6 extends in the second direction and is spaced apart in the first direction. Each main grid 5 intersects with multiple fine grids 6. The fine grid 6 passes through the passivation layer 3 and the insulating layer 4 and is connected to the emitter layer 2. Among them, the main grid 5 extends toward the emitter layer 2. The depth that the main grid 5 extends into the insulating layer 4 exceeds 20% of the thickness D3 of the insulating layer 4, and the depth that the main grid 5 extends into the passivation layer 3 does not exceed 90% of the thickness D2 of the passivation layer 3; the depth direction, the thickness direction of the passivation layer 3, and the thickness direction of the insulating layer 4 are all consistent with the direction toward the semiconductor substrate 1. Exemplarily, the depth D1 that the main grid 5 extends does not exceed 90% of the thickness D2 of the passivation layer 3 and exceeds 20% of the thickness D3 of the insulating layer 4. The depth that the main grid 5 extends into the passivation layer 3 can be 0%, 10%, 15%, 30%, 50%, 80%, or 90% of the thickness of the passivation layer 3, etc.

[0106] For the relevant information of the above semiconductor substrate 1, emitter layer 2, passivation layer 3, and insulating layer 4, reference can be made to the description in the first aspect, which will not be elaborated here. Further, for the above first direction and second direction, the two can be any two directions parallel to the surface of the semiconductor substrate 1 and different from each other. Preferably, referring to Figure 3 , the above first direction A and second direction B are orthogonal.

[0107] In the solar cell provided by the embodiment of the present invention, since the main grid 5 is formed on the insulating layer 4 and the main grid 5 extends toward the emitter layer 2, the depth that the main grid extends into the insulating layer exceeds 20% of the insulating layer thickness, and the depth that the main grid extends into the passivation layer does not exceed 90% of the passivation layer thickness. At this time, a part of the extended main grid 5 (i.e., a part of the main grid) may be only located in the insulating layer 4; it may also be located in both the insulating layer 4 and the passivation layer 3 at the same time, but the depth that the main grid extends into the passivation layer does not exceed 90% of the thickness of the passivation layer 3.

[0108] When a part of the extended main grid 5 is only located in the insulating layer 4, the main grid 5 does not damage the passivation layer 3, ensuring the passivation effect of the passivation layer 3. Based on this, the open-circuit voltage can be increased to reduce or avoid the influence on the photoelectric conversion efficiency.

[0109] When the extended partial main grid 5 is located within both the insulating layer 4 and the passivation layer 3 simultaneously, and the depth that the main grid extends into the passivation layer does not exceed 90% of the thickness of the passivation layer 3, compared with the situation in the prior art where the main grid 5 penetrates through the passivation layer 3 to connect with the silicon substrate, the degree of damage of the main grid 5 to the passivation layer 3 is reduced, ensuring the passivation effect of the passivation layer 3. Based on this, the open-circuit voltage can be increased, thereby reducing the impact on the photoelectric conversion efficiency. Further, the above-mentioned main grid 5 is connected to both the insulating layer 4 and the passivation layer 3 simultaneously. At this time, the mechanical properties of the main grid 5 can be ensured, and the tensile characteristics of the main grid 5 can be improved. Based on this, the probability of the main grid 5 detaching from the solar cell can be reduced or eliminated to ensure the quality and performance of the solar cell.

[0110] As a possible implementation, refer to Figure 2 , the ratio of the depth that the above-mentioned main grid 5 extends into the passivation layer 3 to the thickness of the passivation layer 3 is greater than or equal to 20%. Exemplarily, the ratio can be 20%, 30%, 35%, 46%, 50%, etc. At this time, the main grid 5 is connected to both the insulating layer 4 and the passivation layer 3 simultaneously. At this time, the mechanical properties of the main grid 5 can be ensured, and the tensile characteristics of the main grid 5 can be improved to reduce or eliminate the probability of the main grid 5 detaching from the solar cell, thereby ensuring the quality and performance of the solar cell.

[0111] Combined with the previous description, when the main grid 5 extends into the passivation layer 3, the ratio of the depth that the main grid 5 extends into the passivation layer 3 to the thickness of the passivation layer 3 is greater than or equal to 20% and less than or equal to 90%.

[0112] As a possible implementation, the depth that the above-mentioned main grid extends into the passivation layer is 0. That is, the main grid is only located within the insulating layer. Specifically, the main grid is only located inside the insulating layer, or the main grid is located at the junction of the insulating layer and the passivation layer. At this time, the passivation layer can be prevented from being damaged by the main grid to ensure the passivation effect of the passivation layer. Based on this, the open-circuit voltage can be increased, avoiding the impact on the photoelectric conversion efficiency.

[0113] As a possible implementation, when the thickness of the above-mentioned passivation layer is greater than or equal to 5 nm and less than or equal to 20 nm, the depth that the main grid extends into the passivation layer is greater than or equal to 1 nm and less than or equal to 18 nm. For example, the depth that the main grid extends into the passivation layer can be 1 nm, 5 nm, 9 nm, 13 nm, 15 nm, or 18 nm.

[0114] Since the depth is greater than or equal to 1 nm, at this time, it can be ensured that the main grid is connected to both the insulating layer and the passivation layer simultaneously. Based on this, the mechanical properties of the main grid can be guaranteed, the tensile characteristics of the main grid can be improved, so as to reduce or eliminate the probability of the main grid detaching from the solar cell, and further ensure the quality and performance of the solar cell. Further, since the depth is less than or equal to 18 nm, at this time, the degree of damage to the passivation layer by the main grid can be reduced, the passivation effect of the passivation layer can be ensured, so as to increase the open-circuit voltage and reduce the impact on the photoelectric conversion efficiency.

[0115] As a possible implementation manner, the above emitter layer includes a heavily doped region and a lightly doped region. The fine grid is connected to the heavily doped region and forms an alloy region. The depth of the alloy region extending into the emitter layer is less than the junction depth of the emitter of the emitter layer, and both the depth direction and the junction depth direction of the emitter are consistent with the direction towards the semiconductor substrate.

[0116] In an alternative manner, when the junction depth of the above emitter is greater than or equal to 300 nm and less than or equal to 1200 nm, the depth of the alloy region extending into the emitter is greater than or equal to 50 nm and less than or equal to 1000 nm. For example, the depth of the alloy region extending into the emitter can be 50 nm, 80 nm, 100 nm, 260 nm, 390 nm, 550 nm, 1000 nm, etc. Since the depth is greater than or equal to 50 nm, at this time, the fine grid can be alloyed with the semiconductor substrate to form a good ohmic contact.

[0117] Preferably, when the junction depth of the emitter is greater than or equal to 300 nm and less than or equal to 1200 nm, the depth of the alloy region extending into the emitter is greater than or equal to 50 nm and less than or equal to 100 nm.

[0118] As a possible implementation manner, the thickness of the above insulating layer is greater than or equal to 40 nm and less than or equal to 100 nm. For example, the thickness of the insulating layer can be 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc.

[0119] As a possible implementation manner, see Figure 3 , each main grid 5 includes: a main grid connection line 50 and a pad 51. A plurality of pads 51 are arranged at intervals along the first direction on the main grid connection line 50, the width of the pad 51 is greater than the width of the main grid connection line 50, and both the width direction of the pad 51 and the width direction of the main grid connection line 50 are consistent with the second direction.

[0120] When the number of main grid connection lines 50 is the same, compared with the case where the width of the main grid connection line 50 is equal to the width of the pad 51, while ensuring that the current collection ability of the main grid connection line 50 meets the actual needs, the amount of raw materials for manufacturing the main grid connection line 50 can be reduced, saving raw material costs. At the same time, the shielding of the semiconductor substrate 1 by the main grid connection line 50 can also be reduced, increasing the light-receiving area of the semiconductor substrate 1 and improving the photoelectric conversion efficiency of the solar cell. Further, when manufacturing a battery string in the later stage, the solder strip needs to be connected to the pad 51. At this time, compared with the case where the width of the main grid connection line 50 is equal to the width of the pad 51, the solder strip is more easily connected to the pad 51, reducing the manufacturing difficulty and improving the manufacturing efficiency. It should be understood that the specific structures, manufacturing materials, etc. of the above main grid connection line 50 and pad 51 can refer to the prior art and are not specifically limited herein.

[0121] In an alternative embodiment, referring to Figure 3 , the number of the above main grids 5 is greater than or equal to 8 and less than or equal to 25. For example, the number of the main grids 5 can be 8, 10, 12, 15, 18, 20, 22, or 25, etc.

[0122] And / or, the width of the main grid connection line 50 is greater than or equal to 35 microns and less than or equal to 60 microns. For example, the width of the main grid connection line 50 can be 35 microns, 40 microns, 45 microns, 52 microns, 55 microns, or 60 microns, etc. The width of the pad 51 is greater than or equal to 0.6 mm and less than or equal to 1.3 mm. For example, the width of the pad 51 can be 0.6 mm, 0.8 mm, 1.0 mm, 1.16 mm, 1.23 mm, or 1.3 mm, etc.

[0123] By controlling the number of the main grids 5, the width of the main grid connection line, and the width of the pad, the shielding area of the main grid 5 on the semiconductor substrate 1 can be controlled. At this time, the amount of light injected into the semiconductor substrate 1 can be increased, and the light-receiving area of the semiconductor substrate 1 can be increased to improve the cell efficiency of the solar cell.

[0124] As a possible implementation, referring to Figure 3 , the number of the above fine grids 6 is greater than or equal to 100 and less than or equal to 200. For example, the number of the fine grids 6 can be 100, 120, 150, 180, 195, or 200, etc. The width of the fine grid 6 is greater than or equal to 20 microns and less than or equal to 45 microns, and the width direction of the fine grid 6 is the same as the first direction. For example, the width of the fine grid 6 can be 20 microns, 26 microns, 30 microns, 36 microns, 40 microns, or 45 microns, etc. At this time, the current collection ability of the fine grid 6 can be improved to improve the cell efficiency of the solar cell.

[0125] In a third aspect, an embodiment of the present invention further provides a battery string. The battery string includes a plurality of solder tapes and a plurality of solar cells arranged at intervals as described in the above technical solution, and the solder tapes are correspondingly connected to the main grids.

[0126] The beneficial effects of the battery string provided by the embodiment of the present invention are the same as those of the solar cell described in the above technical solution, and will not be elaborated here.

[0127] As a possible implementation manner, when the above main grid includes a main grid connection line and a pad, the solder tape is arranged on the pad along a first direction and covers the main grid connection line. The maximum width of the solder tape is less than or equal to the width of the pad, and the width directions of the solder tape and the pad are both consistent with a second direction. At this time, the shielding of the semiconductor substrate by the solder tape can be reduced, the light-receiving area of the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0128] In an optional manner, the width of the above solder tape is less than or equal to the width of the main grid connection line, and the width directions of the solder tape and the main grid connection line are both consistent with the second direction. At this time, the shielding of the semiconductor substrate by the solder tape can be reduced, the light-receiving area of the semiconductor substrate can be increased, and the photoelectric conversion efficiency of the solar cell can be improved.

[0129] In an optional manner, the ratio of the width of the above solder tape to the width of the main grid connection line is greater than or equal to 50% and less than or equal to 90%. For example, the ratio can be 50%, 60%, 65%, 70%, 80% or 90%, etc.

[0130] Since the solder tape includes a core layer made of a metal material and a solder layer on the outer surface of the core layer. During the actual welding process of the solder tape and the pad, the solder layer melts and has a certain fluidity. Since the above ratio is greater than or equal to 50% and less than or equal to 90%, the flowing solder can be distributed at the interface between the solder tape and the main grid connection line, giving it sufficient flow space. At this time, the solder can be prevented from flowing onto the semiconductor substrate to avoid solder contamination and shielding of the semiconductor substrate, thereby ensuring the quality and performance of the solar cell.

[0131] In the embodiment of the present invention, the number of solder tapes is the same as the number of main grid connection lines.

[0132] In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0133] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims described above.

Claims

1. A method for manufacturing a solar cell, characterized in that, Comprising: Providing a semiconductor substrate; Forming an emitter layer on one side of the semiconductor substrate; The semiconductor substrate and the emitter layer have opposite conductivity types, and the emitter layer and the semiconductor substrate jointly form a PN junction; Forming a passivation layer on the emitter layer; Forming an insulating layer on the passivation layer; Forming a main gate on the insulating layer; The main gate extends in a first direction and is spaced apart in a second direction; the first direction is different from the second direction; Forming a fine gate on the insulating layer; the fine gate extends in the second direction and is spaced apart in the first direction; each main gate intersects with a plurality of the fine gates; the fine gate passes through the passivation layer and the insulating layer and is connected to the emitter layer; Wherein, the main gate extends towards the emitter layer, the depth of the main gate extending into the insulating layer exceeds 20% of the thickness of the insulating layer, and the depth of the main gate extending into the passivation layer does not exceed 90% of the thickness of the passivation layer; the depth direction, the thickness direction of the passivation layer, and the thickness direction of the insulating layer are all consistent with the direction towards the semiconductor substrate.

2. The manufacturing method of the solar cell according to claim 1, characterized in that The metal solid content in the raw material for forming the main gate is less than the metal solid content in the raw material for forming the fine gate.

3. A solar cell, characterized in that, Comprising: A semiconductor substrate; An emitter layer located on one side of the semiconductor substrate; The semiconductor substrate and the emitter layer have opposite conductivity types, and the emitter layer and the semiconductor substrate jointly form a PN junction; A passivation layer located on the emitter layer; An insulating layer located on the passivation layer; A main gate located on the insulating layer; The main gate extends in a first direction and is spaced apart in a second direction; the first direction is different from the second direction; A fine gate located on the insulating layer; the fine gate extends in the second direction and is spaced apart in the first direction; each main gate intersects with a plurality of the fine gates; the fine gate passes through the passivation layer and the insulating layer and is connected to the emitter layer; Wherein, the main gate extends towards the emitter layer, the depth of the main gate extending into the insulating layer exceeds 20% of the thickness of the insulating layer, and the depth of the main gate extending into the passivation layer does not exceed 90% of the thickness of the passivation layer; the depth direction, the thickness direction of the passivation layer, and the thickness direction of the insulating layer are all consistent with the direction towards the semiconductor substrate.

4. The solar cell according to claim 3, wherein The ratio of the depth of the main gate extending into the passivation layer to the thickness of the passivation layer is greater than or equal to 20%; or, The depth of the main gate extending into the passivation layer is 0.

5. The solar cell according to claim 3, characterized in that, When the thickness of the passivation layer is greater than or equal to 5 nm and less than or equal to 20 nm, the depth of the main gate extending into the passivation layer is greater than or equal to 1 nm and less than or equal to 18 nm.

6. The solar cell according to claim 3, characterized in that, Each main gate includes: a main gate connection line and a pad; A plurality of the pads are arranged at intervals along the first direction on the main gate connection line; The width of the pad is greater than the width of the main gate connection line, and the width directions of the pad and the main gate connection line are both consistent with the second direction.

7. The solar cell according to claim 6, wherein the number of the main grids is greater than or equal to 8 and less than or equal to 25; and / or the width of the main grid connection line is greater than or equal to 35 microns and less than or equal to 60 microns; the width of the pad is greater than or equal to 0.6 mm and less than or equal to 1.3 mm.

8. The solar cell according to claim 3 or 6 or 7, wherein the number of the fine grids is greater than or equal to 100 and less than or equal to 200; the width of the fine grid is greater than or equal to 20 microns and less than or equal to 45 microns; the width direction of the fine grid is consistent with the first direction.

9. A battery string, characterized in that, comprising a plurality of solder tapes and a plurality of solar cells arranged at intervals as described in any one of claims 3 to 8; the solder tape is correspondingly connected to the main grid.

10. The battery string according to claim 9, characterized in that, When the main grid includes a main grid connection line and a pad, the solder tape is disposed on the pad along the first direction and covers the main grid connection line; the maximum width of the solder tape is less than or equal to the width of the pad; the width directions of the solder tape and the pad are both consistent with the second direction.

11. The battery string according to claim 10, wherein, The width of the solder tape is less than or equal to the width of the main grid connection line; the width directions of the solder tape and the main grid connection line are both consistent with the second direction.

12. The battery string according to claim 10 or 11, characterized in that, The ratio of the width of the solder tape to the width of the main grid connection line is greater than or equal to 50% and less than or equal to 90%.

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