Back contact battery and preparation method thereof
By etching paste paste and preparing ohmic contact metal layer, the damage problem of the laser groove process to the doped layer of the cell is solved, improving the pressure opening performance of the cell and reducing production costs.
Patent Information
- Application Number
- CN202510403379.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-01
- Publication Date
- 2025-06-27
AI Technical Summary
When removing the anti-reverse passivation layer, the laser groove process is difficult to control energy, and it is easy to damage the P-type polysilicon doped layer, the N-type polysilicon doped layer and the tunneling layer, resulting in damage to the opening pressure of the battery.
Pattern etching of the passivation layer is performed by etching paste, and the passivation layer on the side of the P-type polysilicon doped layer and the N-type polysilicon doped layer are removed, and the doped layer of the cell is exposed, and an ohmic contact metal layer and metal gate lines are prepared thereon.
It effectively avoids damage to the doped layer by the laser process, improves the pressure opening performance of the battery cell, and reduces production costs and process complexity.
Smart Images
Figure CN120224832A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of crystalline silicon solar cell manufacturing, and particularly relates to a back contact battery and a preparation method thereof. Background Art
[0002] A back contact battery (BC battery) is a photovoltaic battery with high conversion efficiency and characteristics such as being suitable as a tandem battery, etc., and is regarded as one of the important development directions of the future photovoltaic industry.
[0003] In the past, most of the metal grid lines of BC batteries were prepared by the current printing and coating conductive silver paste process. Although it is simple and easy to operate, it loses part of the electrical gain, that is, due to the electrical loss of the high-resistivity silver paste during carrier collection, namely Rs is too high. Moreover, since the metal grid line area of the existing BC battery is greater than 15% or more, it also makes the cost of preparing the conductive grid line with conductive silver paste high, making the manufacturing cost of BC batteries far exceed that of general battery wafers. Therefore, the industry introduces the process of electroplating copper grid lines to replace the expensive conductive silver paste.
[0004] In the conventional process, after the outermost anti-reflection passivation layer of the BC battery wafer is prepared, the anti-reflection passivation layer (commonly such as silicon nitride) is locally removed by a laser process. But this is an ideal state. In fact, since the battery wafer is not completely flat, it is very difficult to control the energy of the laser. In fact, not only the outermost anti-reflection passivation layer is removed, but also the P-type polysilicon doping layer, the N-type polysilicon doping layer and the tunneling layer are damaged. Eventually, the open-circuit voltage of the battery wafer is damaged by up to 2 - 10 mV. Summary of the Invention
[0005] To overcome the above-mentioned drawbacks, one of the purposes of the present invention is to provide a back contact battery and a preparation method thereof, which solve the problem that laser grooving will damage the P-type polysilicon doping layer, the N-type polysilicon doping layer and the tunneling layer.
[0006] To achieve the above purpose, the technical solution adopted by the present invention is: a preparation method of a back contact battery, including the following steps: Step S1: Perform passivation layer patterning etching through an etching paste, etch and remove the passivation layer on one side of the P-type polysilicon doping layer and the N-type polysilicon doping layer to expose the P-type polysilicon doping layer and the N-type polysilicon doping layer of the battery wafer; Step S2: Prepare an ohmic contact metal layer on the P-type polysilicon doping layer and the N-type polysilicon doping layer; Step S3: Prepare a metal grid line and a protective layer on the side of the ohmic contact metal layer away from the battery wafer body through an electroplating deposition process.
[0007] Further, in step S1, an etching paste is coated on the surface of the passivation layer through a screen printing process. The screen mesh count ranges from 150 meshes to 300 meshes; the wire diameter of the steel wire ranges from 15 μm to 30 μm; the screen tension control range is from 20 Newtons to 30 Newtons; the printing speed range is from 100 mm / sec to 500 mm / sec; the downward pressure range is from 20 Newtons to 50 Newtons.
[0008] Further, the heating temperature range for the etching paste to etch the passivation layer is from 200 °C to 400 °C; the heating time is from 30 seconds to 600 seconds.
[0009] Further, in step S2, a nickel ohmic metal layer is deposited on the N-type polysilicon doping layer through an electroplating process, and then an aluminum ohmic metal layer is deposited on the back surface of the cell through a vacuum high-temperature deposition process.
[0010] Further, in step S2, a nickel ohmic metal layer is deposited on the surfaces of the exposed P-type polysilicon doping layer and N-type polysilicon doping layer of the cell through a vacuum high-temperature deposition process.
[0011] Further, in step S3, the following steps are included: a barrier layer is prepared on the side of the ohmic contact metal layer away from the cell body through an electroplating deposition process.
[0012] Further, in step S3, the following steps are also included: a barrier layer is prepared on the back surface of the cell through a vacuum deposition process.
[0013] Further, in step S3, the following steps are also included: a seed layer is prepared on the side of the barrier layer away from the cell through a vacuum deposition process.
[0014] Further, in step S3, a mask layer is prepared on the back surface of the cell through a patterning process, and a metal grid line and a protective layer are prepared by electroplating deposition at the opening of the mask layer.
[0015] The present invention also provides a back-contact cell, which is prepared by the preparation method of the back-contact cell described above.
[0016] The beneficial effects of the present invention are: 1) By using an etching process to etch and remove the passivation layer, replacing the removal of the passivation layer through a laser process, the technical problems of difficult control of laser energy and damage to the P-type polysilicon doping layer, N-type polysilicon doping layer and tunneling layer are solved, and the open voltage of the cell is improved.
[0017] 2) By replacing the laser process with an etching process, expensive laser equipment is not required, reducing the production cost.
[0018] 3) Directly etch the passivation layer with an etching paste. Compared with the etching process of using a masking material in combination with an etching solution, there is no need to use a masking material, and there is no need to perform exposure process, development process, and stripping process on the masking material in the later stage. In addition to saving material costs and reducing production costs, it can also shorten the process flow and improve the overall production efficiency of the battery cells. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The drawings forming a part of this application are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention.
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0021] Figure 1 Schematic diagram of the back contact battery cell of the present invention; Figure 2 Schematic diagram of coating the etching paste on the passivation layer of the present invention; Figure 3 Schematic diagram of the opening of the passivation layer of the present invention; Figure 4 Schematic diagram of depositing a nickel ohmic contact metal layer of the present invention; Figure 5 Schematic diagram of the back contact battery prepared in Example 1 of the present invention; Figure 6 Schematic diagram of preparing a nickel ohmic contact metal layer on the N-type polysilicon doping layer of the present invention; Figure 7 Schematic diagram of preparing an aluminum ohmic contact metal layer on the P-type polysilicon doping layer of the present invention; Figure 8 Schematic diagram of the back contact battery prepared in Example 2 of the present invention; Figure 9 Schematic diagram of depositing a barrier layer and a seed layer on the nickel ohmic contact metal layer of the present invention; Figure 10 Schematic diagram of setting a mask layer on the seed layer of the present invention; Figure 11 Schematic diagram of electroplating to prepare a metal grid line and a protective layer at the opening of the mask layer of the present invention; Figure 12 Schematic diagram of removing the mask layer of the present invention; Figure 13 Schematic diagram of the back contact battery prepared in Example 3 of the present invention; Figure 14 Schematic diagram of the back-contact battery prepared in Embodiment 4 of the present invention; Figure 15 Schematic diagram of preparing a mask layer on the seed layer in Embodiment 5 of the present invention; Figure 16 Schematic diagram of electroplating to prepare metal grid lines and a protective layer at the opening of the mask layer in Embodiment 5; Figure 17 Schematic diagram of removing the mask layer in Embodiment 5 of the present invention; Figure 18 Schematic diagram of the back-contact battery prepared in Embodiment 5 of the present invention; Figure 19 Schematic diagram of the back-contact battery prepared in Embodiment 6 of the present invention; Figure 20 is a comparison diagram of removing the passivation layer by a laser process and by an etching paste, where Figure 20a is the SEM image of the cell after removing the passivation layer by the laser process; Figure 20b is the SEM image of the cell after etching the passivation layer with the etching paste.
[0022] Wherein: 1. Cell; 2. N-type polysilicon doped layer; 3. P-type polysilicon doped layer; 4. Passivation layer; 4a. Aluminum oxide layer; 4b. Silicon nitride layer; 5. Etching paste; 6. Passivation layer opening; 7. Ohmic contact metal layer; 7a. Nickel ohmic contact metal layer; 7b. Aluminum ohmic contact metal layer; 8. Barrier layer; 9. Metal grid line; 10. Protective layer; 11. Seed layer; 12. Mask layer; 13. Mask layer opening. Detailed implementation manners
[0023] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following provides a detailed description of the specific implementation manners of the present invention. Many specific details are set forth in the following description to facilitate a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without departing from the connotation of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed below.
[0024] Unless otherwise indicated in the operating examples or otherwise stated, all numbers representing amounts of ingredients, physical and chemical properties, etc. in the specification and claims are understood to be adjusted by the term "about" in all cases. Therefore, unless otherwise stated, the numerical parameters listed in the above specification and appended claims are approximate values, and those skilled in the art can, using the teachings disclosed herein, seek to obtain the desired characteristics and appropriately change these approximate values. The use of numerical ranges expressed in terms of endpoints includes all numbers within that range and any range within that range. For example, 1 to 5 includes 1, 1.1, 1.3, 1.5, 2, 2.75, 3, 3.80, 4, and 5, and so on.
[0025] The applicant found that when locally removing the antireflection passivation layer (commonly silicon nitride) by laser process, since the battery wafer is not completely flat, it is very difficult to control the energy of the laser. In fact, not only the outermost antireflection passivation layer is removed, but also the P-type polysilicon doping layer, the N-type polysilicon doping layer and the tunneling layer are damaged.
[0026] An embodiment of the present invention provides a method for manufacturing a back contact battery to solve the above problems, which specifically includes the following steps: Step S1, performing patterned etching on the passivation layer through an etching paste, etching and removing the passivation layer on one side of the P-type polysilicon doping layer and the N-type polysilicon doping layer to expose the P-type polysilicon doping layer and the N-type polysilicon doping layer of the battery wafer.
[0027] The passivation layer includes a silicon nitride layer and / or an aluminum oxide layer provided on the back surface of the battery wafer. By etching the passivation layer through an etching process to replace removing the passivation layer by laser process, the technical problems of difficult control of laser energy and damage to the P-type polysilicon doping layer, the N-type polysilicon doping layer and the tunneling layer are solved, and the open-circuit voltage of the battery wafer is improved.
[0028] Specifically, directly performing patterned etching on the passivation layer through the etching paste has simple steps and convenient operation. Coating the etching paste on the surface of the passivation layer through a screen printing process: the mesh number range of the screen plate is 150 meshes to 300 meshes; the wire diameter range of the steel wire is 15 μm to 30 μm; the screen plate tension control range is 20 Newtons to 30 Newtons; the printing speed range is 100 mm / sec to 500 mm / sec; the downward pressure range is 20 Newtons to 50 Newtons. The operating conditions for etching the passivation layer with the etching paste are: the heating temperature range is 200°C to 400°C; the heating time is 30 seconds to 600 seconds. After etching and removing the passivation layer, soak it in hot water at 75°C to 100°C for 30 seconds to 600 seconds to clean the etching paste. After cleaning and drying, the P-type polysilicon doping layer and the N-type polysilicon doping layer of the battery wafer are exposed.
[0029] The etching paste is a fluorine-containing compound, and its components are selected from any one or more of ammonium bifluoride, ammonium fluoride, sodium bifluoride, sodium fluoride, potassium bifluoride, potassium fluoride, barium fluoride, ammonium fluoroborate. These fluorine-containing compounds are the main active components of the etching paste and can effectively etch materials such as silicon, silicon oxide, and silicon nitride. The etching paste used in this application is purchased from Xiamen Haole New Materials Co., Ltd., and the model is HR-868.
[0030] The passivation layer can also be etched by an etching process using a mask material in combination with an etching solution. Specifically: A mask layer is patterned on the surface of the cell, and then the passivation layer at the mask opening is etched by the etching solution to expose the P-type polysilicon doped layer and the N-type polysilicon doped layer of the cell, and then the mask layer is removed by a stripping solution. The etching solution is generally an acid solution such as HF and H3PO4, and the stripping solution is generally an alkaline solution such as KOH or NaOH.
[0031] In the technical solution of the present application, the passivation layer is directly etched by an etching paste. Compared with the etching process using a mask material in combination with an etching solution, there is no need to use a mask material, and there is no need to perform an exposure process, a development process, and a stripping process on the mask material in the later stage. In addition to saving material costs (the costs of the mask material, the etching solution, the developer, and the stripping solution), reducing production costs, the process flow can also be shortened, improving the overall production yield of the cell.
[0032] Step S2: Prepare an ohmic contact metal layer on the P-type polysilicon doped layer and the N-type polysilicon doped layer; In some embodiments, an ohmic metal layer is deposited on the surfaces of the exposed P-type polysilicon doped layer and N-type polysilicon doped layer of the cell by a vacuum high-temperature deposition process.
[0033] Specifically, an ohmic contact metal layer is deposited by a PVD vacuum device; the deposition materials are single metals or alloys such as nickel, titanium, and aluminum, and the material is preferably nickel. The deposition thickness range is 5 nm to 200 nm. The specific operating condition range is: the operating power is 1 KW to 10 KW, the time is 30 seconds to 600 seconds, and the temperature control range is 200 °C to 650 °C.
[0034] In other embodiments, the ohmic contact metal layer includes first depositing a nickel ohmic metal layer on the N-type polysilicon doped layer by an electroplating process, and then depositing an aluminum ohmic metal layer on the back of the cell by a vacuum high-temperature deposition process.
[0035] Specifically, by an electroplating process, a nickel ohmic contact metal layer is deposited on the N-type polysilicon doped layer; the deposition thickness range is 0.01 μm to 5 μm. Then, an aluminum ohmic contact metal layer is prepared by a heating furnace device, the temperature control range is 200 °C to 650 °C, and the heating time is 30 seconds to 600 seconds.
[0036] By depositing a nickel ohmic contact metal layer on the N-type polysilicon doped layer and an aluminum ohmic contact metal layer on the P-type polysilicon doped layer, the problem that in the existing process, a full nickel metal or a full aluminum metal deposition is performed without making a selection process for the P side to form an ohmic contact with the aluminum metal and the N side to form an ohmic contact with the nickel metal, resulting in a decrease in the open voltage of the battery, is solved.
[0037] Step S3: Prepare a metal grid line and a protective layer on the side of the ohmic contact metal layer away from the battery cell body through an electroplating deposition process. The metal grid line is a copper conductive grid line layer with a thickness range of 5 μm to 50 μm; the protective layer is a tin conductive grid line layer with a thickness range of 0.1 μm to 5 μm.
[0038] In some embodiments, remove the nickel metal layer and the aluminum metal layer that did not react with the polysilicon doping layer; retain the nickel silicide layer and the aluminum silicide layer (ohmic contact metal layer).
[0039] Specifically, prepare an etching solution with hydrochloric acid at a volume ratio of 1% to 3% and formic acid at a volume ratio of 1% to 5%, and perform an etching process with an etching time of 30 seconds to 300 seconds and an etching temperature of 30°C to 60°C to remove the unreacted nickel, titanium, and aluminum metal layers on the surface of the battery cell.
[0040] In some embodiments, prepare a barrier layer on the side of the ohmic contact metal layer away from the battery cell body through an electroplating deposition process. The barrier layer is a nickel barrier layer with a thickness range of 0.1 μm to 3 μm. In the electrode structure of the battery cell, metals (such as silver, aluminum, copper, etc.) may diffuse into the semiconductor material (such as silicon or the oxide / phosphate in the lithium electrode), resulting in a decline in electrode performance. By setting the barrier layer, the diffusion of metal atoms can be effectively prevented, maintaining the integrity and stability of the electrode material.
[0041] In some other embodiments, prepare a barrier layer on the back of the battery cell through a vacuum deposition process. The barrier layer material is selected from a single metal such as titanium, tungsten, or an alloy thereof, and the deposition thickness range of the barrier layer is 5 nm to 200 nm. The operating power of the deposition process is 1 KW to 10 KW, the time is 30 seconds to 600 seconds, and the temperature control range is 200°C to 650°C to prepare the barrier layer.
[0042] In some embodiments, prepare a seed layer on the side of the barrier layer away from the battery cell through a vacuum deposition process. Specifically, deposit a bottom seed layer with a PVD vacuum device; the bottom seed layer material is selected from a single metal such as copper, bismuth, gold, silver, or an alloy thereof, and the deposition thickness range is 10 nm to 300 nm. The specific operating condition range is an operating power of 1 KW to 10 KW, a time of 30 seconds to 600 seconds, and a temperature control range of 200°C to 650°C.
[0043] In some embodiments, prepare a mask layer on the back of the battery cell through a patterning process, and electroplate and deposit a metal grid line and a protective layer at the opening of the mask layer.
[0044] In some embodiments, the masking material is a dry masking material (commonly known as dry film) or a liquid masking material. Combined with the exposure and development process, the area of the metal gate line to be electroplated is exposed; the film thickness range is 10um to 50um. The exposure conditions are that the light wavelength range includes but is not limited to 365nm or 405nm and the light intensity range is 10mW / cm 2 ~20mW / cm 2 for image transfer. The developer includes KOH with a concentration ratio of 0.5% to 5% or NaOH with a concentration ratio of 0.5 to 5%; the operating conditions are a temperature of 25°C to 35°C, a time of 30 seconds to 600 seconds, and a spraying pressure of 2.0Kg / cm 2 ~2.5Kg / cm 2 to expose the area to be electroplated. The formed opening width range is 10um to 300um.
[0045] In some other embodiments, the area to be electroplated is exposed by intaglio printing combined with a drying process (without the need for exposure and development processes). The formed opening width range is 50um to 600um.
[0046] In some embodiments, the following steps are further included: removing the masking layer. The battery cell is transferred into the masking removal tank section for the masking removal process, and the operating temperature range is 45°C to 55°C. The operating spraying pressure is 0.5Kg / cm 2 ~2.5Kg / cm 2 . The suitable operating concentration range is 0.5% to 1.5%, and the operating time is 30 seconds to 600 seconds.
[0047] In some embodiments, the following steps are further included: etching the seed layer to remove the seed layer on the back of the battery. The etching solution is 3% to 5% dilute sulfuric acid. The process operating conditions: the temperature is room temperature; the time is 30 seconds to 600 seconds; the spraying pressure is 0.5Kg / cm 2 ~2.5Kg / cm 2 to etch the seed layer.
[0048] In some embodiments, the following steps are further included: etching the barrier layer to remove the barrier layer on the back of the battery. The etching process, the volume concentration is 1% to 5% hydrogen peroxide H2O2. The operating temperature range is 45°C to 55°C, the time is 30 seconds to 600 seconds, and the spraying pressure is 0.5Kg / cm 2 ~2.5Kg / cm 2 .
[0049] In some embodiments, the following process steps are further included: etching the metal layer that has not reacted with the polysilicon doped layer to form an ohmic contact layer, and removing the metal layer on the back of the battery. The etching solution is HF with a volume concentration of 1% to 5%. The operating temperature range is 45°C to 55°C, the operating time is 30 seconds to 600 seconds, and the spraying pressure is 0.5 Kg / cm 2 ~2.5 Kg / cm 2 , and the metal layer is etched and removed. Then it is cleaned and dried. Thus, a BC cell with fine-line-width metal grid lines, a low series resistance structure, and a high breakdown voltage is obtained.
[0050] Embodiment The following embodiments more specifically describe the content disclosed in the present invention. These embodiments are only for illustrative purposes, because various modifications and changes within the scope of the present invention are obvious to those skilled in the art. Unless otherwise stated, all parts, percentages, and ratios reported in the following embodiments are based on weight, and all reagents used in the embodiments are commercially available or synthesized according to conventional methods and can be used directly without further treatment, and all instruments used in the embodiments are commercially available.
[0051] Embodiment 1 Step S1, as shown in the attached Figures 1-3 figure, the passivation layer 4 is patterned and etched through the etching paste 5, and the passivation layer 4 on one side of the P-type polysilicon doped layer 3 and the N-type polysilicon doped layer 2 is etched and removed, exposing the P-type polysilicon doped layer 3 and the N-type polysilicon doped layer 2 of the cell. The passivation layer 4 includes a silicon nitride layer 4b and / or an aluminum oxide layer 4a provided on the back of the cell Specifically, a positive and negative screen printing plate with 25 meshes, a wire diameter of 20 μm, and a screen tension of 42 ± 3 Newtons (the oil film is not printed in the area to be etched) is used, with a printing speed of 120 mm / sec; the downward pressure range is 42 ± 3 Newtons, and the etching paste 5 is printed on the passivation layer 4 on the back of the cell 1. Then the etching paste 5 is heated to 290 ± 10°C; the heating time is 600 seconds. The passivation layer 4 under the etching paste 5 is etched and removed, forming a passivation layer opening 6 on the surface of the cell 1. Then it is soaked in hot water at 85 ± 5°C for 600 seconds to clean the etching paste, and then dried. Thus, a cell with an area of 7.5% of the P-type polysilicon doped layer and the N-type polysilicon doped layer exposed is formed. As shown in the attached Figure 20b figure, the passivation layer is etched through the etching paste without damaging the silicon surface.
[0052] Step S2, as shown in the attached Figure 4 figure, an ohmic contact metal layer 7 is prepared on the P-type polysilicon doped layer 3 and the N-type polysilicon doped layer 2, and the deposited metal is nickel, forming a nickel ohmic contact metal layer 7a.
[0053] Deposit the nickel ohmic contact metal layer 7a with a PVD vacuum device. The deposition thickness ranges from 55 ± 5 nm. The specific operating conditions are as follows: the operating power is 2.5 ± 0.5 KW, the time is 100 seconds, and the temperature control range is 215 ± 15 °C. Prepare the nickel ohmic contact metal layer 7a on the exposed P-type polysilicon doped layer and N-type polysilicon doped layer of the cell.
[0054] Step S3, refer to the appendix Figure 5 As shown, perform an etching process on the unreacted nickel metal layer to remove the nickel metal layer on the surface of the passivation layer. The etching solution for etching the nickel metal layer is 2.4 ± 0.2% HF, the etching temperature is 48 ± 3 °C, the etching time is 125 ± 5 seconds, and the spraying pressure is 2.3 ± 0.3 Kg / cm 2 .
[0055] Then, prepare the barrier layer 8, the metal grid line 9, and the protective layer 10 on the side of the nickel ohmic contact metal layer away from the cell body through an electroplating deposition process. Specifically, the thickness range of the barrier layer 8 is 1 um, and the material of the barrier layer is metal nickel. The metal grid line 9 is a copper conductive grid line layer, and the thickness range is 9 um. Then, continuously use the electroplating process to prepare the tin protective layer 10 on the surface of the metal grid line 9. The thickness range of the tin protective layer 10 is 2 um. By directly electroplating the barrier layer 8, the metal grid line 9, and the protective layer 10 on the nickel ohmic contact metal layer 7a, the preparation process is simple and the production cost is reduced.
[0056] Example 2 In this example, step S1 is the same as step S1 in Example 1 and will not be elaborated here.
[0057] In step S2, deposit the nickel ohmic metal layer 7a on the N-type polysilicon doped layer 2 through an electroplating process, and then deposit the aluminum ohmic metal layer 7b on the back of the cell 1 through a vacuum high-temperature deposition process.
[0058] Specifically, refer to the appendix Figure 6 As shown, deposit the nickel ohmic contact metal layer 7a on the N-type polysilicon doped layer 2 through an electroplating process. The deposition thickness ranges from 1.2 ± 0.3 um.
[0059] Refer to the appendix Figure 7 As shown, then deposit the aluminum ohmic contact metal layer 7b on the P-type polysilicon doped layer 3 with a PVD vacuum device; the deposition thickness ranges from 25 ± 5 nm. The specific operating conditions are as follows: the operating power is 1.5 ± 0.5 KW, the time is 60 seconds, and the temperature control range is 210 ± 10 °C to prepare the aluminum ohmic contact metal layer 7b.
[0060] Step S3, refer to the appendix Figure 8As shown, an etching process is performed on the unreacted nickel metal layer and aluminum metal layer to remove the nickel metal layer and aluminum metal layer on the surface of the passivation layer 4. Then, a barrier layer 8, a metal grid line 9, and a protective layer 10 are prepared on the sides of the nickel ohmic contact metal layer 7a and the aluminum ohmic contact metal layer 7b away from the battery cell body through an electroplating deposition process.
[0061] The etching solution for etching the nickel metal layer and aluminum metal layer is 2.4 ± 0.2% HF, and the operating conditions are: temperature 48 ± 3°C, operating time 125 ± 5 seconds, and spraying pressure 2.3 ± 0.3 Kg / cm 2 .
[0062] Then, through an electroplating process, a barrier layer 8 and a metal grid line 9 are prepared on the surfaces of the nickel ohmic contact metal layer 7a and the aluminum ohmic contact metal layer 7b; the thickness range of the barrier layer 8 is 1um. The metal grid line 9 is a copper conductive grid line layer with a thickness range of 9um. Then, continuously using an electroplating process, a tin protective layer 10 is prepared on the surface of the metal grid line 9, and the thickness range of the tin protective layer 10 is 2um. Thus, a BC battery cell is obtained.
[0063] Example 3 The steps S1 and S2 of Example 3 are the same as those of Example 1 and will not be elaborated here.
[0064] The main difference lies in step S3. Specifically, step S3 in this example is as follows: Step S31, refer to the attachment Figure 9 As shown, a barrier layer 8 is deposited on the back of the battery by a PVD vacuum device; the deposition thickness of the barrier layer 8 is 25 ± 5nm, and the material of the barrier layer is metal titanium. The specific operating conditions are: operating power 4 ± 1KW, deposition time 60 seconds, and temperature control range 360 ± 10°C to prepare the titanium barrier layer 8.
[0065] Step S32, a bottom copper seed layer 11 is deposited on the surface of the barrier layer 8 by a PVD vacuum device; the deposition thickness range of the seed layer 11 is 65 ± 5nm. The specific operating condition range is: operating power 2.5 ± 0.5KW, time 100 seconds, and temperature control range 360 ± 10°C.
[0066] Step S33, refer to the attachment Figure 10 As shown, a 30um thick dry film is pressed on the battery cell to prepare a mask layer 12, and then image transfer is performed with a light wavelength of 405nm and an exposure intensity of 120mW / cm 2 A developer prepared with a NaOH concentration ratio of 1.5% is used; the operating conditions are temperature 30°C, time 110 seconds, and spraying pressure 2.0Kg / cm 2 A mask layer opening 13 is prepared on the mask layer 12. The areas to be electroplated on the P-type polysilicon doping layer and N-type polysilicon doping layer of the battery cell are exposed.
[0067] Step S34. Refer to the appendix Figure 11 As shown, using the electroplating process, a metal gate line 9 and a protective layer 10 are electroplated at the opening 13 of the mask layer. The thickness of the metal gate line 9 is 9 μm, and the thickness of the protective layer 10 is 2 μm. The material of the protective layer 10 is metallic tin.
[0068] Step S35. Refer to the appendix Figure 12 As shown, remove the mask layer 12. The specific operation is as follows: The solar cell is transferred into the mask removal tank section for the mask removal process. The operating temperature is 50 °C, and the operating spray pressure range is 2.5 Kg / cm 2 . The stripping solution is a NaOH solution with a concentration of 1.4%.
[0069] Step S36. Refer to the appendix Figure 13 As shown, remove the exposed copper seed layer 11 on the back of the solar cell. The etching solution for the etching process of the copper seed layer 11 is 4% dilute sulfuric acid. Process operating conditions: The temperature is room temperature, the time is 120 seconds, and the spraying pressure is 2.5 Kg / cm 2 , and etch the seed layer 11.
[0070] Step S37. Refer to the appendix Figure 13 As shown, remove the exposed barrier layer 8 on the back of the solar cell. The etching solution for etching the barrier layer 8 is 5% hydrogen peroxide H2O2. Process operating conditions: The temperature is 50 °C, the time is 120 seconds, and the spraying pressure is 2.0 Kg / cm 2 , and etch the titanium barrier layer 8.
[0071] Step S38. Refer to the appendix Figure 13 As shown, etch and remove the unreacted nickel metal layer. The etching solution is 2.5% HF solution. Process operating conditions: The temperature is 50 °C, the operating time is 120 seconds, and the spraying pressure is 2.5 Kg / cm 2 , and etch and remove the unreacted nickel metal layer. After cleaning and drying, a BC solar cell is obtained.
[0072] Example 4 The process steps of Example 4 and Example 3 are basically the same. The main difference is that no seed layer 11 is prepared between the barrier layer 8 and the metal gate line 9, that is, steps S32 and S36 in Example 3 are not implemented in this example. The prepared solar cell is as shown in the appendix Figure 14 as shown.
[0073] Example 5 Steps S1 and S2 in Example 5 are the same as those in Example 2. The main difference lies in Step S3. Step S3 in this example is similar to Step S3 in Example 3, and specifically includes the following steps: Step S31. Refer to the appendix Figure 15As shown, a barrier layer 8 is deposited on the surfaces of the nickel ohmic contact metal layer 7a and the aluminum ohmic contact metal layer 7b deposited on the back of the battery by a PVD vacuum device; the deposition thickness of the barrier layer 8 is 25 ± 5 nm, and the material of the barrier layer is metallic titanium. Specific operating conditions: operating power 4 ± 1 KW, deposition time 60 seconds, temperature control range 360 ± 10 °C, to prepare the titanium barrier layer 8.
[0074] Step S32: Deposit a bottom copper seed layer 11 on the surface of the barrier layer 8 by a PVD vacuum device; the deposition thickness range of the seed layer 11 is 65 ± 5 nm. The specific operating condition range is: operating power 2.5 ± 0.5 KW, time 100 seconds, temperature control range 360 ± 10 °C.
[0075] Step S33: Press a 30-um-thick dry film on the battery wafer to prepare a mask layer 12, and then perform image transfer with a light wavelength of 405 nm and an exposure intensity of 120 mW / cm. Then use a developer prepared with NaOH with a concentration ratio of 1.5%; the matching operating conditions are a temperature of 30 °C, a time of 110 seconds, and a spraying pressure of 2.0 Kg / cm. 2 Prepare a mask layer opening 13 on the mask layer 12. Expose the areas to be electroplated on the P poly doped layer and the N poly doped layer of the battery wafer. 2
[0076] Step S34: As shown in the appendix Figure 16 As shown, use an electroplating process to electroplate and prepare a metal grid line 9 and a protective layer 10 at the mask layer opening 13. The thickness of the metal grid line 9 is 9 um. The thickness of the protective layer 10 is 2 um, and the material of the protective layer 10 is metallic tin.
[0077] Step S35: As shown in the appendix Figure 17 As shown, remove the mask layer 12. The specific operation is: transfer the battery wafer into the mask removal tank section for the mask removal process, and the operating temperature is 50 °C. The operating spray pressure range is 2.5 Kg / cm. 2 . The stripping solution is a NaOH solution with a concentration of 1.4%.
[0078] Step S36: As shown in the appendix Figure 18 As shown, remove the exposed copper seed layer 11 on the back of the battery. The etching solution for the copper seed layer 11 etching process is 4% dilute sulfuric acid. Process operating conditions: temperature at room temperature, time 120 seconds, and spraying pressure 2.5 Kg / cm. 2 , etch the seed layer 11.
[0079] Step S37: Remove the exposed barrier layer 8 on the back of the battery. The etching solution for etching the barrier layer 8 is 5% hydrogen peroxide H2O2. Process operating conditions: temperature 50 °C, time 120 seconds, spraying pressure 2.0 Kg / cm. 2 , etch the titanium barrier layer 8.
[0080] Step S38: Etch and remove the unreacted nickel metal layer. The etchant is a 2.5% HF solution. Process operating conditions: temperature is 50°C, operating time is 120 seconds, and spraying pressure is 2.5 Kg / cm 2 , etch and remove the unreacted nickel metal layer. After cleaning and drying, a BC cell is obtained.
[0081] Example 6 The process steps of Example 6 and Example 5 are basically the same. The main difference is that no seed layer 11 is prepared between the barrier layer 8 and the metal grid line 9, that is, steps S32 and S36 in Example 3 are not implemented in this example. The prepared cell is as shown in the appendix Figure 19 as shown.
[0082] Example 7 Example 7 is basically the same as Example 1. The main difference is that in step S1, after etching the passivation layer, a cell with the area of the P-type polysilicon doped layer and the N-type polysilicon doped layer being 11.5% is exposed. That is, (area of P-type polysilicon doped layer + area of N-type polysilicon doped layer) / total area of the cell back surface = 11.5%.
[0083] Example 8 Example 8 is basically the same as Example 2. The main difference is that in step S1, after etching the passivation layer, a cell with the area of the P-type polysilicon doped layer and the N-type polysilicon doped layer being 11.5% is exposed. That is, (area of P-type polysilicon doped layer + area of N-type polysilicon doped layer) / total area of the cell back surface = 11.5%.
[0084] Example 9 Example 9 is basically the same as Example 3. The main difference is that in step S1, after etching the passivation layer, a cell with the area of the P-type polysilicon doped layer and the N-type polysilicon doped layer being 11.5% is exposed. That is, (area of P-type polysilicon doped layer + area of N-type polysilicon doped layer) / total area of the cell back surface = 11.5%.
[0085] Example 10 Example 10 is basically the same as Example 4. The main difference is that in step S1, after etching the passivation layer, a cell with the area of the P-type polysilicon doped layer and the N-type polysilicon doped layer being 11.5% is exposed. That is, (area of P-type polysilicon doped layer + area of N-type polysilicon doped layer) / total area of the cell back surface = 11.5%.
[0086] Example 11 Example 11 is basically the same as Example 5. The main difference lies in that in step S1, after etching the passivation layer, a cell wafer with an area of 11.5% of the P-type polysilicon doped layer and the N-type polysilicon doped layer is exposed. That is, (area of P-type polysilicon doped layer + area of N-type polysilicon doped layer) / total area of the back of the cell = 11.5%.
[0087] Example 12 Example 12 is basically the same as Example 6. The main difference lies in that in step S1, after etching the passivation layer, a cell wafer with an area of 11.5% of the P-type polysilicon doped layer and the N-type polysilicon doped layer is exposed. That is, (area of P-type polysilicon doped layer + area of N-type polysilicon doped layer) / total area of the back of the cell = 11.5%.
[0088] Comparative Example 1 The main difference between Comparative Example 1 and Example 1 is that in step S1, the passivation layer on one side of the P-type polysilicon doped layer and the N-type polysilicon doped layer is removed by a laser process to expose the P-type polysilicon doped layer and the N-type polysilicon doped layer of the cell wafer. The remaining process steps are the same. See the appendix Figure 20a As shown, after laser grooving, the matte surface is damaged by the laser (the darker area).
[0089] Experimental Example Perform performance tests on the BC cells prepared in Examples 1 - 12 and Comparative Example 1. The test results are shown in Table 1.
[0090] Table 1
[0091] In Examples 1 - 6 and Comparative Example 1 (laser grooving to remove the passivation layer), after etching the passivation layer, a cell wafer with an area of 7.5% of the P-type polysilicon doped layer and the N-type polysilicon doped layer is exposed. That is, (area of P-type polysilicon doped layer + area of N-type polysilicon doped layer) / total area of the back of the cell = 7.5%.
[0092] According to the data of Examples 1 - 6 and Comparative Example 1 in Table 1, the open-circuit voltage of the back-contact cell obtained by the preparation method provided in this application increases, the series resistance decreases, the short-circuit current increases, and the photoelectric conversion efficiency improves. That is, the performance of the solar cell obtained by the preparation method provided in this application is better.
[0093] From the data of Examples 7 - 12 and Comparative Example 1 in the table, even though the area of the passivation layer removed by the etching process is 4% more than that by the laser process, the open voltage of the cell wafer is not damaged and is still higher than that of the cell wafer with the passivation layer removed by the laser process.
[0094] Comparing Example 1 and Example 2, it can be seen that by depositing a nickel ohmic contact metal layer on the N-type polysilicon doping layer and an aluminum ohmic contact metal layer on the P-type polysilicon doping layer, the open circuit voltage increases, the short circuit current increases, the light point conversion efficiency improves, and the performance of the solar cell is better.
[0095] The present invention uses the above examples to illustrate the detailed process equipment and process flow of the present invention. However, the present invention is not limited to the above detailed process equipment and process flow, that is, it does not mean that the present invention must rely on the above detailed process equipment and process flow to be implemented. Those skilled in the art should understand that any improvement of the present invention, the equivalent replacement of each raw material of the product of the present invention, the change of the structural form, the addition of auxiliary components, the selection of specific methods, etc., all fall within the protection scope and the disclosure scope of the present invention.
[0096] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.
[0097] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable those who are familiar with this technology to understand the content of the present invention and implement it. It cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.
Claims
1. A method for preparing a back contact battery, characterized in that: The steps include: Step S1, etching the passivation layer with an etching paste to remove the passivation layer on one side of the P-type polysilicon doping layer and the N-type polysilicon doping layer, exposing the P-type polysilicon doping layer and the N-type polysilicon doping layer of the cell; Step S2, preparing an ohmic contact metal layer for the P-type polysilicon doping layer and the N-type polysilicon doping layer; Step S3: preparing metal gate lines and a protective layer on the ohmic contact metal layer by an electroplating deposition process.
2. The method for preparing a back contact battery according to claim 1, characterized in that: In step S1, etching paste is coated on the surface of the passivation layer by screen printing process, the screen mesh range is 150 mesh ~ 300 mesh; the wire diameter range is 15um ~ 30um; the screen tension control range is 20 Newton ~ 30 Newton; the printing speed range is 100mm / sec ~ 500mm / sec; the down pressure range is 20 Newton ~ 50 Newton.
3. The method for preparing a back contact battery according to claim 1, characterized in that: In step S1, the heating temperature range of the etching paste for etching the passivation layer is 200° C. to 400° C.; the heating time is 30 seconds to 600 seconds.
4. The method for preparing a back contact battery according to claim 1, characterized in that: In step S2, a nickel ohmic metal layer is deposited on the N-type polysilicon doped layer by an electroplating process, and then an aluminum ohmic metal layer is deposited on the back of the battery cell by a vacuum high-temperature deposition process.
5. The method for preparing a back contact battery according to claim 1, characterized in that: In step S2, a nickel ohmic metal layer is deposited on the surfaces of the P-type polysilicon doping layer and the N-type polysilicon doping layer exposed on the cell by a vacuum high-temperature deposition process.
6. The method for preparing a back contact battery according to any one of claims 4 or 5, characterized in that: Step S3 includes the following steps: preparing a barrier layer on the side of the ohmic contact metal layer away from the battery cell body by an electroplating deposition process.
7. The method for preparing a back contact battery according to any one of claims 4 or 5, characterized in that: Step S3 also includes the following steps: preparing a barrier layer on the back side of the battery cell by a vacuum deposition process.
8. The method for preparing a back contact battery according to claim 7, characterized in that: Step S3 also includes the following steps: preparing a seed layer on the side of the barrier layer away from the battery cell by a vacuum deposition process.
9. The method for preparing a back contact battery according to any one of claims 7 or 8, characterized in that: In step S3, a mask layer is prepared on the back side of the cell by a patterning process, and a metal grid line and a protective layer are prepared by electroplating deposition at the opening of the mask layer.
10. A back-contact battery, prepared according to the method for preparing a back-contact battery according to any one of claims 1 to 9.