Battery preparation method, battery and photovoltaic module

Abstract

This invention discloses a method for fabricating a battery, a battery, and a photovoltaic module. The method for fabricating the battery includes: forming a silicon-based intermediate; fabricating a transparent conductive film layer on a first surface and / or a second surface of the silicon-based intermediate; fabricating an anti-reflection layer on the surface of the transparent conductive film layer; forming a first opening region in the anti-reflection layer using an acidic solution containing fluoride ions, wherein the first opening region is configured as a groove extending toward the silicon-based intermediate, and the bottom of the groove is the transparent conductive film layer; and fabricating an electrode structure in the first opening region, wherein the electrode structure is in direct contact with or extends into the transparent conductive film layer. This ensures the integrity and undamaged surface of the silicon-based intermediate, guarantees sufficient contact for subsequent electrode growth, and, through a mild reaction with minimal additional energy input, prevents a decrease in the fill factor and open-circuit voltage of the first opening region.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, and in particular to a method for preparing a battery, a battery, and a photovoltaic module. Background Technology

[0002] Copper electroplating of battery electrodes is the ultimate route to eliminating silver in the current photovoltaic industry. Realizing copper interconnect technology can effectively reduce the cost of heterojunction batteries and enhance the competitiveness of heterojunction battery products.

[0003] The first opening area formed by copper electroplating of dielectric film is usually removed by direct laser grooving. Due to the additional energy input, damage to the silicon substrate (amorphous silicon / microcrystalline silicon / polycrystalline silicon and other semiconductor films already formed on the surface of the silicon substrate) is inevitable. The damage to the interface will directly affect the subsequent seed layer and electrode growth. Excessive contact resistance will significantly reduce the fill factor (FF) of the cell, and excessive energy will cause damage to the passivation layer, significantly reducing the fill factor and open circuit voltage (Voc) of the cell. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a method for preparing a battery that ensures the surface integrity and undamaged nature of the silicon-based intermediate, thus guaranteeing sufficient contact for subsequent electrode growth. Furthermore, through a mild reaction process with minimal additional energy input, the fill factor and open-circuit voltage of the first opening region are not reduced.

[0005] The present invention further proposes a battery.

[0006] The present invention also proposes a photovoltaic module.

[0007] A method for fabricating a battery according to a first aspect of the present invention includes: forming a silicon-based intermediate having a first surface and a second surface disposed opposite to each other; fabricating a transparent conductive film layer on the first surface and / or the second surface of the silicon-based intermediate; fabricating an antireflective layer on the surface of the transparent conductive film layer; forming a first opening region in the antireflective layer through an acidic solution containing fluoride ions, the first opening region being configured as a groove extending toward the silicon-based intermediate, the bottom of the groove being the transparent conductive film layer; and fabricating an electrode structure in the formed first opening region, the electrode structure being in direct contact with the transparent conductive film layer or extending into the interior of the transparent conductive film layer.

[0008] Therefore, the method for preparing this battery can ensure that the surface of the silicon-based intermediate is intact and undamaged, which can also ensure that the subsequent electrode growth achieves sufficient contact. At the same time, through a mild reaction, without excessive additional energy input, the fill factor and open-circuit voltage of the first opening region can be maintained without reduction.

[0009] According to some embodiments of the present invention, the step of forming a first opening region in the antireflective layer using an acidic solution containing fluoride ions includes: forming the first opening region in the antireflective layer using a hydrofluoric acid solution.

[0010] According to some embodiments of the present invention, the step of forming a first opening region in the antireflective layer using a hydrofluoric acid solution includes: spraying the hydrofluoric acid solution in a predetermined area for forming the first opening region using an image-based method such as inkjet printing or sputtering to form the first opening region.

[0011] According to some embodiments of the present invention, the step of forming a first opening region in the antireflective layer using a hydrofluoric acid solution includes: forming a barrier layer on a local surface of the antireflective layer; placing the silicon-based intermediate in the hydrofluoric acid solution to locally remove the antireflective layer and form the first opening region; and removing the barrier layer.

[0012] According to some embodiments of the present invention, the step of forming the first opening region in the antireflective layer using a hydrofluoric acid solution includes: spraying a solution containing hydrogen ions and a solution containing fluorine ions into the antireflective layer respectively, thereby generating a hydrofluoric acid solution in the antireflective layer through a chemical reaction, and thus forming the first opening region.

[0013] According to some embodiments of the present invention, the step of spraying a solution containing hydrogen ions and a solution containing fluoride ions onto the antireflective layer to generate a hydrofluoric acid solution through a chemical reaction, thereby forming the first opening region, includes: spraying a polyacrylic acid solution onto the antireflective layer; and spraying an ammonium fluoride solution onto the antireflective layer to generate the hydrofluoric acid solution through a chemical reaction, thereby forming the first opening region.

[0014] According to some embodiments of the present invention, prior to the step of spraying ammonium fluoride solution into the antireflective layer, the method further includes: heating the polyacrylic acid solution of the silicon-based intermediate or the antireflective layer until the polyacrylic acid solution becomes gel-like.

[0015] According to some embodiments of the present invention, the step of forming the silicon-based intermediate includes: preparing a textured surface on the surface of a silicon substrate; preparing a passivation layer on the surface of the silicon substrate; and preparing a doped conductive semiconductor layer on the surface of the passivation layer to form the silicon-based intermediate.

[0016] According to some embodiments of the present invention, the step of preparing a textured surface on the surface of the silicon substrate includes: cleaning the surface of the silicon substrate with a hydrofluoric acid solution to remove the oxide layer; immersing the silicon substrate in a solution of potassium hydroxide, sodium hydroxide, or tetramethylammonium hydroxide with added alcohol to form a pyramidal textured surface.

[0017] According to some embodiments of the present invention, the step of preparing a passivation layer on the surface of the silicon substrate and preparing a doped conductive semiconductor layer on the surface of the passivation layer includes: placing the silicon substrate in a vacuum chamber; introducing a silicon source gas into the vacuum chamber and forming the passivation layer on a first surface of the silicon substrate by plasma chemical vapor deposition, wherein the passivation layer is a first intrinsic amorphous silicon film; introducing a silicon source gas, hydrogen gas, and a phosphorus-containing gas into the vacuum chamber and forming the doped conductive semiconductor layer on the surface of the first intrinsic amorphous silicon film by plasma chemical vapor deposition, wherein the doped conductive semiconductor layer is an n-type doped conductive semiconductor layer; flipping the silicon substrate; introducing a silicon source gas into the vacuum chamber and forming the passivation layer on a second surface of the silicon substrate by plasma chemical vapor deposition, wherein the passivation layer is a second intrinsic amorphous silicon film; introducing a silicon source gas, hydrogen gas, and a boron-containing gas into the vacuum chamber and forming the doped conductive semiconductor layer on the surface of the second intrinsic amorphous silicon film by plasma chemical vapor deposition, wherein the doped conductive semiconductor layer is a p-type doped conductive semiconductor layer.

[0018] According to some embodiments of the present invention, the step of preparing the transparent conductive film layer on the surface of the passivation layer includes: depositing a film on the n-type doped conductive semiconductor layer and the p-type doped conductive semiconductor layer by reactive plasma deposition or magnetron sputtering, thereby forming the transparent conductive film layer.

[0019] According to some embodiments of the present invention, the step of preparing an electrode structure in the formed first opening region includes: preparing a seed layer in the formed first opening region; and preparing an electrode on the surface of the seed layer to prepare the electrode structure.

[0020] According to some embodiments of the present invention, the seed layer is made of at least one of silver, aluminum, copper, magnesium, molybdenum, tungsten, chromium, nickel and tin; and / or the electrode is made of at least one of silver, aluminum, copper, magnesium, molybdenum, tungsten, chromium, nickel and tin.

[0021] According to some embodiments of the present invention, between the step of forming a first opening region in the antireflective layer with an acidic solution containing fluoride ions and the step of preparing an electrode structure in the formed first opening region, the method further includes: placing the silicon-based intermediate into an annealing furnace for annealing treatment, wherein the temperature of the annealing furnace is T and the annealing treatment duration is t; wherein T satisfies the relationship: 180℃≤T≤220℃, and t satisfies the relationship: 10min≤t≤20min.

[0022] The battery according to the second aspect embodiment of the present invention is manufactured using the battery manufacturing method described above.

[0023] A photovoltaic module according to a third aspect of the present invention includes: the battery described above.

[0024] The advantages of this invention over the prior art are as follows:

[0025] The fabrication method of this battery ensures the integrity and undamaged surface of the silicon-based intermediate, guaranteeing sufficient contact for subsequent electrode growth. Furthermore, the mild reaction process, requiring minimal additional energy input, prevents a decrease in the fill factor and open-circuit voltage of the first opening region. Additionally, the chemical reaction between hydrogen-ion and fluoride-ion solutions generates hydrofluoric acid, eliminating the need for pre-preparation of the hydrofluoric acid solution and reducing the risks associated with handling highly corrosive substances.

[0026] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0027] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0028] Figure 1 This is a schematic diagram of the structure of a battery according to an embodiment of the present invention;

[0029] Figure 2 This is a flowchart illustrating the formation of a first opening region in the antireflective layer surface of a battery according to an embodiment of the present invention, which contains a gel-like polyacrylic acid solution.

[0030] Figure 3 This is a schematic diagram of the first opening region containing a seed layer according to an embodiment of the present invention;

[0031] Figure 4 This is a flowchart illustrating the formation of a first opening region on the surface of an antireflective layer of a battery according to another embodiment of the present invention, where a blocking layer is present.

[0032] Figure 5 This is a flowchart of a battery preparation method according to an embodiment of the present invention;

[0033] Figure 6 This is a flowchart of the rinsing and annealing process after the silicon-based intermediate forms the first opening region, according to an embodiment of the present invention.

[0034] Figure 7 This is a flowchart illustrating the process before a transparent conductive film layer is fabricated on the surface of a silicon substrate according to an embodiment of the present invention.

[0035] Figure label:

[0036] 100. Battery;

[0037] 10. Transparent conductive film layer; 20. Anti-reflective layer;

[0038] 30. Silicon substrate; 40. Barrier layer;

[0039] 51. First intrinsic amorphous silicon film; 52. n-type doped conductive semiconductor layer; 53. Second intrinsic amorphous silicon film; 54. p-type doped conductive semiconductor layer;

[0040] 60. Polyacrylic acid solution;

[0041] 70. Textured surface; 80. Ammonium fluoride solution source; 81. Seed layer; 82. Metal grid lines;

[0042] 90. First opening region; 91. Silicon-based intermediate. Detailed Implementation

[0043] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0044] The following is for reference. Figures 1-7 A method for preparing a battery 100 according to an embodiment of the present invention is described, which can be used to prepare a heterojunction battery.

[0045] like Figure 5 As shown, a method for preparing a battery 100 according to a first aspect embodiment of the present invention includes:

[0046] A silicon-based intermediate 91 is formed, the silicon-based intermediate 91 having a first surface and a second surface disposed opposite to each other.

[0047] Specifically, firstly, a silicon-based intermediate 91 is selected. The silicon-based intermediate 91 can be an N-type silicon wafer with a resistivity of 0.5 Ω·cm to 3 Ω·cm, a thickness of 90 μm to 120 μm, and a size of 210 mm. Alternatively, a P-type silicon wafer can be selected. Then, dirt and traces on the silicon-based intermediate 91 are cleaned. The surface oxide layer of the silicon-based intermediate 91 is first removed using a hydrofluoric acid solution. The dilution concentration of the hydrofluoric acid solution can be between 2% and 10%, and the immersion time of the silicon-based intermediate 91 in the hydrofluoric acid solution can be between 10 s and 50 s. For example, the dilution concentration of the hydrofluoric acid solution can be 2%, 5%, 8%, and 10%, and the corresponding immersion time of the silicon-based intermediate 91 in the hydrofluoric acid solution can be 40 s, 30 s, 20 s, and 15 s. The first surface can be the front surface of the silicon-based intermediate 91, and the second surface can be the back surface of the silicon-based intermediate 91.

[0048] S1. A transparent conductive film layer 10 is prepared on the first and / or second surfaces of the silicon-based intermediate 91.

[0049] A film is deposited on the first and second surfaces of the silicon-based intermediate 91. The deposition method can be reactive plasma deposition (RPD) or magnetron sputtering. The transparent conductive film layer 10 can be a transparent conductive oxide film (TCO). The transparent conductive oxide film is prepared by depositing a transparent conductive oxide film using a ratio of 99.5% indium oxide and 0.5% tin oxide, thereby forming a transparent conductive film layer 10 on the surface of the silicon-based intermediate 91.

[0050] S2. An antireflection layer 20 is prepared on the surface of the transparent conductive film layer 10.

[0051] Specifically, an antireflection layer 20 is deposited on the transparent conductive film layer 10 using low-temperature plasma-enhanced chemical vapor deposition (PECVD). The antireflection layer 20 can be configured as one or more composite films of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiNOx), thereby facilitating the fabrication of the antireflection layer 20 on the surface of the transparent conductive film layer 10. The low temperature can be between 100℃ and 200℃.

[0052] For example, SiNOx and SiNx form a double-layer antireflection layer 20. The outermost SiNOx layer's optical refractive index n can be set to 1.9, and the thickness of SiNOx can be set to 15nm. The inner SiNx layer's refractive index n can be set to 2.15, and the thickness of the inner SiNx layer can be set to 35nm. In this way, reflection loss can be reduced by optimizing the thickness and refractive index of each layer.

[0053] S3. A first opening region 90 is formed in the antireflection layer 20 by an acidic solution containing fluoride ions, exposing the transparent conductive film layer 10. The first opening region 90 is configured as a groove extending toward the silicon-based intermediate 91, and the bottom of the groove is the transparent conductive film layer 10.

[0054] The step of forming the first opening region 90 in the antireflection layer 20 using an acidic solution containing fluoride ions includes: forming the first opening region 90 in the antireflection layer 20 using an acidic solution containing fluoride ions. The acidic solution containing fluoride ions can be one of hydrofluoric acid solution, fluoroboric acid solution, fluorophosphate solution, and hexafluorosilicic acid solution. The acidic solution containing fluoride ions can also be a hydrofluoric acid solution generated by reacting a salt solution containing fluoride ions with an acidic solution. For example, ammonium fluoride solution reacts with sulfuric acid to generate a hydrofluoric acid solution, and potassium fluoride solution reacts with hydrochloric acid to generate a hydrofluoric acid solution. The acidic solution containing fluoride ions removes the antireflection layer 20 from which the first opening region 90 needs to be formed by etching the antireflection layer 20, forming a groove. The bottom of the groove exposes the transparent conductive film layer 10 in that region. The acidic solution containing fluoride ions reacts mildly during the etching process of the antireflection layer 20 without excessive additional energy input, so that the fill factor and open-circuit voltage of the first opening region 90 are not reduced.

[0055] Furthermore, due to the varying atomic densities of silicon atoms in different crystal orientations within the silicon-based intermediate 91, the corrosion rate of the acidic solution containing fluoride ions differs for each orientation. For instance, in single-crystal silicon, the atomic arrangement on crystal faces is sparser, making them easier to etch, while other crystal orientations are relatively more difficult. Utilizing this characteristic, the corrosion process can be made more targeted by adjusting the composition and concentration of the acidic solution containing fluoride ions, as well as the temperature, thereby ensuring the integrity and undamaged surface of the silicon-based intermediate 91. This guarantees sufficient contact for subsequent electrode growth.

[0056] S4. An electrode structure is prepared in the first opening region 90, and the electrode structure is in direct contact with the transparent conductive film layer 10 or extends into the interior of the transparent conductive film layer 10.

[0057] In this process, after the acidic solution containing fluoride ions forms the first opening region 90, the required metal grid lines 82 are prepared in the first opening region 90, thereby forming an electrode structure.

[0058] Therefore, the method for preparing the battery 100 can ensure that the surface of the silicon-based intermediate 91 is intact and undamaged by forming the first opening region 90 with an acidic solution containing fluoride ions. This also ensures that the subsequent electrode growth can achieve sufficient contact. At the same time, through a mild reaction without excessive additional energy input, the fill factor and open-circuit voltage of the first opening region 90 can be maintained without reduction.

[0059] According to some embodiments of the present invention, step S3 includes: S30, forming a first opening region 90 in the antireflective layer 20 using a hydrofluoric acid solution. It is understood that hydrofluoric acid is a weak acid with extremely strong corrosiveness, capable of severely corroding metals, glass, and silicon-containing materials, and reacting violently with many compounds. Thus, the hydrofluoric acid solution can corrode the antireflective layer 20 in the area where the first opening region 90 needs to be formed, thereby exposing the corresponding transparent conductive film layer 10. The method of forming the first opening region 90 using a hydrofluoric acid solution is simple, stable, and easy to implement.

[0060] According to some embodiments of the present invention, step S30 includes: in the region where a first opening region 90 is pre-formed, the antireflective layer 20 sprays a hydrofluoric acid solution to form the first opening region 90 using an image-based method such as inkjet printing or slit sputtering.

[0061] In this process, when the first opening region 90 is formed by spraying hydrofluoric acid solution using an image-based inkjet printing method, the image-based method involves using computer-aided design (e.g., CAD) software to create the pattern required to form the first opening region 90 and converting it into a format that the inkjet printer can recognize. The hydrofluoric acid solution is loaded into the inkjet printer's reservoir, and the inkjet printer is started according to the preset image. An appropriate amount of hydrofluoric acid solution is sprayed onto the antireflective layer 20. This removes the antireflective layer 20 within the first opening region 90 or at the preset location where the grid line electrode area is formed, exposing the transparent conductive film layer 10.

[0062] Alternatively, a slit sputtering method can be used to spray hydrofluoric acid solution to form the first opening region 90. This slit sputtering method involves using computer-aided design (e.g., CAD) software to create the desired pattern for forming the first opening region 90 and converting it into a format recognizable by the slit sputtering device. The hydrofluoric acid solution is loaded into the reservoir of the slit sputtering device, and the device is activated according to the preset pattern, thus facilitating the spraying of hydrofluoric acid solution onto the antireflective layer 20.

[0063] Using the two patterned windowing methods described above can improve the efficiency of forming the first opening region 90, facilitate the standardization of the first opening region 90, and make the size of the formed pattern more precise, which can facilitate the subsequent preparation of the electrode structure and reduce the loss of battery performance caused by process errors.

[0064] According to other embodiments of the present invention, step S30, forming a first opening region 90 in the antireflection layer 20 using hydrofluoric acid solution, includes: S31, preparing a barrier layer 40 in a portion of the surface of the antireflection layer 20, wherein the region where the first opening region 90 is formed is not covered by the barrier layer 40, and the barrier layer 40 may be paraffin wax.

[0065] In this case, the barrier layer 40 exposes the area where the first opening region 90 needs to be formed. That is, the surface of the antireflective layer 20 is provided with the barrier layer 40 in the area where the first opening region 90 does not need to be formed. This can prevent the area where the first opening region 90 is not formed from being immersed in the hydrofluoric acid solution, thereby preventing the antireflective layer 20 in the area where the first opening region 90 is not formed from reacting with the hydrofluoric acid solution.

[0066] S32. The silicon-based intermediate 91 is placed in a hydrofluoric acid solution to partially remove the antireflective layer 20, forming the first opening region 90. Utilizing the acid resistance of paraffin, the silicon-based intermediate 91 can be immersed in the hydrofluoric acid solution. The antireflective layer 20 forming the first opening region 90 can chemically react with the hydrofluoric acid solution, thus dissolving the antireflective layer 20 at the location where the first opening region 90 needs to be formed. This avoids the antireflective layer 20 obstructing the view, exposing the transparent conductive film layer 10 at the metallized gate line location. The surface of the transparent conductive film layer 10 is used for subsequent electroplating.

[0067] S33, Remove the blocking layer 40.

[0068] The remaining non-grid area blocking layer 40 (paraffin) can be removed with an alkaline solution.

[0069] This method can also form the first opening area 90, and the effect of forming the first opening area 90 is good. The paraffin can also be reused repeatedly, and the consumption is less.

[0070] According to some embodiments of the present invention, step S30, forming a first opening region 90 in the antireflection layer 20 using a hydrofluoric acid solution, includes: spraying a solution containing hydrogen ions and a solution containing fluorine ions into the antireflection layer 20 respectively, thereby generating a hydrofluoric acid solution in the antireflection layer 20 through a chemical reaction to form the first opening region 90.

[0071] In this method, a hydrofluoric acid solution is generated by chemically reacting two solutions containing hydrogen ions and fluoride ions to etch the antireflective layer 20 and form the first opening region 90. This is an indirect way of forming the first opening region 90. The hydrogen ion-containing and fluoride ion-containing solutions used to indirectly form the first opening region 90 have weaker acidity and alkalinity. Compared with directly spraying strong acids such as hydrofluoric acid solution, this can reduce the corrosion of the nozzle.

[0072] According to a specific embodiment of the present invention, the step of spraying a solution containing hydrogen ions and a solution containing fluoride ions onto the antireflection layer 20, thereby generating a hydrofluoric acid solution in the antireflection layer 20 through a chemical reaction, and thus forming the first opening region 90, includes:

[0073] S34. Spray polyacrylic acid solution 60 onto the antireflective layer 20. Polyacrylic acid solution 60 can provide a solution containing hydrogen ions. The concentration of the polyacrylic acid (PAA) solution can be adjusted according to specific needs (e.g., 25% vol) to ensure a sufficient supply of solution containing hydrogen ions.

[0074] S35. An ammonium fluoride solution is sprayed onto the antireflective layer 20 using equipment containing an ammonium fluoride solution source 80. This causes a chemical reaction that generates a hydrofluoric acid solution in the antireflective layer 20, thereby forming the first opening region 90. The ammonium fluoride (NH4F) solution can provide a solution containing fluoride ions. Thus, the polyacrylic acid solution 60 and the ammonium fluoride solution in the antireflective layer 20 can react chemically to generate a hydrofluoric acid solution. This eliminates the need for pre-preparation of the hydrofluoric acid solution, thereby reducing the risk of handling highly corrosive substances.

[0075] Furthermore, the ammonium fluoride solution reacts with the bottom antireflective layer 20 (such as SiNOx) to etch the insulating mask at the electrode grid line, forming the first opening region 90. The sample is then directly rinsed with deionized water to remove all sprayed coatings (such as polyacrylic acid solution 60).

[0076] This method can also form the first opening region 90, and can avoid the corrosion of the equipment by hydrofluoric acid solution, extend the service life of the preparation equipment, and reduce manufacturing costs.

[0077] According to some embodiments of the present invention, before step S35, the step of spraying a solution containing hydrogen ions and a solution containing fluoride ions onto the antireflection layer 20, thereby generating a hydrofluoric acid solution in the antireflection layer 20 through a chemical reaction, and thus forming the first opening region 90, further includes:

[0078] S36. Heat the polyacrylic acid solution 60 of the silicon-based intermediate 91 or the antireflective layer 20 until the polyacrylic acid solution 60 becomes gel-like.

[0079] Specifically, when the silicon-based intermediate 91 is heated, the temperature of the silicon-based intermediate 91 is between 25°C and 40°C. The heated silicon-based intermediate 91 can transfer heat to the polyacrylic acid solution 60, thereby making the polyacrylic acid solution 60 gel-like.

[0080] Alternatively, after the polyacrylic acid solution 60 is sprayed onto the antireflective layer 20, heating the polyacrylic acid solution 60 in the antireflective layer 20 can directly make the polyacrylic acid solution 60 into a gel state. In this way, the gel-like polyacrylic acid solution 60 can better maintain the shape after spraying, which corresponds to the first opening area 90 to be formed, thereby preventing the polyacrylic acid solution 60 from spreading and making the position of forming the first opening area 90 more accurate.

[0081] According to some embodiments of the present invention, the step of forming a silicon-based intermediate 91 includes: preparing a textured surface on the surface of a silicon substrate 30, preparing a passivation layer on the surface of the silicon substrate 30, and preparing a doped conductive semiconductor layer on the surface of the passivation layer to form a silicon-based intermediate 91.

[0082] Specifically, such as Figure 7As shown, the steps for providing silicon-based intermediate 91 include:

[0083] S10. A textured surface 70 is prepared on the surface of the silicon substrate 30.

[0084] Specifically, a silicon substrate 30 is selected, and then the dirt and traces on the silicon substrate 30 are cleaned. The surface of the silicon substrate 30 is first immersed in a 5% diluted hydrofluoric acid solution for 10 to 50 seconds to remove the surface oxide layer of the silicon substrate 30. Using potassium hydroxide (KOH), sodium hydroxide (NaOH), or tetramethylammonium hydroxide (TMAH) with alcohol, the anisotropic etching of single crystal silicon can form a shallow pyramid structure on the surface of the silicon substrate 30, i.e., a textured surface 70 is formed.

[0085] According to some embodiments of the present invention, step S10 includes:

[0086] The surface of the silicon substrate 30 is cleaned with hydrofluoric acid solution to remove the oxide layer. The silicon substrate 30 is then immersed in a solution of potassium hydroxide, sodium hydroxide, or tetramethylammonium hydroxide with added alcohol to form a textured surface 70 with a pyramid structure.

[0087] S11. A passivation layer is prepared on the surface of the silicon substrate 30, and a doped conductive semiconductor layer is prepared on the surface of the passivation layer.

[0088] Passivation treatment is performed on the surface of the silicon substrate 30, and an amorphous silicon film is deposited on the surface of the silicon substrate 30 to form a passivation layer, which can protect the silicon substrate 30.

[0089] By fabricating a doped conductive semiconductor layer on the surface of the passivation layer, its electrical properties can be significantly altered. The doping process introduces additional electrons or holes into the passivation layer, thereby increasing the carrier concentration, reducing resistivity, and giving it good conductivity. The doped conductive semiconductor layer can be either an amorphous silicon film or a crystalline silicon film.

[0090] According to some embodiments of the present invention, step S11 includes:

[0091] A silicon substrate 30 is placed in a vacuum chamber, and a silicon source gas (such as SiH4) is introduced into the vacuum chamber. A passivation layer is formed on the first surface of the silicon substrate 30 by plasma chemical vapor deposition (PECVD). The passivation layer is a first intrinsic amorphous silicon film 51. A silicon source gas (such as SiH4), hydrogen, and a phosphorus-containing gas (such as PH3) are introduced into the vacuum chamber, and a doped conductive semiconductor layer is formed on the surface of the first intrinsic amorphous silicon film 51 by plasma chemical vapor deposition. The doped conductive semiconductor layer is an n-type doped conductive semiconductor layer 52.

[0092] The silicon substrate 30 is flipped over, and a silicon source gas (such as SiH4) is introduced into the vacuum chamber. A passivation layer is formed on the second surface of the silicon substrate 30 by plasma chemical vapor deposition (PECVD). The passivation layer is a second intrinsic amorphous silicon film 53. A silicon source gas (such as SiH4), hydrogen, and boron-containing gas (such as B2H6) are introduced into the vacuum chamber, and a doped conductive semiconductor layer is formed on the surface of the second intrinsic amorphous silicon film 53 by plasma chemical vapor deposition. The doped conductive semiconductor layer is a P-type doped conductive semiconductor layer 54.

[0093] The silicon substrate 30 has a first surface and a second surface, one of which is the front side and the other is the back side.

[0094] For example, firstly, a second intrinsic amorphous silicon film 53 is formed on the second surface (back side) of the silicon substrate 30 by plasma chemical vapor deposition (PECVD). Then, the silicon substrate 30 is flipped over, and a first intrinsic amorphous silicon film 51 is formed on the first surface (front side) of the silicon substrate 30 by plasma chemical vapor deposition (PECVD). Next, silicon source gas (such as SiH4), hydrogen, and phosphorus-containing gas (such as PH3) are introduced into the vacuum chamber, and an n-type doped conductive semiconductor layer 52 is formed on the surface of the first intrinsic amorphous silicon film 51 by plasma chemical vapor deposition. Then, the silicon substrate 30 is flipped over again, and silicon source gas (such as SiH4), hydrogen, and boron-containing gas (such as B2H6) are introduced into the vacuum chamber, and a p-type doped conductive semiconductor layer 54 is formed on the surface of the second intrinsic amorphous silicon film 53 by plasma chemical vapor deposition.

[0095] S12. Prepare a transparent conductive film layer 10 on the surface of the passivation layer.

[0096] In the n-type doped conductive semiconductor layer 52 and the p-type doped conductive semiconductor layer 54, a film is deposited by reactive plasma deposition (RPD) or magnetron sputtering. A transparent conductive oxide film (TCO) is deposited using a ratio of 99.5% indium oxide and 0.5% tin oxide to form a transparent conductive film layer 10 on the surface of the silicon substrate 30.

[0097] According to some embodiments of the present invention, step S12 includes:

[0098] A transparent conductive film layer 10 is formed by depositing an n-type doped conductive semiconductor layer 52 and a p-type doped conductive semiconductor layer 54 using reactive plasma deposition or magnetron sputtering.

[0099] In the case of using reactive plasma deposition of transparent conductive oxide film (TCO), a ratio of 99.5% indium oxide and 0.5% tin oxide is used to prepare the deposited transparent conductive oxide film, thereby forming a transparent conductive film layer 10 on the surface of silicon substrate 30.

[0100] For example, a p-type doped conductive semiconductor layer 54 is disposed on the back side of the silicon substrate 30, which is the side that does not primarily receive sunlight. The back side of the silicon substrate 30 is edge-shielded by a carrier disk design (through a mask), and the specific shielding area around the perimeter is 0.8 mm. The thickness of the transparent conductive film layer 10 can be set to 40 nm. The transparent conductive film layer 10 has high conductivity; for example, the carrier concentration of the transparent conductive film layer 10 is 3 × 10⁻⁶. 20 / cm³ and a migration rate of 80cm² / Vs.

[0101] According to some embodiments of the present invention, step S4, fabricating the electrode structure in the first opening region 90, includes:

[0102] S40, Prepare a seed layer 81 in the first opening region 90. (Example) Figure 3 As shown, after the first opening region 90 is formed, a seed layer 81 can be grown in the first opening region 90 by electroplating or chemical plating. The seed layer 81 is in contact with the transparent conductive film layer 10 by PVD coating technology. The thickness h1 of the seed layer 81 can be from 100 nm to 500 nm. For example, the seed layer 81 is Cu, so a Cu electrode can be made.

[0103] S41. An electrode is fabricated on the surface of the seed layer 81, thereby forming an electrode structure. Specifically, the required metal grid lines 82 are plated on the seed layer 81 that forms the first opening region 90, thereby forming an electrode. The seed layer 81 and the electrode form an electrode structure, which is electrically connected to the transparent conductive film layer 10, thereby enabling the output of current.

[0104] According to some embodiments of the present invention, the seed layer 81 is made of at least one of silver, aluminum, copper, magnesium, molybdenum, tungsten, chromium, nickel, and tin. When it is made of multiple metals, it is an alloy material. Thus, depending on the different properties of silver, aluminum, copper, magnesium, molybdenum, tungsten, chromium, nickel, and tin, the seed layer 81 can be adapted to different application scenarios. For example, when the seed layer 81 is made of silver, it has high conductivity, thereby improving the conductivity of the electrode.

[0105] Furthermore, the electrode material is at least one of silver, aluminum, copper, magnesium, molybdenum, tungsten, chromium, nickel, and tin. Specifically, the electrode is constructed as a combination of metal grid lines 82. The required metal grid lines 82 are plated on the seed layer 81 forming the first opening region 90. The type of grid lines is consistent with the seed layer 81 and can be one or more of silver, aluminum, copper, magnesium, molybdenum, tungsten, chromium, nickel, and tin. This also ensures that the electrode has different characteristics. When the electrode material is copper, copper has high conductivity, second only to silver, and is also relatively inexpensive.

[0106] Furthermore, to obtain the required fine grid pattern, subsequent electrode growth is typically performed using a water-soluble etching solution that is effectively dissolved in water, eliminating the need for additional backwashing and re-etching.

[0107] Taking copper electroplating as an example, copper grid lines are electroplated in a copper plating solution. The width W of the copper grid lines can be set to 15 μm, and the height h2 can be controlled to 10 μm. The copper plating solution includes copper sulfate, sulfuric acid, copper balls, and additives that can optimize the crystal structure of the copper layer. Cu in the copper plating solution... 2+ The concentration is 50 g / L, and the sulfuric acid concentration is 40 g / L.

[0108] Taking tin plating as an example, tin gate lines are plated in a tin plating solution, and the height of the tin layer can be controlled to 3 μm. The tin plating solution includes tin methanesulfonate and tin plating additives. Sn in the tin plating solution... 2+ The concentration is 30 g / L, and the concentration of methanesulfonic acid is 200 g / L.

[0109] According to some embodiments of the present invention, such as Figure 5 and Figure 6 As shown, between steps S3 and S4, that is, between the step of forming the first opening region 90 in the antireflection layer 20 with an acidic solution containing fluoride ions and the step of fabricating the electrode structure in the formed first opening region 90, the preparation method further includes:

[0110] S5. Rinse the silicon-based intermediate 91. Specifically, the sample after forming the first opening region 90 is directly rinsed with deionized water to remove all inkjet coatings.

[0111] S6. Place the silicon-based intermediate 91 into an annealing furnace for annealing treatment. The temperature of the annealing furnace is T, and the annealing time is t. T satisfies the following relationship: 180℃≤T≤220℃, and t satisfies the following relationship: 10min≤t≤20min.

[0112] Silicon-based intermediate 91 is placed in an annealing furnace and heated to a temperature T, where T satisfies the relationship: 180℃≤T≤220℃. The annealing time of silicon-based intermediate 91 in the annealing furnace is t, where t satisfies the relationship: 10min≤t≤20min.

[0113] Specifically, during the annealing process, the temperature range of the annealing furnace is 180°C to 220°C. If the furnace temperature is less than 180°C, it will not provide enough energy to repair the lattice defects in the silicon-based intermediate 91, nor will it effectively release the internal stress generated during the manufacturing process of the battery 100, which will lead to cracks. Therefore, the annealing furnace temperature T should not be less than 180°C.

[0114] If the annealing furnace temperature T exceeds 220℃, excessively high temperatures can cause thermal damage to the silicon-based intermediate 91 or other sensitive materials, leading to problems such as lattice distortion and uncontrolled oxide layer growth. High temperatures can also alter the chemical composition or damage the physical structure of the passivation layer, reducing its passivation effect. Therefore, the annealing furnace temperature T should not exceed 220℃.

[0115] The temperature T of the annealing furnace can be set to 190℃, 200℃ and 210℃. For example, when the temperature T of the annealing furnace is 190℃, there is enough energy to repair the lattice defects in the silicon-based intermediate 91, and the internal stress generated during the manufacturing process of the battery 100 can also be effectively released.

[0116] Furthermore, the annealing time t is 10 min to 20 min. If the annealing time t is less than 10 min, it is insufficient for the atoms of the doped conductive semiconductor layer to diffuse into the lattice of the silicon-based intermediate 91 and occupy appropriate lattice positions, and it is also insufficient to effectively release the internal stress generated during the manufacturing process of the battery 100. Therefore, the annealing time t should not be less than 10 min.

[0117] If the annealing time t is greater than 20 minutes, the chemical composition of the passivation layer will change or be damaged. Extending the annealing time means higher energy consumption and increased production costs.

[0118] The annealing time t can be set to 11 min, 13 min, and 15 min. When the annealing time t is 15 min, the internal stress generated during the manufacturing process of battery 100 can be effectively released without causing changes or damage to the chemical composition of the passivation layer.

[0119] Furthermore, placing the silicon-based intermediate 91 into an annealing furnace for heat treatment can densify the antireflection layer 20, making it more compact. This allows the antireflection layer 20 to better function as a mask during electroplating.

[0120] The antireflective layer 20 can be used during electroplating to deposit highly conductive metallic materials (such as nickel or gold) in designated areas. In this case, the antireflective layer 20 can act as a mask to ensure that only specific areas are electroplated. It also has good corrosion resistance and oxidation resistance, providing additional protection in harsh environments and thus extending its service life.

[0121] Furthermore, after step S4, the preparation method also includes:

[0122] S7. Perform light injection treatment on battery 100. Specifically, after alkaline washing, perform light injection treatment on the obtained battery 100. The light injection treatment temperature is 210°C and the light injection treatment time is 90s.

[0123] In this process, the silicon-based intermediate 91 undergoes photo-implantation treatment. This treatment effectively repairs lattice defects in the silicon-based intermediate 91 and reduces the surface state density, thereby improving its overall electrical performance. Furthermore, photo-implantation treatment after alkaline washing of the silicon-based intermediate 91 further optimizes the interface characteristics between the silicon-based intermediate 91 and the passivation layer or other functional layers. A high-quality interface reduces interfacial recombination losses, thus improving carrier transport efficiency. Additionally, appropriate photo-implantation treatment helps release stress generated during the manufacturing process within the silicon-based intermediate 91, preventing stress-induced cracks or other mechanical damage.

[0124] The following is a control experiment.

[0125] Example 1

[0126] The first opening region 90 is formed using a 20-copper anti-reflection layer and laser technology. The linewidth of the front-side gate lines of the electrode is 20 μm and the number is 150. As shown in Table 1, the fill factor (FF) of this embodiment 1 is 83.90%, the open-circuit voltage (Voc) is 749.0 mV, and the efficiency is 26%.

[0127] Example 2

[0128] The first opening region 90 is formed by using an antireflective layer 20 copper interconnect technology and an acidic solution containing fluoride ions. The line width of the front grid line of the electrode is selected to be 20 μm and the number is 150. As shown in Table 1, the fill factor (FF) of this embodiment 2 is 84.90%, the open circuit voltage (Voc) is 749.9 mV, and the efficiency is 26.32%.

[0129] Comparative Example 1

[0130] Conventional printing technology, using paste printing, was employed, with the front-side grid lines of the electrode having a linewidth of 25 μm and a quantity of 60 lines. Table 1 shows that Comparative Example 1 has a fill factor (FF) of 84.75%, an open-circuit voltage (Voc) of 749.9 mV, and an efficiency of 26.15%.

[0131] Comparative Example 2

[0132] In conventional copper interconnect technology, the linewidth of the front-side gate lines of the electrode is 20 μm and the number is 100. As shown in Table 1, the fill factor (FF) of Comparative Example 2 is 85.30%, the open-circuit voltage (Voc) is 749.8 mV, and the efficiency is 26.33%.

[0133] The electrical performance test results of the embodiments and comparative examples using the above-described method for preparing battery 100 are shown in Table 1:

[0134]

[0135] The results above show that the electrical performance test results of the batteries in the examples and comparative examples are as follows:

[0136] Comparing Comparative Example 1 and Comparative Example 2, conventional copper interconnect technology has finer and denser gate lines compared to conventional printing technology, resulting in lower series resistance (Rs), a 0.55% increase in fill factor (FF), and a 0.18% increase in efficiency.

[0137] Comparison of Example 1 and Comparative Example 2: In Example 1, SiNOx copper electroplating technology and laser are used to form the first opening region 90, which damages the bottom passivation layer and textured surface 70. Although the anti-reflection layer 20 is present, the overall short-circuit current density (Jsc) increases, but the fill factor (FF) decreases by 1.4% and the open-circuit voltage (Voc) decreases by 0.8mV. Therefore, the efficiency decreases by 0.33%.

[0138] Comparison between Example 2 and Example 1: Example 2 uses SiNOx copper electroplating technology and an acidic solution containing fluoride ions to form the first opening region 90, avoiding passivation loss and obtaining optical benefits at the same time, with an efficiency improvement of 0.32%, compared with conventional screen printing technology (Comparative Example 1), the efficiency improvement is 0.17%.

[0139] Compared to the laser-formed first opening region 90 process, this cell 100 exhibits significantly improved fill factor (FF) and open-circuit voltage (Voc), as well as an overall conversion efficiency (Eff) improvement of 0.32%. Compared to traditional ink-based copper electroplating technology, this cell 100 offers comparable efficiency but with lower equipment costs, resulting in a cost advantage. The estimated cost reduction is 0.03 yuan / W (currently, the estimated cost of HJT is 0.20 yuan / W).

[0140] The battery 100 according to the second aspect embodiment of the present invention is manufactured using the manufacturing method of the battery 100 described above.

[0141] A photovoltaic module according to a third aspect of the present invention includes: the battery 100 described above.

[0142] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0143] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0144] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for preparing a battery, characterized in that, include: A silicon-based intermediate is formed, the silicon-based intermediate having a first surface and a second surface disposed opposite to each other; A transparent conductive film layer is prepared on the first surface and / or the second surface of the silicon-based intermediate; An antireflection layer is prepared on the surface of the transparent conductive film layer; A first opening region is formed in the antireflective layer by an acidic solution containing fluoride ions. The first opening region is configured as a groove extending toward the silicon-based intermediate, and the bottom of the groove is the transparent conductive film layer. An electrode structure is fabricated in the first opening region, wherein the electrode structure is in direct contact with the transparent conductive film layer or extends into the interior of the transparent conductive film layer. The step of spraying a solution containing hydrogen ions and a solution containing fluoride ions onto the antireflective layer, thereby generating a hydrofluoric acid solution through a chemical reaction in the antireflective layer and forming the first opening region, includes: A polyacrylic acid solution was sprayed onto the antireflective layer; Ammonium fluoride solution is sprayed onto the antireflective layer, thereby generating hydrofluoric acid solution through a chemical reaction in the antireflective layer, which in turn forms the first opening region. Prior to the step of spraying ammonium fluoride solution onto the antireflective layer, the method further includes: The polyacrylic acid solution of the silicon-based intermediate or the antireflective layer is heated until the polyacrylic acid solution becomes gel-like.

2. The method for preparing a battery according to claim 1, characterized in that, The step of forming the first opening region in the antireflective layer using an acidic solution containing fluoride ions includes: The first opening region is formed in the antireflective layer using a hydrofluoric acid solution.

3. The method for preparing a battery according to claim 2, characterized in that, The step of forming the first opening region in the antireflective layer using a hydrofluoric acid solution includes: A solution containing hydrogen ions and a solution containing fluoride ions are sprayed onto the antireflective layer, thereby generating a hydrofluoric acid solution through a chemical reaction in the antireflective layer, which in turn forms the first opening region.

4. The method for preparing a battery according to any one of claims 1-3, characterized in that, The steps for forming silicon-based intermediates include: A textured surface is prepared on the surface of a silicon substrate; A passivation layer is prepared on the surface of the silicon substrate, and a doped conductive semiconductor layer is prepared on the surface of the passivation layer to form the silicon-based intermediate.

5. The method for preparing a battery according to claim 4, characterized in that, The steps of preparing a textured surface on a silicon substrate include: The surface of the silicon substrate was cleaned with hydrofluoric acid solution to remove the oxide layer; The silicon substrate is immersed in a solution of potassium hydroxide, sodium hydroxide, or tetramethylammonium hydroxide with added alcohol to form a textured surface with a pyramidal structure.

6. The method for preparing a battery according to claim 5, characterized in that, The steps of forming the silicon-based intermediate by forming a passivation layer on the surface of the silicon substrate and a doped conductive semiconductor layer on the surface of the passivation layer include: The silicon substrate is placed in a vacuum chamber; A silicon source gas is introduced into the vacuum chamber, and the passivation layer is formed on the first surface of the silicon substrate by plasma chemical vapor deposition. The passivation layer is a first intrinsic amorphous silicon film. Silicon source gas, hydrogen gas and phosphorus-containing gas are introduced into the vacuum chamber, and the doped conductive semiconductor layer is formed on the surface of the first intrinsic amorphous silicon film by plasma chemical vapor deposition. The doped conductive semiconductor layer is an n-type doped conductive semiconductor layer. Flip the silicon substrate over; A silicon source gas is introduced into the vacuum chamber, and the passivation layer is formed on the second surface of the silicon substrate by plasma chemical vapor deposition. The passivation layer is a second intrinsic amorphous silicon film. Silicon source gas, hydrogen gas, and boron-containing gas are introduced into the vacuum chamber, and the doped conductive semiconductor layer is formed on the surface of the second intrinsic amorphous silicon film by plasma chemical vapor deposition. The doped conductive semiconductor layer is a P-type doped conductive semiconductor layer.

7. The method for preparing a battery according to claim 6, characterized in that, The step of preparing the transparent conductive film layer on the surface of the passivation layer includes: The transparent conductive film layer is formed by depositing the n-type doped conductive semiconductor layer and the p-type doped conductive semiconductor layer using reactive plasma deposition or magnetron sputtering.

8. The method for preparing a battery according to any one of claims 1-7, characterized in that, The step of fabricating an electrode structure in the formed first opening region includes: A seed layer is prepared in the first opening region; An electrode is prepared on the surface of the seed layer to form the electrode structure.

9. The method for preparing a battery according to claim 8, characterized in that, The seed layer is made of at least one of silver, aluminum, copper, magnesium, molybdenum, tungsten, chromium, nickel, and tin; and / or The electrode is made of at least one of the following materials: silver, aluminum, copper, magnesium, molybdenum, tungsten, chromium, nickel, and tin.

10. The method for preparing a battery according to claim 1, characterized in that, Between the step of forming the first opening region in the antireflective layer using an acidic solution containing fluoride ions and the step of fabricating the electrode structure in the formed first opening region, the method further includes: The silicon-based intermediate is placed in an annealing furnace for annealing treatment. The temperature of the annealing furnace is T, and the annealing treatment time is t. Where T satisfies the relationship: 180℃≤T≤220℃, and t satisfies the relationship: 10min≤t≤20min.

11. A battery, characterized in that, It is manufactured using the battery preparation method according to any one of claims 1-10.

12. A photovoltaic module, characterized in that, include: The battery according to claim 11.

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