Solar cell, preparation method thereof and photovoltaic module

Abstract

The embodiment of the invention relates to a solar cell and a preparation method thereof, and a photovoltaic module, the solar cell comprises a substrate, the first surface of the substrate comprises first parts and second parts which are alternately arranged, the first parts are recessed towards the direction of the second surface of the substrate relative to the second parts, and the first parts are provided with a plurality of spaced projection structures; the top surface of the convex structure is lower than the top surface of the second part; the first tunneling layer covers the surface of the first part; the first doped conductive layer covers the surface, away from the substrate, of the first tunneling layer; the first electrode is in electric contact with the first doped conductive layer, and a part of the first electrode is located in the recess of the first part towards the second surface relative to the second part; wherein the width of the first electrode in the first direction is smaller than that of the first doped conductive layer in the first direction, and the first direction is parallel to the first part and perpendicular to the extending direction of the first electrode. The embodiment of the invention is beneficial to improving the photoelectric conversion efficiency of the solar cell.

Description

[0001] Cross - Reference to Related Applications

[0002] This application is a divisional application of a Chinese patent application with an application date of February 23, 2023, an application number of 2023101842114, and an invention title of "Solar Cell and Its Preparation Method, Photovoltaic Module". Technical Field

[0003] Embodiments of this application relate to the field of solar cells, and particularly to a solar cell and its preparation method, and a photovoltaic module. Background Art

[0004] Solar cells have good optoelectronic conversion capabilities. Currently, a tunneling layer and a doped conductive layer are prepared on the surface of the substrate to suppress carrier recombination on the surface of the substrate in the solar cell and enhance the passivation effect on the substrate. Among them, the tunneling layer has a good chemical passivation effect, and the doped conductive layer has a good field passivation effect. In addition, in order to transport and collect the photo-generated carriers generated by the solar cell, an electrode in electrical contact with the doped conductive layer is also prepared to collect the photo-generated carriers.

[0005] The number of photo-generated carriers is related to the absorption and utilization rate of incident light by the substrate. The higher the absorption and utilization rate of incident light by the substrate, the more photo-generated carriers are generated, thereby improving the optoelectronic conversion performance of the solar cell.

[0006] However, the optoelectronic conversion performance of solar cells is poor. Summary of the Invention

[0007] Embodiments of this application provide a solar cell and its preparation method, and a photovoltaic module, which are at least beneficial to improving the optoelectronic conversion efficiency of the solar cell.

[0008] Embodiments of this application provide a solar cell, including: a substrate having opposite first and second surfaces, the first surface including alternately arranged first and second portions, the first portion being recessed toward the second surface relative to the second portion, the first portion having a plurality of spaced-apart protruding structures, the top surface of the protruding structure being lower than the top surface of the second portion; a first tunneling layer covering the surface of the first portion; a first doped conductive layer covering the surface of the first tunneling layer away from the substrate; a first electrode in electrical contact with the first doped conductive layer, and a part of the first electrode being located within the recess of the first portion toward the second surface relative to the second portion; wherein, the width of the first electrode in a first direction is smaller than the width of the first doped conductive layer in the first direction, the first direction being parallel to the first portion and perpendicular to the extending direction of the first electrode.

[0009] In addition, the surface of the first tunneling layer facing the first part has a first texture structure, and the surface of the first tunneling layer away from the first part has a second texture structure. The flatness of the second texture structure is greater than that of the first texture structure. The first texture structure includes a polished surface and a plurality of spaced convex structures located on the polished surface. The area occupied by the plurality of convex structures on the polished surface is not greater than 1 / 2 of the area of the polished surface.

[0010] In addition, the convex structure includes any one of a first pyramid structure or a first platform convex structure.

[0011] In addition, the ratio of the area occupied by the plurality of convex structures on the polished surface to the area of the polished surface is 1:11 to 1:2.

[0012] In addition, the convex structure is a first pyramid structure, and the second texture structure includes: a second platform convex structure.

[0013] In addition, the depression depth of the first part is 1 μm to 5 μm.

[0014] In addition, the ratio of the width of the first doped conductive layer in the first direction to the width of the first electrode in the first direction is less than or equal to 3.

[0015] In addition, it further includes a first passivation layer. The first passivation layer covers the first doped conductive layer and the second part of the first surface. The first electrode penetrates the first passivation layer and is in electrical contact with the first doped conductive layer.

[0016] In addition, the second part of the first surface has a third texture structure, and the third texture structure includes a second pyramid structure.

[0017] In addition, the doping element type of the first doped conductive layer is different from that of the substrate.

[0018] In addition, the material of the first doped conductive layer includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

[0019] In addition, the solar cell further includes an emitter layer. The emitter layer is located in the substrate, faces the second part, and the substrate exposes the top surface of the emitter layer. The top surface of the emitter layer is in contact with the surface of the first passivation layer facing the substrate. The doping element type of the emitter layer is different from that of the substrate.

[0020] In addition, the solar cell further includes: a second tunneling layer located on the second surface; and a second doped conductive layer located on the surface of the second tunneling layer away from the substrate.

[0021] In addition, the type of doping element of the second doped conductive layer is the same as that of the substrate.

[0022] In addition, the material of the second doped conductive layer includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

[0023] Correspondingly, an embodiment of the present application further provides a photovoltaic module, including a battery string formed by connecting a plurality of the solar cells described in any one of the above; an encapsulation layer for covering the surface of the battery string; and a cover plate for covering the surface of the encapsulation layer away from the battery string.

[0024] Correspondingly, an embodiment of the present application further provides a method for manufacturing a solar cell, including: providing an initial substrate having an initial first surface and a second surface opposite thereto; etching the initial substrate from the initial first surface to convert the initial first surface into a first surface, the first surface having an alternately arranged first portion and a second portion, the first portion being recessed toward the second surface relative to the second portion, the first portion having a plurality of spaced protrusion structures, the top surface of the protrusion structure being lower than the top surface of the second portion, and the remaining initial substrate forming a substrate; forming a first tunneling layer covering the first portion; forming a first doped conductive layer covering the surface of the first tunneling layer away from the substrate; forming a first electrode in electrical contact with the first doped conductive layer, and a part of the first electrode being located in the recess of the first portion toward the second surface relative to the second portion; wherein the width of the first electrode in a first direction is less than the width of the first doped conductive layer in the first direction, the first direction being parallel to the first portion and perpendicular to the extending direction of the first electrode.

[0025] In addition, the method for forming the first portion and the second portion includes: forming a mask layer on the initial first surface, the mask layer having a first opening exposing a part of the initial first surface; etching the initial first surface along the first opening to form an initial first groove in the initial substrate and convert the initial first surface into the first surface; performing a polishing process on the side wall and the bottom wall of the initial first groove to make the side wall and the bottom wall of the initial first groove have a polished surface and form an initial second groove; performing a texturing process on the bottom wall and the side wall of the initial second groove to form grooves, the bottom wall and the side wall of the grooves having the protrusion structures; removing the mask layer, the first surface corresponding to the grooves being the first portion, and the portion other than the grooves being the second portion.

[0026] In addition, a texturing process is performed on the bottom wall and the side walls of the initial second groove to form the protruding structure. The method includes: performing a cleaning process on the bottom wall and the side walls of the initial second groove; preparing a texturing additive mother liquor, which includes sodium dodecylbenzenesulfonate and polyvinylpyrrolidone, and the mass ratio of the sodium dodecylbenzenesulfonate to the polyvinylpyrrolidone is 0.1 - 20; providing deionized water, adding the texturing additive mother liquor and sodium hydroxide to the deionized water to prepare an etching solution, wherein the volume ratio of the texturing additive mother liquor to the deionized water is 0.002 - 0.003, and the mass ratio of the sodium hydroxide to the deionized water is 0.03 - 0.1; using the etching solution to clean the bottom wall and the side walls of the initial second groove to form the first texture structure.

[0027] In addition, the method for forming the first tunneling layer includes: forming an initial first tunneling layer on the side walls and the bottom wall of the groove by using a deposition process, and the two opposite surfaces of the initial first tunneling layer have the same first texture structure as the morphologies of the side walls and the bottom wall of the groove; performing a polishing process on the surface of the initial first tunneling layer away from the substrate, and the surface of the initial first tunneling layer away from the substrate after being processed by the polishing process has a second texture structure to form the first tunneling layer.

[0028] The technical solution provided by the embodiment of the present application has at least the following advantages:

[0029] In the technical solution of the solar cell provided by the embodiment of the present application, it is set that the first part of the first surface is recessed towards the second surface relative to the second part, that is, a groove is formed on the first surface of the substrate. The first tunneling layer and the first doped conductive layer covering the first part are equivalent to covering the side walls and the bottom wall of the groove. Since the groove has a large surface area, the surface areas of the formed tunneling layer and the doped conductive layer can be increased. The first electrode is in electrical contact with the doped conductive layer, so that the tunneling layer and the doped conductive layer surround the first electrode, which plays a good passivation role in reducing the high recombination loss caused by the contact between the first electrode and the doped conductive layer, improves the fill factor, and further can improve the photoelectric conversion performance of the solar cell. And the first tunneling layer and the first doped conductive layer are not provided on the second part, which can avoid the parasitic absorption of the incident light by the first doped conductive layer on the second part, and further improves the absorption utilization rate of the incident light.

[0030] In addition, the first tunneling layer and the first doped conductive layer on the side walls of the groove formed in the first part are not directly irradiated by the incident light, so there will be no excessive parasitic absorption. While passivating the high recombination loss of the first electrode, it can ensure a high absorption utilization rate of the incident light, increase the number of carriers, and further improve the photoelectric conversion ability of the solar cell.

[0031] In addition, the presence of the convex structure is beneficial to increasing the contact area between the tunneling layer and the substrate, enlarging the tunneling interface, which is conducive to the tunneling of carriers. The area of the polished surface is relatively large, which can ensure that the interface between the first tunneling layer and the first part is relatively flat, enhancing the passivation ability of the first tunneling layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute limitations on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation.

[0033] Figure 1 Schematic cross-sectional structure diagram of a solar cell provided by an embodiment of the present application;

[0034] Figure 2 Electron microscope image of the first texture structure in a solar cell provided by an embodiment of the present application;

[0035] Figure 3 Schematic cross-sectional structure diagram of another solar cell provided by an embodiment of the present application;

[0036] Figure 4 Schematic diagram of carrier transport in another solar cell provided by an embodiment of the present application;

[0037] Figure 5 Schematic cross-sectional structure diagram of a photovoltaic module provided by another embodiment of the present application;

[0038] Figure 6 Schematic cross-sectional structure diagram corresponding to the step of providing a substrate in a method for manufacturing a solar cell provided by an embodiment of the present application;

[0039] Figure 7 Schematic cross-sectional structure diagram corresponding to the step of forming an emitter in a method for manufacturing a solar cell provided by an embodiment of the present application;

[0040] Figure 8 Schematic cross-sectional structure diagram corresponding to the step of forming a mask layer in a method for manufacturing a solar cell provided by the present application;

[0041] Figure 9 Schematic cross-sectional structure diagram corresponding to the step of forming an initial first groove in a method for manufacturing a solar cell provided by an embodiment of the present application;

[0042] Figure 10 Schematic cross-sectional structure diagram corresponding to the step of forming an initial second groove in a method for manufacturing a solar cell provided by an embodiment of the present application;

[0043] Figure 11Schematic cross-sectional structure diagram corresponding to the step of forming a groove in a method for manufacturing a solar cell provided in an embodiment of the present application;

[0044] Figure 12 Schematic cross-sectional structure diagram corresponding to the step of forming an initial first tunneling layer in a method for manufacturing a solar cell provided in an embodiment of the present application;

[0045] Figure 13 Schematic cross-sectional structure diagram corresponding to the step of forming a first tunneling layer in a method for manufacturing a solar cell provided in an embodiment of the present application;

[0046] Figure 14 Schematic cross-sectional structure diagram corresponding to the step of forming a first doped conductive layer in a method for manufacturing a solar cell provided in an embodiment of the present application;

[0047] Figure 15 Schematic cross-sectional structure diagram corresponding to the steps of forming a second tunneling layer and a second doped conductive layer in a method for manufacturing a solar cell provided in an embodiment of the present application;

[0048] Figure 16 Schematic cross-sectional structure diagram corresponding to the step of forming a first passivation layer in another method for manufacturing a solar cell provided in an embodiment of the present application;

[0049] Figure 17 Schematic cross-sectional structure diagram corresponding to the step of forming a second passivation layer in another method for manufacturing a solar cell provided in an embodiment of the present application. Detailed implementation manners

[0050] As can be seen from the background art, there is a problem that the photoelectric conversion efficiency of current solar cells is relatively low.

[0051] An embodiment of the present application provides a solar cell. A first part of the first surface is recessed towards the second surface relative to a second part, such that the surface areas of the tunneling layer and the doped conductive layer covering the first part are larger. The first electrode is in electrical contact with the doped conductive layer, such that the tunneling layer and the doped conductive layer surround the first electrode, and a better passivation effect on the high recombination loss caused by the contact between the first electrode and the doped conductive layer is achieved. The flatness of the surface of the first tunneling layer away from the first part is greater than the flatness of the surface of the first tunneling layer facing the first part, such that the contact interface between the first doped conductive layer and the first tunneling layer is relatively flat, and the field passivation effect of the first doped conductive layer can be improved. The surface of the first tunneling layer facing the first part is a composite topography of a polished surface and a small number of protruding structures located on the polished surface. The presence of the protruding structures is beneficial to increasing the contact area between the tunneling layer and the substrate, increasing the tunneling interface, and facilitating the tunneling of carriers. The area of the polished surface is relatively large, which can ensure that the interface between the first tunneling layer and the first part is relatively flat and enhance the passivation ability of the first tunneling layer.

[0052] The embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are provided to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0053] Figure 1 It is a schematic cross-sectional structure diagram of a solar cell provided by an embodiment of the present application.

[0054] Reference Figure 1 , the solar cell includes: a substrate 100 having opposite first and second surfaces, the first surface including alternately arranged first part 10 and second part 11, the first part 10 being recessed towards the second surface relative to the second part 11. The solar cell further includes: a first tunneling layer 110 covering the first part 10, the surface of the first tunneling layer 110 facing the first part 10 having a first texture structure, the surface of the first tunneling layer 110 away from the first part 10 having a second texture structure, the flatness of the second texture structure being greater than the flatness of the first texture structure, the first texture structure including a polished surface 1 and a plurality of spaced protruding structures 2 located on the polished surface 1, the area occupied by the plurality of protruding structures 2 on the polished surface 1 being not greater than 1 / 2 of the area of the polished surface 1. The solar cell further includes: a first doped conductive layer 120 covering the surface of the first tunneling layer 110 away from the substrate 100. The solar cell further includes: a first electrode 130 in electrical contact with the first doped conductive layer 120.

[0055] The first electrode 130 penetrates through the first doped conductive layer 120 with a partial thickness and is in electrical contact with the first doped conductive layer 120. The photo-generated carriers generated in the substrate 100 are transmitted from the substrate 100 to the first doped conductive layer 120 and then transmitted into the first electrode 130. The first electrode 130 is used to collect the photo-generated carriers.

[0056] A first part 10 of the first surface is set to be recessed towards the second surface relative to the second part 11 to form a groove. The first tunneling layer 110 and the first doped conductive layer 120 covering the first part 10 are equivalent to covering the side wall and the bottom wall of the groove. Since the groove has a large surface area, the tunneling layer and the doped conductive layer covering the side wall of the groove have a large surface area. The first electrode 130 is in electrical contact with the doped conductive layer, so that the tunneling layer and the doped conductive layer surround the first electrode 130, which plays a good passivation role in reducing the high recombination loss caused by the contact between the first electrode 130 and the doped conductive layer, improves the fill factor, and further can improve the photoelectric conversion performance of the solar cell. And since the first tunneling layer 110 and the first doped conductive layer 120 are not provided in the second part 11, the problem of parasitic absorption of incident light by the first doped conductive layer 120 in the second part 11 can be avoided, and the absorption utilization rate of the substrate 100 for incident light can be improved.

[0057] The first tunneling layer 110 and the first doped conductive layer 120 located on the side wall and the bottom wall of the groove formed by the first part 10 are not directly irradiated by the incident light, avoiding excessive parasitic absorption of the incident light. While increasing the surface area of the first tunneling layer 110 and the first doped conductive layer 120 to improve the high recombination loss of the first electrode 130, it is ensured that the substrate 100 has a high absorption utilization rate for the incident light, which can increase the number of carriers, improve the fill factor, increase the open-circuit voltage and the short-circuit current, and improve the photoelectric conversion performance of the solar cell.

[0058] The surface of the first tunneling layer 110 facing the first part 10 has a first texture structure, and the surface of the first tunneling layer 110 away from the first part 10 has a second texture structure. That is to say, the surface morphology of the first tunneling layer 110 facing the first part 10 is the morphology of the first texture structure, and the surface morphology of the first tunneling layer 110 away from the first part 10 is the morphology of the second texture structure. The flatness of the second texture structure is greater than that of the first texture structure, that is, the surface flatness of the first tunneling layer 110 away from the first part 10 is greater than the surface flatness of the first tunneling layer 110 facing the first part 10.

[0059] That is, the surface flatness of the first tunneling layer 110 away from the first part 10 is relatively high. Since the first doped conductive layer 120 is in contact with the surface of the first tunneling layer 110 away from the first part 10, the contact interface between the first doped conductive layer 120 and the first tunneling layer 110 is relatively flat, which can enhance the field passivation effect of the first doped conductive layer 120. The surface of the first tunneling layer 110 facing the first part 10 has a composite topography of a polished surface 1 and a small number of protruding structures 2 located on the polished surface 1. The existence of the protruding structures 2 is beneficial to increasing the contact area between the tunneling layer and the substrate 100, increasing the tunneling interface, and facilitating the tunneling of carriers. The area of the polished surface 1 is relatively large, which can ensure that the interface between the first tunneling layer 110 and the first part 10 is relatively flat and enhance the passivation ability of the first tunneling layer 110. In some embodiments, the material of the first tunneling layer 110 includes at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon.

[0060] It can be understood that the flatness of the first texture structure refers to the distance difference between the vertex of the relatively protruding structure and the relatively flat surface on the surface of the first tunneling layer 110 facing the first part 10. The smaller the distance difference, the higher the flatness. The flatness of the second texture structure refers to the distance difference between the vertex of the relatively protruding structure and the relatively flat surface on the surface of the second tunneling layer away from the first part 10. The smaller the distance difference, the higher the flatness.

[0061] The substrate 100 is used to receive incident light and generate photo-generated carriers. In some embodiments, the substrate 100 can be a silicon substrate, and the material of the silicon substrate can include at least one of single-crystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon. In some embodiments, the material of the substrate 100 can also be silicon carbide, an organic material, or a multicomponent compound. The multicomponent compound can include, but is not limited to, materials such as perovskite, gallium arsenide, cadmium telluride, and copper indium selenide.

[0062] In some embodiments, both the first surface and the second surface can be used to receive incident light or reflect light. In some embodiments, the second surface can be the light-receiving surface, and the first surface can be the backlight surface. In some embodiments, the first surface can be the light-receiving surface, and the second surface can be the backlight surface. The light-receiving surface refers to the surface that directly receives incident light.

[0063] In some embodiments, the solar cell can be a TOPCON (Tunnel Oxide Passivated Contact) cell.

[0064] In some embodiments, a doped element is present within the substrate 100, and the type of the doped element is N-type or P-type. The N-type element can be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), etc. The P-type element can be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In), etc. For example, when the substrate 100 is a P-type substrate, the type of the doped element inside it is P-type. Or, when the substrate 100 is an N-type substrate, the type of the doped element inside it is N-type.

[0065] Reference Figure 2 , Figure 2 is a SEM image of the first texture structure in the solar cell provided by an embodiment of the present application. In some embodiments, the ratio of the area occupied by the plurality of protrusion structures 2 on the polished surface 1 to the area of the polished surface 1 is 1:11 to 1:2. For example, it can be 1:4 to 1:3, 1:5 to 1:4, 1:6 to 1:5, 1:7 to 1:6, 1:8 to 1:7, 1:9 to 1:8, 1:10 to 1:9, or 1:11 to 1:10.

[0066] Within the above range, the total area occupied by the plurality of protrusion structures 2 on the polished surface 1 is relatively small, so that the roughness of the first texture structure is not too large, and further the flatness of the surface of the first tunneling layer 110 facing the first portion 10 is not too small, avoiding the problem that the chemical passivation ability of the first tunneling layer 110 to the first portion 10 is weakened due to the uneven contact interface between the first tunneling layer 110 and the first portion 10. On the other hand, within the above range, the total area occupied by the plurality of protrusion structures 2 on the polished surface 1 is not too small either, which can appropriately increase the specific surface area of the surface of the first tunneling layer 110 facing the first portion 10, increase the contact area between the first tunneling layer 110 and the first portion 10, and increase the tunneling interface of carriers, which is beneficial to enhancing the carrier collection ability of the first electrode 130.

[0067] The polished surface 1 in the embodiments of the present application refers to a flat surface.

[0068] Reference Figure 1 and Figure 3 , in some embodiments, the protrusion structure 2 includes any one of a first pyramid structure or a first platform protrusion structure.

[0069] Reference Figure 1 and Figure 2 , in some embodiments, the protrusion structure 2 includes a first pyramid structure. The first pyramid structure has a relatively large specific surface area. Setting the protrusion structure 2 as the first pyramid structure can increase the specific surface area of the surface of the first tunneling layer 110 facing the first portion 10, and further can increase the contact area between the first tunneling layer 110 and the first portion 10, and increase the tunneling channel of carriers.

[0070] In some embodiments, the first pyramid structure may be a tetrahedron, an approximate tetrahedron, a pentahedron, an approximate pentahedron, or other structures.

[0071] Reference Figure 3 , in some embodiments, the raised structure 2 is a first platform raised structure, and the first platform raised structure is the base part of the pyramid structure, that is, after removing the tip part of the pyramid structure, the remaining bottom structure. In this way, the top of the raised structure 2 is relatively flat, which can not only increase the contact area between the first tunneling layer 110 and the first part 10, but also ensure that the contact interface between the first tunneling layer 110 and the first part 10 is relatively flat.

[0072] In some embodiments, the raised structure 2 may also be a quasi-platform raised structure. The top surface of the quasi-platform raised structure may be a plane or an inclined plane, and the bottom surface of the quasi-platform raised structure may be a polygon plane, such as a quadrilateral plane or a pentagon plane.

[0073] In some embodiments, the raised structure 2 may be only located on the bottom wall of the groove formed by the first part 10, and the side wall of the groove formed by the first part 10 may be the polished surface 1. In some embodiments, the raised structure 2 may also be located on the bottom wall and the side wall of the groove formed by the first part 10.

[0074] In some embodiments, the raised structure 2 is a first pyramid structure, and the second texture structure includes: a second platform raised structure. The second platform raised structure may be the base structure remaining after removing the tip part of the first pyramid structure. That is to say, compared with the first pyramid structure, the difference in distance between the top surface and the bottom surface of the second platform raised structure is smaller, so that the flatness of the second texture structure is higher, and the one-dimensional size of the bottom surface of the second platform raised structure is larger than the one-dimensional size of the bottom surface of the raised structure 2, so that the degree of protrusion of the second platform raised structure is not too high, which is beneficial to the formation of a higher flatness of the second texture structure.

[0075] It can be understood that the area other than the second platform raised structure in the second texture structure may be a polished surface, and the total area of the bottom surfaces of all the second platform raised structures is not greater than the total area of the polished surface, further increasing the flatness of the second texture structure.

[0076] In some embodiments, the second texture structure may also be entirely a polished surface, that is, all are flat surfaces.

[0077] Reference Figure 1, in some embodiments, the recess depth d of the first portion 10 is 1 μm to 5 μm, and for example, it can be 1 μm to 1.5 μm, 1.5 μm to 2 μm, 2 μm to 2.5 μm, 2.5 μm to 3 μm, 3 μm to 3.5 μm, 3.5 μm to 4 μm, 4 μm to 4.5 μm or 4.5 μm to 5 μm. The recess depth d of the first portion 10 refers to the recess depth of the first portion 10 toward the second surface compared with the second portion 11. Within the above range, the recess depth of the first portion 10 is made larger, so that the first portion 10 has a larger surface area, and the first tunneling layer 110 and the first doped conductive layer 120 formed on the first portion 10 have a larger area, which can improve the passivation effect on the high recombination loss of the first electrode 130 to a certain extent. It can also increase the tunneling interface between the first tunneling layer 110 and the substrate 100. In addition, within the above range, the recess depth of the first portion 10 is not too large. On the one hand, it can prevent greater damage to the substrate 100 and avoid excessive defects in the substrate 100. On the other hand, it can prevent the problem that the thickness of the first doped conductive layer 120 formed on the first portion 10 is too large due to the excessive recess depth of the first portion 10, resulting in excessive parasitic absorption of incident light by the first doped conductive layer 120.

[0078] The first portion 10 is recessed relative to the second portion 11 toward the second surface to form a groove, and the groove has an opening away from the second surface. In some embodiments, the bottom wall of the groove can be a plane, and the side wall of the groove is perpendicular to the bottom wall of the groove. In some embodiments, the bottom of the groove can also have a curvature, that is, the first portion 10 can be an elliptic paraboloid.

[0079] In some embodiments, the width of the first electrode 130 in the first direction X is smaller than the width of the first doped conductive layer 120 in the first direction X. The first direction X is parallel to the first portion 10 and perpendicular to the extension direction of the first electrode 130. In this way, it can be ensured that the first electrode 130 is coated by the first doped conductive layer 120, increasing the contact area between the first electrode 130 and the first doped conductive layer 120, and further reducing the contact resistance between the first electrode 130 and the first doped conductive layer 120, and improving the rate of carrier transmission to the first electrode 130.

[0080] In some embodiments, the material of the first electrode 130 can be a metal material, for example, it can be any one of silver, nickel, aluminum or copper.

[0081] In some embodiments, the ratio of the width of the first doped conductive layer 120 in the first direction X to the width of the first electrode 130 in the first direction X is less than or equal to 3, and can be, for example, 1.1, 1.3, 1.5, 1.7, 2, 2.2, 2.5, 2.8, or 3. Within the above range, the width ratio of the first doped conductive layer 120 to the first electrode 130 is relatively large along the first direction X, which can ensure that the first electrode 130 is covered by the first doped conductive layer 120. Moreover, setting the width of the first doped conductive layer 120 to be relatively large can avoid the problem that when the material for forming the first electrode 130 burns through to the first doped conductive layer 120 during the actual formation of the first electrode 130, it diffuses along the first direction X in the first doped conductive layer 120, resulting in the actual width of the formed first electrode 130 being greater than that of the first doped conductive layer 120, thereby increasing the process window for forming the first electrode 130.

[0082] In addition, within the above range, the width of the first doped conductive layer 120 is not too large compared to the first electrode 130 along the first direction X, which can prevent the problem that the first doped conductive layer 120 receives too much incident light due to its overly large width, thereby resulting in a relatively large parasitic absorption of the first doped conductive layer 120.

[0083] In some embodiments, the type of doping element of the first doped conductive layer 120 is different from that of the substrate 100. That is to say, the first doped conductive layer 120 and the substrate 100 form a PN junction. In some embodiments, if the type of doping element of the substrate 100 is P-type, then the type of doping element of the first doped conductive layer 120 is N-type, and the N-type doping element can be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). In some embodiments, if the type of doping element of the substrate 100 is N-type, then the type of doping element of the first doped conductive layer 120 is P-type, and the P-type doping element can be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0084] In some embodiments, the material of the first doped conductive layer 120 includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

[0085] Reference Figure 1, in some embodiments, it further includes a first passivation layer 150. The first passivation layer 150 covers the first doped conductive layer 120 and the second part 11 of the first surface. The first electrode 130 penetrates the first passivation layer 150 and is in electrical contact with the first doped conductive layer 120. The first passivation layer 150 can be in direct contact with the second part 11. The first passivation layer 150 can have a good passivation effect on the first surface. For example, it can chemically passivate the dangling bonds on the first surface well, reduce the density of defect states on the first surface, and inhibit the carrier recombination on the first surface.

[0086] In some embodiments, if the first passivation layer 150 is a single-layer structure, the material of the first passivation layer 150 can be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, if the first passivation layer 150 is a multi-layer structure, the material of the first passivation layer 150 can be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0087] Reference Figure 4 , in some embodiments, the solar cell further includes an emitter layer 140. The emitter layer 140 is located within the substrate 100, opposite to the second part 11, and the top surface of the emitter layer 140 is exposed from the substrate 100. The top surface of the emitter layer 140 is in contact with the surface of the first passivation layer 150 facing the substrate 100. The doping element type of the emitter layer 140 is different from that of the substrate 100. The emitter layer 140 and the substrate 100 have different doping elements and jointly form a PN junction. In some embodiments, the doping element type of the substrate 100 is P-type, and the doping element type of the emitter is N-type. The N-type doping element can be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). In some embodiments, the doping element type of the substrate 100 is N-type, and the doping element type of the emitter is P-type. The P-type doping element can be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0088] In some embodiments, the material of the emitter layer 140 can be the same as that of the substrate 100. For example, it can be a silicon substrate, and the material of the silicon substrate can include at least one of single-crystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon, or it can also be silicon carbide, an organic material, or a compound. The compound can include, but is not limited to, materials such as perovskite, gallium arsenide, cadmium telluride, and copper indium selenide.

[0089] In some embodiments, the doping element type of the first doped conductive layer 120 is different from that of the substrate 100 to form a PN junction. The emitter and the substrate 100 also form a PN junction, so that the area of the PN junction is larger, and thus more incident light can be converted into photogenerated carriers.

[0090] In some embodiments, the second part 11 of the first surface has a third texture structure, and the third texture structure includes a second pyramid structure. The second pyramid structure may be a tetrahedron, an approximate tetrahedron, a pentahedron, or an approximate pentahedron, etc.

[0091] In some embodiments, the number of the second pyramid structures is plural, and the plural second pyramid structures are arranged at intervals. The second pyramid structures make the second part 11 of the first surface have a suede structure. The second pyramid structure is a tetrahedron structure or a pentahedron structure, which enables the second pyramid structure to have a good reflection ability for incident light. When light irradiates the second surface, the incident light reflected by the second pyramid structures will be reflected multiple times between two adjacent second pyramid structures. Finally, most of the reflected light will be reabsorbed and utilized by the substrate 100, thereby enhancing the utilization rate of the incident light by the substrate 100.

[0092] Reference Figure 1 、 Figure 3 and Figure 4 , in some embodiments, the solar cell further includes: a second tunneling layer 160 located on the second surface; and a second doped conductive layer 170 located on the surface of the second tunneling layer 160 away from the substrate 100. The second tunneling layer 160 has a chemical passivation effect on the second surface, reduces the density of defect states on the second surface, and inhibits carrier recombination on the second surface.

[0093] In some embodiments, the material of the second tunneling layer 160 includes at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon.

[0094] In some embodiments, the type of doping element of the second doped conductive layer 170 is the same as that of the substrate 100. In some embodiments, the type of doping element of both the second doped conductive layer 170 and the substrate 100 is P-type, and the P-type doping element may be a group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In). In some embodiments, the type of doping element of both the second doped conductive layer 170 and the substrate 100 is N-type, and the N-type doping element type may be a group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As).

[0095] In some embodiments, the doping element concentration of the second doped conductive layer 170 is greater than that of the substrate 100, which can form a high-low junction between the second doped conductive layer 170 and the substrate 100 and form a concentration gradient of the same element, producing a barrier effect on carriers and realizing selective transport of carriers.

[0096] In some embodiments, the material of the second doped conductive layer 170 includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

[0097] In some embodiments, it further includes a second passivation layer 180, which is located on the surface of the second doped conductive layer 170 away from the substrate 100. The second passivation layer 180 is used to achieve a good passivation effect on the second surface of the substrate 100, reduce the density of defect states on the second surface, and preferably suppress the carrier recombination on the back surface of the substrate 100. The second passivation layer 180 can also achieve a good antireflection effect, which is beneficial to reducing the reflection of incident light and improving the utilization rate of incident light.

[0098] In some embodiments, if the second passivation layer 180 is a single-layer structure, the material of the second passivation layer 180 can be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, if the second passivation layer 180 is a multi-layer structure, the material of the second passivation layer 180 can be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0099] In some embodiments, it further includes a second electrode 190, which is located on the second surface of the substrate 100 and penetrates through the second passivation layer 180 to be in electrical contact with the second doped conductive layer 170.

[0100] In some embodiments, the material of the second electrode 190 can be a metal, such as copper, silver, nickel, or aluminum.

[0101] In the solar cell provided in the above embodiments, the first part 10 is recessed toward the second surface relative to the second part 11, so that the surface areas of the tunneling layer and the doped conductive layer covering the surface of the first part 10 are relatively large. The tunneling layer and the doped conductive layer can surround the first electrode 130, and play a good passivation role for the high recombination loss caused by the contact between the first electrode 130 and the doped conductive layer. The flatness of the surface of the first tunneling layer 110 away from the first part 10 is greater than the flatness of the surface of the first tunneling layer 110 facing the first part 10, so that the contact interface between the first doped conductive layer 120 and the first tunneling layer 110 is relatively flat, which can enhance the field passivation effect of the first doped conductive layer 120. The surface of the first tunneling layer 110 facing the first part 10 is a composite topography of a polishing surface 1 and a small amount of protruding structures 2 located on the polishing surface 1. The existence of the protruding structures 2 is beneficial to increasing the contact area between the tunneling layer and the substrate 100, increasing the tunneling interface, and facilitating the tunneling of carriers. The area of the polishing surface 1 is relatively large, which can ensure that the interface between the first tunneling layer 110 and the first part 10 is relatively flat and enhance the passivation ability of the first tunneling layer 110.

[0102] Correspondingly, on the other hand, an embodiment of the present application further provides a photovoltaic module. Refer toFigure 5 , the photovoltaic module includes: a battery string formed by connecting a plurality of the solar cells 101 provided in the above embodiments; an encapsulation layer 102 for covering the surface of the battery string; and a cover plate 103 for covering the surface of the encapsulation layer 102 away from the battery string. The solar cells 101 are electrically connected in the form of a whole piece or multiple sub-pieces to form a plurality of battery strings, and the plurality of battery strings are electrically connected in series and / or in parallel.

[0103] In some embodiments, the plurality of battery strings can be electrically connected through a conductive strip 104. The encapsulation layer 102 covers the surface and the back surface of the substrate 100 of the solar cell 101, and the encapsulation layer 102 can be an ethylene-vinyl acetate copolymer (EVA) film, a polyethylene octene copolymer elastomer (POE) film, a polyethylene terephthalate (PET) film, or a polyvinyl butyral (PVB) and other organic encapsulation films. In some embodiments, the cover plate 103 can be a glass cover plate, a plastic cover plate, or other cover plates 103 with a light-transmitting function. The surface of the cover plate 103 facing the encapsulation layer 102 can be an uneven surface, so as to increase the utilization rate of incident light.

[0104] Correspondingly, the embodiment of the present application also provides a method for manufacturing a solar cell, including:

[0105] Referring to Figure 6 , an initial substrate 20 is provided, having an opposite initial first surface 3 and a second surface 4.

[0106] The initial substrate 20 is used to receive incident light and generate photo-generated carriers. In some embodiments, the initial substrate 20 can be a silicon substrate, and the material of the initial substrate 20 can include at least one of single-crystalline silicon, polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0107] In some embodiments, the initial substrate 20 can be an N-type semiconductor substrate, and the doping element of the substrate 100 can be any one of phosphorus, arsenic, or antimony.

[0108] In some embodiments, the initial substrate 20 can also be a P-type semiconductor substrate, and the doping element of the initial substrate 20 can be any one of boron, gallium, or indium.

[0109] In some embodiments, a doping process can be performed on the initial substrate 20, such as an ion implantation process to diffuse doping elements into the initial substrate 20.

[0110] In some embodiments, a texturing process may be performed on the initial first surface 3 to form a textured structure on the initial first surface 3. In some embodiments, the initial first surface 3 may include a pyramid structure. Forming a textured structure on the first surface of the substrate 100 can enhance the parasitic absorption ability of the first surface to incident light.

[0111] In some embodiments, the formed solar cell is a TOPCON cell.

[0112] Reference Figure 7 , in some embodiments, the method for preparing a solar cell includes: forming an emitter layer 140 in the substrate 100, the top surface of the emitter layer 140 is exposed from the substrate 100, and the top surface of the emitter layer 140 coincides with the initial first surface 3. The doping element type of the emitter layer 140 is opposite to that of the substrate 100, and a PN junction is formed with the substrate 100.

[0113] In some embodiments, the method for forming the emitter layer 140 may include: performing a diffusion process on the initial first surface 3 of the initial substrate 20 to diffuse the doping element into a part of the initial substrate 20 to form the emitter layer 140. In some embodiments, the diffusion process may be an ion implantation process.

[0114] In some embodiments, when the initial substrate 20 is an N-type substrate, boron diffusion treatment may be performed on the initial first surface 3, and when the initial substrate 20 is a P-type substrate, phosphorus diffusion treatment may be performed on the initial first surface 3.

[0115] Reference Figures 8 to 11 , etching the initial substrate 20 from the initial first surface 3 to convert the initial first surface 3 into a first surface, the first surface has alternately arranged first portions 10 and second portions 11, the first portions 10 are recessed toward the second surface 4 relative to the second portions 11, and the remaining initial substrate 20 forms the substrate 100.

[0116] That is to say, etching the initial first surface 3 to remove a part of the initial substrate 20, the remaining part of the initial substrate 20 forms the substrate 100, and the initial first surface 3 after etching forms the first surface.

[0117] In some embodiments, the method for forming the first portions 10 and the second portions 11 includes:

[0118] Reference Figure 8 , forming a mask layer 30 on the initial first surface 3, the mask layer 30 has a first opening 31, and the first opening 31 exposes a part of the initial first surface 3. The mask layer 30 can protect the initial first surface 3 that does not need to be etched.

[0119] In some embodiments, the method of forming the mask layer 30 may include: forming an initial mask layer 30 on the initial first surface 3 by a deposition process, which may be either atomic layer deposition or chemical vapor deposition. In some embodiments, the material of the initial mask layer 30 may be silicon oxide.

[0120] In some embodiments, a photolithography process may be used to etch the initial mask layer 30 to form a first opening 31 in the initial mask layer 30.

[0121] Reference Figure 9 , after forming the first opening 31, the initial first surface 3 is etched along the first opening 31 to form an initial first groove 21 in the initial substrate 20 and convert the initial first surface 3 into a first surface. In some embodiments, a mechanical etching, chemical etching or laser etching method may be used to form the initial first groove 21 in the initial substrate 20.

[0122] In some embodiments, a chemical etching method may be used to form the initial first groove 21 in the initial substrate 20. The chemical etching method may include: cleaning the initial first surface 3 exposed by the etching solution in the first opening 31 and corroding the initial substrate 20 starting from the initial first surface 3. In some embodiments, the etching solution may include a hydrofluoric acid solution, and the etching time is controlled within 0.5 min to 5 min. In some embodiments, the mass fraction of the hydrofluoric acid solution may be 2% to 5%.

[0123] In some embodiments, before forming the initial first groove 21, an emitter layer 140 is further formed in the initial substrate 20. Then, in the step of forming the initial first groove 21, the emitter layer 140 opposite to the first opening 31 is also removed, and the emitter layer 140 opposite to the mask layer 30 is retained.

[0124] Reference Figure 10 , a polishing process is performed on the sidewalls and bottom wall of the initial first groove 21 to make the sidewalls and bottom wall of the initial first groove 21 have a polished surface, thereby forming an initial second groove 22. It can be understood that the bottom wall and sidewalls of the initial first groove 21 formed by etching the initial first surface 3 along the first opening 31 will have an uneven morphology. In order to form a composite morphology of a polished surface 1 and a convex structure 2 on the bottom wall and sidewalls of the initial first groove 21 subsequently, a polishing process needs to be performed on the sidewalls and bottom wall of the initial first groove 21 to initially form a polished surface, and the polished surface is a flat surface.

[0125] In some embodiments, the method of the polishing process is an alkaline polishing process. In some embodiments, the alkaline polishing process may include: cleaning the sidewalls and the bottom wall of the initial first groove 21 with an alkaline solution; roughening the sidewalls and the bottom wall of the initial first groove 21 by spraying micro-droplets of the alkaline solution thereon, and then performing pre-cleaning with hydrofluoric acid; polishing the sidewalls and the bottom wall of the initial first groove 21 with a polishing solution. In some embodiments, the concentration of the polishing solution is 0.5% to 5%, the polishing temperature is 50°C to 80°C, and the polishing time is 20 s to 1000 s. By controlling the polishing time and the polishing temperature within the above ranges, the morphology of the sidewalls and the bottom wall of the initial second groove 22 can meet the expectations. In some embodiments, the polishing solution may be a NaOH solution, and in some embodiments, the polishing solution may also be a KOH solution. Finally, the sidewalls and the bottom wall of the polished initial second groove 22 are washed with water and dried.

[0126] Reference Figure 11 , after the initial second groove 22 is formed, a texturing process is performed on the bottom wall and the sidewalls of the initial second groove 22 to form a groove 23, and the bottom wall and the sidewalls of the groove 23 have a first texture structure, and the first texture structure includes a polished surface 1 and a plurality of spaced convex structures 2 located on the polished surface 1, and the area occupied by the plurality of convex structures 2 on the polished surface 1 is not greater than 1 / 2 of the area of the polished surface 1.

[0127] In some embodiments, a texturing process is performed on the bottom wall and the sidewalls of the initial second groove 22 to form a first texture structure, and the method includes:

[0128] First, a cleaning process is performed on the bottom wall and the sidewalls of the initial second groove 22. In some embodiments, the entire substrate 100 may be immersed in deionized water, and ultrasonic treatment may be performed for 2 min to 5 min to remove dirt on the surface of the substrate 100.

[0129] Next, a texturing additive mother liquor is prepared. The texturing additive mother liquor includes sodium dodecylbenzenesulfonate and polyvinylpyrrolidone, and the mass ratio of sodium dodecylbenzenesulfonate to polyvinylpyrrolidone is 0.1 to 20, for example, it may be 0.1 to 0.5, 0.5 to 1, 1 to 3, 3 to 5, 5 to 8, 8 to 10, 10 to 12, 12 to 15, 15 to 17, 17 to 18, 18 to 19, or 19 to 20. In some embodiments, based on the mass ratio of sodium dodecylbenzenesulfonate to polyvinylpyrrolidone, 0.2 g to 2 g of sodium dodecylbenzenesulfonate and 0.1 g to 2 g of polyvinylpyrrolidone may be selected and added to 1000 ml of deionized water to prepare the texturing additive mother liquor.

[0130] Next, deionized water is provided, and a texturing additive mother liquor and sodium hydroxide are added to the deionized water to prepare an etching solution. Among them, the volume ratio of the texturing additive mother liquor to deionized water is 0.002 - 0.003. For example, it can be 0.002 - 0.0021, 0.0021 - 0.0023, 0.0023 - 0.0024, 0.0024 - 0.0025, 0.0025 - 0.0026, 0.0026 - 0.0027, 0.0027 - 0.0028, 0.0028 - 0.0029 or 0.0029 - 0.003; the mass ratio of sodium hydroxide to deionized water is 0.03 - 0.1. For example, it can be 0.03 - 0.04, 0.04 - 0.05, 0.05 - 0.06, 0.06 - 0.07, 0.07 - 0.08, 0.08 - 0.09 or 0.09 - 0.1. In some embodiments, based on the volume ratio of the texturing additive mother liquor to deionized water, 1L - 1.5L of the texturing additive mother liquor can be selected and added to 500L of deionized water. In some embodiments, based on the mass ratio of sodium hydroxide to deionized water, 35 kg of sodium hydroxide can be selected and added to 500L of deionized water.

[0131] The bottom wall and side walls of the initial second groove 22 are cleaned with the etching solution to form a first texture structure. The first texture structure etched with the etching solution having the above-mentioned ratio has a polished surface 1 and a first pyramid structure located on the polished surface 1.

[0132] In some embodiments, by using the etching solution configured with the above-mentioned ratio, the polished surface of the initial second groove 22 can be etched into a first texture structure. In some embodiments, in an environment of 75°C - 90°C, the bottom wall and side walls of the initial second groove 22 can be cleaned with the etching solution for 2 min - 50 min to ensure that the formed first texture structure meets the expectations.

[0133] In some embodiments, if the convex structure 2 is a first platform convex structure, after the first pyramid structure is formed in the above step of cleaning the bottom wall and side walls of the initial second groove 22 with the etching solution, the tip of the first pyramid structure can be removed by a polishing process, and the remaining base part of the first pyramid structure forms the first platform convex structure. In some embodiments, the method of removing the tip of the first pyramid structure by a polishing process may include: polishing the bottom wall and side walls of the groove 23 with a polishing solution. In some embodiments, the concentration of the polishing solution is 0.5% - 3%, the polishing temperature is 50°C - 80°C, and the polishing time is 10 s - 500 s. By controlling the polishing time and polishing temperature within the above ranges, the tip of the first pyramid structure can be removed. In some embodiments, the polishing solution can be a NaOH solution, and in some embodiments, the polishing solution can also be a KOH solution.

[0134] Reference Figures 12 to 13 , in some embodiments, after the groove 23 is formed, a first tunneling layer 110 is formed. The first tunneling layer 110 covers the first portion 10. The surface of the first tunneling layer 110 facing the first portion 10 has a first texture structure, and the surface of the first tunneling layer 110 away from the first portion 10 has a second texture structure. The flatness of the second texture structure is greater than that of the first texture structure.

[0135] In some embodiments, the method of forming the first tunneling layer 110 includes:

[0136] Reference Figure 12 , an initial first tunneling layer 32 is formed on the sidewalls and the bottom wall of the groove 23 by a deposition process. The two opposite surfaces of the initial first tunneling layer 32 have the same first texture structure as the morphologies of the sidewalls and the bottom wall of the groove 23.

[0137] In some embodiments, before the initial first tunneling layer 32 is formed, the mask layer 30 may not be removed, which can prevent the initial first tunneling layer 32 from being formed on the second portion 11.

[0138] In some embodiments, the formed initial first tunneling layer 32 is also located on the surface of the mask layer 30. In subsequent steps, the initial first tunneling layer 32 located on the surface of the mask layer 30 can be removed, and only the initial first tunneling layer 32 is formed in the groove 23. In some embodiments, a deposition process, such as atomic layer deposition or chemical vapor deposition, can be used to form the initial first tunneling layer 32. Since the initial first tunneling layer 32 is formed by a deposition process, the surfaces of the initial first tunneling layer 32 facing the first portion 10 and away from the first portion 10 both have the same morphology as the first texture structure.

[0139] In some embodiments, the material of the initial first tunneling layer 32 includes at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon, or polycrystalline silicon.

[0140] Reference Figure 13 , a polishing process is performed on the surface of the initial first tunneling layer 32 away from the substrate 100. The surface of the initial first tunneling layer 32 treated by the polishing process has a second texture structure, and the first tunneling layer 110 is formed. Since the polishing process is not performed on the surface of the initial first tunneling layer 32 facing the substrate 100, the surface of the first tunneling layer 110 facing the substrate 100 has the same first texture structure as the bottom wall and the sidewalls of the groove 23.

[0141] In some embodiments, the formed second texture structure may be a second platform convex structure, and the area of the second texture structure other than the second platform convex structure may be a polished surface. In some embodiments, the method for forming the second convex structure 2 may refer to the above-mentioned process method for forming the first platform convex structure, which will not be elaborated below.

[0142] In some embodiments, the formed second texture structure may also be entirely a polished surface, that is, entirely a flat surface. In some embodiments, the method for forming the second texture structure as a polished surface may refer to the above-mentioned process method for forming the initial second groove 22 by polishing process, which will not be elaborated below.

[0143] Reference Figure 14 , after forming the first tunneling layer 110, a first doped conductive layer 120 is formed, and the first doped conductive layer 120 covers the surface of the first tunneling layer 110 away from the substrate 100.

[0144] In some embodiments, before the step of forming the first doped conductive layer 120, the first tunneling layer 110 on the surface of the mask layer 30 is not removed, so that the formed first doped conductive layer 120 will not be located in the second part 11.

[0145] In some embodiments, the method for forming the first doped conductive layer 120 may include: forming a first dopable layer on the surface of the first tunneling layer 110 and the surface of the first tunneling layer 110 on the mask layer 30 by a deposition process, and during the deposition process, injecting doping elements into the first dopable layer by an in-situ deposition process to form the original first doped conductive layer 120. Performing the deposition process and the process of injecting doping elements simultaneously can save process time and improve process efficiency.

[0146] After injecting doping elements into the first dopable layer, an annealing process is performed on the original first doped conductive layer 120 to form the first doped conductive layer 120. Through the annealing process, the doping elements in the original first doped conductive layer 120 can be activated to form activated doping elements.

[0147] In some embodiments, during the process of injecting doping elements into the first dopable layer, the concentration of the injected doping elements is controlled to be 1×10 20 atom / cm 3 ~1×10 21 atom / cm 3 .

[0148] In some embodiments, the type of doping element implanted in the first dopable layer is different from that of the substrate 100 to form a PN junction with the substrate 100. In some embodiments, the type of doping element of the substrate 100 is P-type, and the type of doping element of the emitter is N-type. The N-type doping element can be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As). In some embodiments, the type of doping element of the substrate 100 is N-type, and the type of doping element of the emitter is P-type. The P-type doping element can be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0149] In some embodiments, the material of the first dopable layer can be any one of amorphous silicon, polycrystalline silicon, microcrystalline silicon, or silicon carbide.

[0150] It is not difficult to find that the first dopable layer is formed on the surface of the first tunneling layer 110 far from the substrate 100. Since the surface of the first tunneling layer 110 far from the substrate 100 has a second texture structure with a relatively high flatness, the first dopable layer is formed on a relatively flat surface, which can improve the uniformity of the formed first dopable layer, thereby improving the passivation ability of the formed first doped conductive layer 120.

[0151] It should be noted that the formed first doped conductive layer 120 is also located on the surface of the first tunneling layer 110 on the mask layer 30. In some embodiments, after the first doped conductive layer 120 is formed, the first doped conductive layer 120 on the mask layer 30, the first tunneling layer 110 on the mask layer 30, and the mask layer 30 are removed so that the formed first tunneling layer 110 and the first doped conductive layer 120 are located in the groove 23. In some embodiments, an acid pickling process can be used to remove the first doped conductive layer 120 on the mask layer 30, the first tunneling layer 110 on the mask layer 30, and the mask layer 30. For example, a hydrofluoric acid solution or a hydrochloric acid solution can be used to clean the first doped conductive layer 120 on the mask layer 30, the first tunneling layer 110 on the mask layer 30, and the mask layer 30 to remove the first doped conductive layer 120 on the mask layer 30, the first tunneling layer 110 on the mask layer 30, and the mask layer 30.

[0152] Reference Figure 15, in some embodiments, the method for preparing a solar cell further includes: forming a second tunneling layer 160 on the second surface 4 of the substrate 100. In some embodiments, the second tunneling layer 160 can be formed on the second surface 4 by a deposition process, and the deposition process can be any one of atomic layer deposition process or chemical vapor deposition process. In some embodiments, the material of the second tunneling layer 160 can be at least one of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, amorphous silicon or polycrystalline silicon.

[0153] In some embodiments, after forming the second tunneling layer 160, a second doped conductive layer 170 is formed on the surface of the second tunneling layer 160 away from the substrate 100.

[0154] The method for forming the second doped conductive layer 170 can include: forming a second dopable layer on the surface of the second tunneling layer 160 by a deposition process, and during the deposition process, doping elements are implanted into the second dopable layer by an in-situ deposition process to form a raw second doped conductive layer 170.

[0155] After doping elements are implanted into the second dopable layer, an annealing process is performed on the raw second doped conductive layer 170 to form the second doped conductive layer 170.

[0156] In some embodiments, the type of doping elements implanted into the second dopable layer is the same as the type of doping elements in the substrate 100. In some embodiments, the type of doping elements in both the second doped conductive layer 170 and the substrate 100 is P-type, and the P-type doping elements can be group III elements such as boron (B), aluminum (Al), gallium (Ga) or indium (In) elements. In some embodiments, the type of doping elements in both the second doped conductive layer 170 and the substrate 100 is N-type, and the N-type doping element type can be group V elements such as phosphorus (P), bismuth (Bi), antimony (Sb) or arsenic (As) elements.

[0157] In some embodiments, the material of the second dopable layer can be any one of amorphous silicon, polycrystalline silicon, microcrystalline silicon or silicon carbide.

[0158] Reference Figure 16 , in some embodiments, the method for preparing a solar cell further includes: forming a first passivation layer 150, and the first passivation layer 150 covers the first doped conductive layer 120 and the second part 11 of the first surface. In some embodiments, an emitter layer 140 is further formed in the substrate 100, and the top surface of the emitter layer 140 coincides with the second part 11, so that the first passivation layer 150 is located on the top surface of the emitter layer 140 and the top surface of the first doped conductive layer 120.

[0159] In some embodiments, the emitter layer 140 may not be formed in the substrate 100, and then the first passivation layer 150 is in direct contact with the second part 11.

[0160] In some embodiments, the first passivation layer 150 may be a single-layer structure. In some embodiments, the first passivation layer 150 may also be a multi-layer structure.

[0161] In some embodiments, if the first passivation layer 150 is a single-layer structure, the material of the first passivation layer 150 may be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, if the first passivation layer 150 is a multi-layer structure, the material of the first passivation layer 150 may be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0162] In some embodiments, the method of forming the first passivation layer 150 may include: forming the first passivation layer 150 on the surface of the doped conductive layer by using the PECVD (Plasma Enhanced Chemical Vapor Deposition) method.

[0163] Reference Figure 17 , in some embodiments, it further includes: forming a second passivation layer 180 on the surface of the second doped conductive layer 170, and the second passivation layer 180 can achieve a better passivation effect. In some embodiments, the second passivation layer 180 may be a single-layer structure. In some embodiments, the second passivation layer 180 may also be a multi-layer structure.

[0164] In some embodiments, if the second passivation layer 180 is a single-layer structure, the material of the second passivation layer 180 may be one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride. In some embodiments, if the second passivation layer 180 is a multi-layer structure, the material of the second passivation layer 180 may be at least one of silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0165] In some embodiments, the second passivation layer 180 may be formed on the emitter surface by using the PECVD process.

[0166] Reference Figure 3 , the method for manufacturing a solar cell further includes: forming a first electrode 130, and the first electrode 130 is in electrical contact with the first doped conductive layer 120. In some embodiments, the first electrode 130 penetrates the first passivation layer 150 and is in electrical contact with the first doped conductive layer 120.

[0167] In some embodiments, the method of forming the first electrode 130 includes: printing a conductive paste on the surface of the first passivation layer 150 facing the first doped conductive layer 120. For example, the conductive paste can be printed using a screen printing process. The conductive paste may include at least one of silver, aluminum, copper, tin, gold, lead, or nickel. A sintering process is performed on the conductive paste on the surface of the first passivation layer 150, so that the conductive paste penetrates into the first passivation layer 150 and a part of the doped conductive layer, and forms an electrical contact with the doped conductive layer.

[0168] In some embodiments, it further includes: forming a second electrode 190, and the second electrode 190 penetrates through the second passivation layer 180 and is in electrical contact with the second doped conductive layer 170. In some embodiments, the process of forming the second electrode 190 can be the same as the process of forming the first electrode 130, and reference can be made to the above description of the method of forming the first electrode 130.

[0169] Although this application is disclosed above with preferred embodiments, it is not used to limit the claims. Any person skilled in the art can make several possible changes and modifications without departing from the concept of this application. Therefore, the protection scope of this application should be subject to the scope defined by the claims of this application.

[0170] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing this application. In actual applications, various changes can be made in form and details without departing from the spirit and scope of this application. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of this application. Therefore, the protection scope of this application should be subject to the scope defined by the claims.

Claims

1. A solar cell, characterized in that, Comprising: A substrate having opposite first and second surfaces, the first surface including alternating first and second portions, the first portion being recessed in a direction towards the second surface relative to the second portion, the first portion having a plurality of spaced-apart protrusion structures, the top surface of the protrusion structures being lower than the top surface of the second portion; A first tunneling layer covering the surface of the first portion; A first doped conductive layer covering the surface of the first tunneling layer remote from the substrate; A first electrode in electrical contact with the first doped conductive layer, a portion of the first electrode being located within the recess of the first portion in the direction towards the second surface relative to the second portion; Wherein, the width of the first electrode in a first direction is less than the width of the first doped conductive layer in the first direction, the first direction being parallel to the first portion and perpendicular to the extending direction of the first electrode.

2. The solar cell according to claim 1, wherein The surface of the first tunneling layer facing the first portion has a first texture structure, the surface of the first tunneling layer remote from the first portion has a second texture structure, the flatness of the second texture structure being greater than that of the first texture structure, the first texture structure including a polished surface and a plurality of spaced-apart protrusion structures located on the polished surface, the area occupied by the plurality of protrusion structures on the polished surface being not greater than 1 / 2 of the area of the polished surface.

3. The solar cell according to claim 1, wherein, The protrusion structure includes any one of a first pyramid structure or a first platform protrusion structure.

4. The solar cell according to claim 2, characterized in that, The ratio of the area occupied by the plurality of protrusion structures on the polished surface to the area of the polished surface is 1:11 to 1:

2.

5. The solar cell according to claim 2, characterized in that, The protrusion structure is a first pyramid structure, and the second texture structure includes: a second platform protrusion structure.

6. The solar cell according to claim 1, characterized in that, The recess depth of the first portion is 1 μm to 5 μm.

7. The solar cell according to claim 1, characterized in that, The ratio of the width of the first doped conductive layer in the first direction to the width of the first electrode in the first direction is less than or equal to 3.

8. The solar cell according to claim 1, characterized in that, Further including a first passivation layer, the first passivation layer covering the first doped conductive layer and the second portion of the first surface, the first electrode penetrating the first passivation layer to be in electrical contact with the first doped conductive layer.

9. The solar cell according to claim 8, wherein, The second portion of the first surface has a third texture structure, the third texture structure including a second pyramid structure.

10. The solar cell according to claim 8, characterized in that, The doping element type of the first doped conductive layer is different from that of the substrate.

11. The solar cell according to claim 10, characterized in that, The material of the first doped conductive layer includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

12. The solar cell according to claim 8 or 10, characterized in that, Further including: An emitter layer located within the substrate, opposite to the second portion, and the substrate exposes the top surface of the emitter layer, the top surface of the emitter layer being in contact with the surface of the first passivation layer facing the substrate, the doping element type of the emitter layer being different from that of the substrate.

13. The solar cell according to claim 1 or 10, characterized in that, The solar cell further includes: A second tunneling layer located on the second surface; A second doped conductive layer located on the surface of the second tunneling layer remote from the substrate.

14. The solar cell according to claim 13, characterized in that, The doping element type of the second doped conductive layer is the same as that of the substrate.

15. The solar cell according to claim 14, characterized in that, The material of the second doped conductive layer includes at least one of amorphous silicon, polycrystalline silicon, and silicon carbide.

16. A photovoltaic module, characterized in that, including: a battery string formed by connecting a plurality of solar cells as described in any one of claims 1 to 15; a packaging layer for covering the surface of the battery string; a cover plate for covering the surface of the packaging layer away from the battery string.

17. A method for preparing a solar cell, characterized in that, including: providing an initial substrate having an opposite initial first surface and a second surface; etching the initial substrate from the initial first surface to convert the initial first surface into a first surface, the first surface having an alternately arranged first part and a second part, the first part being recessed in the direction of the second surface relative to the second part, the first part having a plurality of spaced protrusion structures, the top surface of the protrusion structure being lower than the top surface of the second part, and the remaining initial substrate forming a substrate; forming a first tunneling layer covering the first part; forming a first doped conductive layer covering the surface of the first tunneling layer away from the substrate; forming a first electrode in electrical contact with the first doped conductive layer, and a part of the first electrode being located in the recess of the first part in the direction of the second surface relative to the second part; wherein, the width of the first electrode in a first direction is smaller than the width of the first doped conductive layer in the first direction, the first direction is parallel to the first part, and perpendicular to the extending direction of the first electrode.

18. The manufacturing method of the solar cell according to claim 17, characterized in that, The method for forming the first part and the second part includes: forming a mask layer on the initial first surface, the mask layer having a first opening exposing a part of the initial first surface; etching the initial first surface along the first opening to form an initial first groove in the initial substrate and convert the initial first surface into the first surface; performing a polishing process on the side wall and the bottom wall of the initial first groove to make the side wall and the bottom wall of the initial first groove have a polished surface and form an initial second groove; performing a texturing process on the bottom wall and the side wall of the initial second groove to form grooves, the bottom wall and the side wall of the grooves having the protrusion structures; removing the mask layer, the first surface corresponding to the groove being the first part, and the part other than the groove being the second part.

19. The manufacturing method of the solar cell according to claim 18, wherein, The method for performing the texturing process on the bottom wall and the side wall of the initial second groove to form the protrusion structures includes: performing a cleaning process on the bottom wall and the side wall of the initial second groove; configuring a texturing additive mother liquor, the texturing additive mother liquor including sodium dodecylbenzenesulfonate and polyvinylpyrrolidone, and the mass ratio of sodium dodecylbenzenesulfonate to polyvinylpyrrolidone being 0.1 to 20; providing deionized water, adding the texturing additive mother liquor and sodium hydroxide to the deionized water to prepare an etching solution, wherein the volume ratio of the texturing additive mother liquor to the deionized water is 0.002 to 0.003, and the mass ratio of sodium hydroxide to the deionized water is 0.03 to 0.1; Clean the bottom wall and side walls of the initial second groove with the described etching solution to form the raised structure.

20. The method for preparing a solar cell according to claim 19, wherein, The method for forming the first tunneling layer includes: Form an initial first tunneling layer on the side walls and bottom wall of the groove by a deposition process, and the two opposite surfaces of the initial first tunneling layer have a first texture structure identical to the topography of the side walls and bottom wall of the groove; Perform a polishing process on the surface of the initial first tunneling layer away from the substrate, and the surface of the initial first tunneling layer away from the substrate treated by the polishing process has a second texture structure to form the first tunneling layer.

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