Full-passivation contact TOPCon battery structure and preparation method thereof

Abstract

The invention belongs to the technical field of crystalline silicon solar cells, and particularly relates to a full-passivation contact TOPCon cell structure and a preparation method thereof, and the full-passivation contact TOPCon cell structure comprises an N-type silicon substrate which comprises a light receiving surface and a backlight surface; a passivation contact area and a light receiving area which are arranged in an interdigital structure are arranged on the light receiving surface; an N + internal expansion layer, a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer are sequentially stacked on the passivation contact region to form a poly passivation contact structure; a P + internal expansion layer, a tunneling oxide layer and a boron-doped polycrystalline silicon layer are sequentially stacked on the backlight surface to form a back junction structure; according to the invention, the boron-doped polycrystalline silicon is set as the phosphorus-doped patterned interdigital poly passivation contact structure on the light receiving surface, the passivation parasitic absorption problem of the polycrystalline silicon arranged on the front surface is effectively solved, and meanwhile, the boron-doped amorphous silicon on the backlight surface adopts a film stacking and annealing design, so that the defect that the boron-doped polycrystalline silicon cannot give consideration to contact and passivation at the same time is overcome, and the service life of the device is prolonged. And the battery efficiency of the double-sided full-passivation contact battery is further improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of crystalline silicon solar cells, and particularly relates to a fully passivated contact TOPCon cell structure and a preparation method thereof. Background Art

[0002] TOPCon (Tunnel Oxide Passivated Contact) cells have the characteristics of high efficiency and high stability, and are favored by the market.

[0003] By introducing Tunnel Oxide Passivated Contact (metal - poly - SiO2 - Si) on both sides of the cell to replace the traditional direct contact between metal and silicon, surface recombination can be reduced, the open - circuit voltage and fill factor of the cell can be increased, thereby improving the cell efficiency.

[0004] However, in existing TOPCon cells, only the back side uses the passivated contact technology, and the front side still uses the traditional metal - semiconductor contact. Carriers (electrons and holes) recombine due to the high interface state density, resulting in large recombination losses and restricting the improvement of cell efficiency.

[0005] Therefore, how to provide a fully passivated crystalline silicon cell that overcomes the recombination losses of traditional back - side TOPCon cells is a technical problem that urgently needs to be solved in this field.

[0006] It should be noted that the above information disclosed in this background art section is only used to understand the background art of the concept of this application. Therefore, the above description is not considered as information of the prior art. Summary of the Invention

[0007] The embodiments of the present disclosure at least provide a fully passivated contact TOPCon cell structure and a preparation method thereof.

[0008] In a first aspect, the embodiments of the present disclosure provide a fully passivated contact TOPCon cell structure, including: an N - type silicon substrate, including a light - receiving surface and a back - light surface; on the light - receiving surface, there are passivated contact regions and light - receiving regions arranged in an interdigitated structure; on the passivated contact regions, an N + inner diffusion layer, a tunneling oxide layer, and a phosphorus - doped polysilicon layer are sequentially stacked to form a poly passivated contact structure; on the back - light surface, a P + inner diffusion layer, a tunneling oxide layer, and a boron - doped polysilicon layer are sequentially stacked to form a back - junction structure.

[0009] In an optional embodiment, the back - junction structure of the back - light surface is obtained by high - temperature oxidation annealing of a tunneling oxide layer, an intrinsic amorphous silicon layer, a carbon - doped amorphous silicon layer, and a boron - doped amorphous silicon layer sequentially stacked from the back - light surface; wherein, the intrinsic amorphous silicon layer, the carbon - doped amorphous silicon layer, and the boron - doped amorphous silicon layer form a boron - doped polysilicon layer; the P + inner diffusion layer is formed after boron atoms in the boron - doped amorphous silicon layer are pushed into the N - type silicon substrate to form tunneling pinholes.

[0010] In an alternative embodiment, on the passivation contact region, the doped thickness of the phosphorus-doped polysilicon layer is 30 nm to 200 nm, and the effective doping concentration is 5×10 19 cm -3 ~1×10 22 cm -3 ; the thickness of the tunneling oxide layer is 0.5 nm to 3 nm, and the thickness ratio of the tunneling oxide layer to the phosphorus-doped polysilicon layer is 1:60 to 1:200; the diffusion depth of the N+ inner diffusion layer is 20 nm to 100 nm; the pattern width of the poly passivation contact structure in the passivation contact region is 50 μm to 300 μm.

[0011] In an alternative embodiment, on the backlight surface, the thickness of the tunneling oxide layer is 0.5 nm - 3 nm; the thickness of the boron-doped polysilicon layer is 30 nm to 500 nm, and the thickness ratio of the tunneling oxide layer to the boron-doped polysilicon layer is 1:50 to 1:500, and the effective doping concentration is 5×10 19 cm -3 ~1×10 21 cm -3 ; the diffusion depth of the P+ inner diffusion layer is 30 nm to 120 nm.

[0012] In an alternative embodiment, the light-receiving surface of the N-type silicon substrate has a pyramid texture morphology, and the reflectivity is 9% to 12%; the height of the pyramid is 0.8 μm to 5 μm, and the width of the tower is 1 μm to 5 μm.

[0013] In an alternative embodiment, the backlight surface of the N-type silicon substrate has an alkaline-etched tower base morphology, and the reflectivity is 35% to 45%; the size of the alkaline-etched tower base is 5 μm to 15 μm.

[0014] In an alternative embodiment, a passivation antireflection layer is provided on the outermost sides of both the light-receiving surface and the backlight surface; the passivation antireflection layer includes any one or a combination of multiple of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, and amorphous silicon; the film thickness of the passivation antireflection layer is 50 nm to 200 nm, and the refractive index is 1.8 to 2.2.

[0015] In an alternative embodiment, the N-type silicon substrate includes any one of Czochralski single crystal and ingot single crystal.

[0016] In an alternative embodiment, corresponding metal electrodes are provided on the passivation contact region and the passivation antireflection layer of its backlight surface region; the metal electrodes include any one or a combination of multiple of silver, copper, aluminum, and tin; the width of the metal electrode is 10 μm to 50 μm, and the height is 5 μm to 20 μm.

[0017] In a second aspect, an embodiment of the present disclosure further provides a method for preparing the fully passivated contact TOPCon cell structure as described above, including the following steps: providing a clean double-sided polished silicon wafer to obtain an N-type silicon substrate; sequentially preparing a tunneling oxide layer, an intrinsic amorphous silicon layer, a carbon-doped amorphous silicon layer, and a boron-doped amorphous silicon layer on the backlight side of the N-type silicon substrate; performing high-temperature oxidation annealing to obtain a back contact structure with a P+ inner diffusion layer, a tunneling oxide layer, and a boron-doped polysilicon layer on the backlight side; texturing the light-receiving side of the N-type silicon substrate; sequentially depositing a tunneling oxide layer and a phosphorus-doped amorphous silicon layer on the light-receiving side of the N-type silicon substrate, and performing high-temperature oxidation annealing to obtain a poly passivated contact structure with an N+ inner diffusion layer, a tunneling oxide layer, and a phosphorus-doped polysilicon layer; locally opening a film on the light-receiving side of the N-type silicon substrate to prepare a patterned finger structure; re-texturing the film-opening area on the light-receiving side, and cleaning the light-receiving side and the backlight side; respectively depositing a passivation and antireflection film on the light-receiving side and the backlight side; performing screen printing and sintering to obtain metal electrodes.

[0018] The beneficial effect of the present invention is that, by setting the boron-doped polysilicon as a patterned finger poly passivated contact structure doped with phosphorus on the light-receiving side, the present fully passivated contact TOPCon cell structure and its preparation method effectively solve the problem of passivation parasitic absorption of polysilicon on the front side. At the same time, the boron-doped amorphous silicon on the backlight side adopts a stacked film and re-annealing design, which solves the defect that boron-doped polysilicon cannot balance low contact resistance and high passivation, and realizes further improvement of the cell efficiency of the double-sided fully passivated contact cell.

[0019] Other features and advantages of the present invention will be described in the following specification, and part of them will become obvious from the specification, or will be understood by implementing the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structures specifically pointed out in the specification and the drawings.

[0020] To make the above objectives, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes the following detailed description. Description of the Drawings

[0021] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 It is a schematic structural diagram of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0023] Figure 2Process flow diagram for the preparation of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0024] Figure 3 Schematic structural diagram of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0025] Figure 4 Process flow diagram for the preparation of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0026] Figure 5 Schematic structural diagram of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0027] Figure 6 Schematic structural diagram of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0028] Figure 7 Process flow diagram for the preparation of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0029] Figure 8 Schematic structural diagram of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0030] Figure 9 Process flow diagram for the preparation of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0031] Figure 10 Schematic structural diagram of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0032] Figure 11 Schematic structural diagram of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0033] Figure 12 Process flow diagram for the preparation of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0034] Figure 13 Schematic structural diagram of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure;

[0035] Figure 14 Schematic structural diagram of a fully passivated contact TOPCon cell provided by an embodiment of the present disclosure.

[0036] In the figure:

[0037] 1. N-type silicon substrate; 2. Light-receiving surface (front surface); 21. Passivated contact region; 22. Light-receiving region; 3. Backlight surface (back surface); 4. Tunneling oxide layer; 5. Boron-doped polysilicon layer; 51. Intrinsic amorphous silicon layer; 52. Carbon-doped amorphous silicon layer; 53. Boron-doped amorphous silicon layer; 61. P+ inner diffusion layer; 62. N+ inner diffusion layer; 7. Annealed oxide layer; 8. Phosphorus-doped polysilicon layer; 91. Aluminum oxide layer; 92. Silicon nitride layer; 10. Metal electrode. Detailed implementation manners

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0039] As used herein, phrases such as "in one embodiment", "according to one embodiment", "in some embodiments", etc. generally refer to the fact that the specific features, structures, or characteristics after the phrase can be included in at least one embodiment of the present disclosure. Therefore, the specific features, structures, or characteristics can be included in more than one embodiment of the present disclosure, such that these phrases do not necessarily refer to the same embodiment. As used herein, terms such as "example", "exemplary", etc. are used "for the purpose of serving as an example, instance, or illustration. Any embodiment, aspect, or design described herein as "example" or "exemplary" is not necessarily construed as being preferred or superior to other embodiments, aspects, or designs. Instead, the use of terms such as "example", "exemplary", etc. is intended to present concepts in a specific manner.

[0040] In this document, example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0041] The terms used in this document are only for describing specific exemplary configurations and are not intended to be restrictive. As used herein, the singular articles "a", "an", and "the" may also be intended to include the plural forms, unless it is clearly stated otherwise in the context. The terms "comprising", "including", and "having" are inclusive, so they specify the presence of features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or their combinations. The method steps, processes, and operations described herein should not be construed as necessarily requiring them to be performed in the specific order discussed or shown, unless specifically identified as the order of execution. Additional or alternative steps may be employed.

[0042] In this document, "poly" refers to polysilicon and "TOPCon" refers to tunnel oxide passivated contact.

[0043] There are two reasons why the existing cells do not use tunnel passivated contact on the front side: 1. Boron-doped polysilicon has strong parasitic absorption of photons, and using poly for passivation on the front side results in extremely large optical losses; 2. Boron atoms in boron-doped polysilicon are difficult to be activated during the annealing process to prepare a material with low contact resistance. At the same time, the solubility of boron atoms in silicon oxide is relatively high, and during the annealing activation process, it is very easy to damage the tunnel oxide layer, resulting in passivation failure.

[0044] The existing process, such as Patent No. CN 118983352 A, has the following process steps: 1. Double-sided polishing; 2. LP preparation of tunnel oxide layer; 3. LP preparation of intrinsic polysilicon layer; 4. ALD preparation of alumina barrier layer; 5. PECVD preparation of boron-doped amorphous silicon; 6. Annealing; 7. Anti-reflection film deposition; that is, boron-doped polysilicon is prepared by using LP intrinsic polysilicon + ALD alumina barrier layer + PECVD doping layer + annealing. The intrinsic polysilicon and alumina barrier layer reduce boron inward diffusion and improve cell passivation. It has the following disadvantages: 1. Using three different deposition methods of equipment to prepare boron-doped poly, the process is complex and the cost is high; 2. Tube LPCVD and tube PECVD both have overcoating, and additional cleaning equipment is required to remove it.

[0045] Regarding the defects existing in the above solutions, they are all the results obtained by the inventors after practice and careful research. Therefore, the process of discovering the above problems and the solutions proposed by the present disclosure for the above problems in the following text should all be the contributions made by the inventors during the process of this disclosure.

[0046] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0047] The following will, in conjunction with the accompanying drawings, elaborate on some embodiments of the present invention. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0048] The embodiments of the present disclosure provide a fully passivated contact TOPCon cell structure, including: an N-type silicon substrate, including a light-receiving surface and a backlight surface; a passivated contact region and a light-receiving region arranged in a finger-like structure are provided on the light-receiving surface; an N+ inner diffusion layer, a tunneling oxide layer, and a phosphorus-doped polysilicon layer are sequentially stacked on the passivated contact region to form a poly passivated contact structure; a P+ inner diffusion layer, a tunneling oxide layer, and a boron-doped polysilicon layer are sequentially stacked on the backlight surface to form a back junction structure.

[0049] Specifically, phosphorus-doped amorphous silicon is placed on the front of the cell in a patterned finger-like manner, and boron-doped amorphous silicon is placed on the back of the cell, greatly reducing the parasitic absorption of photons by amorphous silicon and solving the problem of low current density in traditional double-sided poly cells.

[0050] In some embodiments, specifically, the back junction structure on the backlight surface is obtained by high-temperature oxidation annealing of a tunneling oxide layer, an intrinsic amorphous silicon layer, a carbon-doped amorphous silicon layer, and a boron-doped amorphous silicon layer sequentially stacked from the backlight surface; wherein, the intrinsic amorphous silicon layer, the carbon-doped amorphous silicon layer, and the boron-doped amorphous silicon layer form a boron-doped polysilicon layer; the P+ inner diffusion layer is formed after boron atoms in the boron-doped amorphous silicon layer are pushed into the N-type silicon substrate to form tunneling pinholes.

[0051] Specifically, boron-doped polysilicon is prepared by a structure of intrinsic amorphous silicon + buffer amorphous silicon + boron-doped amorphous silicon, first crystallized at a low temperature and then annealed at a high temperature, reducing the boron atom propulsion speed and increasing the activation time, and solving the problem that traditional boron-doped amorphous silicon cannot simultaneously meet the requirements of high passivation and low contact resistance.

[0052] In some embodiments, specifically, on the passivated contact region, the doping thickness of the phosphorus-doped polysilicon layer is 30 nm to 200 nm, and the effective doping concentration is 5×10 19 cm -3 ~1×10 22 cm -3 ; the thickness of the tunneling oxide layer is 0.5 nm - 3 nm, and the thickness ratio of the tunneling oxide layer to the phosphorus-doped polysilicon layer is (1:60) - (1:200); the diffusion depth of the N+ inner diffusion layer is 20 nm to 100 nm; the graphic width of the poly passivated contact structure in the passivated contact region is 50 μm to 300 μm.

[0053] In some embodiments, specifically, on the backlight surface, the thickness of the tunneling oxide layer is 0.5 nm to 3 nm; the thickness of the boron-doped polysilicon layer is 30 nm to 500 nm, and the thickness ratio of the tunneling oxide layer to the boron-doped polysilicon layer is 1:50 to 1:500, and the effective doping concentration is 5×10 19 cm -3 ~1×10 21 cm -3 ; the diffusion depth of the P+ inner diffusion layer is 30 nm to 120 nm.

[0054] In some embodiments, specifically, the light-receiving surface of the N-type silicon substrate has a pyramid texture, and the reflectivity is 9% to 12%; the height of the pyramid is 0.8 μm to 5 μm, and the width of the pyramid is 1 μm to 5 μm.

[0055] In some embodiments, specifically, the backlight surface of the N-type silicon substrate has an alkaline-etched tower base texture, and the reflectivity is 35% to 45%; the size of the alkaline-etched tower base is 5 μm to 15 μm.

[0056] In some embodiments, specifically, a passivation and antireflection layer is provided on the outermost sides of both the light-receiving surface and the backlight surface; the passivation and antireflection layer includes any one or a combination of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, and amorphous silicon; the film thickness of the passivation and antireflection layer is 50 nm to 200 nm, and the refractive index is 1.8 to 2.2.

[0057] In some embodiments, specifically, the N-type silicon substrate includes any one of Czochralski single crystal and ingot single crystal.

[0058] In some embodiments, specifically, corresponding metal electrodes are provided on the passivation contact region and the passivation and antireflection layer of its backlight surface region; the metal electrodes include any one or a combination of silver, copper, aluminum, and tin; the width of the metal electrode is 10 μm to 50 μm, and the height is 5 μm to 20 μm.

[0059] The embodiments of the present disclosure also provide a preparation method of the fully passivated contact TOPCon cell structure as described above, including the following steps:

[0060] Step S1, providing a clean double-sided polished silicon wafer to obtain N-type silicon substrate 1, to obtain the structure as Figure 1 shown, and the specific process is as Figure 2 shown;

[0061] In this step, a clean silicon wafer surface is obtained by wet cleaning, and the specific implementation steps and results are as follows:

[0062] Clean the surface of the silicon wafer with a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 15%) to remove the dirt on the silicon wafer surface. Process temperature: 55°C - 70°C, process time: 2 min - 5 min;

[0063] Use water washing to remove the residual chemicals and dirt on the surface. Cleaning time: 2 min - 3 min;

[0064] Use a mixed solution of potassium hydroxide (1% - 10%) and additive (0.5% - 5%) to polish the surface of the silicon wafer to form an alkaline polishing tower base morphology and remove the cutting damage. Process temperature: 60°C - 85°C, process time (3 min - 5 min);

[0065] Use water washing to remove the residual chemicals and dirt on the surface. Cleaning time: 2 min - 3 min;

[0066] Clean the surface of the silicon wafer with a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 20%) to remove the additive residue. Process temperature: 55°C - 70°C, process time: 2 min - 5 min;

[0067] Use water washing to remove the residual chemicals and dirt on the surface. Cleaning time: 2 min - 3 min;

[0068] Use a mixed solution of hydrofluoric acid (0.1% - 2%), hydrochloric acid (0.1% - 2%) and O3 (10 ppm - 50 ppm) to clean the surface of the silicon wafer. At the same time, the weak etching system of O3 and HF lubricates the surface of the silicon wafer and reduces the burr defects on the silicon wafer surface, (which is more beneficial to the passivation of the silicon wafer surface). Process temperature: 15°C - 25°C, process time: 2 min - 3 min;

[0069] Use water washing to remove the residual chemicals and dirt on the surface. Cleaning time: 2 min - 3 min;

[0070] Clean the surface of the silicon wafer with a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%). Process temperature: room temperature, process time: 3 min - 5 min;

[0071] Use water washing to remove the residual chemicals and dirt on the surface. Cleaning time: 2 min - 3 min;

[0072] Use slow lifting to remove the dirt on the surface of the silicon wafer and dehydrate the silicon wafer. Cleaning time: 0.5 min - 1 min, cleaning temperature: 20°C - 70°C;

[0073] Place the silicon wafer in a drying tank and blow it with high temperature. Dry the surface of the silicon wafer. Blowing gas: nitrogen or compressed air, temperature: 80°C - 100°C, drying time: 5 min - 15 min;

[0074] Weight reduction of silicon wafer: 0.3g - 0.6g; (taking 182.2-sized silicon wafer as an example)

[0075] Surface reflectivity: 35% - 45%;

[0076] Tower base size: 5um - 15um.

[0077] Step S2, sequentially prepare a tunneling oxide layer 4, an intrinsic amorphous silicon layer 51, a carbon-doped amorphous silicon layer 52, and a boron-doped amorphous silicon layer 53 on the backlight surface 3 of the N-type silicon substrate 1 to obtain the structure as shown in Figure 3 shown, and the specific process is as shown in Figure 4 shown;

[0078] In this step, the tunneling oxide layer can be prepared by tube-type LP, PE, ALD, plate-type PE, PVD, ALD, or wet oxygen in a tank;

[0079] Intrinsic amorphous silicon can be prepared by plate-type PVD, PE, tube-type LP, or PE;

[0080] Doped amorphous silicon (buffer layer) can be prepared by plate-type PVD, PE, or tube-type PE;

[0081] Boron-doped amorphous silicon can be prepared by plate-type PVD, PE, tube-type LP, or PE;

[0082] The present invention preferably uses plate-type PECVD to prepare the tunneling oxide layer, plate-type PVD to prepare the intrinsic amorphous silicon, plate-type PVD to prepare the doped amorphous silicon layer (buffer layer), and plate-type PVD to prepare the boron-doped amorphous silicon. Plate-type PVD has the characteristics of single-sided deposition without overplating, fast deposition rate, easy in-situ doping, and easy crystallization. At the same time, plate-type equipment has the advantage of integrating different types of film layers for coating, reducing equipment investment and the frequency of breaking the vacuum for coating the battery;

[0083] The doped amorphous silicon layer (buffer layer) can be one or a combination of C, O, and N doping;

[0084] The present invention preferably uses CH4 as the doping gas for the doped amorphous silicon layer (buffer layer), and the doping element is C. CH4 has the characteristics of low cost, and at the same time, the silicon carbide film layer can effectively slow down the boron atom propulsion speed;

[0085] The present invention uses plate-type PECVD to prepare the tunneling oxide layer, which can be prepared by using O2, O3, N2O, or a combination of SiH4 and one or more of the above gases. The present invention preferably uses O2 with low cost and high safety for preparation;

[0086] The boron doping source in this step can be borane, boron chloride, boron fluoride, trimethyl boron, boron-doped target, etc.;

[0087] The present invention preferably uses borane as the doping gas. Borane has the characteristics of high doping efficiency, easy decomposition, etc., and has a high matching degree with PVD coating;

[0088] The specific implementation steps and results are as follows:

[0089] The back surface of the silicon wafer after double-sided alkaline polishing is oxidized by a flat PECVD method to prepare a tunneling oxide layer. A layer of intrinsic amorphous silicon, a layer of carbon-doped amorphous silicon, and a layer of boron-doped amorphous silicon are deposited on the oxidized silicon wafer by a flat PVD method.

[0090] The silicon wafer after double-sided alkaline polishing is placed on a perforated carrier plate. The carrier plate is transferred to the loading chamber 1, and the chamber is evacuated. The carrier plate is transferred to the PECVD1 reaction chamber 1. The O2 is ionized to plasma by the PECVD method, and the tunneling silicon oxide is prepared by oxidizing the surface of the silicon wafer from bottom to top through the perforated carrier plate. The carrier plate is transferred to the transition chamber, and the chamber is evacuated. The carrier plate is transferred to the buffer chamber and then to the PVD1 reaction chamber 2. By the PVD method, the intrinsic amorphous silicon is deposited from bottom to top through the perforated carrier plate. Then it is transferred to the PVD2 reaction chamber 3. By the PVD method, the carbon-doped amorphous silicon (buffer layer) is deposited from bottom to top through the perforated carrier plate. Then it is transferred to the PVD3 reaction chamber 4. By the PVD method, the boron-doped amorphous silicon is deposited from bottom to top through the perforated carrier plate. Then it is transferred to the buffer chamber, and the carrier plate is transferred to the cooling chamber and then to the unloading chamber 1. The unloading chamber is backfilled with nitrogen to the atmospheric state, and the carrier plate is transferred out of the chamber to collect the silicon wafer, completing the film preparation;

[0091] PECVD1 reaction chamber 1: When oxidizing to prepare the tunneling oxide layer by the PECVD method, oxygen is used as the process gas. The process pressure is 5 Pa - 20 Pa, the process temperature is 150 °C - 350 °C, the power is 50 W - 500 W, and the process belt speed is 10 cm / min - 500 cm / min;

[0092] PVD1 reaction chamber 2: When preparing the intrinsic amorphous silicon by the PVD method, a silicon target is used as the silicon source, and argon is used as the working gas. The process pressure is 0.1 Pa - 1 Pa, the process temperature is 200 °C - 500 °C, the power is 10 kW - 40 kW, and the process belt speed is 10 cm / min - 500 cm / min;

[0093] PVD2 reaction chamber 3: When preparing the carbon-doped amorphous silicon by the PVD method, a silicon target is used as the silicon source, and argon is used as the working gas, and CH4 is used as the doping gas. The process pressure is 0.1 Pa - 1 Pa, the process temperature is 200 °C - 500 °C, the power is 1 kW - 40 kW, the process belt speed is 10 cm / min - 500 cm / min, and the CH4 flow rate is 5 sccm - 50 sccm;

[0094] PVD3 Reaction Chamber 4: When preparing boron-doped amorphous silicon by PVD method, a silicon target is used as the silicon source, argon is used as the working gas, and B2H6 is used as the doping gas. Process pressure: 0.1 Pa - 1 Pa, process temperature: 200 °C - 500 °C, power: 10 kW - 40 KW, process belt speed: 10 cm / min - 500 cm / min, B2H6 flow rate: 5 sccm - 100 sccm;

[0095] Tunneling oxide thickness: 0.5 nm - 3 nm, which can be freely adjusted by power, belt speed, flow rate, and temperature to meet the process requirements;

[0096] Intrinsic amorphous silicon thickness: 10 nm - 300 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements;

[0097] Carbon-doped amorphous silicon layer (buffer layer) thickness: 1 nm - 20 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements;

[0098] Carbon doping concentration of carbon-doped amorphous silicon layer (buffer layer): 1×10 19 cm -3 ~1×10 21 cm -3 , which can be freely adjusted by the CH4 flow rate;

[0099] Boron-doped amorphous silicon layer thickness: 10 nm - 200 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements;

[0100] Boron doping concentration of boron-doped amorphous silicon layer: 1×10 19 cm -3 ~1×10 21 cm -3、 , which can be freely adjusted by the B2H6 flow rate;

[0101] Thickness ratio of intrinsic amorphous silicon / carbon-doped amorphous silicon / boron-doped amorphous silicon: (100:1:20) - (100:2:100);

[0102] Ratio of the number of targets in PVD1 Reaction Chamber 2 / PVD2 Reaction Chamber 3 / PVD3 Reaction Chamber 4: (1:1:1) - (3:1:1);

[0103] Power ratio of PVD1 Reaction Chamber 2 / PVD2 Reaction Chamber 3 / PVD3 Reaction Chamber 4: (100:1:20) - (100:2:100).

[0104] Step S3, high-temperature oxidation annealing obtains a back junction structure with a P+ inner diffusion layer 61, a tunneling oxide layer 4, and a boron-doped polysilicon layer 5 on the backlight side, obtaining the structure as Figure 5 shown;

[0105] Specifically, high-temperature oxidation annealing is used to crystallize the backside intrinsic amorphous silicon, carbon-doped amorphous silicon, and boron-doped amorphous silicon into polycrystalline silicon. Meanwhile, the boron atoms in the boron-doped amorphous silicon are activated to form boron-doped polycrystalline silicon. The boron atoms first advance to the silicon carbide polycrystalline silicon layer (the buffer layer slows down the boron advancement speed), then to the intrinsic polycrystalline silicon layer (slowing down the boron advancement speed), and finally to the tunneling oxide layer and enter the silicon substrate, forming tunneling pinholes, resulting in P+ inward diffusion and preparing a PN junction.

[0106] Specifically, the boron-doped amorphous silicon layer serves as a boron source. Under the action of high-temperature annealing, all the amorphous layers on the backside are crystallized into boron-doped polycrystalline silicon, showing a trend of gradient doping. The surface metal contact area has highly doped boron polycrystalline silicon, and the bottom passivation area has low-doped boron-doped polycrystalline silicon.

[0107] The specific implementation steps and results are as follows:

[0108] The silicon wafer with the backside coated is inserted into a quartz carrier and transferred to a high-temperature annealing furnace tube. After opening the furnace door - loading the boat - evacuating - heating up - maintaining a constant temperature - leak detection - low-temperature crystallization - heating up - maintaining a constant temperature - oxidation - cooling down - breaking the vacuum - unloading the boat, the oxidation annealing is completed.

[0109] Among them, the temperature of the low-temperature crystallization step is 400°C - 600°C. The purpose is to first crystallize the amorphous silicon into dense polycrystalline silicon, improve the blocking effect, and reduce the boron advancement speed.

[0110] Among them, during the heating-up step after leak detection, gradient heating is adopted to reduce the annealing process effect differences caused by the initial temperature differences at the furnace mouth - furnace middle - furnace tail due to opening the furnace door. The specific heating method is as follows: 800°C - 820°C - 840°C - 860°C - 880°C - 900°C - 920°C - 950°C replaces the traditional 800°C - 840°C - 880°C - 950°C; different oxidation annealing temperatures are used in different temperature zones to avoid the annealing process effect differences at different positions caused by the rapid cooling at the furnace mouth and furnace tail due to the water cooling of the furnace tube and the slow heating at the furnace mouth and fast heating at the furnace tail due to opening the furnace door. The specific temperature setting method is as follows: furnace mouth - furnace middle - furnace tail: 960°C - 950°C - 955°C replaces the traditional furnace mouth - furnace middle - furnace tail: 950°C - 950°C - 950°C.

[0111] Low-temperature crystallization time: 4 min - 20 min;

[0112] Oxidation annealing time: 30 min to 120 min;

[0113] Oxidation annealing temperature: 880°C - 1050°C;

[0114] Oxidation annealing pressure: 600 mBar - 900 mBar;

[0115] Effective doping concentration of boron-doped polysilicon surface layer: 1×10 19 cm -3 ~1×10 21 cm -3 ; It can be freely adjusted by the flow rate of borane, process pressure, process time, annealing temperature, and annealing time to meet the process requirements;

[0116] Boron diffusion depth: 30nm - 120nm;

[0117] Annealed silicon oxide thickness: 50nm - 100nm, which can be freely adjusted by the oxygen flow rate, annealing time, and annealing temperature to meet the process requirements.

[0118] Step S4, texture the light-receiving surface 2 of the N-type silicon substrate to obtain the structure as shown in Figure 6 shown, and the specific process is as shown in Figure 7 shown;

[0119] In this step, wet cleaning is used to prepare a pyramid morphology on the front side;

[0120] The specific steps are as follows:

[0121] Use a hydrofluoric acid (1% - 10%) solution for single-sided chain pickling to remove the annealed silicon oxide on the front side of the silicon wafer. Process temperature: room temperature, process time: 3min - 5min;

[0122] Use water washing to remove the residual chemicals and dirt on the surface. Cleaning time: 2min - 3min;

[0123] Place the silicon wafer on the drying trough for transmission, and blow it with high temperature to dry the surface of the silicon wafer. Blowing gas: nitrogen or compressed air, temperature: 80°C - 100°C, drying time: 2min - 3min;

[0124] Use a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 15%) to clean the surface of the silicon wafer to remove the dirt on the surface. Process temperature: 55°C - 70°C, process time: 1min - 3min;

[0125] Use water washing to remove the residual chemicals and dirt on the surface. Cleaning time: 2min - 3min;

[0126] Use a mixed solution of potassium hydroxide (1% - 10%) and texturing additive (0.5% - 5%) to form a pyramid texture on the front side of the silicon wafer. Process temperature: 70°C - 85°C, process time (3min - 5min);

[0127] Use water washing to remove the residual chemicals and dirt on the surface. Cleaning time: 2min - 3min;

[0128] Clean the surface of the silicon wafer with a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 20%) to remove the residual additives. Process temperature: 55°C - 70°C, process time: 1 min - 3 min;

[0129] Use water washing to remove the residual medicine and dirt on the surface. Cleaning time: 2 min - 3 min;

[0130] Clean the surface of the silicon wafer with a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%). Process temperature: room temperature, process time: 3 min - 5 min;

[0131] Use water washing to remove the residual medicine and dirt on the surface. Cleaning time: 2 min - 3 min;

[0132] Use slow lifting to remove the dirt on the surface of the silicon wafer and dehydrate the silicon wafer. Cleaning time: 0.5 min - 1 min, cleaning temperature: 20°C - 70°C;

[0133] Place the silicon wafer in a drying tank and perform high-temperature purging to dry the surface of the silicon wafer. Purging gas: nitrogen or compressed air, temperature: 80°C - 100°C, drying time: 5 min - 15 min;

[0134] Weight loss of the silicon wafer: 0.1 g - 0.2 g; (taking the 182.2-sized silicon wafer as an example)

[0135] Luminescence surface reflectivity: 9% - 12%;

[0136] Pyramid height: 0.8 μm - 5 μm;

[0137] Pyramid width: 1 μm - 5 μm.

[0138] In step S5, sequentially deposit a tunneling oxide layer 4 and a phosphorus-doped amorphous silicon layer on the light-receiving surface 2 of the N-type silicon substrate 1, and perform high-temperature oxidation annealing to obtain a poly passivation contact structure with an N+ inner diffusion layer 62, a tunneling oxide layer 4, and a phosphorus-doped polycrystalline silicon layer 8, obtaining the structure as shown in Figure 8 shown, and the specific process is as shown in Figure 9 shown;

[0139] In this step, first deposit a tunneling oxide layer and phosphorus-doped amorphous silicon on the front side of the silicon wafer, and then through high-temperature annealing, crystallize the phosphorus-doped amorphous silicon into phosphorus-doped polycrystalline silicon. At the same time, phosphorus atoms are pushed into the tunneling oxide layer and enter the silicon substrate to form tunneling pinholes and form N+ inner diffusion;

[0140] In this step, the tunneling oxide layer can be prepared by tube LP, PE, ALD, plate PE, PVD, ALD, and tank wet oxygen;

[0141] Phosphorus-doped amorphous silicon can be prepared by plate PVD, PE, tube LP, and PE;

[0142] The present invention preferably uses plate-type PECVD to prepare the tunneling oxide layer, and plate-type PVD to prepare phosphorus-doped amorphous silicon. The plate-type PVD has the characteristics of single-sided deposition without edge plating, fast deposition rate, easy in-situ doping, and easy crystallization. At the same time, the plate-type equipment has the advantage of integrating different types of film layers for coating, reducing equipment investment and the frequency of breaking the vacuum for battery coating;

[0143] The present invention uses plate-type PECVD to prepare the tunneling oxide layer, which can be prepared using O2, O3, N2O, or a combination of one or more of the above gases with SiH4. The present invention preferably uses O2 with low cost and high safety for preparation;

[0144] In this step, the phosphorus doping source can be phosphine, phosphorus, phosphorus-doped target, etc.;

[0145] The present invention preferably uses phosphine as the doping gas. Phosphine has the characteristics of high doping efficiency, easy decomposition, etc., and has a high matching degree with PVD coating;

[0146] The specific implementation steps and results are as follows:

[0147] Adopt the plate-type PECVD method to oxidize the front side of the textured silicon wafer to prepare the tunneling oxide layer, and use the plate-type PVD method to deposit an intrinsic amorphous silicon layer and a phosphorus-doped amorphous silicon layer on the front side of the oxidized silicon wafer. Adopt the high-temperature oxidation annealing method to prepare phosphorus-doped polysilicon and N+ internal diffusion;

[0148] The textured silicon wafer is placed on the hollow carrier plate, and the carrier plate is transferred to the loading chamber 2. The chamber is evacuated, and the carrier plate is transferred to the PECVD2 reaction chamber 5. The PECVD method is used to ionize O2 into plasma, and the tunneling silicon oxide is prepared by oxidizing the surface of the silicon wafer from bottom to top through the hollow carrier plate. The carrier plate is transferred to the transition chamber, the chamber is evacuated, the carrier plate is transferred to the buffer chamber, and then transferred to the PVD4 reaction chamber 6. The PVD method is used to deposit phosphorus-doped amorphous silicon from bottom to top through the hollow carrier plate, and then transferred to the buffer chamber. The carrier plate is transferred to the cooling chamber, and the carrier plate is transferred to the unloading chamber 2. The unloading chamber is backfilled with nitrogen to the atmospheric state, the carrier plate is transferred out of the chamber, and the silicon wafer is collected to complete the film layer preparation;

[0149] The silicon wafer with the front side coated is inserted into the quartz carrier and transferred to the high-temperature annealing furnace tube. After opening the furnace door - loading the boat - evacuating - heating - constant temperature - leak detection - heating - constant temperature - oxidation - cooling - breaking the vacuum - unloading the boat, the oxidation annealing is carried out to complete the preparation of phosphorus-doped polysilicon, the tunneling oxide layer, and N+ internal diffusion;

[0150] Among them, during the post-leak detection heating step, gradient heating is adopted to reduce the annealing process effect differences caused by the initial temperature differences at the furnace mouth - furnace middle - furnace tail due to opening the furnace door. The specific heating method is as follows: 800°C - 820°C - 840°C - 860°C - 880°C replaces the traditional 800°C - 840°C - 880°C; different oxidation annealing temperatures are used in different temperature zones to avoid the annealing process effect differences at different positions caused by the rapid cooling at the furnace mouth and furnace tail due to the water cooling of the furnace tube and the slow heating at the furnace mouth and fast heating at the furnace tail caused by opening the furnace door. The specific temperature setting method is as follows: furnace mouth - furnace middle - furnace tail: 890°C - 880°C - 885°C replaces the traditional furnace mouth - furnace middle - furnace tail: 880°C - 880°C - 880°C;

[0151] Oxidation annealing time: 30 min to 120 min;

[0152] Oxidation annealing temperature: 840°C - 950°C;

[0153] Oxidation annealing pressure: 600 mBar - 900 mBar;

[0154] Tunneling oxide layer thickness: 0.5 nm - 3 nm, which can be freely adjusted by power, belt speed, flow rate, and temperature to meet the process requirements;

[0155] Effective doping concentration of phosphorus-doped polysilicon doping: 5×10 19 cm -3 ~1×10 22 cm -3 , which can be freely adjusted by phosphine flow rate, process pressure, and process time to meet the process requirements;

[0156] Thickness of phosphorus-doped polysilicon: 30 nm - 200 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements;

[0157] Thickness of annealed silicon oxide: 20 nm - 50 nm, which can be freely adjusted by oxygen flow rate, annealing time, and annealing temperature to meet the process requirements;

[0158] Phosphorus inward diffusion depth: 20 nm - 100 nm.

[0159] Step S6, locally open the film on the light-receiving surface 2 of the N-type silicon substrate 1 to prepare a patterned interdigital structure, and obtain the structure as Figure 10 shown;

[0160] In this step, patterning can be prepared by laser film opening method or pattern mask etching method;

[0161] The present invention preferably uses the laser film opening method for preparation. The laser film opening method has the advantages of high speed and low cost;

[0162] Further lasers can use nanosecond lasers, picosecond lasers, and femtosecond lasers. The present invention preferably uses picosecond lasers with low cost, low loss, and high film opening rate. Combining with subsequent wet etching to remove damage, non-destructive patterning preparation can be achieved. The specific implementation steps and results are as follows:

[0163] Place the battery on a horizontal tabletop. Use a pulsed ultraviolet picosecond laser to etch the front annealing oxide layer to the phosphorus-doped polysilicon layer, and retain part of the phosphorus-doped polysilicon layer and the tunneling oxide layer;

[0164] Laser power: 50W - 500W;

[0165] Film opening width: 50um - 500um;

[0166] Width of the retained annealing oxide layer: 50um - 300um.

[0167] Step S7, perform secondary texturing on the film opening area of the light-receiving surface 2, and clean the light-receiving surface 2 and the backlight surface 3 to obtain the structure as shown in Figure 11 shown, and the specific process is as shown in Figure 12 shown;

[0168] Use a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 15%) to clean the surface of the silicon wafer, remove the dirt and laser dust on the surface of the silicon wafer, process temperature: 55°C - 70°C, process time: 0.5min - 1min;

[0169] Use water washing to remove the residual chemicals and dirt on the surface, cleaning time: 2min - 3min;

[0170] Use a mixed solution of potassium hydroxide (1% - 10%) and additive (0.5% - 5%) to remove the polysilicon and tunneling oxide layer in the front film opening area while texturing, process temperature: 60°C - 85°C, process time: 0.5min - 1min;

[0171] Use water washing to remove the residual chemicals and dirt on the surface, cleaning time: 2min - 3min;

[0172] Use a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 20%) to clean the surface of the silicon wafer, remove the residual additives, process temperature: 55°C - 70°C, process time: 0.5min - 1min;

[0173] Use water washing to remove the residual chemicals and dirt on the surface, cleaning time: 2min - 3min;

[0174] Use a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%) to clean the surface of the silicon wafer, process temperature: room temperature, process time: 3min - 5min;

[0175] Use water washing to remove surface drug residues and dirt, washing time: 2 min to 3 min;

[0176] Use slow lifting to remove dirt on the surface of the silicon wafer, dehydrate the silicon wafer, washing time 0.5 min to 1 min, washing temperature: 20°C - 70°C;

[0177] Place the silicon wafer in a drying tank, blow with high temperature, dry the surface of the silicon wafer, blowing gas: nitrogen or compressed air, temperature: 80°C - 100°C, drying time: 5 min to 15 min;

[0178] Washing method: The silicon wafer enters the solution vertically, the laser line direction of the silicon wafer is perpendicular to the solution surface, and the detachment of surface drug residues on the silicon wafer is not affected by the front groove morphology;

[0179] Weight loss of the silicon wafer: 0.1 g - 0.2 g; (taking the 182.2 - sized silicon wafer as an example)

[0180] Surface reflectivity of the velvet surface: 9% - 12%.

[0181] Step S8, deposit a passivation and antireflection film on the light - receiving surface 2 and the backlight surface 3 respectively to obtain the structure as Figure 13 shown;

[0182] The passivation and antireflection layer includes one or more combinations of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, amorphous silicon. The present invention preferably uses an aluminum oxide layer 91 and a silicon nitride layer 92 as the passivation and antireflection film;

[0183] Aluminum oxide can be prepared by plate - type PECVD, plate - type ALD, plate - type PVD, tube - type PECVD, tube - type ALD; Silicon nitride can be prepared by plate - type PECVD, plate - type PVD, tube - type PECVD;

[0184] The present invention preferably uses tube - type ALD to prepare aluminum oxide on the front and back. Tube - type ALD can deposit aluminum oxide on the front and back simultaneously. Use tube - type PECVD to prepare silicon nitride on the back and plate - type PECVD to prepare silicon nitride on the front. The plate - type coating equipment has no stuck - point marks like tube - type equipment, and the front of the battery is beautiful;

[0185] Use tube - type ALD to prepare double - sided aluminum oxide. Place the silicon wafer on a metal carrier and transfer it to the process tube. Use trimethylaluminum and water as process gases, process temperature: 200°C - 400°C, process time: 3 min to 30 min, trimethylaluminum / water flow ratio: 1:2 - 2:1;

[0186] Use tube - type PECVD to prepare silicon nitride on the back. Place the silicon wafer on a graphite boat and transfer it to the process tube. Use silane and ammonia as process gases, process temperature: 400°C - 600°C, process time: 20 min to 60 min, silane / ammonia flow ratio: 1:3 - 3:1;

[0187] The front-side silicon nitride is prepared by plate-type PECVD. The silicon wafer is placed on a carbon fiber carrier plate and transferred to the process chamber. Silane and ammonia are used as process gases. Process temperature: 350°C - 550°C, process time: 2 min - 10 min, silane / ammonia flow ratio: 1:3 - 3:1; (There is no sticking mark in the front-side deposition by plate-type PECVD, and the battery is beautiful)

[0188] Aluminum oxide thickness: 2 nm - 40 nm;

[0189] Front-side silicon nitride thickness: 70 nm - 150 nm, refractive index: 1.8 - 2.2;

[0190] Back-side silicon nitride thickness: 70 nm - 150 nm, refractive index: 1.8 - 2.2.

[0191] Step S9, screen printing and sintering to obtain the metal electrode 10, obtaining the structure as Figure 14 shown.

[0192] Print the metal paste at the positions of the front and back polysilicon film layers;

[0193] After printing the silicon wafer, transfer it to a sintering furnace for high-temperature sintering. The metal forms an ohmic contact with the silicon wafer to fabricate a cell;

[0194] Width of the metal electrode: 10 μm - 50 μm;

[0195] Height of the metal electrode: 5 μm - 20 μm.

[0196] Specifically, the above process can complete the high-passivation and low-contact-resistance boron-doped polysilicon passivated contact structure through a single coating equipment.

[0197] In summary, in the full-passivated contact TOPCon cell structure and its preparation method of the present invention, by setting the boron-doped polysilicon as a phosphorus-doped patterned interdigitated poly passivated contact structure on the light-receiving surface, the passivation parasitic absorption problem of setting polysilicon on the front side is effectively solved. At the same time, the boron-doped amorphous silicon on the backlight side adopts a stacked film and annealing design, solving the defect that boron-doped polysilicon cannot balance contact and passivation, and realizing further improvement of the cell efficiency of the double-sided full-passivated contact cell.

[0198] Based on the above ideal embodiments of the present invention as inspiration, through the above description, relevant workers can completely make various changes and modifications without departing from the technical idea of this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A fully passivated contact TOPCon battery structure, characterized in that: include: An N-type silicon substrate (1) comprising a light-receiving surface (2) and a backlight surface (3); The light receiving surface (2) is provided with a passivation contact area (21) and a light receiving area (22) arranged in an interdigitated structure; An N+ inner expansion layer (62), a tunneling oxide layer (4), and a phosphorus-doped polysilicon layer (8) are sequentially stacked on the passivation contact region (21) to form a poly passivation contact structure; A P+ inner expansion layer (61), a tunneling oxide layer (4) and a boron-doped polysilicon layer (5) are sequentially stacked on the backlight surface (3) to form a back junction structure.

2. The fully passivated contact TOPCon battery structure according to claim 1, characterized in that: The back junction structure of the backlight surface (3) is obtained by high-temperature oxidation annealing of a tunneling oxide layer (4), an intrinsic amorphous silicon layer (51), a carbon-doped amorphous silicon layer (52) and a boron-doped amorphous silicon layer (53) which are sequentially stacked on the backlight surface; The intrinsic amorphous silicon layer (51), the carbon-doped amorphous silicon layer (52) and the boron-doped amorphous silicon layer (53) form a boron-doped polysilicon layer (5); The P+ inner expansion layer (61) is formed by pushing boron atoms in the boron-doped amorphous silicon layer (53) into the N-type silicon base (1) to form tunnel pinholes.

3. The fully passivated contact TOPCon battery structure according to claim 1, characterized in that: On the passivation contact area, the doping thickness of the phosphorus-doped polysilicon layer is 30nm to 200nm, and the effective doping concentration is 5×10 19 cm -3 ~1×10 22 cm -3 ; The thickness of the tunnel oxide layer is 0.5 nm to 3 nm, and the ratio of the thickness of the tunnel oxide layer to the thickness of the phosphorus-doped polysilicon layer is 1:60 to 1:200; The diffusion depth of the N+ inner expansion layer is 20nm to 100nm; The pattern width of the poly passivation contact structure in the passivation contact area is 50um to 300um.

4. The fully passivated contact TOPCon battery structure according to claim 1, characterized in that: On the backlight surface, the thickness of the tunnel oxide layer is 0.5 nm to 3 nm; The thickness of the boron-doped polysilicon layer is 30 nm to 500 nm, and the ratio of the thickness of the tunneling oxide layer to the boron-doped polysilicon layer is 1:50 to 1:500, and the effective doping concentration is 5×10 19 cm -3 ~1×10 21 cm -3 ; The diffusion depth of the P+ inner diffusion layer is 30nm to 120nm.

5. The fully passivated contact TOPCon battery structure according to claim 1, characterized in that: The light-receiving surface of the N-type silicon substrate has a pyramid velvet morphology with a reflectivity of 9% to 12%; The pyramid has a height of 0.8um to 5um and a width of 1um to 5um.

6. The fully passivated contact TOPCon battery structure according to claim 1, characterized in that: The backlight surface of the N-type silicon substrate has an alkali-polished tower-based morphology, and a reflectivity of 35% to 45%; The size of the alkali polishing tower base is 5um to 15um.

7. The fully passivated contact TOPCon battery structure according to claim 1, characterized in that: The outermost sides of the light-receiving surface and the backlight surface are both provided with a passivation anti-reflection layer; The passivation anti-reflection layer comprises any one or more combinations of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon and amorphous silicon; The passivation anti-reflection layer has a thickness of 50 nm to 200 nm and a refractive index of 1.8 to 2.

2.

8. The fully passivated contact TOPCon battery structure according to claim 1, characterized in that: The N-type silicon substrate includes any one of a Czochralski single crystal and a cast single crystal.

9. The fully passivated contact TOPCon battery structure according to claim 1, characterized in that: The passivation contact area and the passivation anti-reflection layer of the backlight surface area are provided with corresponding metal electrodes; The metal electrode includes any one or more combinations of silver, copper, aluminum, and tin; The metal electrode has a width of 10um to 50um and a height of 5um to 20um.

10. A method for preparing a fully passivated contact TOPCon battery structure as claimed in any one of claims 1 to 9, characterized in that: The steps include: Providing a clean double-sided polished silicon wafer to obtain an N-type silicon substrate (1); A tunneling oxide layer (4), an intrinsic amorphous silicon layer (51), a carbon-doped amorphous silicon layer (52) and a boron-doped amorphous silicon layer (53) are sequentially prepared on the backlight surface (3) of the N-type silicon substrate (1); High temperature oxidation annealing is performed to obtain a back junction structure having a P+ inner diffusion layer (61), a tunneling oxide layer (4) and a boron-doped polysilicon layer (5) on the back-light surface (3); Texturing the light-receiving surface (2) of the N-type silicon substrate (1); A tunneling oxide layer (4) and a phosphorus-doped amorphous silicon layer are sequentially deposited on the light-receiving surface (2) of the N-type silicon substrate (1), and high-temperature oxidation annealing is performed to obtain a poly passivation contact structure having an N+ inner expansion layer (62), a tunneling oxide layer (4) and a phosphorus-doped polycrystalline silicon layer (8); Partially opening a film on a light-receiving surface (2) of an N-type silicon substrate (1) to prepare a patterned interdigitated structure; Secondary texturing is performed on the film opening area of ​​the light-receiving surface (2), and the light-receiving surface (2) and the backlight surface (3) are cleaned; Depositing passivation anti-reflection films on the light-receiving surface (2) and the backlight surface (3) respectively; Screen printing and sintering are performed to obtain a metal electrode (10).

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