High-efficiency combined passivation battery structure and preparation method thereof

Abstract

The invention belongs to the technical field of crystalline silicon solar cells, and particularly relates to an efficient combined passivation cell structure and a preparation method thereof.The efficient combined passivation cell structure comprises an N-type silicon substrate which is provided with a light receiving face with pyramid suede morphology, and the light receiving face is provided with passivation contact areas and light receiving areas which are arranged in an interdigital structure; an N + internal expansion layer, a tunneling oxide layer, a phosphorus-doped polycrystalline silicon layer, a front conductive film layer and a silicon nitride layer are sequentially stacked on the passivation contact region; passivation antireflection layers are arranged on the light receiving area and the outer side of the silicon nitride layer of the passivation contact area in a stacked mode. The passivation contact area is also provided with a local windowing and is provided with a metal electrode which is contacted with the front conductive film layer. And the pyramid suede morphology is in a micron scale in a light receiving area and is in a nano scale in a passivation contact area.

Description

Technical Field

[0001] The present invention belongs to the technical field of crystalline silicon solar cells, and particularly relates to a high-efficiency combined passivation cell structure and a preparation method thereof. Background Art

[0002] The existing HJT cell structure is arranged from top to bottom including: metal electrode, transparent conductive film ITO, phosphorus-doped hydrogenated amorphous silicon, intrinsic hydrogenated amorphous silicon, front pyramid texture, silicon substrate, back alkali-etched tower texture, intrinsic hydrogenated amorphous silicon, boron-doped hydrogenated amorphous silicon, transparent conductive film ITO, metal electrode.

[0003] Currently, one improvement direction for HJT cells is to use a doped polysilicon and tunneling oxide layer passivation contact structure (TOPCon technology) on the front to replace the traditional HJT structure. However, compared with the polished surface, after introducing the TOPCon passivation contact structure on the textured surface, the tips, edges, and bottoms of the pyramids cannot obtain uniform high-quality tunneling oxide layer chemical passivation and N+ internal diffusion field passivation, resulting in a decrease in cell efficiency.

[0004] Therefore, how to overcome the defect of the decrease in cell efficiency after the combination of the TOPCon passivation contact structure and the HJT cell is a technical problem that urgently needs to be solved in this field.

[0005] It should be noted that the above information disclosed in this background art part is only used to understand the background art of the concept of this application. Therefore, it is not considered that the above description constitutes the information of the prior art. Summary of the Invention

[0006] The embodiments of the present disclosure at least provide a high-efficiency combined passivation cell structure and a preparation method thereof.

[0007] In a first aspect, the embodiments of the present disclosure provide a high-efficiency combined passivation cell structure, including: an N-type silicon substrate having a light-receiving surface with a pyramid texture, on which a passivation contact area and a light-receiving area arranged in an interdigitated structure are provided; an N+ internal diffusion layer, a tunneling oxide layer, a phosphorus-doped polysilicon layer, a front conductive film layer, and a silicon nitride layer are sequentially stacked on the passivation contact area; a passivation and antireflection layer is stacked on both the light-receiving area and the outside of the silicon nitride layer of the passivation contact area; a metal electrode touching the front conductive film layer is locally opened on the passivation contact area; and, the pyramid texture is micron-sized in the light-receiving area and nanometer-sized in the passivation contact area.

[0008] In an optional embodiment, the width of the passivation contact area is 30 - 200 μm; the width of the light-receiving area is 100 - 600 μm; and the area ratio of the passivation contact area to the light-receiving area is 1:1 - 1:6.

[0009] In an alternative embodiment, the front conductive film layer comprises any one or a combination of more than one of a metal, a metal compound, and a carbon-based compound; the thickness of the front conductive film layer is 5 nm to 100 nm, and the sheet resistance does not exceed 120.

[0010] In an alternative embodiment, the passivation and antireflection layer comprises any one or a combination of more than one of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, and amorphous silicon; the thickness of the passivation and antireflection layer is 40 nm to 150 nm, and the refractive index is 1.8 to 2.2.

[0011] In an alternative embodiment, the depth of the N+ inner diffusion layer is 20 nm to 100 nm; the thickness of the tunneling oxide layer is 0.5 nm to 3 nm; the thickness of the phosphorus-doped polysilicon layer is 15 nm to 300 nm, and the effective doping concentration is 5E+19 cm -3 ~1E+22 cm -3 ; and the thickness ratio of the tunneling oxide layer to the phosphorus-doped polysilicon layer is 1:20 to 1:300.

[0012] In an alternative embodiment, the reflectivity of the pyramid texture on the light-receiving surface in the light-receiving area is 9% to 12%, the pyramid height is 1 μm to 5 μm, and the pyramid width is 1 μm to 5 μm; the reflectivity of the pyramid texture on the light-receiving surface in the passivation contact area is 9% to 12%, the pyramid height is 0.6 μm to 1.2 μm, and the pyramid width is 0.8 μm to 1.5 μm.

[0013] In an alternative embodiment, the backlight surface of the N-type silicon substrate has a micron-scale pyramid texture, and an intrinsic hydrogenated amorphous layer, a boron-doped hydrogenated amorphous layer, and a back conductive film layer are sequentially stacked on the micron-scale pyramid texture; wherein, a metal electrode is further provided on the back conductive film layer.

[0014] In an alternative embodiment, the back conductive film layer is a metal compound; the thickness of the back conductive film layer is 70 nm to 150 nm, and the sheet resistance is 50 to 120.

[0015] In an alternative embodiment, the thickness of the intrinsic hydrogenated amorphous layer is 3 nm to 10 nm; the thickness of the boron-doped hydrogenated amorphous layer is 3 nm to 10 nm, and the doping concentration is 1E+19 cm -3 ~5E+19 cm -3 ; the thickness of the back conductive film layer is 10 nm to 30 nm, and the doping concentration is 5E+19 cm -3 ~2E+20 cm -3 .

[0016] Second aspect, embodiments of the present disclosure further provide a method for preparing the high-efficiency combined passivation cell structure as described above, including the following steps: preparing a nanoscale small pyramid texture on the light-receiving surface and the backlight surface of the N-type silicon substrate; sequentially depositing and preparing a tunneling oxide layer and a phosphorus-doped polysilicon layer on the light-receiving surface to form a passivated contact structure, and performing high-temperature annealing to form an N+ inner diffusion layer in the contact area between the tunneling oxide layer and the N-type silicon substrate, and forming an annealing oxide layer on the outermost layers of the light-receiving surface and the backlight surface respectively; pickling to remove the annealing oxide layers on the light-receiving surface and the backlight surface; sequentially depositing a front conductive film layer and a silicon nitride layer outside the phosphorus-doped polysilicon layer on the light-receiving surface; setting a passivated contact area and a light-receiving area on the light-receiving surface, and opening a film in the light-receiving area to prepare a patterned interdigitated structure; etching the light-receiving area to expose the silicon substrate, and texturing to form a micron-scale pyramid texture on the light-receiving area; depositing a passivation and antireflection layer on the light-receiving surface; sequentially depositing and preparing an intrinsic hydrogenated amorphous layer and a boron-doped hydrogenated amorphous layer on the backlight surface; depositing a back conductive film layer on the boron-doped hydrogenated amorphous layer on the backlight surface; locally opening a film in the passivated contact area on the light-receiving surface to expose the front conductive film layer; and preparing metal electrodes on the front conductive film layer and the back conductive film layer respectively.

[0017] The beneficial effects of the present invention are that the high-efficiency combined passivation cell structure and its preparation method divide the passivated contact area and the light-receiving area on the light-receiving surface. By separately setting the passivated contact structure in the passivated contact area, the thickness of the crystalline silicon can be increased and the contact resistance can be reduced without causing optical loss. At the same time, depositing the TOPCon passivated contact structure on the nanoscale small pyramid texture to achieve passivated contact can effectively avoid the problem of low passivation on the texture, realizing the effective combination of the TOPCon passivation structure and the HJT cell.

[0018] Other features and advantages of the present invention will be described in the subsequent specification, and part of them will become obvious from the specification or be understood by implementing the present invention. The objectives and other advantages of the present invention are achieved and obtained by the structures specifically pointed out in the specification and the drawings.

[0019] To make the above objectives, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, provides detailed descriptions as follows. Description of the Drawings

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0021] Figure 1Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 2 Process flow chart for preparing a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 3 Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 4 Process flow chart for preparing a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 5 Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 6 Process flow chart for preparing a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 7 Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 8 Process flow chart for preparing a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 9 Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 10 Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 11 Process flow chart for preparing a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 12 Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 13 Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 14 Process flow chart for preparing a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 15 Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 16 Process flow chart for preparing a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 17 Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure; Figure 18 Schematic diagram of a high-efficiency combined passivation battery structure provided by an embodiment of the present disclosure.

[0022] In the figure: 1. N-type silicon substrate; 2. Light-receiving surface; 21. Passivated contact region; 22. Light-receiving region; 3. Backlight surface; 4. N+ inner diffusion layer; 5. Tunneling oxide layer; 6. Phosphorus-doped polysilicon layer; 7. Annealed oxide layer; 8. Front conductive film layer; 9. Silicon nitride layer; 10. Aluminum oxide layer; 11. Intrinsic hydrogenated amorphous layer; 12. Boron-doped hydrogenated amorphous layer; 13. Back conductive film layer; 14. Metal electrode. Detailed implementation manners

[0023] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0024] As used herein, phrases such as "in one embodiment", "according to one embodiment", "in some embodiments", etc. generally refer to the fact that the specific features, structures, or characteristics after such phrases can be included in at least one embodiment of the present disclosure. Therefore, a specific feature, structure, or characteristic can be included in more than one embodiment of the present disclosure, such that these phrases do not necessarily refer to the same embodiment. As used herein, terms such as "example", "exemplary", etc. are used "as an example, instance, or illustration. Any embodiment, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or superior to other embodiments, aspects, or designs. Instead, the use of terms such as "example", "exemplary", etc. is intended to present concepts in a specific manner.

[0025] In this document, example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as "at least one of..." modify the entire list of elements when following a list of elements, rather than modifying individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0026] The terms used in this document are only for describing specific exemplary configurations and are not intended to be restrictive. As used herein, the singular articles "a", "an", and "the" may also be intended to include the plural forms, unless clearly stated otherwise in this document. The terms "comprising", "including", and "having" are inclusive, thus specifying the presence of features, steps, operations, elements, and / or components, but not precluding the presence or addition of one or more other features, steps, operations, elements, components, and / or their combinations. The method steps, processes, and operations described herein should not be construed as necessarily requiring them to be performed in the specific order discussed or shown, unless specifically identified as the order of execution. Additional or alternative steps may be employed.

[0027] In the process of combining the TOPCon passivation structure with the HJT cell, the inventors found the following problems: 1. After introducing the TOPCon passivated contact structure on the textured surface, the tips, edges, and bottoms of the pyramids cannot obtain uniform high-quality tunneling oxide chemical passivation and N+ internal diffusion field passivation. This is because the tunneling oxide layers at the tips and bottoms are extremely prone to being damaged by phosphorus atoms during high-temperature annealing, resulting in low passivation.

[0028] 2. When the thickness of the polysilicon cell is below 50 nm, there is a problem of high contact resistance. However, although polysilicon with a thickness above 50 nm can reduce the contact resistance, it will bring serious parasitic absorption. For example, in patent number CN 220189670 U, the steps are as follows: S1. Double-sided texturing; S2. Depositing amorphous silicon + first doped amorphous silicon + transparent conductive film on the front side; S3. Depositing amorphous silicon + second doped amorphous silicon + transparent conductive film on the back side; S4. Metallization; The scheme concept is a traditional HJT cell with double-sided textured surface, double-sided amorphous silicon, double-sided differently doped amorphous silicon, and double-sided transparent conductive film structure, having the following disadvantages: 1. The front-side amorphous silicon has strong parasitic absorption, affecting the cell current density; 2. The front-side amorphous silicon passivation has ultraviolet attenuation.

[0029] 3. The existing doped polysilicon + tunneling oxide passivated contact structure is usually prepared by using tube LPCVD or tube PECVD combined with phosphorus diffusion or annealing. The tube deposition equipment has problems of over-deposition and over-diffusion, and additional processes are required to remove them, increasing the preparation process and limiting the cell yield. For example, in patent number CN 118016731 A; The scheme concept is to use the TOPCON structure to replace the amorphous silicon structure on the front side of the HJT cell to solve the problem of ultraviolet attenuation of the front-side amorphous silicon of the HJT cell; It has the following disadvantages: 1. It does not consider the over-deposition and over-diffusion processes in the preparation of the TOPCON structure by the LPPECVD method, and the preparation is cumbersome; 2. The cell front side is a textured surface, and directly introducing the TOPCON structure results in low passivation and low cell efficiency; 3. The front side is fully covered with polysilicon, with serious parasitic absorption and low cell efficiency.

[0030] The defects existing in the above solutions are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above problems and the solutions proposed by the present disclosure for the above problems below should be the contributions made by the inventor to the present disclosure during the disclosure process.

[0031] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0032] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0033] The disclosed embodiment provides a high-efficiency combined passivation cell structure, comprising: an N-type silicon base having a light-receiving surface with a pyramid velvet morphology, on which a passivation contact region and a light-receiving region arranged in an interdigitated structure are arranged; an N+ inner expansion layer, a tunneling oxide layer, a phosphorus-doped polysilicon layer, a front conductive film layer and a silicon nitride layer are sequentially stacked on the passivation contact region; a passivation anti-reflection layer is stacked on the light-receiving region and on the outside of the silicon nitride layer of the passivation contact region; a metal electrode touching the front conductive film layer is also partially opened on the passivation contact region; and the pyramid velvet morphology is at the micrometer level in the light-receiving region and at the nanometer level in the passivation contact region.

[0034] In some embodiments, specifically, the N-type silicon substrate includes any one of a Czochralski single crystal and a cast single crystal.

[0035] In some embodiments, specifically, the width of the passivation contact region is 30 to 200 μm; the width of the light receiving region is 100 to 600 μm; and the ratio of the area of ​​the passivation contact region to the area of ​​the light receiving region is 1:1 to 1:6.

[0036] In some embodiments, specifically, the front conductive film layer includes any one or more combinations of metals, metal compounds and carbon-based compounds, including any one or more combinations of Ti, Cu, Sn, Al, Ag, Au, W, TiW, V, ITO, IWO, TiO, TiN, AZO and carbon fiber; the thickness of the front conductive film layer is 5nm to 100nm, and the square resistance is 0 to 120.

[0037] Specifically, in addition to using metal compounds such as ITO, the front conductive film layer can also be replaced by low-resistance base metals, which can greatly reduce the preparation cost while obtaining low contact resistance.

[0038] In some embodiments, specifically, the passivation and antireflection layer includes any one or a combination of multiple of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, amorphous silicon; the thickness of the passivation and antireflection layer is 40 nm to 150 nm, and the refractive index is 1.8 to 2.2.

[0039] Specifically, the setting of the passivation and antireflection layer can avoid the influence of materials with high parasitic absorption such as amorphous silicon, polycrystalline silicon, and TCO on the battery, reduce the battery current loss, and at the same time, without using hydrogenated amorphous silicon, reduce the risk of ultraviolet attenuation of the battery.

[0040] In some embodiments, specifically, the depth of the N+ inner diffusion layer is 20 nm to 100 nm; the thickness of the tunneling oxide layer is 0.5 nm to 3 nm; the thickness of the phosphorus-doped polysilicon layer is 15 nm to 300 nm, and the effective doping concentration is 5E+19 cm -3 ~1E+22 cm -3 ; and the thickness ratio of the tunneling oxide layer to the phosphorus-doped polysilicon layer is 1:20 to 1:300.

[0041] In some embodiments, specifically, the reflectivity of the pyramid texture on the light-receiving surface in the light-receiving area is 9% to 12%, the pyramid height is 1 μm to 5 μm, and the pyramid width is 1 μm to 5 μm; the reflectivity of the pyramid texture on the light-receiving surface in the passivation contact area is 9% to 12%, the pyramid height is 0.6 μm to 1.2 μm, and the pyramid width is 0.8 μm to 1.5 μm.

[0042] Specifically, it is difficult to deposit a uniform tunneling oxide layer and doped amorphous silicon on the pyramid tips, edges, and valleys of the texture. During the annealing process, the tunneling oxide layer at the valleys and tips is extremely easy to thin or even disappear, resulting in a reduction in the surface chemical passivation quality and affecting the battery efficiency; compared with the micron-scale pyramid texture, the nano-scale pyramid texture is easier to deposit a uniform tunneling oxide layer and doped amorphous silicon, and during the annealing process, it can balance chemical passivation (tunneling oxide layer passivation) and field effect passivation (N+ inner diffusion passivation) to achieve high passivation performance.

[0043] In some embodiments, specifically, the backlight surface of the N-type silicon substrate has a micron-scale pyramid texture, and an intrinsic hydrogenated amorphous layer, a boron-doped hydrogenated amorphous layer, and a back conductive film layer are sequentially stacked on the micron-scale pyramid texture; wherein, a metal electrode is further provided on the back conductive film layer.

[0044] In some embodiments, specifically, the back conductive film layer is a metal compound, including any one or a combination of multiple of ITO, IWO, TiO, TiN, AZO; the thickness of the back conductive film layer is 70 nm to 150 nm, and the sheet resistance is 50 to 120.

[0045] In some embodiments, specifically, the thickness of the intrinsic hydrogenated amorphous layer is 3 nm to 10 nm; the thickness of the boron-doped hydrogenated amorphous layer is 3 nm to 10 nm, and the doping concentration is 1E+19 cm -3 ~5E+19 cm -3 ; the thickness of the back conductive film layer is 10 nm to 30 nm, and the doping concentration is 5E+19 cm -3 ~2E+20 cm -3 .

[0046] In some embodiments, specifically, the metal electrode includes one or a combination of silver, copper, aluminum, and tin. The width of the metal electrode is 10 μm to 50 μm, and the height of the metal electrode is 5 μm to 20 μm.

[0047] The embodiments of the present disclosure further provide a preparation method for the high-efficiency combined passivation battery structure as described above, including the following steps: Step S1, preparing a nano-scale small pyramid texture on the light-receiving surface and the backlight surface of the N-type silicon substrate to obtain the structure as Figure 1 shown, and the specific process is as Figure 2 shown; Clean the surface of the silicon wafer with a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 15%) to remove the dirt on the surface of the silicon wafer. Process temperature: 55°C to 70°C, process time: 1 min to 3 min; Use water washing to remove the residual chemicals and dirt on the surface. Cleaning time: 2 min to 3 min; Use a mixed solution of potassium hydroxide (1% - 5%) and texturing additive (0.5% - 3%) to form a large pyramid texture on the front surface of the silicon wafer. Process temperature: 70°C to 75°C, process time (3 min to 4 min); In this step, use low-temperature, low-concentration alkali and low-concentration additive to remove the cutting damage of the silicon wafer and prepare a large pyramid texture on the surface of the silicon wafer; Specifically, in this step, the height of the pyramid is 3 - 4 μm, the width is 5 - 6 μm, and the reflectivity is 14% - 16%; Use a mixed solution of potassium hydroxide (5% - 10%) and texturing additive (3% - 5%) to perform secondary texturing on the surface of the silicon wafer to form a small pyramid texture. Process temperature: 75°C to 85°C, process time 3 min to 4 min; In this step, use high-temperature, high-concentration alkali and high-concentration additive to perform secondary texturing on the surface of the original large pyramid texture to prepare a small pyramid texture; Specifically, in this step, the height of the pyramid is: 0.8 μm to 1.4 μm, the width of the pyramid is: 1 μm to 1.7 μm; the reflectivity is: 8% - 11%; Use water washing to remove surface drug residues and dirt, cleaning time: 2 min - 3 min; Use a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 15%) to clean the surface of the silicon wafer, removing the dirt on the surface of the silicon wafer, process temperature: 55 °C - 70 °C, process time: 1 min - 3 min; Use water washing to remove surface drug residues and dirt, cleaning time: 2 min - 3 min; Use a mixed solution of hydrofluoric acid (0.1% - 2%), hydrochloric acid (0.1% - 2%) and O3 (10 ppm - 50 ppm) to clean the surface of the silicon wafer. At the same time, the weak etching system of O3 and HF corrodes the surface of the smooth pyramid, process temperature: 15 °C - 25 °C, process time: 3 min - 6 min; In this step, use the weak etching system of O3 and HF to weakly etch the silicon substrate on the surface of the original small pyramid texture, and reduce the volume of the pyramid again to form a nano-scale pyramid texture; Specifically, in this step, the pyramid height: 600 nm - 1200 nm, the pyramid width: 800 nm - 1500 nm, the reflectivity: 9% - 12%; Use water washing to remove surface drug residues and dirt, cleaning time: 2 min - 3 min; Use a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%) to clean the surface of the silicon wafer, process temperature: room temperature, process time: 3 min - 5 min; Use water washing to remove surface drug residues and dirt, cleaning time: 2 min - 3 min; Use slow lifting to remove the dirt on the surface of the silicon wafer and dehydrate the silicon wafer, cleaning time 0.5 min - 1 min, cleaning temperature: 20 °C - 70 °C; Place the silicon wafer in a drying tank, blow it with high temperature, dry the surface of the silicon wafer, the blowing gas: nitrogen or compressed air, temperature: 80 °C - 100 °C, drying time: 5 min - 15 min; The weight loss of the silicon wafer: 0.3 g - 0.5 g; (taking the 182.2 size silicon wafer as an example) Pyramid height: 600 nm - 1200 nm; Pyramid width: 800 nm - 1500 nm; Reflectivity: 9% - 12%; Specifically, the nano-scale small pyramid texture is more conducive to improving the deposition and annealing uniformity of the subsequent tip, edge and valley film layers, and improving passivation.

[0048] Step S2, a tunneling oxide layer and a phosphorus-doped polysilicon layer are sequentially deposited on the light-receiving surface to form a passivated contact structure, and high-temperature annealing is performed to form an N+ inner diffusion layer in the contact region between the tunneling oxide layer and the N-type silicon substrate, and annealing oxide layers are respectively formed on the outermost layers of the light-receiving surface and the backlight surface, obtaining the structure as shown in Figure 3 shown, and the specific process is as shown in Figure 4 shown; In this step, a tunneling oxide layer and phosphorus-doped amorphous silicon are first deposited on the front side of the silicon wafer, and then through high-temperature annealing, the phosphorus-doped amorphous silicon is crystallized into phosphorus-doped polysilicon, and at the same time, phosphorus atoms are pushed into the tunneling oxide layer and enter the silicon substrate to form tunneling pinholes, forming N+ inner diffusion; In this step, the tunneling oxide layer can be prepared by tube-type LP, PE, ALD, plate-type PE, PVD, ALD, or wet oxygen in a tank; Phosphorus-doped amorphous silicon can be prepared by plate-type PVD, PE, tube-type LP, or PE; The present invention preferably uses plate-type PECVD to prepare the tunneling oxide layer and plate-type PVD to prepare phosphorus-doped amorphous silicon. Plate-type PVD has the characteristics of single-sided deposition without plating around, fast deposition rate, easy in-situ doping, and easy crystallization. At the same time, plate-type equipment has the advantage of integrating different types of film layers for coating, reducing equipment investment and the frequency of breaking the vacuum for battery coating; The present invention uses plate-type PECVD to prepare the tunneling oxide layer, which can be prepared using O2, O3, N2O, or a combination of SiH4 and one or more of the above gases. The present invention preferably uses O2 with low cost and high safety for preparation; In this step, the phosphorus doping source can be phosphine, phosphorus, a phosphorus-doped target, etc.; The present invention preferably uses phosphine as the doping gas. Phosphine has the characteristics of high doping efficiency, easy decomposition, etc., and has high matching with PVD coating; The specific implementation steps and results are as follows: The front side of the polished silicon wafer is oxidized by plate-type PECVD to prepare a tunneling oxide layer, and a layer of phosphorus-doped amorphous silicon is deposited on the front side of the oxidized silicon wafer by plate-type PVD, and phosphorus-doped polysilicon and N+ inner diffusion are prepared by high-temperature oxidation annealing; The polished silicon wafer is placed on a perforated carrier plate, which is transferred to the loading chamber 1. The chamber is evacuated, and the carrier plate is transferred to the PECVD1 reaction chamber 1. The PECVD method is used to ionize O2 into plasma, and the surface of the silicon wafer is oxidized from bottom to top through the perforated carrier plate to prepare tunneling oxide silicon. The carrier plate is transferred to the transition chamber, the chamber is evacuated, the carrier plate is transferred to the buffer chamber 1, and then transferred to the PVD1 reaction chamber 2. The PVD method is used to deposit phosphorus-doped amorphous silicon from bottom to top through the perforated carrier plate. Then it is transferred to the PVD2 reaction chamber 3, and the PVD method is used to deposit a silicon oxide mask from top to bottom through the perforated carrier plate. Then it is transferred to the buffer chamber 2, the carrier plate is transferred to the cooling chamber 1, the carrier plate is transferred to the unloading chamber 1, the unloading chamber is backfilled with nitrogen to the atmospheric state, the carrier plate is transferred out of the chamber, and the silicon wafer is collected to complete the film layer preparation; The silicon wafer with the front side coated is inserted into a quartz carrier and transferred to a high-temperature annealing furnace tube. Through the steps of opening the furnace door - loading the boat - evacuating - heating up - maintaining a constant temperature - leak detection - heating up - maintaining a constant temperature - oxidation - cooling down - breaking the vacuum - unloading the boat, oxidation annealing is carried out to complete the preparation of phosphorus-doped polysilicon, tunneling oxide layer, and N+ internal diffusion; PECVD1 reaction chamber 1: When the tunneling oxide layer is oxidized and prepared by the PECVD method, oxygen is used as the process gas, the process pressure is 5 Pa to 20 Pa, the process temperature is 150 °C to 350 °C, the power is 50 W to 500 W, and the process belt speed is 10 cm / min to 500 cm / min; PVD1 reaction chamber 2: When phosphorus-doped amorphous silicon is prepared by the PVD method, a silicon target is used as the silicon source, argon is used as the working gas, and phosphine is used as the doping gas. The process pressure is 0.1 Pa to 1 Pa, the process temperature is 200 °C to 500 °C, the power is 10 kW to 40 kW, and the process belt speed is 10 cm / min to 500 cm / min; PVD2 reaction chamber 3: When silicon oxide is prepared by the PVD method, a silicon target is used as the silicon source, argon is used as the working gas, and oxygen is used as the doping gas. The process pressure is 0.1 Pa to 1 Pa, the process temperature is 200 °C to 500 °C, the power is 10 kW to 40 kW, and the process belt speed is 10 cm / min to 500 cm / min; In the step of heating up after leak detection, gradient heating is adopted to reduce the annealing process effect difference caused by the initial temperature difference at the furnace mouth - furnace middle - furnace tail stages due to opening the furnace door. The specific heating method is as follows: 800 °C - 820 °C - 840 °C - 860 °C - 880 °C replaces the traditional 800 °C - 840 °C - 880 °C; Different oxidation annealing temperatures are adopted in different temperature zones to avoid the annealing process effect difference at different positions caused by the rapid cooling at the furnace mouth and furnace tail due to the water cooling of the furnace tube and the slow heating at the furnace mouth and fast heating at the furnace tail due to opening the furnace door. The specific temperature setting method is as follows: furnace mouth - furnace middle - furnace tail: 890 °C - 880 °C - 885 °C replaces the traditional furnace mouth - furnace middle - furnace tail: 880 °C - 880 °C - 880 °C; Oxidation annealing time: 30 min to 120 min; Oxidation annealing temperature: 840 °C to 950 °C; Oxidation annealing pressure: 600 mBar to 900 mBar; Tunneling oxide layer thickness: 0.5 nm to 3 nm, which can be freely adjusted by power, belt speed, flow rate, and temperature to meet the process requirements; Effective doping concentration of phosphorus-doped polysilicon doping: 5E+19 cm -3 ~1E+22 cm -3 , which can be freely adjusted by phosphine flow rate, process pressure, and process time to meet the process requirements; Thickness of phosphorus-doped polysilicon: 15 nm to 300 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of silicon targets to meet the process requirements; Thickness of annealed silicon oxide: 10 nm to 30 nm, which can be freely adjusted by oxygen flow rate, annealing time, and annealing temperature to meet the process requirements; N+ internal diffusion depth: 20 nm to 100 nm.

[0049] Step S3, pickling to remove the annealed silicon oxide layer on the light-receiving surface and the backlight surface, obtaining the structure as Figure 5 shown, and the specific process is as Figure 6 shown; In this step, hydrofluoric acid and hydrochloric acid are used to remove the annealed silicon oxide layer on the front and back surfaces of the silicon wafer; The specific steps are as follows: Use water washing to remove the residual medicine and dirt on the surface, washing time: 2 min to 3 min; Use a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%) to wash the surface of the silicon wafer, process temperature: room temperature, process time: 3 min to 5 min; Use water washing to remove the residual medicine and dirt on the surface, washing time: 2 min to 3 min; Use slow lifting to remove the dirt on the surface of the silicon wafer to dehydrate the silicon wafer, washing time 0.5 min to 1 min, washing temperature: 20 °C to 70 °C; Place the silicon wafer in a drying tank, blow it with high temperature, dry the surface of the silicon wafer, blowing gas: nitrogen or compressed air, temperature: 80 °C to 100 °C, drying time: 5 min to 15 min.

[0050] Step S4, deposit a front conductive film layer and a silicon nitride layer in sequence outside the phosphorus-doped polysilicon layer on the light-receiving surface, obtaining the structure as Figure 7 shown, and the specific process is as Figure 8 shown; The front conductive film described in this step includes one or more combinations of metals, metal compounds, and carbon-based compounds, such as one or more combinations of Ti, Cu, Sn, Al, Ag, Au, W, TiW, V, ITO, IWO, TiO, TiN, AZO, graphene, etc. When using a metal film for the conductive film, high-temperature annealing is required for activation; The deposition method of the conductive film can be PVD, RPD, CVD, ALD, spin coating, etc.; In the present invention, it is preferred to use the plate-type PVD coating method to deposit Ti to prepare the front conductive film. The plate-type PVD has the characteristics of fast deposition rate and excellent uniformity between and within wafers. Ti has the characteristics of high conductivity and high stability; Furthermore, when using Ti metal as the conductive film, a mask needs to be added for the high-temperature annealing protection layer of the metal, while no mask needs to be added when using metal compounds; Deposit a layer of metal Ti on the front side of the pickled silicon wafer by plate-type PVD, and then deposit a layer of silicon nitride mask on the front side of the silicon wafer by plate-type PECVD; The specific implementation steps are as follows: For the pickled silicon wafer, place it face down on the perforated carrier plate, first transfer it to the loading chamber 2 for evacuation, then transfer it to the transition chamber 2 for secondary evacuation using a molecular pump, then transfer it to the buffer chamber 3, and then transfer it to the PVD2 reaction chamber 3. Deposit a layer of metal Ti conductive film from bottom to top by plate-type PVD, and then transfer it to the buffer chamber 4 to complete the preparation of metal Ti; For the silicon wafer deposited with metal Ti, first transfer it to the transition chamber 3 for evacuation, then transfer it to the PECVD2 reaction chamber 4 to deposit a layer of silicon nitride from bottom to top, then transfer it to the cooling chamber 2, and finally transfer it to the unloading chamber 2. Backfill the atmosphere with nitrogen, take out the carrier plate from the chamber, and collect the silicon wafers; For the silicon wafer deposited with the film layer, transfer it to the high-temperature annealing furnace for sintering through the track conveyor to complete the ohmic contact between the polysilicon and Ti, the annealing of Ti, and the H implantation of the silicon nitride mask; PVD2 reaction chamber 3: When using the PVD method to prepare the front Ti conductive film, use a Ti target as the Ti source and argon as the working gas. Process temperature: 100 - 250 °C, process pressure: 0.2 Pa - 2 Pa, power: 5000 W - 40000 W; PECVD2 reaction chamber 4: Use the PECVD method to prepare the silicon nitride mask, with SiH4, NH3, and N2 as the process gases. Process temperature: 100 °C - 450 °C, process pressure: 10 Pa - 50 Pa, SiH4:NH3:N2 flow ratio: 1:1:1 - 5:1:1, power: 50 W - 300 W; Ti film thickness: 5 nm - 150 nm; Silicon nitride mask thickness: 50 nm - 100 nm; Sheet resistance after annealing: 0 - 120; Annealing temperature: 500°C - 900°C; Annealing time: 1 min - 10 min.

[0051] Step S5, set the passivation contact area and the light-receiving area on the light-receiving surface, and open the film in the light-receiving area to prepare a patterned interdigital structure, obtaining the structure as Figure 9 shown; In this step, patterning can be prepared by using the laser film opening method or the graphic mask etching method; The present invention preferably uses the laser film opening method for preparation. The laser film opening method has the advantages of fast speed and low cost; Furthermore, the laser can use nanosecond laser, picosecond laser, or femtosecond laser. The present invention preferably uses picosecond laser with low cost, low loss, and high film opening rate. Combining with subsequent wet etching to remove damage, non-destructive patterning preparation can be achieved; The specific implementation steps and results are as follows: Place the battery on a horizontal tabletop, use a pulsed ultraviolet picosecond laser to etch the front silicon nitride mask and the conductive film to the phosphorus-doped polysilicon layer, and retain part of the phosphorus-doped polysilicon layer and the tunneling oxide layer; Laser power: 50 W - 500 W; Film opening width: 100 μm - 600 μm; Width of the retained silicon nitride mask: 30 μm - 200 μm.

[0052] Step S6, etch the light-receiving area to expose the silicon substrate, and texture the light-receiving area to form a micron-level pyramid texture morphology, obtaining the structure as Figure 10 shown, and the specific process is as Figure 11 shown; In this step, the selective etching of silicon and silicon nitride by potassium hydroxide is used to prepare a structure with a small texture in the passivation contact area (metal contact area) and a conventional texture interdigital arrangement in the light-receiving area (non-metal contact area) on the front side; The specific steps are as follows: Use a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 15%) to clean the surface of the silicon wafer, remove the dirt and laser dust on the surface of the silicon wafer, process temperature: 55°C - 70°C, process time: 0.5 min - 1 min; Use water washing to remove the residual chemicals and dirt on the surface, washing time: 2 min - 3 min; Use a mixed solution of potassium hydroxide (1% - 10%) and an additive (0.5% - 5%) to remove the polysilicon and the tunneling oxide layer in the front film opening area and texture at the same time, process temperature: 60°C - 85°C, process time: 0.5 min - 1 min; Use water washing to remove the residual chemicals and dirt on the surface, washing time: 2 min - 3 min; Clean the surface of the silicon wafer with a mixed solution of potassium hydroxide (1% - 10%) and hydrogen peroxide (5% - 20%) to remove the residual additives. Process temperature: 55°C - 70°C, process time: 0.5 min - 1 min; Use water washing to remove the residual medicine and dirt on the surface. Washing time: 2 min - 3 min; Clean the surface of the silicon wafer with a mixed solution of hydrofluoric acid (1% - 10%) and hydrochloric acid (1% - 10%). Process temperature: room temperature, process time: 3 min - 5 min; Use water washing to remove the residual medicine and dirt on the surface. Washing time: 2 min - 3 min; Use slow lifting to remove the dirt on the surface of the silicon wafer and dehydrate the silicon wafer. Cleaning time: 0.5 min - 1 min, cleaning temperature: 20°C - 70°C; Place the silicon wafer in a drying tank and blow it with high temperature to dry the surface of the silicon wafer. Blowing gas: nitrogen or compressed air, temperature: 80°C - 100°C, drying time: 5 min - 15 min; Cleaning method: The silicon wafer enters the solution vertically, the laser line direction of the silicon wafer is perpendicular to the solution surface, and the detachment of the residual medicine on the silicon wafer surface is not affected by the back groove morphology; Weight loss of the silicon wafer: 0.1 g - 0.2 g; (taking the 182.2 - sized silicon wafer as an example) Suede reflectivity: 9% - 12%; Pyramid height: 1 μm - 5 μm; Pyramid width: 1 μm - 5 μm.

[0053] In step S7, deposit a passivation and antireflection layer on the light - receiving surface to obtain the structure as Figure 12 shown; The passivation and antireflection layer described in this step includes one or a combination of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, amorphous silicon. In the present invention, it is preferred to use aluminum oxide and silicon nitride as the passivation and antireflection film; Aluminum oxide can be prepared by plate - type PECVD, plate - type ALD, plate - type PVD, tube - type PECVD, tube - type ALD; Silicon nitride can be prepared by plate - type PECVD, plate - type PVD, tube - type PECVD; In the present invention, it is preferred to use plate - type ALD to prepare the front - side aluminum oxide and plate - type PECVD to prepare the front - side silicon nitride. The plate - type coating equipment has no over - plating and no sticking marks, and the front of the battery is beautiful; Use plate - type ALD to prepare the front - side aluminum oxide. Place the silicon wafer on a carbon fiber carrier plate and transfer it to the process chamber. Use trimethylaluminum and water as the process gases. Process temperature: 200°C - 400°C, process time: 3 min - 30 min, trimethylaluminum / water flow ratio: 1:2 - 2:1; Plate-type PECVD is used to prepare front silicon nitride. The silicon wafer is placed on a carbon fiber carrier and transferred to the process chamber. Silane and ammonia are used as process gases. The process temperature is 400℃~450℃, the process time is 2min~10min, and the silane / ammonia flow ratio is 1:3~3:1. Specifically, plate-type PECVD, with a deposition temperature of 400 to 450 degrees Celsius, can better protect the H passivation of excited aluminum oxide.

[0054] Alumina thickness: 2nm~40nm; Silicon nitride thickness: 40nm~150nm, refractive index: 1.8~2.2.

[0055] Step S8, depositing an intrinsic hydrogenated amorphous layer and a boron-doped hydrogenated amorphous layer on the backlight surface in sequence to obtain Figure 13 The structure shown in the figure, the specific process is as follows Figure 14 As shown; The back passivation structure of the present invention is a stacked film of hydrogenated intrinsic amorphous silicon, boron-doped amorphous silicon, and boron-doped microcrystalline carbon oxide silicon from the inside to the outside; The deposition method can be plate-type PECVD or plate-type HWCVD; The present invention preferably uses plate-type PECVD deposition; Boron-doped microcrystalline carbon oxide silicon wafer, the carbon and oxygen sources can be one or more of CH4, CO2, TMB, O2; CO2 and TMB are preferably used as the carbon and oxygen sources in this paper; The specific implementation steps and results are as follows: A flat-plate PECVD method is used to first deposit a layer of ia:Si from top to bottom on the back of the silicon wafer after the front coating, and then the deposited surface is cleaned by HPT (H ion cleaning), and finally a flat-plate PECVD method is used to first deposit Pa:Si from top to bottom on the back of the silicon wafer. The deposition includes (a layer of Pa:Si and a layer of P-uc-SiOxCy); The double-sided cleaned silicon wafer is placed on a hollow carrier, which is then transferred to the loading chamber 3, where the chamber is evacuated, and then transferred to the preheating buffer chamber 5, and then transferred to the PECVD3 reaction chamber 5 to deposit a layer of ia:Si from top to bottom, and then transferred to the HPT cleaning buffer chamber 6, where H ions clean the deposited surface to complete the preparation of ia:Si. The carrier is first transferred to the transition chamber 4, then to the buffer chamber 7, and then to the PECVD4 reaction chamber 6, where a layer of Pa:Si and a layer of P-uc-SiOxCy are deposited from top to bottom, and then transferred to the buffer chamber 8 to complete the preparation of Pa:Si; The carrier is transferred to the unloading chamber 3, backfilled with nitrogen to the atmospheric state, the carrier is transferred out, the silicon wafer is collected, and the back passivation film layer is prepared; PECVD3 Reaction Chamber 5: Prepare i-a:Si by PECVD method, using SiH4 and H2 as process gases, process temperature: 100°C to 250°C, process pressure: 10 Pa to 50 Pa, SiH4:H2 flow ratio: 1:10 to 1:30, power: 50 W to 300 W; PECVD4 Reaction Chamber 6: Prepare P-a:Si by PECVD method. P-a:Si is divided into two layers: conventional B-doped amorphous silicon (P-a:Si) and B-doped microcrystalline carbon oxide silicon (P-uc-SiOxCy); Prepare conventional B-doped amorphous silicon (P-a:Si), using SiH4, H2, and B2H6 as process gases, process temperature: 100°C to 250°C, process pressure: 10 Pa to 50 Pa, SiH4:H2:B2H6(2%) flow ratio: 1:20:5 to 1:30:15, power: 50 W to 300 W; Prepare B-doped microcrystalline carbon oxide silicon (P-uc-SiOxCy), using SiH4, H2, B2H6, CO2, and TMB as process gases, process temperature: 100°C to 250°C, process pressure: 50 Pa to 100 Pa, SiH4:H2:B2H6(2%) flow ratio: 1:30:10 to 1:60:30, CO2 and TMB micro-doping gas flow: 5 sccm - 20 sccm, power: 300 W to 500 W; HPT Cleaning Buffer Chamber: Ionize H by PECVD method to clean the deposited surface of the silicon wafer, using H2 as the process gas, Process temperature: 100°C to 250°C, process pressure: 50 Pa to 100 Pa, power: 50 W to 400 W; i:a-Si thickness: 2 nm to 10 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of ion sources to meet the process requirements; P:a-Si thickness: 10 nm to 20 nm, P-uc-SiOxCy thickness: 20 nm to 50 nm, which can be freely adjusted by power, belt speed, flow rate, temperature, and the number of ion sources to meet the process requirements; P:a-Si doping concentration: 1E+18 cm -3 ~5E+18 cm -3 :P-uc-SiOxCy doping concentration: 5E+18 cm -3 ~2E+19 cm -3 , and the doping amount can be freely adjusted by belt speed, pressure, flow rate, and temperature to meet the process requirements.

[0056] Step S9, deposit a back conductive film layer on the boron-doped amorphous hydrogenated layer on the backlight side to obtain the structure as Figure 15 shown, and the specific process is as Figure 16 shown; In this step, the transparent conductive film layer can be prepared by plate PVD, plate RPD, or plate ALD. The transparent conductive film can be one or a combination of ITO, IWO, TiO, TiN, AZO, etc. The present invention preferably uses plate PVD coating to deposit ITO to prepare the back transparent conductive film. Plate PVD has the characteristics of fast deposition rate and excellent uniformity between and within wafers. ITO has the characteristics of high light transmittance and high conductivity. Use flat plate PVD to deposit a layer of ITO from bottom to top on the back of the amorphous deposited silicon wafer. The specific implementation steps are as follows: The amorphous deposited silicon wafer is placed face up on the perforated carrier plate, first transferred to the loading chamber 4 for vacuum pumping, then transferred to the transfer chamber 5, then transferred to the buffer chamber 9, and finally transferred to the PVD3 reaction chamber 7 to deposit a layer of ITO from bottom to top to complete the deposition of the back ITO. The silicon wafer with the back ITO deposition completed is first transferred to the buffer chamber 10, then transferred to the cooling chamber 2, and finally transferred to the unloading chamber 4. Nitrogen is used to backfill the atmosphere, the carrier plate is taken out of the chamber, and the silicon wafer is collected. PVD2 reaction chamber 5: When using PVD method to prepare the back ITO, use ITO target (In2O3 / SnO2 mass ratio: 90:10), and use argon and oxygen as working gases. Process temperature: 100 - 250 °C, process pressure: 0.2 Pa - 2 Pa, Ar / O2 flow ratio: 200:1 - 100:1, power: 5000 W - 40000 W; ITO thickness: 70 nm - 150 nm; ITO sheet resistance: 50 - 120.

[0057] Step S10, locally open the film in the passivated contact area of the light-receiving surface to expose the front conductive film layer, obtaining the structure as Figure 17 shown; Locally open the film in the front passivated contact area to remove the surface aluminum oxide, silicon nitride, and silicon nitride mask, exposing the conductive film; In this step, the film opening can be prepared by laser film opening method or pattern mask etching method; The present invention preferably uses the laser film opening method to prepare. The laser film opening method has the advantages of fast speed and low cost; Furthermore, the laser can use nanosecond laser, picosecond laser, or femtosecond laser. The present invention preferably uses femtosecond laser with low cost, low loss, and high film opening rate; The specific implementation steps are as follows: Place the battery on a horizontal tabletop, use a pulsed ultraviolet femtosecond laser to locally open the film to remove the surface aluminum oxide, silicon nitride, and silicon nitride mask, exposing the conductive film; Film opening width: 10 μm - 50 μm.

[0058] Step S11, metal electrodes are respectively prepared on the front conductive film layer and the back conductive film layer to obtain the structure as Figure 18 shown; Metal electrodes are prepared on the surfaces of the front and back conductive films; The metallization method can be electroplating or the method of curing screen-printed metal paste; in this article, the simple and environmentally friendly method of curing screen-printed metal paste is preferably used; the metal paste can be one or a combination of silver paste, silver-coated copper paste, and copper paste, and silver-coated copper paste is preferably used in this article; The specific implementation steps are as follows: The silicon wafer after laser film opening is placed on a horizontal tabletop. Through screen printing technology, silver-coated copper paste is printed on the front and back of the battery. The printed silicon wafer is transferred to a curing furnace, dried and cured to form an ohmic contact with the conductive film; The battery is transferred to an annealing furnace for annealing photo-injection to excite H and improve passivation; The battery preparation is completed; Width of the metal electrode: 10 μm to 50 μm; Height of the metal electrode: 5 μm to 20 μm.

[0059] Specifically, the above process uses the plate PVD non-bypass plating single-sided deposition in-situ doping technology to solve the problems of bypass plating and diffusion in the preparation of phosphorus-doped polysilicon with TOPCON structure.

[0060] In summary, in the high-efficiency combined passivation battery structure and its preparation method of the present invention, by dividing the passivation contact area and the light-receiving area on the light-receiving surface, and separately setting the passivation contact structure in the passivation contact area, the thickness of the crystalline silicon can be increased and the contact resistance can be reduced without causing optical loss; at the same time, depositing the TOPCon passivation contact structure on the nano-scale small pyramid texture surface to achieve passivation contact can effectively avoid the problem of low passivation on the texture surface, realizing the effective combination of the TOPCon passivation structure and the HJT battery.

[0061] Taking the above ideal embodiments based on the present invention as an inspiration, through the above description, relevant staff can completely make various changes and modifications without departing from the technical idea of the present invention. The technical scope of the present invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A high-efficiency combined passivation battery structure, characterized in that: include: An N-type silicon substrate (1) having a light-receiving surface (2) with a pyramid velvet morphology, wherein a passivation contact region (21) and a light-receiving region (22) arranged in an interdigitated structure are provided on the light-receiving surface (2); An N+ inner expansion layer (4), a tunneling oxide layer (5), a phosphorus-doped polysilicon layer (6), a front conductive film layer (8) and a silicon nitride layer (9) are sequentially stacked on the passivation contact region (21); A passivation anti-reflection layer is stacked on the light receiving area (22) and on the outer side of the silicon nitride layer (9) of the passivation contact area (21); The passivation contact area (21) is also partially provided with a metal electrode (14) that contacts the front conductive film layer (8); Furthermore, the pyramid velvet surface morphology is at the micrometer level in the light receiving area (2) and at the nanometer level in the passivation contact area (21).

2. The high-efficiency combined passivation battery structure according to claim 1, characterized in that: The width of the passivation contact area is 30 to 200 μm; The width of the light receiving area is 100 to 600 μm; The area ratio of the passivation contact area to the light receiving area is 1:1 to 1:

6.

3. The high-efficiency combined passivation battery structure according to claim 1, characterized in that: The front conductive film layer includes any one or more combinations of metals, metal compounds and carbon-based compounds; The thickness of the front conductive film layer is 5nm-100nm, and the sheet resistance is not more than 120.

4. The high-efficiency combined passivation battery structure according to claim 1, characterized in that: The passivation anti-reflection layer comprises any one or more combinations of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride, magnesium fluoride, hydrogenated amorphous silicon, and amorphous silicon; The thickness of the passivation anti-reflection layer is 40nm-150nm, and the refractive index is 1.8-2.

2.

5. The high-efficiency combined passivation battery structure according to claim 1, characterized in that: The depth of the N+ inner expansion layer is 20nm to 100nm; The thickness of the tunnel oxide layer is 0.5nm to 3nm; The thickness of the phosphorus-doped polysilicon layer is 15nm to 300nm, and the effective doping concentration is 5E+19cm -3 ~1E+22cm -3 ; And the thickness ratio of the tunneling oxide layer to the phosphorus-doped polysilicon layer is 1:20 to 1:

300.

6. The high-efficiency combined passivation battery structure according to claim 1, characterized in that: The pyramid velvet morphology of the light-receiving surface has a reflectivity of 9% to 12% in the light-receiving area, a pyramid height of 1 μm to 5 μm, and a pyramid width of 1 μm to 5 μm; The pyramid velvet morphology of the light-receiving surface has a reflectivity of 9% to 12% in the passivation contact area, a pyramid height of 0.6 μm to 1.2 μm, and a pyramid width of 0.8 μm to 1.5 μm.

7. The high-efficiency combined passivation battery structure according to claim 1, characterized in that: The backlight surface (3) of the N-type silicon substrate (1) has a micron-scale pyramid velvet morphology, and an intrinsic hydrogenated amorphous layer (11), a boron-doped hydrogenated amorphous layer (12) and a back conductive film layer (13) are sequentially stacked on the micron-scale pyramid velvet morphology; Wherein, a metal electrode (14) is also provided on the back conductive film layer (13).

8. The high-efficiency combined passivation battery structure according to claim 7, characterized in that: The back conductive film layer is a metal compound; The thickness of the back conductive film layer is 70nm-150nm, and the sheet resistance is 50-120.

9. The high-efficiency combined passivation battery structure according to claim 7, characterized in that: The thickness of the intrinsic hydrogenated amorphous layer is 3nm to 10nm; The boron-doped hydrogenated amorphous layer has a thickness of 3 nm to 10 nm and a doping concentration of 1E+19 cm -3 ~5E+19cm -3 ; The thickness of the back conductive film layer is 10nm to 30nm, and the doping concentration is 5E+19cm -3 ~2E+20cm -3 .

10. A method for preparing a high-efficiency combined passivation battery structure, characterized in that: The steps include: Nano-scale small pyramid velvet morphologies are prepared on the light-receiving surface (2) and the backlight surface (3) of the N-type silicon substrate (1); A tunneling oxide layer (5) and a phosphorus-doped polysilicon layer (6) are sequentially deposited on the light-receiving surface (2) to form a passivation contact structure, high-temperature annealing is performed to form an N+ inner expansion layer (4) in the contact area between the tunneling oxide layer (5) and the N-type silicon base (1), and an annealed oxide layer (7) is formed on the outermost layers of the light-receiving surface (2) and the backlight surface (3); Removing the annealed oxide layer (7) on the light-receiving surface (2) and the backlight surface (3); Depositing a front conductive film layer (8) and a silicon nitride layer (9) in sequence on the outer side of the phosphorus-doped polysilicon layer (6) of the light-receiving surface (2); A passivation contact region (21) and a light receiving region (22) are set on the light receiving surface (2), and a patterned interdigital structure is prepared by film-cutting in the light receiving region (22); The light receiving area (22) is corroded to expose the silicon base, and the silicon base is textured so that the light receiving area (22) forms a micron-scale pyramid textured surface morphology; Depositing a passivation anti-reflection layer on the light-receiving surface (2); On the backlight surface (3), an intrinsic hydrogenated amorphous layer (11) and a boron-doped hydrogenated amorphous layer (12) are sequentially deposited and prepared; Depositing a back conductive film layer (13) on the boron-doped hydrogenated amorphous layer (12) on the backlight side (3); Partially opening the film in the passivation contact area (21) of the light-receiving surface (2) to expose the front conductive film layer (8); Metal electrodes (14) are prepared on the front conductive film layer (8) and the back conductive film layer (13), respectively.

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