Light-emitting semiconductor structure and manufacturing method thereof

Abstract

The invention provides a light-emitting semiconductor structure. The light-emitting semiconductor structure comprises a substrate, an anode electrode, an epitaxial structure, a gate electrode and a cathode electrode, the anode electrode is arranged on the lower surface of the substrate, the epitaxial structure is arranged on the upper surface of the substrate and comprises a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, a second N-type semiconductor layer and a light emitting layer, the first P-type semiconductor layer is arranged on the upper surface of the substrate, the first N-type semiconductor layer is arranged on the first P-type semiconductor layer, and the second N-type semiconductor layer is arranged on the second N-type semiconductor layer. The second P-type semiconductor layer is arranged on the first N-type semiconductor layer, the second N-type semiconductor layer is arranged on the second P-type semiconductor layer, and the light-emitting layer is arranged between the second P-type semiconductor layer and the second N-type semiconductor layer.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and particularly relates to a light-emitting semiconductor structure. Background Art

[0002] Generally, the light-emitting component of an LED printhead (LPH) is implemented using an epitaxial structure, and an epitaxial structure for implementing a light-emitting component includes a light-emitting thyristor with a PNPN structure, that is, the light-emitting thyristor includes a P-type semiconductor, an N-type semiconductor, a P-type semiconductor, and an N-type semiconductor from bottom to top.

[0003] However, there is still a great deal of room for improvement in the light-emitting efficiency of the current epitaxial structure of the light-emitting thyristor. Moreover, when manufacturing the epitaxial structure of the light-emitting thyristor, the surface and edge sidewalls of the epitaxial component are often damaged or affected during the etching process step, thereby affecting the driving characteristics, IV characteristic curve (IV curve), and impedance characteristics of the epitaxial component. In addition, due to more defects at the edge of the semiconductor, the electrons and holes injected into the epitaxial component are often affected by the capture of the edge defect traps of the semiconductor, resulting in ineffective light emission at the edge of the light-emitting thyristor, thereby affecting the overall light-emitting efficiency of the component. Summary of the Invention

[0004] In some embodiments, a light-emitting semiconductor structure includes a substrate, an anode electrode, an epitaxial structure, a gate electrode, and a cathode electrode; the anode electrode is disposed on the lower surface of the substrate, the epitaxial structure is disposed on the upper surface of the substrate, the epitaxial structure includes a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, a second N-type semiconductor layer, and a light-emitting layer, the first P-type semiconductor layer is disposed on the upper surface of the substrate, the first N-type semiconductor layer is disposed on the first P-type semiconductor layer, the second P-type semiconductor layer is disposed on the first N-type semiconductor layer, the second N-type semiconductor layer is disposed on the second P-type semiconductor layer, the light-emitting layer is disposed between the second P-type semiconductor layer and the second N-type semiconductor layer, the gate electrode is disposed on the upper surface of the second P-type semiconductor layer, and the cathode electrode is disposed on the upper surface of the second N-type semiconductor layer.

[0005] In some embodiments, the light-emitting layer is a multiple quantum well layer, and the multiple quantum well layer includes a plurality of stacked well layers and a plurality of barrier layers.

[0006] In some embodiments, the light-emitting layer is an intrinsic semiconductor layer.

[0007] In some embodiments, the number of the plurality of well layers and the plurality of barrier layers is 5 to 30, the material of the plurality of well layers is gallium arsenide (GaAs), and the material of the plurality of barrier layers is aluminum gallium arsenide (AlGaAs) or indium gallium phosphide (InGaP).

[0008] In some embodiments, the light-emitting semiconductor structure further includes a current flow limiting layer disposed between the light-emitting layer and the second P-type semiconductor layer or between the light-emitting layer and the second N-type semiconductor layer. The current flow limiting layer includes a peripheral insulating region and a central conductive region.

[0009] In some embodiments, the peripheral insulating region is disposed directly below the cathode electrode.

[0010] In some embodiments, the material of the current flow limiting layer is aluminum arsenide (AlAs), and the peripheral insulating region is formed by oxidizing aluminum (Al) in the current flow limiting layer.

[0011] In some embodiments, the first P-type semiconductor layer includes a first buffer layer, a second buffer layer, and an anode layer. The first buffer layer is disposed on the upper surface of the substrate, the second buffer layer is disposed on the first buffer layer, and the anode layer is disposed on the second buffer layer.

[0012] In some embodiments, the second N-type semiconductor layer includes a blocking layer, a cathode layer, and a covering layer. The blocking layer is disposed on the upper surface of the light-emitting layer, the cathode layer is disposed on the blocking layer, and the covering layer is disposed on the cathode layer.

[0013] In some embodiments, a method of manufacturing a light-emitting semiconductor structure includes forming a cathode electrode on an upper surface of a semiconductor base structure. The semiconductor base structure includes a substrate, a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, a second N-type semiconductor layer, a light-emitting layer, a current flow limiting layer, and a highly doped P-type semiconductor layer. The first P-type semiconductor layer is disposed on the upper surface of the substrate. The first N-type semiconductor layer is disposed on the first P-type semiconductor layer. The second P-type semiconductor layer is disposed on the first N-type semiconductor layer. The second N-type semiconductor layer is disposed on the second P-type semiconductor layer. The light-emitting layer is disposed between the second P-type semiconductor layer and the second N-type semiconductor layer. The current flow limiting layer is disposed between the light-emitting layer and the second P-type semiconductor layer. The highly doped P-type semiconductor layer is disposed between the light-emitting layer and the current flow limiting layer. Forming a protective layer on the exposed surfaces of the cathode electrode and the semiconductor base structure. Performing a first dry etching step to form a first trench on one side of a predetermined light-emitting portion of the semiconductor base structure and a second trench on the other side of the predetermined light-emitting portion. The first trench and the second trench extend from the protective layer to the second P-type semiconductor layer and do not penetrate the second P-type semiconductor layer. Oxidizing the side surfaces of the current flow limiting layer through the first trench and the second trench. Performing a second dry etching step to form a third trench on one side of a predetermined switching portion of the semiconductor base structure and a fourth trench on the other side of the predetermined switching portion. And causing the second trench to penetrate the second P-type semiconductor layer and the first N-type semiconductor layer and extend to the first P-type semiconductor layer and not penetrate the first P-type semiconductor layer. The third trench is formed between the first trench and the predetermined switching portion. The third trench and the fourth trench extend from the protective layer to the second P-type semiconductor layer and do not penetrate the second P-type semiconductor layer. Forming a plurality of gate electrodes on the bottom surfaces of the third trench and the fourth trench. Performing a third dry etching step to form a fifth trench between two adjacent gate electrodes in the fourth trench. And causing the second trench to penetrate the first P-type semiconductor layer and extend to the substrate and not penetrate the substrate. The fifth trench extends from the bottom surface of the fourth trench to the first P-type semiconductor layer and does not penetrate the first P-type semiconductor layer. After the third dry etching step, integrally forming a passivation layer on the exposed surfaces of the semiconductor base structure, the cathode electrode, and the plurality of gate electrodes. After integrally forming the passivation layer on the exposed surfaces of the semiconductor base structure, the cathode electrode, and the plurality of gate electrodes, performing a fourth dry etching step to form a cathode opening above the cathode electrode and a gate opening above the gate electrode. And forming a wiring layer on the passivation layer. The wiring layer is electrically connected to the cathode electrode through the cathode opening and electrically connected to the gate electrode through the gate opening.

[0014] The following describes in detail the detailed features and advantages of the present case in the embodiments. The content is sufficient for any person skilled in the art to understand the technical content of the present case and implement it accordingly. And according to the content disclosed in this specification, the scope of the patent application, and the drawings, any person skilled in the art can easily understand the related purposes and advantages of the present case. Description of the Drawings

[0015] Figure 1 A cross-sectional schematic diagram of an embodiment of the light-emitting semiconductor structure of the present invention.

[0016] Figure 2 A cross-sectional schematic diagram of an embodiment of the light-emitting layer of the present invention.

[0017] Figure 3 A line graph comparing the luminous intensities of the light-emitting semiconductor structure of the present invention and the semiconductor structure of the prior art.

[0018] Figure 4A A cross-sectional schematic diagram of another embodiment of the light-emitting semiconductor structure of the present invention.

[0019] Figure 4B A cross-sectional schematic diagram of yet another embodiment of the light-emitting semiconductor structure of the present invention.

[0020] Figure 5A A cross-sectional schematic diagram of still another embodiment of the light-emitting semiconductor structure of the present invention.

[0021] Figure 5B A cross-sectional schematic diagram of still another embodiment of the light-emitting semiconductor structure of the present invention.

[0022] Figure 6 A top view of an embodiment of the light-emitting semiconductor array chip unit of the present invention.

[0023] Figure 7 is Figure 6 A cross-sectional view of the light-emitting semiconductor array chip unit along section line 7.

[0024] Figures 8A to 8I A step schematic diagram of an embodiment of the manufacturing method of the light-emitting semiconductor structure of the present invention.

[0025] Figure 9 A flowchart of an embodiment of the manufacturing method of the light-emitting semiconductor structure of the present invention.

[0026] Description of the reference numerals:

[0027] 1: Light-emitting semiconductor structure;

[0028] 10: Substrate;

[0029] 11: Anode electrode;

[0030] 12: First P-type semiconductor layer;

[0031] 13: First N-type semiconductor layer;

[0032] 14: Second P-type semiconductor layer;

[0033] 15: Light-emitting layer;

[0034] 16: Second N-type semiconductor layer;

[0035] 17: Gate electrode;

[0036] 18: Cathode electrode;

[0037] 120: First buffer layer;

[0038] 121: Second buffer layer;

[0039] 122: Anode layer;

[0040] 160: Blocking layer;

[0041] 161: Cathode layer;

[0042] 162: Cover layer;

[0043] 20: Epitaxial structure;

[0044] 151: Energy well layer;

[0045] 152: Energy barrier layer;

[0046] 19: Current flow limiting layer;

[0047] 190: Peripheral insulation region;

[0048] 191: Central conductive region;

[0049] 21: Highly doped P-type semiconductor layer;

[0050] 3: Light-emitting semiconductor array chip unit;

[0051] 30: Transmission part;

[0052] 31: Odd-even switch part;

[0053] 32: Light-emitting part;

[0054] 7: Hatching;

[0055] 180~181: Cathode electrode;

[0056] 1800~1801: Side surface of the cathode electrode;

[0057] 1900~1901: Side surface of the peripheral insulation region;

[0058] L: Length of the central conductive region;

[0059] 22: Semiconductor base structure;

[0060] 70: Protective layer;

[0061] 101~105: Grooves;

[0062] 40: Predetermined light-emitting part;

[0063] 41: Predetermined switching part;

[0064] 172: Gate opening;

[0065] 182: Cathode opening;

[0066] 71: Passivation layer;

[0067] 72: Circuit layer;

[0068] S01~S10: Steps. Detailed implementation manners

[0069] Figure 1 is a cross-sectional schematic diagram of an embodiment of the light-emitting semiconductor structure 1. Please refer to Figure 1 , the light-emitting semiconductor structure 1 includes a substrate 10, an anode electrode 11, an epitaxial structure 20, a gate electrode 17, and a cathode electrode 18. The anode electrode 11 is disposed on the lower surface of the substrate 10, the epitaxial structure 20 is disposed on the upper surface of the substrate 10, the epitaxial structure 20 includes a first P-type semiconductor layer 12, a first N-type semiconductor layer 13, a second P-type semiconductor layer 14, a second N-type semiconductor layer 16, and a light-emitting layer 15. The first P-type semiconductor layer 12 is disposed on the upper surface of the substrate 10, the first N-type semiconductor layer 13 is disposed on the first P-type semiconductor layer 12, the second P-type semiconductor layer 14 is disposed on the first N-type semiconductor layer 13, the second N-type semiconductor layer 16 is disposed on the second P-type semiconductor layer 14, the light-emitting layer 15 is disposed between the second P-type semiconductor layer 14 and the second N-type semiconductor layer 16, the gate electrode 17 is disposed on the upper surface of the second P-type semiconductor layer 14, and the cathode electrode 18 is disposed on the upper surface of the second N-type semiconductor layer 16.

[0070] Figure 2 is a cross-sectional schematic diagram of an embodiment of the light-emitting layer 15. Please refer to Figure 1 and Figure 2 , the light-emitting layer 15 includes a plurality of quantum well layers 151 and a plurality of barrier layers 152 stacked in groups. In Figure 2 the embodiment, the light-emitting layer 15 includes 5 quantum well layers 151 and 5 barrier layers 152, but the number of the plurality of quantum well layers 151 and the plurality of barrier layers 152 is not limited thereto. In some embodiments, the number of the plurality of quantum well layers 151 and the plurality of barrier layers 152 is 5 to 30.

[0071] In some embodiments, the material of the energy well layer 151 can be, but is not limited to, gallium arsenide (GaAs), and the material of the energy barrier layer 152 can be, but is not limited to, aluminum gallium arsenide (AlGaAs) or indium gallium phosphide (InGaP).

[0072] In some embodiments, the light-emitting layer 15 is an intrinsic semiconductor layer, that is, the light-emitting layer 15 is an undoped (non-doped) and lattice-intact pure crystal semiconductor, and the concentrations of free electrons (negatively charged carriers) and holes (positively charged carriers) that participate in conduction in the light-emitting layer 15 are equal and in equilibrium. In other words, in some embodiments, the epitaxial structure 20 is a PNPIN structure rather than a PNPN structure.

[0073] In some embodiments, the material of the substrate 10 can be, but is not limited to, GaAs, the material of the anode electrode 11 can be, but is not limited to, chromium (Cr) or Au, the material of the gate electrode 17 can be, but is not limited to, Au or gold-zinc alloy (AuZn), and the cathode electrode 18 can be, but is not limited to, Au, germanium (Ge) or nickel (Ni).

[0074] In some embodiments, the first P-type semiconductor layer 12 includes a first buffer layer 120, a second buffer layer 121, and an anode layer 122; the first buffer layer 120 is disposed on the upper surface of the substrate 10, the second buffer layer 121 is disposed on the first buffer layer 120, and the anode layer 122 is disposed on the second buffer layer 121. In some embodiments, the material of the first buffer layer 120 can be, but is not limited to, GaAs, and the materials of the second buffer layer 121 and the anode layer 122 can be, but is not limited to, AlGaAs.

[0075] In some embodiments, the second N-type semiconductor layer 16 includes a blocking layer 160, a cathode layer 161, and a covering layer 162. The blocking layer 160 is disposed on the upper surface of the light-emitting layer 15, the cathode layer 161 is disposed on the blocking layer 160, and the covering layer 162 is disposed on the cathode layer 161. In some embodiments, the material of the covering layer 162 can be, but is not limited to, GaAs, and the materials of the blocking layer 160 and the cathode layer 161 can be, but is not limited to, AlGaAs.

[0076] In some embodiments, the thickness of the substrate 10 may be, but is not limited to, 300 micrometers (μm), the thickness of the first buffer layer 120 may be, but is not limited to, 100 nanometers (nm), the thickness of the second buffer layer 121 may be, but is not limited to, 250 nm, the thickness of the anode layer 122 may be, but is not limited to, 400 nm, the thickness of the first N-type semiconductor layer 13 may be, but is not limited to, 320 nm, the thickness of the second P-type semiconductor layer 14 may be, but is not limited to, 680 nm, the thickness of the barrier layer 160 may be, but is not limited to, 15 nm, the thickness of the cathode layer 161 may be, but is not limited to, 560 nm, and the thickness of the cover layer 162 may be, but is not limited to, 25 nm.

[0077] In some embodiments, the wavelength of the light emitted by the epitaxial structure 20 is from 760 nm to 820 nm.

[0078] Table 1 below shows the materials, compositions, carrier types, and dopants of each layer in an embodiment of the light-emitting semiconductor structure, but the present case is not limited thereto.

[0079] Table 1

[0080]

[0081] Table 2 below shows the peak wavelength values, thickness ranges, and carrier concentration ranges of each layer in an embodiment of the light-emitting semiconductor structure 1, but the present case is not limited thereto.

[0082] Table 2

[0083]

[0084]

[0085] Figure 3 It is a line graph comparing the light emission intensities of the light-emitting semiconductor structure 1 and the semiconductor structure of the prior art. Please refer to the figure. Structure 2 is the semiconductor structure of the prior art of a light-emitting thyristor using a PNPN structure conventionally, and structure 1 is the light-emitting semiconductor structure 1 of the epitaxial structure 20 using a PNPIN structure in the present case; from Figure 3 it can be seen that the light-emitting semiconductor structure 1 has approximately 4 times higher light emission intensity than the semiconductor structure of the prior art. In Figure 3 the embodiment, the number of the multiple quantum well layers 151 and the multiple barrier layers 152 of the light-emitting semiconductor structure 1 is 5.

[0086] Figure 4A It is a cross-sectional schematic diagram of another embodiment of the light-emitting semiconductor structure 1. Please refer to Figure 4A, in some embodiments, the light-emitting semiconductor structure 1 further includes a current flow limiting layer 19 disposed between the light-emitting layer 15 and the second P-type semiconductor layer 14, and the current flow limiting layer 19 includes a peripheral insulating region 190 and a central conductive region 191. Figure 4B is a schematic cross-sectional view of another embodiment of the light-emitting semiconductor structure 1. Please refer to Figure 4B , in some embodiments, the current flow limiting layer 19 is disposed between the light-emitting layer 15 and the second N-type semiconductor layer 16.

[0087] In some embodiments, the peripheral insulating region 190 is formed by selectively oxidizing a specific element in the material of the current flow limiting layer 19 from at least one side surface of the current flow limiting layer 19. In some embodiments, the material of the current flow limiting layer 19 may be, but is not limited to, aluminum arsenide (AlAs), and the peripheral insulating region 190 is formed by oxidizing aluminum (Al) in the current flow limiting layer 19, but the present case is not limited thereto.

[0088] Since there are more defects at the edge of the semiconductor, by providing the peripheral insulating region 190, the defects at the edge of the current flow limiting layer 19 can be eliminated, so that the current flowing through the current flow limiting layer 19 is not affected by the defects at the edge of the current flow limiting layer 19 and concentrates on the central conductive region 191, greatly improving the light-emitting efficiency of the light-emitting semiconductor structure 1.

[0089] Figure 5A is a schematic cross-sectional view of yet another embodiment of the light-emitting semiconductor structure 1. Please refer to Figure 5A , in some embodiments, the light-emitting semiconductor structure 1 further includes a highly doped P-type semiconductor layer 21 disposed between the light-emitting layer 15 and the current flow limiting layer 19. In some embodiments, the material of the highly doped P-type semiconductor layer 21 is the same as that of the second P-type semiconductor layer 14, and the doping concentration of the highly doped P-type semiconductor layer 21 may be, but is not limited to, 10 times the doping concentration of the second P-type semiconductor layer 14; for example, if the doping concentration of the second P-type semiconductor layer 14 is 10 17 (cm -3 ), the doping concentration of the highly doped P-type semiconductor layer 21 at this time is 10 18 (cm -3 ). Figure 5B is a schematic cross-sectional view of yet another embodiment of the light-emitting semiconductor structure 1. Please refer to Figure 5B , in some embodiments, the current flow limiting layer 19 is disposed between the light-emitting layer 15 and the second N-type semiconductor layer 16.

[0090] Traditionally, the driving components of a light-emitting thyristor fluid are usually arranged in the middle or lower part of its structure. For example, if the structure of the light-emitting thyristor fluid is a PNPN structure, its driving components are usually arranged in the first P-type semiconductor layer, the first N-type semiconductor layer, and the second P-type semiconductor layer from bottom to top. However, during manufacturing, the layer where the driving components of the light-emitting thyristor fluid are located is often etched during the etching process, resulting in the driving characteristics, driving voltage, IV curve, and impedance characteristics of the light-emitting thyristor fluid being affected, thereby increasing the time required for the light-emitting thyristor fluid to switch on and off at a frequency.

[0091] In the light-emitting semiconductor structure 1, since the light-emitting layer 15 and the current flow limiting layer 19 are arranged above the second P-type semiconductor layer 14 where the gate electrode 17 is located, during manufacturing, it is only necessary to etch to the second P-type semiconductor layer 14. In other words, the first P-type semiconductor layer 12 and the first N-type semiconductor layer 13 will not be etched and will not be affected by subsequent edge oxidation insulation processes. Therefore, the turn-on and turn-off frequency preparation time of the PNP transistor in the light-emitting thyristor fluid driving section composed of the first P-type semiconductor layer, the first N-type semiconductor layer, and the second P-type semiconductor layer from the wafer substrate upward will remain relatively stable and will not be affected by the etching and edge oxidation processes.

[0092] Figure 6 It is a top view of an embodiment of the light-emitting semiconductor array chip unit 3. Please refer to Figure 6 , the light-emitting semiconductor array chip unit 3 includes a transmission section 30, a parity switch section 31, and a light-emitting section 32. The light-emitting semiconductor array chip includes a plurality of light-emitting semiconductor array chip units 3, and the structure of the light-emitting semiconductor array chip is the light-emitting semiconductor structure 1. The present case does not limit the number of the plurality of light-emitting semiconductor array chip units 3 included in the light-emitting semiconductor array chip.

[0093] Figure 7 It is Figure 6 a cross-sectional view of the light-emitting semiconductor array chip unit 3 along the section line 7. Please refer to Figure 7 , in some embodiments, the cathode electrode 18 of the light-emitting section 32 is a surrounding cathode electrode. Therefore, in Figure 7In the cross-sectional view, the cathode electrode 18 of the light-emitting portion 32 has two parts (for convenience of description, hereinafter referred to as the cathode electrode 180 and the cathode electrode 181). At this time, the light-emitting region of the light-emitting portion 32 is the middle region surrounded by the surround-type cathode electrode 18. In some embodiments, the peripheral insulating region 190 of the light-emitting portion 32 is disposed directly below the cathode electrode 180 and the cathode electrode 181. In some embodiments, the side surface 1900 of the peripheral insulating region 190 disposed directly below the cathode electrode 180 and close to the center of the epitaxial structure 20 is aligned with the side surface 1800 of the cathode electrode 180 close to the center of the epitaxial structure 20, and the side surface 1901 of the peripheral insulating region 190 disposed directly below the cathode electrode 181 and close to the center of the epitaxial structure 20 is aligned with the side surface 1801 of the cathode electrode 181 close to the center of the epitaxial structure 20. At this time, the length L of the central conductive region 191 of the light-emitting portion 32 is the distance between the side surface 1800 of the cathode electrode 180 close to the center of the epitaxial structure 20 and the side surface 1801 of the cathode electrode 181 close to the center of the epitaxial structure 20.

[0094] Figures 8A to 8I FIG. is a schematic diagram of steps of an embodiment of a method for manufacturing a light-emitting semiconductor structure 1 Figure 9 FIG. is a flowchart of an embodiment of a method for manufacturing a light-emitting semiconductor structure 1. Please refer to Figures 8A to 8I and Figure 9 , first, a cathode electrode 18 is formed on the upper surface of the semiconductor base structure 22 (step S01). The semiconductor base structure 22 includes a substrate 10, a first P-type semiconductor layer 12, a first N-type semiconductor layer 13, a second P-type semiconductor layer 14, a second N-type semiconductor layer 16, a light-emitting layer 15, a current flow limiting layer 19, and a highly doped P-type semiconductor layer 21. The first P-type semiconductor layer 12 is disposed on the upper surface of the substrate 10, the first N-type semiconductor layer 13 is disposed on the first P-type semiconductor layer 12, the second P-type semiconductor layer 14 is disposed on the first N-type semiconductor layer 13, the second N-type semiconductor layer 16 is disposed on the second P-type semiconductor layer 14, the light-emitting layer 15 is disposed between the second P-type semiconductor layer 14 and the second N-type semiconductor layer 16, the current flow limiting layer 19 is disposed between the light-emitting layer 15 and the second P-type semiconductor layer 14, and the highly doped P-type semiconductor layer 21 is disposed between the light-emitting layer 15 and the current flow limiting layer 19 (as Figure 8A shown).

[0095] Next, a protective layer 70 is formed on the exposed surfaces of the cathode electrode 18 and the semiconductor base structure 22 (step S02) (as Figure 8BAs shown). Then, a first dry etching step is performed to form a first trench 101 on one side of a predetermined light-emitting portion 40 of the semiconductor base structure 22 and a second trench 102 on the other side of the predetermined light-emitting portion 40 (step S03). The first trench 101 and the second trench 102 extend from the protective layer 70 to the second P-type semiconductor layer 14 and do not penetrate the second P-type semiconductor layer 14 (as Figure 8C shown). Then, through the first trench 101 and the second trench 102, the side surfaces of the current flow restriction layer 19 are oxidized (step S04) (as Figure 8D shown).

[0096] Next, a second dry etching step is performed to form a third trench 103 on one side of a predetermined switching portion 41 of the semiconductor base structure 22 and a fourth trench 104 on the other side of the predetermined switching portion 41, and to make the second trench 102 penetrate the second P-type semiconductor layer 14 and the first N-type semiconductor layer 13 and extend to the first P-type semiconductor layer 12 and not penetrate the first P-type semiconductor layer 12 (step S05). The third trench 103 is formed between the first trench 101 and the predetermined switching portion 41. The third trench 103 and the fourth trench 104 extend from the protective layer 70 to the second P-type semiconductor layer 14 and do not penetrate the second P-type semiconductor layer 14 (as Figure 8E shown). Then, a plurality of gate electrodes 17 are formed on the bottom surfaces of the third trench 103 and the fourth trench 104 (step S06) (as Figure 8F shown).

[0097] Next, a third dry etching step is performed to form a fifth trench 105 between two adjacent gate electrodes 17 of the fourth trench 104, and to make the second trench 102 penetrate the first P-type semiconductor layer 12 and extend to the substrate 10 and not penetrate the substrate 10 (step S07). The fifth trench 105 extends from the bottom surface of the fourth trench 104 to the first P-type semiconductor layer 12 and does not penetrate the first P-type semiconductor layer 12 (as Figure 8G shown). Then, after the third dry etching step, a passivation layer 71 is integrally formed on the exposed surfaces of the semiconductor base structure 22, the cathode electrode 18 and the gate electrode 17 (step S08). Then, after depositing the passivation layer 71 on the exposed surfaces of the semiconductor base structure 22, the cathode electrode 18 and the gate electrode 17, a fourth dry etching step is performed to form a cathode opening 182 above the cathode electrode 18 and a gate opening 172 above the gate electrode 17 (step S09) (as Figure 8H shown). Finally, a wiring layer 72 is formed on the passivation layer 71 (step S10). The wiring layer 72 is electrically connected to the cathode electrode 18 through the cathode opening 182 and electrically connected to the gate electrode 17 through the gate opening 172 (as Figure 8I shown).

[0098] In some embodiments, the method of forming the cathode electrode 18 on the upper surface of the semiconductor substrate structure 22 (step S01) may be, but is not limited to, plating the metal of the cathode electrode 18 on the upper surface of the semiconductor substrate structure 22 using an electron gun. In some embodiments, the method of forming the protective layer 70 on the exposed surfaces of the cathode electrode 18 and the semiconductor substrate structure 22 (step S02) may be, but is not limited to, depositing the protective layer 70 on the exposed surfaces of the cathode electrode 18 and the semiconductor substrate structure 22 using chemical vapor deposition (CVD). In some embodiments, the material of the protective layer 70 may be, but is not limited to, silicon nitride (SiN). In some embodiments, the thickness of the protective layer 70 may be, but is not limited to, 500 angstroms. In some embodiments, the operating temperature when forming the protective layer 70 on the exposed surfaces of the cathode electrode 18 and the semiconductor substrate structure 22 using CVD may be, but is not limited to, 320 °C.

[0099] In some embodiments, the depths of the first trench 101 and the second trench 102 after performing step S03 may be, but are not limited to In other words, the depths of the first trench 101 and the second trench 102 in the semiconductor substrate structure 22 may be, but are not limited to (i.e., the depths of the first trench 101 and the second trench 102 after performing step S03 minus the thickness of the protective layer 70 ).

[0100] In some embodiments, the depths of the third trench 103 and the fourth trench 104 may be, but are not limited to In other words, the depths of the third trench 103 and the fourth trench 104 in the semiconductor substrate structure 22 may be, but are not limited to (i.e., the depths of the third trench 103 and the fourth trench 104 minus the thickness of the protective layer 70 ). In some embodiments, after performing step S05, the depth to which the second trench 102 extends may be, but is not limited to In other words, after performing the second dry etching step, the depth of the second trench 102 may be, but is not limited to (i.e., the depth of the second trench 102 after performing step S03 plus the depth to which the second trench 102 extends ). In some embodiments, after performing step S05, the depth to which the second trench 102 extends is However, the present case is not limited thereto.

[0101] In some embodiments, the method of forming a plurality of gate electrodes 17 on the bottom surfaces of the third trench 103 and the fourth trench 104 (step S06) may be, but is not limited to, depositing the metal of the gate electrodes 17 on the bottom surfaces of the third trench 103 and the fourth trench 104 by thermal evaporation deposition.

[0102] In some embodiments, the depth of the fifth trench 105 may be, but is not limited to or In some embodiments, after the third dry etching step, the method of integrally forming the passivation layer 71 on the exposed surfaces of the semiconductor base structure 22, the cathode electrode 18 and the gate electrode 17 (step S08) may be, but is not limited to, integrally forming the passivation layer 71 on the exposed surfaces of the semiconductor base structure 22, the cathode electrode 18 and the gate electrode 17 by CVD. In some embodiments, the material of the passivation layer 71 may be, but is not limited to, SiN. In some embodiments, the thickness of the passivation layer 71 may be, but is not limited to In some embodiments, the operating temperature when integrally forming the passivation layer 71 on the exposed surfaces of the semiconductor base structure 22, the cathode electrode 18 and the gate electrode 17 by CVD may be, but is not limited to, 320 °C. In some embodiments, the method of forming the wiring layer 72 on the passivation layer 71 may be, but is not limited to, plating the wiring layer 72 on the passivation layer 71 by electroplating. In some embodiments, the material of the wiring layer 72 may be, but is not limited to, gold (Au).

[0103] In summary, in some embodiments, by providing the light-emitting layer 15, the light-emitting semiconductor structure 1 having a PNPIN structure has a light-emitting intensity approximately 4 times higher than that of the semiconductor structure of the prior art. Moreover, by providing the peripheral insulation region 190 and disposing the light-emitting layer 15 and the current flow limiting layer 19 in the light-emitting semiconductor structure 1 above the second P-type semiconductor layer 14 where the gate electrode 17 is located, the light-emitting efficiency of the light-emitting semiconductor structure 1 is further improved.

[0104] Although the technical content of this case has been disclosed above with preferred embodiments, it is not intended to limit this case. Any person skilled in the art, without departing from the spirit of this case, making some modifications and refinements should be covered within the scope of this case. Therefore, the protection scope of this case shall be determined by the scope of the patent application.

Claims

1. A light-emitting semiconductor structure, characterized in that: Include: substrate; an anode electrode, disposed on the lower surface of the substrate; The epitaxial structure is disposed on the upper surface of the writing substrate and includes: A first P-type semiconductor layer is disposed on the upper surface of the substrate; A first N-type semiconductor layer, disposed on the first P-type semiconductor layer; A second P-type semiconductor layer, disposed on the first N-type semiconductor layer; A second N-type semiconductor layer, disposed on the second P-type semiconductor layer; and A light emitting layer, disposed between the second P-type semiconductor layer and the second N-type semiconductor layer; A gate electrode, disposed on the upper surface of the second P-type semiconductor layer; and The cathode electrode is disposed on the upper surface of the second N-type semiconductor layer.

2. The light-emitting semiconductor structure according to claim 1, characterized in that: The light-emitting layer is a multiple quantum well layer, and the multiple quantum well layer includes a plurality of energy well layers and a plurality of energy barrier layers stacked in groups.

3. The light-emitting semiconductor structure according to claim 2, characterized in that: The light-emitting layer is an intrinsic semiconductor layer.

4. The light emitting semiconductor structure according to claim 3, characterized in that: The number of the multiple energy well layers and the multiple energy barrier layers is 5 to 30, the material of the multiple energy well layers is gallium arsenide, and the material of the multiple energy barrier layers is aluminum gallium arsenide or indium gallium phosphide.

5. The light-emitting semiconductor structure according to claim 4, characterized in that: It also includes a current flow limiting layer, which is arranged between the light-emitting layer and the second P-type semiconductor layer or between the light-emitting layer and the second N-type semiconductor layer. The current flow limiting layer includes a peripheral insulating area and a central conductive area.

6. The light emitting semiconductor structure according to claim 5, characterized in that: The peripheral insulating region is arranged directly below the cathode electrode.

7. The light-emitting semiconductor structure according to claim 6, characterized in that: The material of the current flow limiting layer is aluminum arsenide, and the peripheral insulating region is formed by oxidizing the aluminum in the current flow limiting layer.

8. The light-emitting semiconductor structure according to claim 7, characterized in that: The first P-type semiconductor layer includes a first buffer layer, a second buffer layer and an anode layer. The first buffer layer is disposed on the upper surface of the substrate, the second buffer layer is disposed on the first buffer layer, and the anode layer is disposed on the second buffer layer.

9. The light emitting semiconductor structure according to claim 8, characterized in that: The second N-type semiconductor layer includes a blocking layer, a cathode layer and a covering layer. The blocking layer is arranged on the upper surface of the light-emitting layer, the cathode layer is arranged on the blocking layer, and the covering layer is arranged on the cathode layer.

10. A method for manufacturing a light-emitting semiconductor structure, characterized in that: Include: forming a cathode electrode on the upper surface of a semiconductor base structure, wherein the semiconductor base structure comprises a substrate, a first P-type semiconductor layer, a first N-type semiconductor layer, a second P-type semiconductor layer, a second N-type semiconductor layer, a light-emitting layer, a current flow limiting layer and a highly doped P-type semiconductor layer, wherein the first P-type semiconductor layer is disposed on the upper surface of the substrate, the first N-type semiconductor layer is disposed on the first P-type semiconductor layer, the second P-type semiconductor layer is disposed on the first N-type semiconductor layer, the second N-type semiconductor layer is disposed on the second P-type semiconductor layer, the light-emitting layer is disposed between the second P-type semiconductor layer and the second N-type semiconductor layer, the current flow limiting layer is disposed between the light-emitting layer and the second P-type semiconductor layer, and the highly doped P-type semiconductor layer is disposed between the light-emitting layer and the current flow limiting layer; forming a protective layer on the exposed surface of the cathode electrode and the semiconductor base structure; Performing a first dry etching step to form a first trench on one side of a predetermined light emitting portion of the semiconductor base structure and a second trench on the other side of the predetermined light emitting portion, wherein the first trench and the second trench extend from the protection layer to the second P-type semiconductor layer and do not penetrate the second P-type semiconductor layer; Oxidizing the side surface of the current flow limiting layer through the first trench and the second trench; Performing a second dry etching step to form a third trench on one side of a predetermined switch portion of the semiconductor base structure and a fourth trench on the other side of the predetermined switch portion, and making the second trench penetrate the second P-type semiconductor layer and the first N-type semiconductor layer and extend to the first P-type semiconductor layer without penetrating the first P-type semiconductor layer, the third trench is formed between the first trench and the predetermined switch portion, and the third trench and the fourth trench extend from the protection layer to the second P-type semiconductor layer without penetrating the second P-type semiconductor layer; forming a plurality of gate electrodes on the bottom surfaces of the third trench and the fourth trench; Performing a third dry etching step to form a fifth trench between two adjacent gate electrodes of the fourth trench, and allowing the second trench to penetrate the first P-type semiconductor layer and extend to the substrate without penetrating the substrate, and the fifth trench to extend from the bottom surface of the fourth trench to the first P-type semiconductor layer without penetrating the first P-type semiconductor layer; After the third dry etching step, a passivation layer is integrally formed on the exposed surfaces of the semiconductor base structure, the cathode electrode and the gate electrodes; After depositing the passivation layer on the exposed surfaces of the semiconductor base structure, the cathode electrode and the gate electrodes, performing a fourth dry etching step to form a cathode opening above the cathode electrode and a gate opening above the gate electrode; and A circuit layer is formed on the passivation layer, wherein the circuit layer is electrically connected to the cathode electrode through the cathode opening and is electrically connected to the gate electrode through the gate opening.

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