Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a plurality of pixel driving circuits and a plurality of light-emitting parts arranged corresponding to the pixel driving circuits, and the light-emitting parts are arranged on one sides of the pixel driving circuits. The pixel driving circuit comprises a switch transistor, a driving transistor, a first capacitor and a second capacitor, the first capacitor is connected between the switch transistor and the driving transistor, and the second capacitor is connected between the switch transistor and the first capacitor; wherein the light-emitting part comprises a bottom surface close to the pixel driving circuit, the bottom surface of the light-emitting part is not overlapped with the first capacitor in the thickness direction of the display panel, and the bottom surface of the light-emitting part is not overlapped with the second capacitor in the thickness direction of the display panel; according to the invention, the flatness of the film layer at the position of the light-emitting part can be improved, and the film thickness uniformity and yield of the light-emitting part are improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] As a new type of self-luminous display panel, an Organic Light-Emitting Diode (OLED) display panel is ultra-clear, thin, flexible, and highly designable. At the same time, it uses organic semiconductors for light emission, has a wide range of material choices, and is easy to achieve full-color display within the visible light range. In particular, the top-emitting OLED display panel, with advantages such as a large aperture ratio, is increasingly widely used in various fields.

[0003] Specifically, the OLED display panel includes a planarization layer disposed on a thin-film transistor device layer, an anode layer disposed on the planarization layer, a pixel definition layer disposed on the anode layer, and a light-emitting layer disposed on the pixel definition layer; wherein, the anode layer includes a plurality of anodes, the pixel definition layer includes a plurality of pixel openings corresponding one-to-one to the plurality of anodes, and the light-emitting layer includes light-emitting portions disposed on the anodes corresponding to the respective pixel openings.

[0004] However, due to the distribution of devices and traces in the thin-film transistor layer, the film surface within the pixel opening is uneven, which in turn affects the light-emitting effect and light-emitting efficiency of the light-emitting portions formed within the pixel openings. Summary of the Invention

[0005] Embodiments of this application provide a display panel and a display device, which can improve the flatness of the film layer at the position where the light-emitting portions are located, and improve the light-emitting effect and light-emitting efficiency of the display panel.

[0006] Embodiments of this application provide a display panel, the display panel includes a plurality of pixel driving circuits and a plurality of light-emitting portions corresponding to the plurality of pixel driving circuits, and the light-emitting portions are disposed on one side of the pixel driving circuits;

[0007] The pixel driving circuit includes a switching transistor, a driving transistor, a first capacitor, and a second capacitor, the first capacitor is connected between the switching transistor and the driving transistor, and the second capacitor is connected between the switching transistor and the first capacitor;

[0008] Wherein, the light-emitting portion includes a bottom surface close to the pixel driving circuit, and the bottom surface of the light-emitting portion does not overlap with the first capacitor in the thickness direction of the display panel, and the bottom surface of the light-emitting portion does not overlap with the second capacitor in the thickness direction of the display panel.

[0009] In an embodiment of the present application, the first capacitor includes a first electrode plate and a second electrode plate which are oppositely arranged, and the second capacitor includes a third electrode plate and a fourth electrode plate which are oppositely arranged;

[0010] The first electrode plate is connected to the switching transistor at a first node, the second electrode plate is connected to the driving transistor at a second node, and the third electrode plate is connected to the first node;

[0011] The first electrode plate, the second electrode plate, the third electrode plate, and the fourth electrode plate do not overlap with the bottom surface of the light-emitting part in the thickness direction of the display panel.

[0012] In an embodiment of the present application, the driving transistor includes a driving active part, and the display panel further includes:

[0013] A substrate;

[0014] A semiconductor layer disposed on the substrate, and the semiconductor layer includes the driving active part;

[0015] A first gate layer disposed on a side of the semiconductor layer away from the substrate, and the first gate layer includes the second electrode plate disposed on a side of the driving active part away from the substrate, and the second electrode plate partially overlaps with the driving active part in the thickness direction of the display panel.

[0016] In an embodiment of the present application, at least a part of the driving active part does not overlap with the bottom surface of the light-emitting part in the thickness direction of the display panel.

[0017] In an embodiment of the present application, the first gate layer further includes the third electrode plate;

[0018] The display panel further includes:

[0019] A second gate layer disposed on a side of the first gate layer away from the semiconductor layer, and the second gate layer includes the first electrode plate and the fourth electrode plate.

[0020] In an embodiment of the present application, a plurality of the light-emitting parts are arranged in a first direction and a second direction, the first capacitor is located between two adjacent light-emitting parts along the second direction, the second capacitor is located between two adjacent light-emitting parts along the second direction, and the first direction and the second direction intersect.

[0021] In an embodiment of the present application, the light-emitting part partially overlaps with two adjacent pixel driving circuits along the second direction.

[0022] In an embodiment of the present application, the switching transistor includes a switching active portion, and the semiconductor layer further includes the switching active portion. In the same pixel driving circuit, the switching active portion is located on a side of the second capacitor away from the driving active portion;

[0023] The display panel further includes:

[0024] A first conductive layer is disposed on a side of the semiconductor layer away from the substrate. The first conductive layer includes a first power supply signal line extending along the first direction, and the first power supply signal line is connected to the fourth electrode plate;

[0025] A second conductive layer is disposed on a side of the first conductive layer away from the semiconductor layer. The second conductive layer includes a second power supply signal line extending along the second direction and a data signal line extending along the second direction;

[0026] The data signal line is connected to the switching active portion, and the second power supply signal line is connected to the first power supply signal line.

[0027] In an embodiment of the present application, the pixel driving circuit further includes a first light-emitting control transistor connected to the driving transistor. The first light-emitting control transistor includes a first light-emitting control active portion;

[0028] The semiconductor layer includes the first light-emitting control active portion. In the same pixel driving circuit, the first light-emitting control active portion is located on a side of the driving active portion away from the switching active portion and extends along the second direction. The first light-emitting control active portion is connected between a third node and a fourth node, and the driving active portion is connected to the third node;

[0029] The second conductive layer includes an anode connection line. The anode connection line extends along the second direction. A first end of the anode connection line is connected to the fourth node, and a second end of the anode connection line does not overlap with the bottom surface of the light-emitting portion in the thickness direction of the display panel.

[0030] In an embodiment of the present application, the display panel further includes:

[0031] An anode layer is disposed on a side of the second conductive layer away from the first conductive layer. The anode layer includes a plurality of anodes corresponding to the plurality of light-emitting portions. The anodes are disposed between the corresponding light-emitting portions and the substrate, and the anodes are connected to the second ends;

[0032] A pixel definition layer is disposed on a side of the anode layer away from the second conductive layer. A plurality of pixel openings corresponding to the plurality of anodes are formed in the pixel definition layer. The light-emitting part is disposed in the pixel openings. The pixel openings do not overlap with the first capacitor in the thickness direction of the display panel, and the pixel openings do not overlap with the second capacitor in the thickness direction of the display panel.

[0033] In an embodiment of the present application, the pixel definition layer includes a plurality of first barriers arranged along the second direction and a plurality of second barriers arranged along the first direction. The first barriers extend along the first direction, the second barriers extend along the second direction, and the plurality of first barriers and the plurality of second barriers intersect to surround the plurality of pixel openings.

[0034] The first barrier is located between two adjacent pixel openings along the second direction. A positive projection of the first capacitor on the substrate is located within a positive projection of the first barrier on the substrate, and a positive projection of the second capacitor on the substrate is located within a positive projection of the first barrier on the substrate.

[0035] In an embodiment of the present application, the first power signal line is connected to the second power signal line through a first via, the anode is connected to the anode connection line through a second via, the first via partially overlaps with the first capacitor in the thickness direction of the display panel, and the second via partially overlaps with the first capacitor in the thickness direction of the display panel.

[0036] In an embodiment of the present application, the first via and the second via at least partially overlap in the first direction.

[0037] In an embodiment of the present application, the second power signal line includes a first line segment and a second line segment connected to the first line segment. The first line segment partially overlaps with the first via in the first direction, the first line segment partially overlaps with the second via in the first direction, and a width of the first line segment in the first direction is less than a width of the second line segment in the first direction.

[0038] In an embodiment of the present application, in the same pixel driving circuit, the second capacitor is located between the corresponding light-emitting part and the first capacitor.

[0039] Based on the above object of the present application, an embodiment of the present application further provides a display device, and the display device includes the display panel.

[0040] The present application provides a display panel and a display device. By setting the first capacitor and the second capacitor in the pixel driving circuit to not overlap with the bottom surface of the light-emitting portion, the film layer flatness at the position where the light-emitting portion is located can be improved, the film thickness uniformity and the yield of the light-emitting portion are improved, and thus the light-emitting effect and the light-emitting efficiency of the display panel can be improved.

[0041] Other features and advantages of the present application will be described in detail in the following specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] In order to more fully understand the present application and its beneficial effects, the following will be described in conjunction with the drawings, where the same reference numerals in the following description represent the same parts.

[0044] Figure 1 FIG. 15 is a schematic cross-sectional structure diagram of a display panel provided by an embodiment of the present application;

[0045] Figure 2 FIG. 19 is a structural diagram of a pixel driving circuit of a display panel provided by an embodiment of the present application;

[0046] Figure 3 FIG. 23 is a schematic plan view of a display panel provided by an embodiment of the present application;

[0047] Figure 4 FIG. 27 is a film stack diagram of a sub-pixel of a display panel provided by an embodiment of the present application;

[0048] Figure 5 FIG. 31 is provided by an embodiment of the present application Figure 4 structural diagram of the semiconductor layer therein;

[0049] Figure 6 FIG. 37 is provided by an embodiment of the present application Figure 4 structural diagram of the first gate layer therein;

[0050] Figure 7 FIG. 43 is provided by an embodiment of the present application Figure 4 stacked diagram of the semiconductor layer and the first gate layer therein;

[0051] Figure 8 FIG. 49 is provided by an embodiment of the present application Figure 4 structural diagram of the second gate layer therein;

[0052] Figure 9Provided by the embodiments of the present application Figure 4 Stacked diagram of the semiconductor, the first gate layer and the second gate layer therein;

[0053] Figure 10 Provided by the embodiments of the present application Figure 4 Structural diagram of the first conductive layer therein;

[0054] Figure 11 Provided by the embodiments of the present application Figure 4 Stacked diagram of the semiconductor, the first gate layer, the second gate layer and the first conductive layer therein;

[0055] Figure 12 Provided by the embodiments of the present application Figure 4 Structural diagram of the second conductive layer therein;

[0056] Figure 13 Provided by the embodiments of the present application Figure 4 Stacked diagram of the semiconductor, the first gate layer, the second gate layer, the first conductive layer and the second conductive layer therein;

[0057] Figure 14 Provided by the embodiments of the present application Figure 4 Structural diagram of the anode layer therein;

[0058] Figure 15 Provided by the embodiments of the present application Figure 2 Schematic plan view of the first pixel definition layer and the second pixel definition layer therein.

[0059] Explanation of reference numerals:

[0060] AA, display area; NA, non-display area; PX, sub-pixel; PD, pixel driving circuit; EL, light-emitting device;

[0061] 10. Substrate; 11. Gate driving circuit; 12. Bonding terminal; 100. Light-emitting part; 1001. Bottom surface; 20. Semiconductor layer; 21. First reset signal auxiliary line; 30. First gate layer; 40. Second gate layer; 41. First jumper wire; 50. First conductive layer; 51. Second jumper wire; 52. Third jumper wire; 53. Fourth jumper wire; 54. Fifth jumper wire; 55. Sixth jumper wire; 56. Seventh jumper wire; 57. Eighth jumper wire; 58. Ninth jumper wire; 59. Tenth jumper wire; 510. Eleventh jumper wire; 511. Twelfth jumper wire; 512. Thirteenth jumper wire; 60. Second conductive layer; 61. Anode connection wire; 62. Second reset signal auxiliary line; 63. Functional trace; 64. Second power signal line; 70. Anode layer; 71. Anode; 81. First gate insulating layer; 82. Second gate insulating layer; 83. Interlayer dielectric layer; 84. First planarization layer; 85. Second planarization layer; 86. Pixel definition layer; 861. First barrier wall; 862. Second barrier wall; 860. Pixel opening; 91. First via; 92. Second via;

[0062] T1. Switching transistor; T2. Driving transistor; T3. Compensation transistor; T4. First reset transistor; T5. Second reset transistor; T6. Third reset transistor; T7. Fourth reset transistor; T8. First light-emitting control transistor; T9. Second light-emitting control transistor; C1. First capacitor; C2. Second capacitor; C3. Third capacitor; C4. Fourth capacitor; C5. Fifth capacitor; C6. Sixth capacitor; SCAN1. First control signal line; SCAN2. Second control signal line; SCAN3. Third control signal line; SCAN4. Fourth control signal line; EM1. First light-emitting control signal line; EM2. Second light-emitting control signal line; DATA. Data signal line; DATA1. First data signal line; DATA2. Second data signal line; DATA3. Third data signal line; VI1. First reset signal line; VI2. Second reset signal line; VI3. Third reset signal line; VI4. Fourth reset signal line; VDD. First power signal line; VSS. Third power signal line; N1. First node; N2. Second node; N3. Third node; N4. Fourth node; N5. Fifth node;

[0063] C11. First electrode plate; C12. Second electrode plate; C21. Third electrode plate; C22. Fourth electrode plate; C31. Fifth electrode plate; C41. Sixth electrode plate; C51. Seventh electrode plate; C61. Eighth electrode plate;

[0064] T1A, switch active part; T2A, driving active part; T3A, compensation active part; T4A, first reset active part; T5A, second reset active part; T6A, third reset active part; T7A, fourth reset active part; T8A, first light-emitting control active part; T9A, second light-emitting control active part;

[0065] T1G, switch gate; T2G, driving gate; T3G, compensation gate; T4G, first reset gate; T5G, second reset gate; T6G, third reset gate; T7G, fourth reset gate; T8G, first light-emitting control gate; T9G, second light-emitting control gate;

[0066] T1D, switch drain; T2D, driving drain; T3D, compensation drain; T4D, first reset drain; T5D, second reset drain; T6D, third reset drain; T7D, fourth reset drain; T8D, first light-emitting control drain; T9D, second light-emitting control drain;

[0067] T1S, switch source; T2S, driving source; T3S, compensation source; T4S, first reset source; T5S, second reset source; T6S, third reset source; T7S, fourth reset source; T8S, first light-emitting control source; T9S, second light-emitting control source. Detailed implementation manners

[0068] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0069] Please refer to Figure 1 and Figure 2 , an embodiment of the present application provides a display panel, the display panel includes a plurality of pixel driving circuits PD and a plurality of light-emitting parts 100 correspondingly arranged with the plurality of pixel driving circuits PD, and the light-emitting parts 100 are arranged on one side of the pixel driving circuits PD.

[0070] The pixel driving circuit PD includes a switching transistor T1, a driving transistor T2, a first capacitor C1, and a second capacitor C2. The first capacitor C1 is connected between the switching transistor T1 and the driving transistor T2, and the second capacitor C2 is connected between the switching transistor T1 and the first capacitor C1.

[0071] Among them, the light-emitting part 100 includes a bottom surface 1001 close to the pixel driving circuit PD, and the bottom surface 1001 of the light-emitting part 100 does not overlap with the first capacitor C1 in the thickness direction of the display panel, and the bottom surface 1001 of the light-emitting part 100 does not overlap with the second capacitor C2 in the thickness direction of the display panel.

[0072] In the implementation and application process, in the embodiment of the present application, by setting the first capacitor C1 and the second capacitor C2 in the pixel driving circuit PD not to overlap with the bottom surface 1001 of the light-emitting part 100, the film layer flatness at the position where the light-emitting part 100 is located can be improved, the film thickness uniformity and yield of the light-emitting part 100 are improved, and thus the light-emitting effect and light-emitting efficiency of the display panel can be improved.

[0073] Specifically, please refer to Figure 3 , the display panel may include a display area AA and a non-display area NA adjacent to the display area AA. The non-display area NA may be arranged around the display area AA, and the non-display area NA may be the border area of the display panel.

[0074] In some embodiments, the display panel further includes a plurality of sub-pixels PX disposed in the display area AA and used to implement the display function of the display panel, and a gate driving circuit 11 disposed in the non-display area NA. Among them, the gate driving circuit 11 is used to input a control signal into the sub-pixels PX in the display area AA.

[0075] In some embodiments, a pixel driving circuit PD is provided in each sub-pixel PX, and the gate driving circuit 11 is used to input a gate control signal into the transistors in the pixel driving circuit PD.

[0076] In some embodiments, a bonding terminal 12 is provided on the lower side of the display area AA. The display panel further includes a data signal line DATA extending into the display area AA and connected to the pixel driving circuit PD; the bonding terminal 12 can be connected to an external circuit, and the bonding terminal 12 transmits the signal input by the external circuit to the data signal line DATA, so as to drive the display panel to display an image. For example, the bonding terminal 12 can be bonded and connected to a chip or a chip-on-film, etc., for providing power supply and driving signals for the display panel.

[0077] In some embodiments, the gate driving circuit 11 is disposed in the non-display area NA, and the gate driving circuit 11 can be disposed on both sides of the display area AA; the gate driving circuit 11 may include a plurality of cascaded gate driving units, and the structure of the gate driving unit is not specifically limited in the present application.

[0078] In some embodiments, a plurality of the pixel driving circuits PD may be arranged in an array within the display area AA. The pixel driving circuits PD may be pixel driving circuits PD such as 7T1C, 7T2C, 8T1C, 8T2C, 8T3C, 8T4C, 9T2C, 9T6C, etc. In the following embodiments, the 9T6C pixel driving circuit PD will be taken as an example for illustration.

[0079] Please refer to Figure 2 , the pixel driving circuit PD includes a switching transistor T1, a driving transistor T2, a compensating transistor T3, a first reset transistor T4, a second reset transistor T5, a third reset transistor T6, a fourth reset transistor T7, a first light-emitting control transistor T8, a second light-emitting control transistor T9, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The display panel further includes a light-emitting device EL connected to the pixel driving circuit PD.

[0080] Furthermore, the display panel further includes a plurality of signal lines, and the plurality of signal lines are used to connect the pixel driving circuit PD and transmit signals to the pixel driving circuit PD; in some embodiments, the signal lines include a first control signal line SCAN1, a second control signal line SCAN2, a third control signal line SCAN3, a fourth control signal line SCAN4, a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, a data signal line DATA, a first reset signal line VI1, a second reset signal line VI2, a third reset signal line VI3, a fourth reset signal line VI4, a first power supply signal line VDD, a second power supply signal line 64, and a third power supply signal line VSS.

[0081] Wherein, the drain of the switching transistor T1 is connected to the data signal line DATA to receive a data signal Data, the source of the switching transistor T1 is connected to a first node N1, and the gate of the switching transistor T1 is connected to the first control signal line SCAN1 to receive a first control signal Scan1.

[0082] The drain of the driving transistor T2 is connected to a fifth node N5, the source of the driving transistor T2 is connected to a third node N3, and the gate of the driving transistor T2 is connected to a second node N2.

[0083] The drain of the compensating transistor T3 is connected to the second node N2, the source of the compensating transistor T3 is connected to the third node N3, and the gate of the compensating transistor T3 is connected to the second control signal line SCAN2 to receive a second control signal Scan2.

[0084] The drain of the first reset transistor T4 is connected to a first reset signal line VI1 to receive a first reset signal Vi1. The source of the first reset transistor T4 is connected to the second node N2. The gate of the first reset transistor T4 is connected to a third control signal line SCAN3 to receive a third control signal Scan3.

[0085] The drain of the second reset transistor T5 is connected to a second reset signal line VI2 to receive a second reset signal Vi2. The source of the second reset transistor T5 is connected to the fourth node N4. The gate of the second reset transistor T5 is connected to a fourth control signal line SCAN4 to receive a fourth control signal Scan4.

[0086] The drain of the third reset transistor T6 is connected to a third reset signal line VI3 to receive a third reset signal Vi3. The source of the third reset transistor T6 is connected to the fifth node N5. The gate of the third reset transistor T6 is connected to the fourth control signal line SCAN4 to receive a fourth control signal Scan4.

[0087] The drain of the fourth reset transistor T7 is connected to a fourth reset signal line VI4 to receive a fourth reset signal Vi4. The source of the fourth reset transistor T7 is connected to the first node N1. The gate of the fourth reset transistor T7 is connected to the second control signal line SCAN2 to receive a second control signal Scan2.

[0088] The drain of the first light-emitting control transistor T8 is connected to the third node N3. The source of the first light-emitting control transistor T8 is connected to the fourth node N4. The gate of the first light-emitting control transistor T8 is connected to a first light-emitting control signal line EM1 to receive a first light-emitting control signal Em1.

[0089] The drain of the second light-emitting control transistor T9 is connected to a first power supply signal line VDD to receive a first power supply signal Vdd. The source of the second light-emitting control transistor T9 is connected to the fifth node N5. The gate of the second light-emitting control transistor T9 is connected to a second light-emitting control signal line EM2 to receive a second light-emitting control signal Em2.

[0090] The display panel further includes a light-emitting device EL connected to the pixel driving circuit PD. One end of the light-emitting device EL is connected to the fourth node N4, and the other end of the light-emitting device EL is connected to a third power supply signal line VSS to receive a third power supply signal Vss.

[0091] One plate of the first capacitor C1 is connected to the first node N1, and the other plate of the first capacitor C1 is connected to the second node N2; one plate of the second capacitor C2 is connected to the first node N1, and the other plate of the second capacitor C2 is connected to the first power supply signal line VDD; the third capacitor C3 and the fourth capacitor C4 are connected in series between the active part of the switching transistor T1 and the active part of the fourth reset transistor T7; one plate of the fifth capacitor C5 is connected to the active part of the first reset transistor T4, and the other plate of the fifth capacitor C5 is connected to the first power supply signal line VDD; one plate of the sixth capacitor C6 is connected to the active part of the compensation transistor T3, and the other plate of the sixth capacitor C6 is connected to the first power supply signal line VDD.

[0092] It should be noted that in the embodiment of the present application, the first capacitor C1 can couple a signal to the second node N2, that is, to the gate of the driving transistor T2; and the first capacitor C1 and the second capacitor C2 can stabilize the potentials of the first node N1 and the second node N2, reducing the probability of signal instability and signal flicker; the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 are respectively used to prevent the switching transistor T1, the fourth reset transistor T7, the first reset transistor T4, and the compensation transistor T3 from leaking electricity, and can also reduce the probability of signal flicker.

[0093] For the switching transistors T1 in different sub-pixels PX, the data signal lines DATA they are connected to are different. In the present application, only one of them is taken as an example for illustration.

[0094] In this embodiment, the first power supply signal line VDD is used to provide a constant high level to the pixel driving circuit PD, and the third power supply signal line VSS is used to provide a constant low level to the pixel driving circuit PD.

[0095] In this embodiment, the switching transistor T1, the driving transistor T2, the compensation transistor T3, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, the fourth reset transistor T7, the first light-emitting control transistor T8, and the second light-emitting control transistor T9 are each independently selected from one of a P-type transistor and an N-type transistor; in the present application, the switching transistor T1, the driving transistor T2, the compensation transistor T3, the first reset transistor T4, the second reset transistor T5, the third reset transistor T6, the fourth reset transistor T7, the first light-emitting control transistor T8, and the second light-emitting control transistor T9 are all P-type transistors as an example for illustration.

[0096] In this embodiment, the source electrode is only the output terminal of the present application, and the drain electrode is only the input terminal of the present application. They only have a difference in naming.

[0097] Next, for the structure of Figure 1 the film layer structure of the pixel circuit of the present application will be described.

[0098] The display area AA and the non-display area NA of the display panel may be provided with a substrate 10 and an array driving layer disposed on the substrate 10; within the display area AA, the display panel may further include a pixel definition layer 86 disposed on the array driving layer and a light-emitting portion 100 disposed on the pixel definition layer 86. Next, the film layer structure within the display area AA will be mainly described.

[0099] In some embodiments, the substrate 10 supports each layer disposed on the substrate 10. When the display panel is a bottom-emitting light-emitting display device or a double-sided emitting light-emitting display device, a transparent substrate may be used. When the display panel is a top-emitting light-emitting display device, a semi-transparent or opaque substrate and a transparent substrate may be used.

[0100] In this embodiment, the substrate 10 is used to support each film layer disposed on the substrate 10, and the substrate 10 may be made of an insulating material such as glass, quartz, or polymer resin. The substrate 10 may be a rigid substrate or a flexible substrate that can be bent, folded, curled, etc. Examples of flexible materials for the flexible substrate include polyimide (PI), but are not limited to polyimide (PI).

[0101] In this embodiment, the substrate 10 may include a first flexible substrate, a first barrier layer, a second flexible substrate, and a second barrier layer stacked. The first flexible substrate and the second flexible substrate may be formed of the same material such as polyimide, and the first barrier layer and the second barrier layer may be formed of an inorganic material including at least one of SiOx and SiNx, for example.

[0102] Please refer to Figure 1 , the array driving layer may include a plurality of thin film transistors. The thin film transistors may be of an etch-stop type, a back-channel etch type, or may be classified into a bottom-gate thin film transistor, a top-gate thin film transistor, etc. according to the position of the gate and the active portion, or may be classified into an N-type thin film transistor and a P-type thin film transistor according to the performance of the thin film transistor; wherein, Figure 1 the thin film transistors in Figure 2 do not represent the structure diagram of any transistor in

[0103] Please refer to Figure 1, the array driving layer may include a semiconductor layer 20 disposed on the substrate 10, a first gate insulating layer 81 disposed on the semiconductor layer 20, a first gate layer 30 disposed on the first gate insulating layer, a second gate insulating layer 82 disposed on the first gate layer 30, a second gate layer 40 disposed on the second gate insulating layer, an interlayer dielectric layer 83 disposed on the second gate layer 40, a first conductive layer 50 disposed on the interlayer dielectric layer 83, a first planarization layer 84 disposed on the first conductive layer 50, a second conductive layer 60 disposed on the first planarization layer 84, a second planarization layer 85 disposed on the second conductive layer 60, a light-emitting device EL disposed on the second planarization layer 85, and a pixel definition layer 86.

[0104] In some embodiments, the material of the semiconductor layer 20 may be a silicon semiconductor. For example, the material of the semiconductor layer 20 in this application may be low-temperature polycrystalline silicon.

[0105] In some embodiments, the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer 83 are respectively disposed on corresponding metal layers or the semiconductor layer 20, and are separated by different layers of metal layers or the semiconductor layer 20; and the materials of the first gate insulating layer, the second gate insulating layer, and the interlayer dielectric layer 83 may be inorganic substances combined with silicon oxynitride or organic materials with flatness.

[0106] In some embodiments, the first gate layer 30 and the second gate layer 40 are respectively disposed on corresponding insulating layers, and the materials of the first gate layer 30 and the second gate layer 40 may be copper, molybdenum, or molybdenum-titanium alloy, etc.

[0107] In some embodiments, the materials of the first conductive layer 50 and the second conductive layer 60 may be copper, molybdenum, molybdenum-titanium alloy, or a three-layer metal such as titanium-aluminum-titanium, etc.

[0108] In some embodiments, the first planarization layer 84 and the second planarization layer 85 are laid as a whole layer to ensure the flatness of the film layer of the array driving layer, and the materials of the first planarization layer 84 and the second planarization layer 85 may be inorganic substances combined with silicon oxynitride or organic materials with flatness.

[0109] It should be noted that the pixel definition layer 86 is disposed on the planarization layer and is provided with a plurality of pixel openings 860. The light-emitting device EL may include an anode 71, a light-emitting portion 100, and a cathode which are stacked. The anode 71 is located within the pixel opening 860, the light-emitting portion 100 is disposed within the pixel opening 860 and on the anode 71, and the cathode is located on the light-emitting portion 100.

[0110] It can be understood that each thin film transistor and signal line in the pixel driving circuit PD can be located in the array driving layer. For example, the active part of each thin film transistor can be located in the semiconductor layer 20, and other electrodes of each thin film transistor or the connected signal lines can be located in the first gate layer 30, the second gate layer 40, the first conductive layer 50 or the second conductive layer 60.

[0111] In the embodiment of the present application, since the areas of the first capacitor C1 and the second capacitor C2 are relatively large, the influence on the flatness of the film layer in the display panel is relatively large. Therefore, in the embodiment of the present application, the bottom surface 1001 of the light emitting part 100 close to the pixel driving circuit PD is set not to overlap with the first capacitor C1 in the thickness direction of the display panel, and the bottom surface 1001 of the light emitting part 100 is also set not to overlap with the second capacitor C2 in the thickness direction of the display panel. The bottom surface 1001 is the surface of the light emitting part 100 close to the substrate 10 and is the surface of the light emitting part 100 close to the array driving layer. Furthermore, the embodiment of the present application can improve the flatness of the film layer at the position of the light emitting part 100, improve the film thickness uniformity and yield of the light emitting part 100, and further improve the light emitting effect and light emitting efficiency of the display panel.

[0112] It should be noted that the bottom surface 1001 of the light emitting part 100 is the surface of the light emitting part 100 close to the substrate 10.

[0113] Please refer to Figure 4 , the display panel may include a plurality of pixel driving circuits PD arranged along the first direction X and the second direction Y, and the first direction and the second direction intersect; in some embodiments, the first direction X and the second direction Y are perpendicular to each other.

[0114] Among them, the display panel includes a plurality of repeating units, and Figure 4 as shown is one of the repeating units. Each repeating unit includes three pixel driving circuits PD arranged along the first direction X and three data signal lines DATA connected to the three pixel driving circuits PD in the repeating unit.

[0115] In the following embodiments, the technical solution of the present application will be described by taking the structure of each film layer in the pixel driving circuit PD in one repeating unit as an example.

[0116] Please refer to Figure 5, the semiconductor layer 20 includes a switching active portion T1A of the switching transistor T1, a driving active portion T2A of the driving transistor T2, a compensating active portion T3A of the compensating transistor T3, a first reset active portion T4A of the first reset transistor T4, a second reset active portion T5A of the second reset transistor T5, a third reset active portion T6A of the third reset transistor T6, a fourth reset active portion T7A of the fourth reset transistor T7, a first light emission control active portion T8A of the first light emission control transistor T8, a second light emission control active portion T9A of the second light emission control transistor T9, and a first reset signal auxiliary line 21.

[0117] Among them, the switching active portion T1A is connected to the fourth reset active portion T7A and is spaced apart from other active portions; the first reset signal auxiliary line 21 extends along the first direction X and connects the fourth reset active portions T7A in a plurality of the pixel driving circuits PD arranged along the first direction X together.

[0118] Among them, the switching active portion T1A is in an n shape, and one end of the switching active portion T1A is used to be connected to the data signal line DATA, and the other end of the switching active portion T1A is connected to the fourth reset active portion T7A; the fourth reset active portion T7A is in an n shape, one end of the fourth reset active portion T7A is connected to the switching active portion T1A, and the other end of the fourth reset active portion T7A is connected to the first reset signal auxiliary line 21; the switching active portion T1A and the fourth reset active portion T7A are connected at the first node N1.

[0119] The driving active portion T2A, the compensating active portion T3A, the first reset active portion T4A, the second reset active portion T5A, the third reset active portion T6A, the first light emission control active portion T8A, and the second light emission control active portion T9A are connected, and the third reset active portions T6A in a plurality of the pixel driving circuits PD arranged along the first direction X are connected together.

[0120] Among them, the driving active part T2A is in an n shape. One end of the driving active part T2A is connected to the third node N3, and the other end of the driving active part T2A is connected to the fifth node N5. One end of the compensating active part T3A is connected to the second node N2, and the other end of the compensating active part T3A is connected to the third node N3. One end of the first reset active part T4A is connected to the second node N2, and the other end of the first reset active part T4A is for signal input. One end of the first light-emitting control active part T8A is connected to the third node N3, and the other end of the first light-emitting control active part T8A is connected to the fourth node N4. One end of the second reset active part T5A is connected to the fourth node N4, and the other end of the second reset active part T5A is for signal input. One end of the second light-emitting control active part T9A is connected to the fifth node N5, and the other end of the second light-emitting control active part T9A is for signal input. One end of the third reset active part T6A is connected to the fifth node N5, and the other end of the third reset active part T6A is for signal input.

[0121] Further, the compensating active part T3A, the first reset active part T4A, the second reset active part T5A, the third reset active part T6A, the first light-emitting control active part T8A, and the second light-emitting control active part T9A are all located on the side of the driving active part T2A away from the switching active part T1A.

[0122] In some embodiments, in the same pixel driving circuit PD, the first light-emitting control active part T8A is located on the side of the driving active part T2A away from the switching active part T1A and extends along the second direction Y.

[0123] Please refer to Figure 6 and Figure 7 , the first gate layer 30 is disposed on the side of the semiconductor layer 20 away from the substrate 10, and the first gate layer 30 includes the gates of the transistors in the pixel driving circuit PD.

[0124] Specifically, the first gate layer 30 includes the switching gate T1G of the switching transistor T1, the driving gate T2G of the driving transistor T2, the compensating gate T3G of the compensating transistor T3, the first reset gate T4G of the first reset transistor T4, the second reset gate T5G of the second reset transistor T5, the third reset gate T6G of the third reset transistor T6, the fourth reset gate T7G of the fourth reset transistor T7, the first light-emitting control gate T8G of the first light-emitting control transistor T8, the second light-emitting control gate T9G of the second light-emitting control transistor T9, as well as the second electrode plate C12 of the first capacitor C1 and the third electrode plate C21 of the second capacitor C2.

[0125] Among them, the second electrode plate C12 of the first capacitor C1 is multiplexed as the driving gate T2G.

[0126] Please refer to Figure 5 , Figure 6 and Figure 7 . There are two overlapping positions between the switching gate T1G and the switching active part T1A, so that the switching transistor T1 can form a double-gate structure; there are two overlapping positions between the fourth reset gate T7G and the fourth reset active part T7A, so that the fourth reset transistor T7 can form a double-gate structure; there are two overlapping positions between the compensating gate T3G and the compensating active part T3A, which can make the compensating transistor T3 form a double-gate structure; there are two overlapping positions between the first reset transistor T4 and the first reset active part T4A, so that the first reset transistor T4 can form a double-gate structure. It can be understood that the thin-film transistors with the above double-gate structure can effectively reduce the leakage current and improve the electrical properties of the thin-film transistors.

[0127] In addition, the driving gate T2G is disposed on the side of the driving active part T2A away from the substrate 10, the driving gate T2G overlaps with the driving active part T2A, the second reset gate T5G overlaps with the second reset active part T5A, the third reset gate T6G overlaps with the third reset active part T6A, the first light-emitting control gate T8G overlaps with the first light-emitting control active part T8A, and the second light-emitting control gate T9G overlaps with the second light-emitting control active part T9A.

[0128] It should be noted that the fourth control signal line SCAN4 extends along the first direction X and simultaneously overlaps with the second reset active part T5A and the third reset active part T6A to be multiplexed as the second reset gate T5G and the third reset gate T6G.

[0129] Further, the opposite end of the switching active part T1A away from the first node N1 can be multiplexed as the switching drain T1D, and the end of the switching active part T1A close to the first node N1 can be multiplexed as the switching source T1S; the opposite end of the fourth reset active part T7A away from the first node N1 can be multiplexed as the fourth reset drain T7D, and the end of the fourth reset active part T7A close to the first node N1 can be multiplexed as the fourth reset source T7S.

[0130] The end of the driving active part T2A close to the fifth node N5 can be multiplexed as the driving drain T2D, and the end of the driving active part T2A close to the third node N3 can be multiplexed as the driving source T2S; the end of the compensating active part T3A close to the second node N2 can be multiplexed as the compensating drain T3D, and the end of the compensating active part T3A close to the third node N3 can be multiplexed as the compensating source T3S; the end of the first reset active part T4A close to the second node N2 can be multiplexed as the first reset source T4S, and the end of the first reset active part T4A away from the second node N2 can be multiplexed as the first reset drain T4D; the end of the first light-emitting control active part T8A close to the third node N3 can be multiplexed as the first light-emitting control drain T8D, and the end of the first light-emitting control active part T8A close to the fourth node N4 can be multiplexed as the first light-emitting control source T8S; the end of the second reset active part T5A close to the fourth node N4 can be multiplexed as the second reset drain T5D, and the opposite end of the second reset active part T5A away from the fourth node N4 can be multiplexed as the second reset source T5S; the end of the second light-emitting control active part T9A close to the fifth node N5 can be multiplexed as the second light-emitting control source T9S, and the opposite end of the second light-emitting control active part T9A away from the fifth node N5 can be multiplexed as the second light-emitting control drain T9D; the end of the third reset active part T6A close to the fifth node N5 can be multiplexed as the third reset source T6S, and the opposite end of the third reset active part T6A away from the fifth node N5 can be multiplexed as the third reset drain T6D.

[0131] Please refer to Figure 8 and Figure 9 The second gate layer 40 is disposed on a side of the first gate layer 30 away from the semiconductor layer 20, and the second gate layer 40 includes a plurality of signal lines and capacitor plates.

[0132] Specifically, the second gate layer 40 includes the first electrode plate C11 of the first capacitor C1, the fourth electrode plate C22 of the second capacitor C2, the fifth electrode plate C31, the sixth electrode plate C41, the seventh electrode plate C51, and the eighth electrode plate C61, the first reset signal line VI1, the third reset signal line VI3, the first light-emitting control signal line EM1, the second light-emitting control signal line EM2, and the first jumper wire 41; and the fifth electrode plate C31 and the sixth electrode plate C41 are both connected to the third reset signal line VI3, and the seventh electrode plate C51 and the eighth electrode plate C61 are both connected to the fourth electrode plate C22.

[0133] Wherein, the first electrode plate C11 and the second electrode plate C12 are oppositely arranged to form the first capacitor C1, the fourth electrode plate C22 and the third electrode plate C21 are oppositely arranged to form the second capacitor C2, the fifth electrode plate C31 and the switching active part T1A are oppositely arranged to form the third capacitor C3, the sixth electrode plate C41 and the fourth reset active part T7A are oppositely arranged to form the fourth capacitor C4, the seventh electrode plate C51 and the first reset active part T4A are oppositely arranged to form the fifth capacitor C5, and the eighth electrode plate C61 and the compensation active part T3A are oppositely arranged to form the sixth capacitor C6.

[0134] The first light-emitting control signal line EM1 is used for electrically connecting to the first light-emitting control gate T8G to transmit signals, the second light-emitting control signal line EM2 is used for electrically connecting to the second light-emitting control gate T9G to transmit signals, the first reset signal line VI1 is used for electrically connecting to the first reset drain T4D, and the third reset signal line VI3 is used for electrically connecting to the third reset drain T6D; the specific connection relationship can be seen in the subsequent embodiments.

[0135] Please refer to Figure 10 and Figure 11 , the first conductive layer 50 is disposed on a side of the second gate layer 40 away from the first gate layer 30, and the first conductive layer 50 includes the first control signal line SCAN1, the second control signal line SCAN2, the third control signal line SCAN3, the second reset signal line VI2, the fourth reset signal line VI4, the first power supply signal line VDD, the second jumper wire 51, the third jumper wire 52, the fourth jumper wire 53, the fifth jumper wire 54, the sixth jumper wire 55, the seventh jumper wire 56, the eighth jumper wire 57, the ninth jumper wire 58, the tenth jumper wire 59, the eleventh jumper wire 510, the twelfth jumper wire 511, and the thirteenth jumper wire 512.

[0136] Wherein, please combine Figure 6 , Figure 10 andFigure 11 The first power supply signal line VDD extends along the first direction X and is connected to the fourth electrode plate C22.

[0137] The switch gate T1G is connected to the first control signal line SCAN1, and the switch active part T1A is connected to the second jumper wire 51.

[0138] The fourth reset gate T7G is connected to the second control signal line SCAN2, and the fourth reset active part T7A is connected to the first reset signal auxiliary line 21.

[0139] The third jumper wire 52 is connected between the fourth reset active part T7A and the first reset signal auxiliary line 21;

[0140] One end of the fourth jumper wire 53 is connected to the first node N1, and the other end of the fourth jumper wire 53 is connected to the third electrode plate C21 and the first electrode plate C11; the fifth jumper wire 54 is connected between the second node N2 and the second electrode plate C12; the sixth jumper wire 55 is connected between the second light emission control signal line EM2 and the second light emission control gate T9G; the seventh jumper wire 56 is connected between the first reset signal line VI1 and the first reset active part T4A; the eighth jumper wire 57 is connected to the second light emission control active part T9A; the ninth jumper wire 58 is connected between the first light emission control signal line EM1 and the first light emission control gate T8G; the tenth jumper wire 59 is connected to the fourth node N4; the eleventh jumper wire 510 is connected between the third reset active part T6A and the first jumper wire 41, and the third jumper wire 52 is connected to Figure 11 the third reset signal line VI3 in another repeating unit in the lower middle; both the second jumper wire 51 and the thirteenth jumper wire 512 are connected between the second reset active part T5A and the second reset signal line VI2.

[0141] Please refer to Figure 12 and Figure 13 As shown in and, the second conductive layer 60 includes a data signal line DATA extending along the second direction Y, a second power supply signal line 64 extending along the second direction Y, an anode connection line 61 extending along the second direction Y, a second reset signal auxiliary line 62 extending along the second direction Y, and a functional trace 63 extending along the second direction Y.

[0142] The data signal line DATA is connected to the second jumper wire 51, and further the data signal line DATA is connected to the switch active part T1A through the second jumper wire 51.

[0143] In some embodiments, in a repeating unit, the data signal line DATA may include a first data signal line DATA1, a second data signal line DATA2, and a third data signal line DATA3, and the first data signal line DATA1, the second data signal line DATA2, and the third data signal line DATA3 are respectively connected to one of the pixel driving circuits PD. For example, the light-emitting device EL corresponding to the pixel driving circuit PD connected to the first data signal line DATA1 emits red light, the light-emitting device EL corresponding to the pixel driving circuit PD connected to the second data signal line DATA2 emits green light, and the light-emitting device corresponding to the pixel driving circuit PD connected to the third data signal line DATA3 emits blue light.

[0144] The second reset signal auxiliary line 62 is connected to the third transfer line 52. Further, the second reset signal auxiliary line 62 is connected to the fourth reset active part T7A and the first reset signal auxiliary line 21 through the third transfer line 52. The first reset signal auxiliary lines 21 extending along the first direction X among the plurality of pixel driving circuits PD are connected to the second reset signal auxiliary lines 62 extending along the second direction Y to form a network, which can reduce the impedance while realizing signal transmission.

[0145] The second power supply signal line 64 is connected to the first power supply signal line VDD, and can also be used to transmit a high-level potential. The first power supply signal lines VDD extending along the first direction X among the plurality of pixel driving circuits PD are connected to the second power supply signal lines 64 extending along the second direction Y to form a network, which can reduce the impedance while realizing signal transmission.

[0146] The anode connection line 61 extends along the second direction Y. The first end of the anode connection line 61 is connected to the fourth node N4. The anode connection line 61 further includes a second end opposite to the first end, and the second end is used to connect to the anode 71.

[0147] The functional trace 63 extends along the second direction Y, and one functional trace 63 can be provided in each repeating unit.

[0148] In some embodiments, the functional trace 63 can extend into the non-display area NA and be connected to a constant low-level signal located in the non-display area NA to form an auxiliary cathode line, reducing the resistance of the cathode in the display panel.

[0149] In some embodiments, the functional trace 63 can be used to connect at least one of the first reset signal line VI1, the second reset signal line VI2, and the third reset signal line VI3 extending along the first direction X to form a mesh trace structure, reducing the trace resistance.

[0150] Please refer to Figure 14 , the anode layer 70 is disposed on a side of the second flat layer 85 away from the first flat layer 84. The anode layer 70 includes a plurality of anodes 71, and the anodes 71 are connected to the second ends of the anode connection lines 61, that is, the anodes 71 are connected to the first light-emitting control active part T8A through the anode connection lines 61.

[0151] In some embodiments, the first power supply signal line VDD is connected to the second power supply signal line 64 through a first via 91, and the anode 71 is connected to the anode connection line 61 through a second via 92. The first via 91 and the first capacitor C1 partially overlap in the thickness direction of the display panel, and the second via 92 and the first capacitor C1 partially overlap in the thickness direction of the display panel.

[0152] Furthermore, the first via 91 and the second via 92 at least partially overlap in the first direction X.

[0153] In some embodiments, the second power supply signal line 64 includes a first line segment 641 and a second line segment 642 connected to the first line segment 641, and both the first line segment 641 and the second line segment 642 extend along the second direction Y. The first line segment 641 and the first via 91 partially overlap in the first direction X, the first line segment 641 and the second via 92 partially overlap in the first direction X, and the width W1 of the first line segment 641 in the first direction X is smaller than the width W2 of the second line segment in the first direction. Since the extension direction of the second power supply signal line 64 interferes with the position of the connection via of the anode 71, therefore, in the embodiments of the present application, the width of the second power supply signal line 64 corresponding to the position of the second via 92 is reduced to avoid the second via 92, reducing the probability of interference and signal crosstalk between the anode 71, the anode connection line 61, and the second power supply signal line 64.

[0154] Please refer to Figure 1 and Figure 15 , the pixel definition layer 86 is disposed on a side of the anode layer 70 away from the second conductive layer 60. A plurality of pixel openings 860 are formed in the pixel definition layer 86, and each pixel opening 860 exposes a partial surface of the corresponding anode 71.

[0155] A plurality of the light-emitting portions 100 are disposed corresponding to a plurality of the pixel openings 860. One of the light-emitting portions 100 is disposed within a corresponding one of the pixel openings 860 and is located on a side of the anode 71 away from the substrate 10.

[0156] The light-emitting portion 100 includes a bottom surface 1001 close to one side of the pixel driving circuit PX. The second end of the anode connection line 61 does not overlap with the bottom surface 1001 of the light-emitting portion 100 in a thickness direction of the display panel, and is connected to the anode 71. In an embodiment of the present application, by setting a connection hole of the anode 71 not to overlap with the bottom surface 1001 of the light-emitting portion 100, the film layer flatness of a region where the light-emitting portion 100 is located can be further improved, and the film thickness uniformity and light-emitting efficiency of the light-emitting portion 100 can be improved.

[0157] In some embodiments, the pixel opening 860 does not overlap with the first capacitor C1 in a thickness direction of the display panel, and the pixel opening 860 does not overlap with the second capacitor C2 in the thickness direction of the display panel. Thereby, it is possible to avoid the first capacitor C1 and the second capacitor C2 from affecting the film layer flatness within the pixel opening 860, which is beneficial to improving the film layer flatness within the pixel opening 860.

[0158] Further, in some embodiments, the pixel defining layer 86 includes a plurality of first barrier walls 861 arranged along the second direction Y and a plurality of second barrier walls 862 arranged along the first direction X. The first barrier walls 861 extend along the first direction X, the second barrier walls 862 extend along the second direction Y, and the plurality of first barrier walls 861 intersect with the plurality of second barrier walls 862 to surround the plurality of pixel openings 860. Among them, the first barrier walls 861 are located between two adjacent pixel openings 860 along the second direction Y, and a positive projection of the first capacitor C1 on the substrate 10 is located within a positive projection of the first barrier wall 861 on the substrate 10, and a positive projection of the second capacitor C2 on the substrate 10 is located within a positive projection of the first barrier wall 861 on the substrate 10.

[0159] In some embodiments, a side wall of the pixel opening 860 may be perpendicular to the substrate 10. At this time, the pixel opening 860 and the bottom surface 1001 of the light-emitting portion 100 may coincide.

[0160] In some embodiments, a side wall of the pixel opening 860 may be inclined with respect to a direction perpendicular to the substrate 10. For example Figure 1 as shown, and thus a range of the pixel opening 860 is larger than a bottom surface 1001 of the light-emitting portion 100.

[0161] Continuing from the above, in the embodiment of the present application, the first capacitor C1 does not overlap with the bottom surface 1001 of the light-emitting part 100 in the thickness direction of the display panel, and the second capacitor C2 does not overlap with the bottom surface 1001 of the light-emitting part 100 in the thickness direction of the display panel; thereby, it is possible to avoid the first capacitor C1 and the second capacitor C2 from affecting the flatness of the bottom of the pixel aperture 860, effectively improving the film flatness of the bottom of the pixel aperture 860, and improving the film thickness uniformity and light-emitting performance of the light-emitting part 100.

[0162] In some embodiments, the first electrode plate C11, the second electrode plate C12, the third electrode plate C21, and the fourth electrode plate C22 do not overlap with the bottom surface 1001 of the light-emitting part 100 in the thickness direction of the display panel.

[0163] In some embodiments, since the driving gate T2G and the second electrode plate C12 are integrated, therefore, the driving gate T2G does not overlap with the bottom surface 1001 of the light-emitting part 100 in the thickness direction of the display panel, and thus at least a part of the driving active part does not overlap with the bottom surface 1001 of the light-emitting part 100 in the thickness direction of the display panel.

[0164] In some embodiments, the first capacitor C1 is located between two adjacent light-emitting parts 100 along the second direction Y, and the second capacitor C2 is located between two adjacent light-emitting parts 100 along the second direction Y.

[0165] In some embodiments, such as Figure 4As shown, the light-emitting part 100 partially overlaps with two adjacent pixel driving circuits PD along the second direction Y, and the pixel driving circuit PD partially overlaps with two adjacent light-emitting parts 100 along the second direction Y; since in the embodiment of the present application, the bottom surface 1001 of the light-emitting part 100 is set not to overlap with the first capacitor C1 and the second capacitor C2, the area of the light-emitting part 100 will be reduced and the aperture ratio will be decreased; however, in the embodiment of the present application, by setting the pixel driving circuit PD to partially overlap with the bottom surface 1001 of two adjacent light-emitting parts 100 along the second direction, that is, moving the positions of the pixel opening 860 and the light-emitting part 100 along the second direction, and moving them between two adjacent first capacitors C1 along the second direction and between two adjacent second capacitors C2 along the second direction, on the basis that the bottom surface 1001 of the light-emitting part 100 partially overlaps with its corresponding pixel driving circuit PD, the bottom surface 1001 of the light-emitting part 100 also partially overlaps with the adjacent pixel driving circuit PD, so as to compensate for the lost aperture area due to avoiding the first capacitor C1 and the second capacitor C2, that is, in the embodiment of the present application, on the basis of improving the film thickness uniformity of the light-emitting part 100, the area of the light-emitting part 100 can be ensured, and the aperture area of the display panel can be ensured.

[0166] In some embodiments, on the basis that the bottom surface 1001 of the light-emitting part 100 partially overlaps with its corresponding pixel driving circuit PD, it can also partially overlap with any one of two adjacent pixel driving circuits PD along the second direction Y.

[0167] For example, Figure 4 the light-emitting part 100 shown in partially overlaps with two adjacent pixel driving circuits PD along the second direction Y, and the first capacitor C1 and the second capacitor C2 in the figure belong to the pixel driving circuit PD located above, however, the light-emitting part 100 corresponds to the pixel driving circuit PD located below, and the anode 71 corresponding to the light-emitting part 100 is also connected to the pixel driving circuit PD below. Correspondingly, in the embodiment of the present application Figure 14 the connection site of the anode 71 in is located below.

[0168] In some embodiments, the second capacitor C2 is located between the corresponding light-emitting part 100 and the first capacitor C1.

[0169] In other embodiments of the present application, the connection site of the anode 71 can also be set at Figure 14 above the anode 71 shown in, then the light-emitting part 100 and the anode 71 are connected to Figure 4The pixel driving circuit PD in the upper middle is correspondingly connected, and the first capacitor C1 and the second capacitor C2 also belong to the pixel driving circuit PD located above. Correspondingly, the first capacitor C1 is located between the corresponding light-emitting portion 100 and the second capacitor C2.

[0170] In some embodiments, in the same pixel driving circuit PD, the switching active portion T1A is located on a side of the second capacitor C2 away from the driving active portion T2A.

[0171] In summary, in the embodiment of the present application, by setting the first capacitor C1 and the second capacitor C2 in the pixel driving circuit PD not to overlap with the bottom surface 1001 of the light-emitting portion 100, the film layer flatness at the position where the light-emitting portion 100 is located can be improved, the film thickness uniformity and the yield of the light-emitting portion 100 are improved, and thus the light-emitting effect and the light-emitting efficiency of the display panel can be improved.

[0172] According to the above object of the present application, an embodiment of the present application further provides a display device, and the display device includes the display panel.

[0173] It can be understood that since the display device has the same display panel as that in the above embodiment, therefore, the display device has the same beneficial effects as the display panel, and details are not described herein again.

[0174] In the description of the present application, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, "a plurality of" means two or more, unless otherwise specifically defined.

[0175] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0176] Among the embodiments, embodiments, and related technical features of the present application, they can be combined and replaced with each other without conflict.

[0177] The above are only the preferred embodiments of the present application, and do not impose any form of limitation on the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a plurality of pixel driving circuits and a plurality of light emitting units arranged corresponding to the plurality of pixel driving circuits, wherein the light emitting units are arranged on one side of the pixel driving circuits; The pixel driving circuit includes a switch transistor, a drive transistor, a first capacitor and a second capacitor, wherein the first capacitor is connected between the switch transistor and the drive transistor, and the second capacitor is connected between the switch transistor and the first capacitor; Among them, the light-emitting portion includes a bottom surface close to the pixel driving circuit, and the bottom surface of the light-emitting portion does not overlap with the first capacitor along the thickness direction of the display panel, and the bottom surface of the light-emitting portion does not overlap with the second capacitor along the thickness direction of the display panel.

2. The display panel according to claim 1, characterized in that: The first capacitor includes a first electrode plate and a second electrode plate which are arranged opposite to each other, and the second capacitor includes a third electrode plate and a fourth electrode plate which are arranged opposite to each other; The first electrode plate and the switch transistor are connected to a first node, the second electrode plate and the drive transistor are connected to a second node, and the third electrode plate is connected to the first node; The first electrode plate, the second electrode plate, the third electrode plate, and the fourth electrode plate do not overlap with the bottom surface of the light-emitting portion along the thickness direction of the display panel.

3. The display panel according to claim 2, characterized in that: The driving transistor includes a driving active portion, and the display panel further includes: substrate; A semiconductor layer, disposed on the substrate, wherein the semiconductor layer includes the driving active portion; The first gate layer is arranged on the side of the semiconductor layer away from the substrate, and the first gate layer includes the second electrode plate arranged on the side of the driving active part away from the substrate, and the second electrode plate partially overlaps with the driving active part along the thickness direction of the display panel.

4. The display panel according to claim 3, characterized in that: At least a portion of the driving active portion and the bottom surface of the light emitting portion do not overlap along the thickness direction of the display panel.

5. The display panel according to claim 3, characterized in that: The first gate layer also includes the third electrode plate; The display panel further includes: The second gate layer is arranged on a side of the first gate layer away from the semiconductor layer, and the second gate layer includes the first electrode plate and the fourth electrode plate.

6. The display panel according to any one of claims 3 to 5, characterized in that: The plurality of light emitting portions are arranged along a first direction and a second direction, the first capacitor is located between two adjacent light emitting portions along the second direction, the second capacitor is located between two adjacent light emitting portions along the second direction, and the first direction and the second direction intersect.

7. The display panel according to claim 6, characterized in that: The light emitting portion partially overlaps with two adjacent pixel driving circuits along the second direction.

8. The display panel according to claim 6, characterized in that: The switch transistor includes a switch active portion, the semiconductor layer also includes the switch active portion, and in the same pixel driving circuit, the switch active portion is located on a side of the second capacitor away from the driving active portion; The display panel further includes: A first conductive layer, disposed on a side of the semiconductor layer away from the substrate, the first conductive layer comprising a first power signal line extending along the first direction, the first power signal line being connected to the fourth electrode plate; A second conductive layer is disposed on a side of the first conductive layer away from the semiconductor layer, the second conductive layer comprising a second power signal line extending along the second direction and a data signal line extending along the second direction; The data signal line is connected to the switch active portion, and the second power signal line is connected to the first power signal line.

9. The display panel according to claim 8, characterized in that: The pixel driving circuit further includes a first light emission control transistor connected to the driving transistor, wherein the first light emission control transistor includes a first light emission control active portion; The semiconductor layer includes the first light-emitting control active portion, in the same pixel driving circuit, the first light-emitting control active portion is located on a side of the driving active portion away from the switch active portion and extends along the second direction, the first light-emitting control active portion is connected between a third node and a fourth node, and the driving active portion is connected to the third node; The second conductive layer includes an anode connection line extending along the second direction, a first end of the anode connection line connected to the fourth node, and a second end of the anode connection line not overlapping with the bottom surface of the light-emitting portion along the thickness direction of the display panel.

10. The display panel according to claim 9, characterized in that: The display panel further includes: an anode layer, arranged on a side of the second conductive layer away from the first conductive layer, the anode layer comprising a plurality of anodes arranged corresponding to the plurality of light-emitting portions, the anodes being arranged between the corresponding light-emitting portions and the substrate, and the anodes being connected to the second end; A pixel definition layer is arranged on a side of the anode layer away from the second conductive layer, and a plurality of pixel openings corresponding to the plurality of anodes are opened in the pixel definition layer. The light-emitting portion is arranged in the pixel openings, and the pixel opening and the first capacitor do not overlap along the thickness direction of the display panel, and the pixel opening and the second capacitor do not overlap along the thickness direction of the display panel.

11. The display panel according to claim 10, characterized in that: The pixel definition layer includes a plurality of first retaining walls arranged along the second direction and a plurality of second retaining walls arranged along the first direction, the first retaining walls extend along the first direction, the second retaining walls extend along the second direction, and the plurality of first retaining walls intersect with the plurality of second retaining walls to be arranged around the plurality of pixel openings; The first blocking wall is located between two adjacent pixel openings along the second direction, and the orthographic projection of the first capacitor on the substrate is located within the orthographic projection of the first blocking wall on the substrate, and the orthographic projection of the second capacitor on the substrate is located within the orthographic projection of the first blocking wall on the substrate.

12. The display panel according to claim 10, characterized in that: The first power signal line is connected to the second power signal line through a first via hole, the anode is connected to the anode connecting line through a second via hole, the first via hole partially overlaps with the first capacitor along the thickness direction of the display panel, and the second via hole partially overlaps with the first capacitor along the thickness direction of the display panel.

13. The display panel according to claim 12, characterized in that: The first via hole at least partially overlaps with the second via hole along the first direction.

14. The display panel according to claim 12, characterized in that: The second power signal line includes a first line segment and a second line segment connected to the first line segment, the first line segment partially overlaps with the first via along the first direction, the first line segment partially overlaps with the second via along the first direction, and the width of the first line segment along the first direction is smaller than the width of the second line segment along the first direction.

15. The display panel according to any one of claims 1 to 5, characterized in that: In the corresponding pixel driving circuit, the second capacitor is located between the corresponding light-emitting portion and the first capacitor.

16. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 15.

Images