Perovskite crystalline silicon laminated cell and manufacturing method thereof

Abstract

The invention relates to the technical field of perovskite crystalline silicon laminated cells, in particular to a perovskite crystalline silicon laminated cell and a manufacturing method thereof. The method comprises the following steps: preparing a bottom cell, and manufacturing a top cell on the upper surface of the bottom cell; in the preparation process of the bottom cell, a doped tunneling layer technology is used to replace a TCO (composite junction) technology, the bottom cell adopts a double-sided poly technology, the surface of a P-type substrate doped polycrystalline silicon layer of the bottom cell forms a tunneling junction after secondary double-sided poly growth and boron diffusion annealing, and the bottom cell forms a P-type doped polycrystalline silicon layer, so that the technological process is shortened, the product preparation process is simplified, and the production efficiency is improved. And the key auxiliary material cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of perovskite / silicon tandem cells, and particularly to a perovskite / silicon tandem cell and a manufacturing method thereof. Background Art

[0002] At present, during the manufacturing process of silicon / calcium titanium oxide two-terminal tandem cells, they are mainly small-area tandem cells in the laboratory (within 5 cm * 5 cm), and industrial production has not yet been formed. The important problems faced in the industrial preparation process are mainly due to high manufacturing costs, unsatisfactory electrical parameter matching between the top cell and the bottom cell, etc. (especially manifested in the current parameter. In the performance parameters of the two-terminal series tandem cell, there is a cask effect in the current. Improving the current parameter can further improve the performance parameters of the product). The silicon / calcium titanium oxide tandem cell mainly consists of a bottom cell, a perovskite top cell, a tunneling layer or a composite connection layer. Currently, the bottom cell mostly uses N-type TOPCon, heterojunction or P-type cells. The efficiency of the P-type bottom cell is currently low. In the mainstream technology of the two-terminal tandem cell in the industry, the bottom cell mostly uses N-type bottom cells. Compared with P-type cells, N-type bottom cells have better performance parameters, and the current and voltage are more advantageous overall, making it more competitive to prepare two-terminal tandem cells. And currently, the overall production cost of N-type TOPCon cells is more advantageous than that of N-type heterojunction cells. The main material costs of the tandem cell include silicon wafers and precious metals (materials such as silver paste, TCO, chemicals, etc.). Except for the raw material silicon wafers, the current relatively large costs are mainly the silver paste material of the bottom cell, the TCO material of the top cell, and the TCO of the composite connection layer and other materials, as Figure 1a shown. Aiming at the current problems of high production and manufacturing costs and low current parameter matching degree between the top cell and the bottom cell, in order to improve the production cost and comprehensively consider the product performance.

[0003] The manufacturing process of conventional silicon / calcium titanium oxide two-terminal tandem cells generally includes processes such as single-sided or double-sided texturing, and then multiple single-sided preparations of the P-poly layer and / or single-sided preparations of the n+poly layer. And after each single-sided growth of the doped polysilicon layer, annealing and cleaning are required, resulting in a long preparation cycle, a high rejection rate, and an increase in manufacturing costs at the same time.

[0004] Among them, the single-sided texturing has disadvantages such as unsatisfactory optical matching between the top cell and the bottom cell and being unfavorable for improving the optical performance of the bottom cell;

[0005] Multiple single-sided preparations of the doped polysilicon layer have disadvantages such as a long process flow, many wet chemical etching processes, an unoptimized preparation process for the environment, and a cumbersome product process preparation. Double-sided texturing and double-sided doped polysilicon layer have advantages such as a simple preparation process, few wet chemical etching processes involved, and a short preparation cycle.

[0006] Therefore, there is an urgent need to propose a new perovskite / silicon tandem cell and its manufacturing method to solve the problems of the above-mentioned cumbersome preparation process, long preparation cycle, and a more environmentally friendly preparation process (relatively few wet chemical processes in the preparation process, relatively simple use and treatment of chemical drugs). Summary of the Invention

[0007] To solve the problems of the prior art, the present invention provides a perovskite / silicon tandem cell and its manufacturing method. The present invention provides the following technical solutions:

[0008] In the first aspect of the present invention, a manufacturing method of a perovskite / silicon tandem cell is provided. The method includes preparing a bottom cell and fabricating a top cell on the upper surface of the bottom cell. Among them, the preparation process of the bottom cell includes:

[0009] Performing double-sided texturing, double-sided growth of a tunneling oxide layer, and double-sided growth of a first polysilicon layer on the upper surface and the lower surface of the silicon wafer in sequence;

[0010] Performing a diffusion mask layer on the first polysilicon layer on the lower surface of the silicon wafer;

[0011] Performing phosphorus doping and annealing on the first polysilicon layer on the upper surface of the silicon wafer in sequence to obtain an N-type substrate doped polysilicon layer and a phosphosilicate glass layer;

[0012] Removing the mask layer and the phosphosilicate glass layer;

[0013] Performing double-sided growth of a second polysilicon layer on the first polysilicon layer on the lower surface of the silicon wafer and the N-type substrate doped polysilicon layer on the upper surface of the silicon wafer after removing the mask layer;

[0014] Performing boron doping on the surfaces of the second polysilicon layers on the upper surface and the lower surface of the silicon wafer to obtain a first P-type substrate doped polysilicon layer and a second P-type substrate doped polysilicon layer;

[0015] Growing an alumina layer and a silicon oxide layer on the surface of the second P-type substrate doped polysilicon layer in sequence.

[0016] Further, the height of the pyramidal texture of the double-sided texturing is 0.05 - 0.3 μm, and the integrated monochromaticity rate is controlled at 8% - 20%.

[0017] Further, the mask layer is one or more of silicon nitride, silicon oxynitride, or silicon oxide materials.

[0018] Further, removing the mask layer and the phosphosilicate glass layer includes:

[0019] Using a chain cleaning method, in combination with an HF solution with a mass concentration of 1% - 30%, and etching for 20 - 500 s to remove the mask layer and the phosphosilicate glass layer.

[0020] Further, the thickness of the primary polysilicon layer is 20 nm - 150 nm;

[0021] and / or, the thickness of the secondary polysilicon layer is 1 nm - 100 nm.

[0022] Further, boron doping is performed on the surfaces of the secondary polysilicon layers on the upper surface and the lower surface of the silicon wafer to obtain a first P-type substrate doped polysilicon layer and a second P-type substrate doped polysilicon layer, including:

[0023] Using a high-temperature tube furnace, introducing a boron source and nitrogen gas, and at a temperature of 800 - 1000 °C, boron doping is performed on the surfaces of the secondary polysilicon layers on the upper surface and the lower surface of the silicon wafer to obtain a first P-type substrate doped polysilicon layer and a second P-type substrate doped polysilicon layer.

[0024] Further, after boron doping is performed on the surfaces of the secondary polysilicon layers on the upper surface and the lower surface of the silicon wafer to obtain a first P-type substrate doped polysilicon layer and a second P-type substrate doped polysilicon layer, it further includes:

[0025] Annealing the first P-type substrate doped polysilicon layer and the second P-type substrate doped polysilicon layer, and respectively forming a first borosilicate glass layer and a second borosilicate glass layer on the surfaces of the first P-type substrate doped polysilicon layer and the second P-type substrate doped polysilicon layer;

[0026] Using an HF solution with a mass concentration of 1% - 49% to clean and remove the first borosilicate glass layer and the second borosilicate glass layer.

[0027] Further, using a plasma-enhanced chemical vapor deposition or atomic layer deposition device, alumina is grown on the surface of the second P-type substrate doped polysilicon layer, and the thickness of the alumina is controlled within 1 - 3 nm.

[0028] Further, the silicon oxide layer is selected from one or more of silicon nitride, silicon oxynitride, and silicon oxide;

[0029] The thickness of the silicon oxide layer is 80 - 100 nm.

[0030] Further, a top cell is fabricated on the surface of the first P-type substrate doped polysilicon layer.

[0031] There is also provided a perovskite-silicon tandem solar cell prepared by the manufacturing method as described above.

[0032] The technical effects and advantages of the present invention:

[0033] During the manufacturing process, by using the doped tunneling layer process to replace the TCO (Transparent Conductive Oxide) composite junction, and adopting the double-sided poly process for the bottom cell. After the surface of the P-type substrate doped polysilicon layer of the bottom cell undergoes secondary double-sided poly growth and boron diffusion annealing, a tunneling junction is formed, and a P-type doped polysilicon layer is formed in the bottom cell, shortening the process flow, simplifying the product preparation process, and reducing the cost of key auxiliary materials.

[0034] Compared with the prior art, the present application adopts double-sided growth of polysilicon layers twice, simplifying the production process. The purpose of double-sided poly growth is to symmetrically grow poly silicon on both sides. Due to the difference in stress coefficients between polysilicon and single-crystalline silicon, single-sided growth is likely to cause the silicon wafer to bend. On the one hand, it can reduce the bending degree of the silicon wafer caused by uneven stress during single-sided deposition of poly silicon, and further reduce the breakage rate of semi-finished products in the subsequent production process; on the other hand, adopting the double-sided growth poly process reduces the process flow steps, shortens the process time, and further reduces the direct production cost of the product.

[0035] Along with the trend of reducing the thickness of the crystalline silicon bottom cell, by adopting the secondary double-sided poly process preparation method, it is easy to reduce the breakage rate of semi-finished products during the preparation process of the bottom cell.

[0036] Adopting the secondary double-sided Poly preparation process can realize the preparation of the P-type substrate doped polysilicon layer on the back of the bottom cell and the tunneling junction between the top cell and the bottom cell at one time. It reduces the upfront equipment investment cost and the product process production cost. This process flow reduces the impact of laser cutting on the performance of the bottom cell through special process steps, and improves the efficiency of the bottom cell and the tandem cell.

[0037] Other features and advantages of the present invention will be described in the subsequent specification, and part of them will become obvious from the specification or be understood by implementing the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the structures pointed out in the specification and the drawings. Brief Description of the Drawings

[0038] Figure 1a It is a simplified structure diagram of a tandem cell provided by an embodiment of the present application;

[0039] Figure 1b It is a structure diagram of a tandem cell provided by an embodiment of the present application;

[0040] Figure 2 It is a flowchart of the manufacturing method of a perovskite crystalline silicon tandem cell provided by an embodiment of the present application;

[0041] Figure 3a It is a diagram of the original N-type silicon wafer provided by an embodiment of the present application;

[0042] Figure 3bIt is a diagram of the silicon wafer after texturing provided by an embodiment of the present application;

[0043] Figure 4 It is a schematic diagram of the bottom cell after the double-sided growth of the tunneling oxide layer and the polysilicon layer provided by an embodiment of the present application;

[0044] Figure 5 It is a schematic diagram of preparing a mask layer on the lower surface of the bottom cell provided by an embodiment of the present application;

[0045] Figure 6 It is a schematic diagram of preparing an n+poly doping layer on the upper surface of the bottom cell provided by an embodiment of the present application;

[0046] Figure 7 It is a schematic diagram of cleaning the PSG layer on the upper and lower surfaces of the bottom cell provided by an embodiment of the present application;

[0047] Figure 8 It is a schematic diagram of the double-sided secondary growth of the poly layer on the bottom cell provided by an embodiment of the present application;

[0048] Figure 9 It is a schematic diagram of the double-sided p-poly doping of the bottom cell provided by an embodiment of the present application;

[0049] Figure 10 It is a schematic diagram of annealing after the double-sided p-poly doping of the bottom cell provided by an embodiment of the present application;

[0050] Figure 11 It is a schematic diagram of double-sided cleaning to remove BSG from the bottom cell provided by an embodiment of the present application;

[0051] Figure 12 It is a schematic diagram of growing aluminum oxide on the lower surface of the bottom cell provided by an embodiment of the present application;

[0052] Figure 13 It is a schematic diagram of growing silicon nitride on the back surface of the bottom cell provided by an embodiment of the present application;

[0053] Figure 14 It is a schematic diagram of preparing a top cell HTL (hole transport layer) on the front surface of the bottom cell provided by an embodiment of the present application;

[0054] Figure 15 It is a schematic diagram of the perovskite silicon tandem cell of the present application provided by an embodiment of the present application;

[0055] Figure 16 It is a schematic diagram of growing a tunneling oxide layer in Comparative Example 1 of the present application;

[0056] Figure 17 It is a schematic diagram after boron doping and annealing in Comparative Example 1 of the present application;

[0057] Figure 18It is the hydrofluoric acid cleaning of the bottom cell BSG dielectric layer in Comparative Example 1 of the present application;

[0058] Figure 19 It is the removal of the wrap plating on the upper surface of the bottom cell (N+ surface removal of the wrap plating) in Comparative Example 1 of the present application;

[0059] Figure 20 It is the poly doping and annealing treatment of the upper surface of the bottom cell (single-sided doping of the upper surface of the bottom cell) provided in the embodiment of the present application in Comparative Example 1;

[0060] Figure 21a It is the structural diagram of the bottom cell after HF cleaning the lower surface psg and the wrap plated n+poly of the bottom cell in Comparative Example 1 of the present application;

[0061] Figure 21b It is the structural diagram of the bottom cell after HF cleaning the upper surface psg and the wrap plated n+poly of the bottom cell in Comparative Example 1 of the present application;

[0062] Figure 22 It is the growth of a p+poly layer by doping on the upper surface of the bottom cell in Comparative Example 1 of the present application, and annealing the poly layer;

[0063] Figure 23a It is the structural diagram of the bottom cell after secondary cleaning and removal of the wrap plating on the lower surface of the bottom cell in Comparative Example 1 of the present application;

[0064] Figure 23b It is the structural diagram of the bottom cell before hydrofluoric acid cleaning the upper and lower surfaces BSG dielectric layers of the bottom cell in Comparative Example 1 of the present application;

[0065] Figure 24 It is the schematic diagram after deposition of the alumina dielectric layer in Comparative Example 1 of the present application;

[0066] Figure 25 It is the schematic diagram of the bottom cell prepared in Comparative Example 1 of the present application;

[0067] Figure 26 It is the schematic diagram of the cell prepared in Comparative Example 1 of the present application;

[0068] Figure 27 It is the schematic structural diagram of the bottom cell after cleaning the wrap plating layer on the p+poly surface of the lower surface of the bottom cell in Comparative Example 2 of the present application;

[0069] Figure 28 It is the schematic structural diagram of the bottom cell after cleaning the PSG and BSG on the upper and lower surfaces of the bottom cell in Comparative Example 2 of the present application;

[0070] Figure 29 It is the schematic diagram of the cell prepared in Comparative Example 2 of the present application. Detailed implementation manners

[0071] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0072] To solve the deficiencies of the prior art, the present invention discloses a method for manufacturing a perovskite / silicon tandem solar cell. The method includes preparing a bottom cell and fabricating a top cell on the upper surface of the bottom cell. As shown in Figure 1, the preparation process of the bottom cell includes:

[0073] Step 1: Sequentially perform double-sided texturing, double-sided growth of tunneling oxide layers, and double-sided growth of a first polysilicon layer on the upper surface and the lower surface of the silicon wafer. The specific operations are as follows:

[0074] Step 101: Texturing: Clean the original silicon wafer, as Figure 2 shown;

[0075] Perform double-sided micro-texturing on the upper and lower surfaces of the original silicon wafer using a common cleaning and texturing process: control the mass concentration of sodium hydroxide at about 1.0%-2.5%, and mix it with a certain proportion of additive solution. Preferably, common additive solutions for texturing, such as commercially common texturing, anti-reflection coating, or polishing additives, are used. Control the temperature at 80-85°C and the etching time at about 450s-600s to complete texturing. As shown in Figure 3, control the height of the pyramid-shaped texture on the surface at 0.05-0.3μm and the integral monochromaticity rate in the range of 8%-20%. It should be noted that: control the size of the texture on the surface at 0.05-0.3μm. The main purpose of performing micro-texturing is to consider the passivation effect on the lower surface of the bottom cell and the conformability of the hole transport layer and the perovskite layer of the top cell. At the same time, consider the optical absorption effect of the bottom cell to improve the overall performance of the bottom cell.

[0076] Step 102: Double-sided growth of tunneling oxide layers and polysilicon layers on the bottom cell, as Figure 4 shown:

[0077] Prepare by means of LPCVD (low-pressure chemical vapor deposition), ALD (atomic layer deposition), PECVD (plasma-enhanced chemical vapor deposition), etc. Through oxygen, silane, and hydrogen gas sources, perform chemical reactions in a high-temperature environment to grow a tunneling oxide layer with a certain thickness on both sides. Among them, the tunneling oxide layer can be silicon oxide, silicon oxynitride, or a composite layer of both. The thickness of the tunneling oxide layer on each side is 0.5-3.0nm;

[0078] Using vacuum equipment such as high-temperature LPCVD and PECVD, through gaseous sources of oxygen, silane, and hydrogen, a chemical reaction is carried out in a high-temperature environment to grow a polysilicon dielectric layer (poly layer) on both sides at once. Among them, the thickness of polysilicon on each side is controlled within 20 - 150 nm. The purpose of growing polysilicon on both sides is to grow polysilicon symmetrically on both sides. Due to the difference in stress coefficients between polysilicon and single-crystalline silicon, growing on one side alone easily causes the silicon wafer to bend. On the one hand, it can reduce the bending degree of the silicon wafer caused by uneven deposition stress of polysilicon on one side, and further reduce the breakage rate of semi-finished products in the subsequent production process. On the other hand, using the process of growing polysilicon on both sides reduces the process flow steps, and in the secondary deposition doping process in the key step 601, the preparation of the tunneling junction p+poly of the stacked cell and the p-poly doping of the bottom cell are realized in one step. It further reduces the direct production cost of the product and the equipment purchase cost. Among them, p+poly represents the P-type polysilicon doping on the upper surface of the bottom cell, and p-poly represents the P-type polysilicon doping on the lower surface of the bottom cell.

[0079] Step 2: On the polysilicon layer on the lower surface of the silicon wafer, a diffusion mask layer is carried out, such as Figure 5 shown;

[0080] A diffusion mask layer is prepared on the primary poly surface on the lower surface of the bottom cell. The mask layer can be a single layer of silicon nitride, silicon oxynitride, silicon oxide, or a composite layer of two or three of these three materials. The total thickness of the mask layer is 10 - 100 nm. It fully protects the phosphorus doping that is plated around to the lower surface during the preparation of phosphorus doping on the upper surface of the bottom cell in Step 3 from passing through the polysilicon layer and the tunneling oxide layer and doping into the p-poly on the lower surface of the bottom cell, reducing the impact on the performance of the bottom cell.

[0081] Step 3: Phosphorus doping and annealing are successively carried out on the primary polysilicon layer on the upper surface of the silicon wafer to obtain an N-type substrate doped polysilicon layer and a phosphosilicate glass layer; among them,

[0082] Step 301: As Figure 6 shown, phosphorus doping (n+poly doping) is carried out, including the following steps:

[0083] The polysilicon layer is doped with phosphorus and annealed using high-temperature doping annealing equipment or the PECVD method.

[0084] Such as a tube-type high-temperature doping equipment: Using phosphorus oxychloride diffusion source, the high-temperature doping promotion temperature is controlled at about 800 - 1000 °C. Considering that too long high-temperature doping time is likely to cause the passivation effect of polysilicon to deteriorate, the high-temperature promotion time of phosphorus doping (above 850 degrees) is controlled within the range of 30 - 100 min.

[0085] Step 302: As Figure 6As shown, after phosphorus doping (n+ poly doping), annealing is carried out. The annealing time is controlled within the range of 20 - 100 min, and the temperature is controlled within the range of 600 - 900 degrees. Among them, the oxygen passing time is controlled within 3 - 15 min, and the oxygen flow rate is controlled within 50 - 500 sccm. A layer of PSG (phosphosilicate glass layer) is formed on the surface of the N-type substrate doped polysilicon layer. Annealing activates the phosphorus doping layer and further repairs lattice defects.

[0086] Step 4: Remove the mask layer and the phosphosilicate glass layer, as Figure 7 shown;

[0087] Use a chain cleaning device, combined with a 1% - 30% HF solution, and etch for 20 - 500 s to clean both sides of the bottom cell. Remove the mask layer on the lower surface of the bottom cell in Steps 3 and 4 and the PSG oxide layer that is deposited on the lower surface of the bottom cell and around the bottom cell during the preparation of the n+ poly doped layer. Then perform an alkali cleaning on both sides of the bottom cell. The alkali solution uses sodium hydroxide or potassium hydroxide solution, and the concentration is controlled within the range of 0.5% - 5%. Remove the n+ doped layer on the lower surface of the bottom cell, and then use a 1% - 30% HF solution to clean the PSG layers on the upper and lower surfaces of the bottom cell.

[0088] Step 5: Grow a secondary polysilicon layer on both sides of the silicon wafer on the lower surface of the primary polysilicon layer after removing the mask layer and on the N-type substrate doped polysilicon layer on the upper surface of the silicon wafer, as Figure 8 shown, including:

[0089] Use an LPCVD device, introduce gases such as silane and nitrogen, and prepare a secondary poly layer on both sides of the bottom cell, with a thickness of 1 nm - 100 nm.

[0090] Step 6: Perform boron doping on the surfaces of the secondary polysilicon layers on the upper and lower surfaces of the silicon wafer to obtain a first P-type substrate doped polysilicon layer and a second P-type substrate doped polysilicon layer; including the following steps:

[0091] Step 601: As Figure 9 shown, perform p-poly doping on both sides of the bottom cell: Use a high-temperature tube furnace device, introduce boron source and nitrogen gas, and prepare a poly layer on both sides of the bottom cell, with a thickness of 1 nm - 100 nm.

[0092] Use a high-temperature tube furnace device, introduce boron source and nitrogen gas, control the temperature within the range of 800 - 1000, perform double-sided boron doping on the bottom cell, and form a p+ poly doped layer for the tunneling junction and a P-poly doped layer for the bottom cell on the upper and lower surfaces of the bottom cell respectively.

[0093] Step 602: As Figure 10As shown, after boron doping (n+ poly doping), annealing is carried out. The annealing time is controlled within the range of 10 - 100 min, and the temperature is controlled within the range of 600 - 950 °C. Among them, the oxygen passing time is controlled within 3 - 20 min, and the oxygen flow rate is controlled within 50 - 500 sccm. A layer of BSG (boron silicate glass layer) is formed on the surface of the P-type substrate doped polysilicon layer. Annealing activates the boron doping layer and further repairs lattice defects.

[0094] Step 603: As Figure 11 shown, the bottom cell is cleaned on both sides to remove BSG

[0095] Use an HF solution with a mass concentration of 1% - 49% to clean the boron silicate glass generated on the surface of the bottom cell during the process of Step 602.

[0096] It should be noted that: based on this step, the poly doping layer is prepared twice on both sides through Steps 601 and 602 to complete the preparation of the p-poly on the back of the bottom cell and the preparation of the tunneling junction on the front (the tunneling junction is composed of p+ poly and n+ poly between the bottom cell and the top cell), shortening the process flow.

[0097] Step 7: Grow an alumina layer and a silicon oxide layer on the surface of the second P-type substrate doped polysilicon layer in sequence; the specific steps are as follows:

[0098] Step 701: As Figure 12 shown, grow alumina on the lower surface of the bottom cell:

[0099] Use PECVD or ALD equipment to grow alumina on the back of the bottom cell. The thickness of the alumina is controlled within 1 - 3 nm.

[0100] Step 702: As Figure 13 shown, grow a silicon oxide layer on the lower surface of the bottom cell:

[0101] Use PECVD equipment, introduce silane, ammonia, nitrous oxide, and nitrogen gas sources, and carry out a chemical reaction under a high-temperature and low-pressure environment to grow a silicon oxide layer on the lower surface of the bottom cell. The silicon oxide layer is prepared by selecting silicon nitride, silicon oxynitride, silicon oxide deposition, or a composite layer of two or three of these three dielectric layers.

[0102] Step 8: Prepare the top cell: Prepare the top cell on the surface of the first P-type substrate doped polysilicon layer.

[0103] Step 801: As Figure 14 shown, prepare the top cell HTL (hole transport layer) on the front surface of the bottom cell:

[0104] The HTL can be prepared by evaporation, sputtering, RPD (reactive plasma deposition), spin coating, slot die coating, etc. The hole transport layer material can be selected from organic macromolecular materials, organic small molecule materials, SAM layer (Self-Assembled Monolayers) materials, or inorganic materials (such as nickel oxide).

[0105] Step 802: Prepare the perovskite layer.

[0106] For the preparation of the perovskite layer, materials of 3D, 2D structural types or 3D, 2D stacked composite structural types can be selected; the thickness is controlled within 100 - 1000 nm.

[0107] Step 803: As Figure 15 shown, sequentially prepare the top cell electron transport layer, metal conductive layer, top cell electrode, and bottom cell electrode layer:

[0108] For the electron transport layer, one or more of C60 ("fullerene" or "buckyball"), PCBM (benzothieno[3,2-b]thiophene-2,6-dicarboxylic acid bis-(2-ethylhexyl)ester), BCP (bathocuproine)) or materials such as tin oxide can be used.

[0109] For the metal conductive layer, one or more composite layer materials of TCO (Transparent Conductive Oxide) (FTO / Fluorine-doped Tin Oxide, ITO / Indium Tin Oxide, IZO / Indium Zinc Oxide, AZO / Aluminum-doped Zinc Oxide, IWO / Indium Tungsten Oxide) can be selected for preparation. The preparation method can be thermal evaporation, sputtering, or RPD (reactive plasma deposition) method.

[0110] Through mask pattern design, the top cell electrode can be prepared by evaporation, and the preparation method can be thermal evaporation, sputtering, or RPD method. The electrode materials include one or more composite laminated materials of gold, silver, copper, bismuth, or materials such as silver-coated copper. Or through screen printing, combined with low-temperature metallization paste, electrode printing and drying sintering are carried out to complete the preparation of the top cell electrode.

[0111] Grow a metal electrode on the lower surface of the bottom cell. The preparation method of the metal electrode can use the evaporation method or the low-temperature paste screen printing and drying method.

[0112] The metal electrode material can be one or a mixture of gold, silver, and copper.

[0113] The tandem cell fabricated by the method of the present invention simplifies the preparation process by 4 - 5 steps compared with the current tunneling crystalline silicon / perovskite tandem cell.

[0114] Along with the trend of reducing the thickness of the crystalline silicon bottom cell, by using the secondary double-sided poly process preparation method, it is easy to reduce the breakage rate of semi-finished products during the preparation of the bottom cell.

[0115] By using the secondary double-sided Poly preparation process, the p-poly doping on the back side of the bottom cell and the preparation of the tunneling junction between the top cell and the bottom cell can be achieved at one time. This reduces the upfront equipment investment cost and the product process manufacturing cost.

[0116] The technical solution of the present invention will be further described below in conjunction with specific embodiments.

[0117] Example 1:

[0118] 1. Clean the original silicon wafer and perform double-sided micro-texturing on the bottom cell

[0119] Use a general cleaning and texturing process. Control the mass concentration of sodium hydroxide at about 1.0% - 2.5%, and mix it with a certain proportion of additive solution (commonly used additive solution for texturing). Control the temperature at 80 - 85°C and the etching time at about 450s - 600s. Control the pyramid height at 0.05 - 0.3μm and the integrated monochromaticity rate within the range of 8% - 20%.

[0120] 2. Grow tunneling oxide layers and polysilicon layers on both sides of the bottom cell

[0121] Use high-temperature LPCVD\PECVD and other vacuum equipment. Through gaseous sources of oxygen, silane, and hydrogen, carry out chemical reactions in a high-temperature environment to grow tunneling oxide layers and polysilicon dielectric layers of a certain thickness; control the polysilicon thickness at 20 - 150nm and grow polysilicon on both sides. The tunneling oxide layer can be silicon oxide, silicon oxynitride, or a composite layer of both, with a thickness of 0.5 - 3.0nm. The tunneling oxide layer can be prepared by LPCVD, ALD, PECVD, etc.

[0122] 3. Prepare a mask layer on the lower surface of the bottom cell

[0123] Prepare a diffusion mask layer on the poly surface of the bottom cell surface. The mask layer can be a single layer of silicon nitride, silicon oxynitride, silicon oxide, or a composite layer of two or three of these three materials. The total thickness of the mask layer is 10 - 100 nm. This fully protects the phosphorus doped on the upper surface of the bottom cell in step 4 from passing through the polysilicon layer and the tunneling oxide layer and doping into the p-poly on the bottom cell surface during the preparation process, reducing the impact on the performance of the bottom cell.

[0124] 4. Prepare an n+poly doped layer on the upper surface of the bottom cell

[0125] Use a high-temperature doping annealing equipment or PECVD method to perform phosphorus doping and annealing treatment on the polysilicon layer.

[0126] Tube-type high-temperature doping equipment: Use phosphorus oxychloride diffusion source, and control the high-temperature doping promotion temperature at about 800 - 1000 °C. Considering that too long high-temperature doping time is likely to cause the passivation effect of polysilicon to deteriorate, the high-temperature promotion time of phosphorus doping (above 850 °C) is controlled within the range of 30 - 100 min.

[0127] 5. Clean the bottom cell

[0128] Use a chain cleaning equipment, with a 1% - 30% HF solution, and the etching time is 20 - 500 s to clean both sides of the bottom cell. Remove the mask layer on the lower surface of the bottom cell in steps 3 and 4 and the PSG oxide layer that is deposited on the lower surface and the periphery of the bottom cell during the preparation of the n+poly doped layer. Then perform an alkali cleaning on both sides of the bottom cell. The alkali solution uses sodium hydroxide or potassium hydroxide solution, and the concentration is controlled within the range of 0.5% - 5%. Remove the n+ doped layer on the lower surface of the bottom cell, and then use a 1% - 30% HF solution to clean the PSG layer on the upper and lower surfaces of the bottom cell.

[0129] 6. Secondary growth of poly layer on both sides of the bottom cell

[0130] Use an LPCVD equipment, introduce gases such as silane and nitrogen, and prepare a poly layer on both sides of the bottom cell with a thickness of 1 nm - 100 nm.

[0131] 7. p-poly doping on both sides of the bottom cell

[0132] Use a high-temperature tube-type equipment, introduce boron source and nitrogen gas, and prepare a poly layer on both sides of the bottom cell with a thickness of 1 nm - 100 nm.

[0133] Use a high-temperature tube-type equipment, introduce boron source and nitrogen gas, control the temperature within the range of 800 - 1000 °C, perform double-sided boron doping on the bottom cell, and form a tunneling layer and a P-poly doped layer on the upper and lower surfaces of the bottom cell respectively.

[0134] 8. Clean both sides of the bottom cell to remove BSG

[0135] Use an HF solution with a concentration of 1%-49% by mass to clean the borosilicate glass generated on the surface of the bottom cell during the process of step 7.

[0136] 9. Grow aluminum oxide on the lower surface of the bottom cell.

[0137] Use PECVD or ALD equipment to grow aluminum oxide on the back surface of the bottom cell. The thickness of the aluminum oxide is controlled at 2.0 nm.

[0138] 10. Grow a silicon oxide layer on the lower surface of the bottom cell

[0139] Use PECVD equipment to introduce silane, ammonia, nitrous oxide, and nitrogen gas sources to carry out a chemical reaction in a high-temperature and low-pressure environment to grow a silicon oxide layer on the lower surface of the bottom cell. The silicon oxide layer is prepared by depositing silicon nitride, silicon oxynitride, silicon oxide, or a composite layer of two or three of these three dielectric layers.

[0140] 11. Prepare the hole transport layer (HTL) on the front surface of the bottom cell

[0141] The HTL can be prepared by methods such as evaporation, sputtering, RPD, spin coating, and slot die coating. The hole transport layer material can be selected from organic macromolecular materials, organic small molecule materials, SAM layer materials, or inorganic materials (such as nickel oxide, etc.).

[0142] 12. Prepare the perovskite layer.

[0143] The perovskite layer can be prepared using 3D, 2D structural type materials or 3D, 2D stacked composite type structural materials; the thickness is controlled at 400 nm.

[0144] 13. Sequentially prepare the electron transport layer, metal conductive layer, top cell electrode, and bottom cell electrode layer of the top cell,

[0145] The electron transport layer can be made of one or more of C60, PCBM, BCP, or materials such as tin oxide.

[0146] The metal conductive layer can be selected from one or more composite layer materials of TCO (FTO, ITO, IZO, AZO, IWO) for preparation. The preparation method can be thermal evaporation, sputtering, or RPD method.

[0147] Through mask pattern design, use evaporation, thermal evaporation, sputtering, or RPD method to prepare the top cell electrode. The electrode material includes one or more composite laminated materials of gold, silver, copper, bismuth, or materials such as silver-coated copper. Or through screen printing, combined with low-temperature metallization paste, carry out electrode printing and drying sintering to complete the preparation of the top cell electrode.

[0148] Grow a metal electrode on the lower surface of the bottom cell. The preparation method of the metal electrode can use evaporation coating method or low-temperature paste screen printing and drying method.

[0149] The metal electrode material can be one or a mixture of gold, silver, and copper.

[0150] Comparative example:

[0151] 1. Clean the original silicon wafer and texture the bottom cell ( Figure 3a and Figure 3b )

[0152] Use a general cleaning and texturing process. Control the mass concentration of strong sodium hydroxide at about 1.0%-2.5%, mix with a certain proportion of additive solution (commonly used additive solution for texturing), control the temperature at 80-85°C, control the etching time at about 450s-600s, control the pyramid height at 1.0-3.0μm, and control the integral monochromaticity rate in the range of 8%-20%.

[0153] 2. Prepare the single-sided tunneling oxide layer of the bottom cell

[0154] 3. Boron dope the bottom cell and perform an annealing process to prepare the P-poly layer

[0155] As Figure 16 and Figure 17 shown, use vacuum equipment such as high-temperature LPCVD or PECVD, and through gaseous sources of oxygen, silane, and hydrogen, carry out chemical reactions in a high-temperature environment to grow a tunneling oxide layer of a certain thickness ( Figure 16 ) and a p-type doped polysilicon dielectric layer (P-poly layer) ( Figure 17 ); control the thickness of the p-type doped polysilicon at 20-150nm and grow polysilicon on one side. The tunneling oxide layer can be silicon oxide, silicon oxynitride, or a composite layer of both, with a thickness of 1.0-3.0nm. The tunneling oxide layer can be prepared by LPCVD, ALD, PECVD, etc.

[0156] After growing the polysilicon dielectric layer, perform annealing, and a BSG (borosilicate glass) layer is obtained on the upper surface of the polysilicon dielectric layer.

[0157] 4. Clean the BSG dielectric layer on the bottom cell with hydrofluoric acid

[0158] As Figure 18 shown, use chain cleaning, mix with a 1%-49% HF solution, and etch for 20-500S to clean the BSG dielectric layer coated on the upper surface of the bottom cell. After HF cleaning, use DI water to clean for 100-300S and perform drying treatment.

[0159] 5. Remove the overcoating on the upper surface of the bottom cell (remove the overcoating on the N+ side)

[0160] As Figure 19 shown, use a sodium hydroxide solution with a concentration in the range of 0.5% - 3%, in combination with an additive, and the cleaning and etching time is about 100 - 500 s. Then use an HF solution with a concentration controlled within the range of 1% - 10% to clean for 100 - 200 s, and then perform a water washing treatment to clean the p-poly, SiO2 (silicon dioxide), and SiOxNy (silicon oxynitride) layers plated around the upper surface of the bottom cell.

[0161] 6. Grow a tunneling oxide layer and a poly layer on the upper surface of the bottom cell

[0162] 7. Perform poly doping and annealing treatment on the upper surface of the bottom cell (single-sided doping on the upper surface of the bottom cell) as Figure 20 shown.

[0163] 8. Use HF to clean the lower surface and the upper surface PSG and the plated n+poly of the bottom cell to obtain the bottom cell structure as shown in Figure 21a and 21b shown.

[0164] Use a chain wet etching equipment. First, use an HF solution (concentration 1% - 10%, time 10 - 200 s, normal temperature) to remove the PSG layer on the lower surface of the bottom cell, and then use a sodium hydroxide solution (concentration 0.5% - 5%, time 30 - 300 s, temperature 65 - 80 °C) to remove the plated n+poly layer on the lower surface of the bottom cell.

[0165] 9. Dope and grow a p+poly layer on the upper surface of the bottom cell, and perform an annealing process on the poly layer, as Figure 22 shown:

[0166] Use a PECVD or LPCVD equipment to prepare a p+poly layer on the upper surface of the cell and perform an annealing treatment. Such as a tube-type high-temperature doping equipment: (Use boron trichloride and boron tribromide diffusion sources, and control the high-temperature doping promotion temperature at about 800 - 1000 °C. Considering that too long high-temperature doping time is likely to lead to a poor passivation effect of polysilicon, the high-temperature doping promotion time (850 - 950 °C) is controlled within the range of 10 - 100 min.

[0167] 10. Perform a secondary cleaning on the lower surface of the bottom cell to remove the plated layer to obtain the bottom cell structure as shown in Figure 23a shown:

[0168] Use a chain equipment to perform an HF cleaning on the lower surface of the bottom cell. Control the concentration of hydrofluoric acid within the range of 2% - 49%, and the time is controlled within 10 - 50 s. Then use a sodium hydroxide or potassium hydroxide solution with a concentration controlled within the range of 0.2% - 3.0% and the etching time is controlled within the range of 10 - 300 s to remove the p-poly layer on the lower surface of the bottom cell.

[0169] 11. Clean the BSG dielectric layers on the upper and lower surfaces of the bottom cell with hydrofluoric acid. For the bottom cell structure as shown in Figure 23b , use a chain or tank wet etching equipment to immerse the bottom cell in an HF solution. Use an HF solution with a concentration in the range of 1% - 50% to clean and etch the BSG dielectric layers on the upper and lower surfaces of the bottom cell. Control the time within the range of 10 - 100 s.

[0170] Grow an alumina dielectric layer on the lower surface of the bottom cell using PECVD or ALD equipment to obtain the bottom cell structure as shown in Figure 24 .

[0171] Through a high - temperature vacuum ALD (Atomic Layer Deposition) equipment, introduce two gaseous sources, TMA (TrimethylAluminum) and pure water, at a temperature of 100 - 300 °C to grow an alumina dielectric layer with a thickness of 1.0 - 3.0 nm;

[0172] Through a high - temperature vacuum PECVD equipment, introduce silane, ammonia, and nitrous oxide gaseous sources, and oxygen at 450 - 600 °C.

[0173] 12. Use PECVD equipment to grow a silicon oxide layer on the lower surface of the bottom cell. The silicon oxide layer is a single dielectric layer of silicon nitride, silicon oxynitride, or silicon oxide, or a composite dielectric layer containing two or three of them. Grow the medium layer to a thickness of 80 nm to complete the preparation of the bottom cell and obtain the bottom cell as shown in Figure 25 .

[0174] 13. As shown in Figure 26 , grow a top cell on the bottom cell. The structure of the top cell is a PIN structure (the P+ emitter of the bottom cell is below); among them, the PIN structure of the perovskite cell of the top cell is successively a hole - transporting layer (or a hole - transporting layer, Sam layer), a perovskite layer, an electron - transporting layer, and a metal electrode. The preparation methods of each dielectric layer of the top cell can adopt the current mainstream preparation methods of perovskite cells.

[0175] For example, for the hole - transporting layer: methods such as slot - die coating, spin - coating, vacuum evaporation, and magnetron sputtering can be used for preparation. The hole - transporting layer can use materials such as NiOx (nickel oxide), PTAA (poly(triarylamine)), PEDOT:PSS (poly(3,4 - ethylenedioxythiophene) - polystyrene sulfonate), CuI (copper iodide), and Cu2O (copper oxide).

[0176] For example, for the perovskite layer: it can be prepared by using a slot-die coating method, a spin-coating method, a one-step vacuum evaporation method, or a two-step method combining vacuum evaporation with a slot-die coating method. The perovskite layer has a chemical formula of ABX3, where A is one or more of methylammonium, formamidinium, Cs (cesium), and Rb (rubidium); B is Pb or Sn; and X is one or more of I (iodine), Br (bromine), and Cl (chlorine).

[0177] Electron transport layer: It can be prepared by using a slot-die coating method, a spin-coating method, or a vacuum evaporation method.

[0178] The electron transport layer can be an organic or inorganic material such as SnO2 (tin oxide), ZnO (zinc oxide), C60 (fullerene), PCBM ([6,6]-phenyl-C61-butyric acid methyl ester), etc.

[0179] Metal conductive oxide layer: It can be prepared by using a vacuum evaporation method, radio frequency sputtering, or an RPD method. One or more composite layers of common materials such as ITO, IZO, AZO, and IWO are acceptable.

[0180] 14. A metal electrode is grown on the lower surface of the bottom cell. The preparation method of the metal electrode can use an evaporation method or a low-temperature paste screen printing and drying method.

[0181] The metal electrode material can be one or a mixture of gold, silver, and copper.

[0182] Comparative Example 2:

[0183] The first 7 steps are the same as those in Comparative Example 1 and will not be described here. After N+ surface doping and annealing, the structure diagram is as Figure 20 shown.

[0184] 8. HF cleaning of the PSG on the P+ surface of the bottom cell

[0185] Use an HF solution with a mass concentration of 1% - 10% to clean the phosphosilicate glass (PSG) generated on the surface of the bottom cell during the process of Step 7 for 15 - 100 seconds.

[0186] 9. Cleaning the bypass plating layer on the P+ surface of the lower surface of the bottom cell (formed in Step 7)

[0187] Use a NaOH solution with a mass concentration of 0.5% - 5%, combined with a bypass plating removal additive (any commonly used bypass plating removal additive on the market), clean for 50 - 400 seconds at a temperature controlled at 60 - 75°C to clean the n+poly bypass plating layer generated on the surface of the bottom cell during the process of Step 7, and obtain the structure as Figure 27 shown.

[0188] 10. Clean the PSG (phosphosilicate glass) and BSG (borosilicate glass) dielectric layers on the upper and lower surfaces of the bottom cell with HF.

[0189] Use an HF solution with a mass concentration of 1% - 49% to clean the PSG and BSG dielectric layers on the upper and lower surfaces of the bottom cell for 50 - 300 s, obtaining the structure as Figure 28 shown.

[0190] 11. Grow Al2O3 on the lower surface of the bottom cell

[0191] Use PECVD or ALD equipment to grow alumina on the back of the bottom cell. The thickness of the alumina is controlled at 1 - 3 nm.

[0192] 12. Grow a silicon oxide layer on the lower surface of the bottom cell

[0193] Use PECVD equipment, introduce silane, ammonia, nitrous oxide, and nitrogen gas sources, and carry out a chemical reaction in a high - temperature and low - pressure environment to grow a silicon oxide layer on the lower surface of the bottom cell. The silicon oxide layer is prepared by depositing silicon nitride, silicon oxynitride, silicon oxide, or a composite layer of two or three of these three dielectric layers.

[0194] 13. Prepare the composite connection layer of the tandem cell

[0195] For the composite connection layer conductor, one or more composite layer materials selected from TCO (FTO, ITO, IZO, AZO, IWO) can be used for preparation. The preparation method can adopt thermal evaporation, sputtering method, or RPD method.

[0196] 14. Prepare the top cell, and sequentially prepare the hole - transporting layer, perovskite cell, electron - transporting layer, and metal conductive layer of the top cell.

[0197] For example, for the hole - transporting layer: it can be prepared by methods such as slot - die coating, spin - coating, vacuum evaporation, and magnetron sputtering. The hole - transporting layer can use materials such as NiOx, PTAA, PEDOT:PSS, CuI, and Cu2O.

[0198] For example, for the perovskite layer: it can be jointly prepared by methods such as slot - die coating, spin - coating, one - step vacuum evaporation, or two - step method combining vacuum evaporation and slot - die coating. The perovskite layer has the ABX3 structural formula, where A is one or more of methylamino, formamidinium, Cs, and Rb; B is Pb or Sn; and C is one or more of I, Br, and Cl.

[0199] For the electron - transporting layer: it can be prepared by methods such as slot - die coating, spin - coating, and vacuum evaporation.

[0200] The electron - transporting layer can be organic or inorganic materials such as SnO2, ZnO, C60, and PCBM.

[0201] Metal conductive oxide layer: It can be prepared by vacuum evaporation, radio frequency sputtering or RPD method. One or more composite layers of common materials such as ITO, IZO, AZO, IWO, etc. are acceptable.

[0202] 15. Grow metal electrodes on the surfaces of the bottom cell and the top cell. The preparation method of the metal electrodes can use the evaporation method or the low-temperature paste screen printing and drying method. Obtain the final product, as Figure 29 shown.

[0203] The metal electrode material can be one or a mixture of gold, silver, and copper.

[0204] Table 1: Comparison of process flows

[0205]

[0206]

[0207] Combined with Table 1, compare according to the example and Comparative Example 1: The fragmentation rate in Comparative Example 1 is 0.7%, and the fragmentation rate of the example is 0.4%. It can be clearly seen that the laminated battery made by the method of the present application simplifies the preparation process of the current tunneling crystalline silicon / perovskite laminated battery by 4-5 steps.

[0208] According to the comparison between the example and Comparative Example 2, it can be known that Comparative Document 2 adopts the process of a crystalline silicon / perovskite two-terminal laminated battery (conductive composite layer), and the present invention adopts the process of a crystalline silicon / perovskite two-terminal laminated battery (tunneling junction).

[0209] Along with the trend of reducing the thickness of the crystalline silicon bottom cell, adopting the secondary double-sided poly process preparation method is easy to reduce the breakage rate of semi-finished products during the preparation process of the bottom cell.

[0210] Adopting the secondary double-sided Poly preparation process can achieve the p-poly doping on the lower surface of the bottom cell and the preparation of the tunneling junction between the top cell and the bottom cell at one time. Reduce the upfront equipment investment cost and the product process production cost.

[0211] Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a perovskite crystalline silicon tandem battery, characterized in that: The method comprises preparing a bottom battery and manufacturing a top battery on the upper surface of the bottom battery; wherein the preparation process of the bottom battery comprises: Double-sided texturing, double-sided tunnel oxide layer growth, and double-sided primary polysilicon layer growth are sequentially performed on the upper surface and the lower surface of the silicon wafer; A diffusion mask layer is formed on the primary polysilicon layer on the lower surface of the silicon wafer; Performing phosphorus doping and annealing in sequence on the primary polysilicon layer on the upper surface of the silicon wafer to obtain an N-type base doped polysilicon layer and a phosphorus silicon glass layer; removing the mask layer and the phosphosilicate glass layer; Double-sided growth of a secondary polysilicon layer is performed on the primary polysilicon layer on the lower surface of the silicon wafer after the mask layer is removed and on the N-type base doped polysilicon layer on the upper surface of the silicon wafer; Boron doping is performed on the surface of the secondary polysilicon layer on the upper surface and the lower surface of the silicon wafer to obtain a first P-type base doped polysilicon layer and a second P-type base doped polysilicon layer; An aluminum oxide layer and a silicon oxide layer are sequentially grown on the surface of the second P-type substrate doped polysilicon layer.

2. The method for manufacturing the perovskite crystalline silicon tandem cell according to claim 1, characterized in that: The height of the velvet pyramid of double-sided velvet is 0.05-0.3μm, and the integrated monochrome rate is controlled at 8%-20%.

3. The method for manufacturing the perovskite crystalline silicon tandem cell according to claim 1, characterized in that: The mask layer is one or more of silicon nitride, silicon oxynitride or silicon oxide materials.

4. The method for manufacturing the perovskite crystalline silicon tandem cell according to claim 1, characterized in that: Removing the mask layer and the phosphosilicate glass layer comprises: The mask layer and the phosphorus silicon glass layer are removed by using a chain cleaning method, with an HF solution having a mass concentration of 1% to 30%, and an etching time of 20 to 500 seconds.

5. The method for manufacturing the perovskite crystalline silicon tandem cell according to claim 1, characterized in that: The thickness of the primary polysilicon layer is 20nm-150nm; And / or, the thickness of the secondary polysilicon layer is 1 nm-100 nm.

6. The method for manufacturing the perovskite crystalline silicon tandem cell according to claim 1, characterized in that: Boron doping is performed on the surface of the secondary polysilicon layer on the upper surface and the lower surface of the silicon wafer to obtain a first P-type base doped polysilicon layer and a second P-type base doped polysilicon layer, including: Using high-temperature tubular equipment, a boron source and nitrogen gas are introduced at a temperature of 800-1000°C to dope the secondary polysilicon layer on the upper and lower surfaces of the silicon wafer with boron to obtain a first P-type base-doped polysilicon layer and a second P-type base-doped polysilicon layer.

7. The method for manufacturing a perovskite crystalline silicon tandem cell according to claim 1, characterized in that: After boron doping is performed on the surfaces of the secondary polysilicon layers on the upper surface and the lower surface of the silicon wafer to obtain a first P-type substrate doped polysilicon layer and a second P-type substrate doped polysilicon layer, the method further includes: Annealing the first P-type substrate doped polysilicon layer and the second P-type substrate doped polysilicon layer to form a first borosilicate glass layer and a second borosilicate glass layer on the surfaces of the first P-type substrate doped polysilicon layer and the second P-type substrate doped polysilicon layer, respectively; The first borosilicate glass layer and the second borosilicate glass layer are cleaned and removed using an HF solution with a mass concentration of 1% to 10%.

8. The method for manufacturing a perovskite crystalline silicon tandem cell according to claim 1, characterized in that: A plasma enhanced chemical vapor deposition or atomic layer deposition equipment is used to grow aluminum oxide on the surface of the second P-type substrate doped polysilicon layer, and the thickness of the aluminum oxide is controlled to be 1-3 nm.

9. The method for manufacturing a perovskite crystalline silicon tandem cell according to claim 1, characterized in that: The silicon oxide layer is selected from one or more of silicon nitride, silicon oxynitride or silicon oxide; The thickness of the silicon oxide layer is 80-100 nm.

10. The method for manufacturing a perovskite crystalline silicon tandem cell according to claim 1, characterized in that: A top cell is prepared on the surface of the first P-type substrate doped polysilicon layer.

11. A perovskite crystalline silicon tandem battery prepared by the method according to any one of claims 1 to 10.

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