Data transmission method, device and system

Abstract

The invention discloses a data transmission method, a data transmission device and a data transmission system, which are used for reducing error correction processing time delay in a core particle interconnection system and improving data transmission efficiency. Before a sending end sends data, processing such as ECC coding, interleaving and PAM-N coding of single-bit error correction is carried out on original data, after a receiving end receives the data, processing such as PAM-N decoding, de-interleaving and ECC decoding of single-bit error correction is carried out on the data, and the original data is recovered. According to the invention, error correction can be carried out by using a single-bit error correction technology in the core particle interconnection system, and compared with a multi-bit error correction technology or a retransmission technology, lower time delay and smaller area power consumption can be realized.

Description

A data transmission method, device and system Technical Field The present application relates to the field of electronic technology, and in particular to a data transmission method, device and system. Background Art In a chiplet interconnection system, chiplets can be interconnected through multiple channels and transmit data. For a fixed number of channels, increasing the rate of a single channel can increase the interconnection bandwidth. However, when a certain rate is reached, further increasing the rate will reduce energy efficiency. If a multi-level encoding method is used in the channel, the signal transmission bandwidth can be increased without changing the baud rate. For example, Figure 1 is a schematic diagram of channel transmission with three-level pulse amplitude modulation (Pulse Amplitude Modulation-3, PAM-3) encoding and channel transmission with non-return-to-zero (NRZ) encoding. NRZ encoding can transmit 3 bits of data in the channel using 3 unit intervals (Unit Interval, UI), and PAM-3 encoding can transmit 3 bits of data in the channel using 2 UI. PAM-3 encoding can increase the interconnection bandwidth by 1.5 times compared to NRZ encoding. In the multi-level coding method, if an original bit error of 1UI occurs in the channel, multiple bit errors may be generated after decoding. For example, for PAM-3 coding, 3 bits of data are transmitted every 2 UI in the channel. If an original bit error of 1UI occurs in the channel, 2 to 3 bits of bit errors may be generated after decoding. Therefore, the receiving end needs to correct errors through error correction technology to reduce the bit error rate of the interconnection interface. However, the existing technology generally uses multi-bit error correction technology or retransmission technology for error correction, and the error correction process has a large delay, which affects the data transmission efficiency. Summary of the invention The present application provides a data transmission method, device and system for reducing the error correction processing delay in a chip interconnection system and improving data transmission efficiency. In a first aspect, a data transmission device is provided, which may be a transmitting end or the device is located at the transmitting end, and the device includes: an ECC encoder, which is used to perform single-bit error correction ECC encoding on N groups of data bit streams to obtain N groups of ECC encoded bit streams; wherein each group of data bit streams in the N groups of data bit streams includes M data bits, and the encoded bits in each group of ECC encoded bit streams in the N groups of ECC encoded bit streams include M data bits and P check bits; an interleaver, which is used to read the encoded bits from the N groups of ECC encoded bit streams in a polling manner, reorganized into a first coded bit stream; wherein, every N coded bits in the first coded bit stream is a unit, and the N coded bits in each unit are respectively from different ECC coded bit streams; an IO data distributor is used to distribute each unit in the first coded bit stream to Q IO pins to obtain Q groups of IO data streams; a PAM encoder is used to perform PAM-N encoding on the Q groups of IO data streams to obtain Q groups of PAM coded bit streams; Q IO pins are used to send Q groups of PAM coded bit streams; wherein N, M, P, and Q are positive integers. In the embodiment of the present application, the transmitting end performs single-bit ECC encoding on N groups of data bit streams, and then interleaves the encoded N groups of ECC encoded bit streams to ensure that the N bits in a unit in the interleaved bit stream correspond to different ECCs, and PAM encoding is performed with the unit as the granularity, so that when a bit error occurs in a unit, the error will be dispersed to different ECCs, so that the receiving end can complete multi-bit error correction processing through a single-bit error correction method. Compared with multi-bit error correction technology or retransmission technology, the transmitting end can achieve lower processing delay and smaller area power consumption. In a possible implementation, the device may further include a data grouper, which is used to group the original data bit streams to obtain N groups of data bit streams; and transmit the N groups of data bit streams to the ECC encoder respectively. In this way, the original data bit streams can be grouped into N groups of data bit streams, and the N groups of data bit streams can be encoded with different ECCs, thereby improving the reliability of the solution. In a possible implementation, the data lengths of the IO data streams in the Q groups of IO data streams are the same. In other words, the IO data distributor evenly distributes the units in the first coded bit stream to the Q IO pins. In this way, the parallelism of data processing can be improved, and the data processing efficiency can be further improved. In a possible implementation, the single-bit error correction ECC code includes an extended Hamming code for implementing SEC-DED, such as an optimal minimum odd-weight column code. Of course, this is only an example, and there may be other extended Hamming codes for implementing SEC-DED. In a possible implementation, the value of N is any one of 3, 4, 6, 8 or 16. In this way, single-bit ECC encoding can be implemented in PAM scenarios such as PAM-3, PAM-4, PAM-8, and PAM-16. In a second aspect, a data transmission device is provided, which may be a receiving end or the device is located at the receiving end, and the device includes: Q IO pins, respectively used to receive Q groups of PAM coded bit streams; a PAM decoder, used to perform PAM-N decoding on the Q groups of PAM coded bit streams to obtain Q groups of IO data streams; a first aggregator, used to aggregator the Q groups of IO data streams to obtain a first coded bit stream, wherein each N coded bits in the first coded bit stream is a unit; a deinterleaver, used to read coded bits from each unit of the first coded bit stream, and reorganize them into N groups of ECC coded bit streams; wherein the N coded bits in each unit are respectively allocated to different ECC coded bit streams, and the coded bits in each group of the N groups of ECC coded bit streams include M data bits and P check bits; an ECC decoder, used to perform ECC decoding for single-bit error correction on the N groups of ECC coded bit streams to obtain N groups of data bit streams; wherein N, M, P, and Q are positive integers. In the embodiment of the present application, the receiving end performs PAM-N decoding on the Q-group PAM coded bit stream, and converges and interleaves the decoded IO data stream, so that different coded bits in the same unit are scattered on different ECCs. When a bit error occurs in a unit, the error will be scattered on different ECCs, and the receiving end can use a single-bit error correction method to complete multi-bit error correction processing. Compared with multi-bit error correction technology or retransmission technology, the receiving end can achieve lower processing delay and smaller area power consumption. In a possible implementation, the device may further include: a second aggregator, configured to aggregate N groups of data bit streams into an original data bit stream. Through this implementation, the original data bit stream can be restored, thereby improving the reliability of the solution. In a possible implementation, the data lengths of the IO data streams in the Q group of IO data streams are the same. In one possible implementation, the single-bit error correction ECC encoding includes an extended Hamming code for implementing SEC-DED, such as an optimal minimum odd-weight column code. In a possible implementation, the value of N is any one of 3, 4, 6, 8 or 16. In a third aspect, a data transmission method is provided, comprising: performing single-bit error correction ECC encoding on N groups of data bit streams to obtain N groups of ECC encoded bit streams; wherein each group of data bit streams in the N groups of data bit streams includes M data bits, and the encoded bits in each group of ECC encoded bit streams in the N groups of ECC encoded bit streams include M data bits and P check bits; reading the encoded bits from the N groups of ECC encoded bit streams in a polling manner and reorganizing them into a first encoded bit stream; wherein each N encoded bits in the first encoded bit stream is a unit, and the N encoded bits in each unit come from different ECC encoded bit streams; distributing each unit in the first encoded bit stream to Q IO pins to obtain Q groups of IO data streams; performing PAM-N encoding on the Q groups of IO data streams to obtain Q groups of PAM encoded bit streams; and sending the Q groups of PAM encoded bit streams through the Q IO pins; wherein N, M, P, and Q are positive integers. In a possible implementation manner, the method further includes: grouping the original data bit streams to obtain N groups of data bit streams. In a possible implementation, the data lengths of the IO data streams in the Q group of IO data streams are the same. In one possible implementation, the single-bit error correction ECC encoding includes an extended Hamming code for implementing SEC-DED, such as an optimal minimum odd-weight column code. In a possible implementation, the value of N is any one of 3, 4, 6, 8 or 16. In a fourth aspect, a data transmission method is provided, comprising: receiving Q groups of PAM coded bit streams through Q IO pins; performing PAM-N decoding on the Q groups of PAM coded bit streams to obtain Q groups of IO data streams; aggregating the Q groups of IO data streams to obtain a first coded bit stream, wherein each N coded bits in the first coded bit stream is a unit; reading coded bits from each unit of the first coded bit stream, and reorganizing them into N groups of ECC coded bit streams; wherein the N coded bits in each unit are respectively allocated to different ECC coded bit streams, and the coded bits in each group of the N groups of ECC coded bit streams include M data bits and P check bits; performing single-bit error correction ECC decoding on the N groups of ECC coded bit streams to obtain N groups of data bit streams; wherein N, M, P, and Q are positive integers. In a possible implementation manner, the method further includes: aggregating N groups of data bit streams into an original data bit stream. In a possible implementation, the data lengths of the IO data streams in the Q group of IO data streams are the same. In one possible implementation, the single-bit error correction ECC encoding includes an extended Hamming code for implementing SEC-DED, such as an optimal minimum odd-weight column code. In a possible implementation, the value of N is any one of 3, 4, 6, 8 or 16. In a fifth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium is used to store instructions. When the instructions are executed, the method described in the third aspect or any possible implementation of the third aspect is implemented, or the method described in the fourth aspect or any possible implementation of the fourth aspect is implemented. In a sixth aspect, a computer program product is provided, wherein instructions are stored in the computer program product, which, when executed on a computer, causes the method described in the third aspect or any possible implementation of the third aspect to be executed, or causes the method described in the fourth aspect or any possible implementation of the fourth aspect to be executed. In a seventh aspect, a data transmission system is provided, comprising an apparatus as described in the first aspect or any possible implementation of the first aspect and an apparatus as described in the second aspect or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS FIG1 is a schematic diagram of PAM-3 coded channel transmission and NRZ coded channel transmission; FIG. 2 is a schematic diagram of NRZ encoding; FIG3A is a schematic diagram of a PAM-3 encoding; FIG3B is a schematic diagram showing a single UI error causing multiple bit errors after PAM-3 decoding; FIG4 is a schematic diagram of an application scenario provided in an embodiment of the present application; FIG5 is a schematic diagram of a data transmission system provided in an embodiment of the present application; FIG6A is a schematic diagram of a data processing flow in the data transmission device 01; FIG6B is a schematic diagram of a data processing flow in the data transmission device 02; FIG7 is a schematic diagram of a data transmission device 01 provided in an embodiment of the present application; FIG8 is a schematic diagram of data interleaving provided in an embodiment of the present application; FIG9 is a schematic diagram of IO data distribution provided in an embodiment of the present application; FIG10 is a schematic diagram of another data transmission device 01 provided in an embodiment of the present application; FIG11 is a schematic diagram of another data transmission device 01 provided in an embodiment of the present application; FIG12 is a schematic diagram of a specific data processing example; FIG13 is a schematic diagram of a data transmission device 02 provided in an embodiment of the present application; FIG14 is a schematic diagram of IO data aggregation provided by an embodiment of the present application; FIG15 is a schematic diagram of data deinterleaving provided in an embodiment of the present application; FIG16 is a schematic diagram of another data transmission device 02 provided in an embodiment of the present application; FIG17 is a schematic diagram of another data transmission device 02 provided in an embodiment of the present application; FIG18 is a schematic diagram of a specific data processing example; FIG19 is a schematic diagram of a specific single-bit error correction example. DETAILED DESCRIPTION In order to facilitate understanding of the technical solutions of the embodiments of the present application, some technical terms involved in this article are first introduced below. 1) Pulse Amplitude Modulation (PAM): It is a modulation method in which the amplitude of the pulse carrier changes with the baseband signal. PAM is divided into many types according to the modulation level. For example, for ease of description, in this article, PAM-N can be used to represent N-level pulse amplitude modulation, where N is a positive integer. Level N can represent how many level values ​​there are, for example, in PAM-3, there are three level values: high, medium, and low. 2) Non-Return-to-Zero (NRZ) coding: also known as Pulse Amplitude Modulation-2 (PAM-2) coding, which uses two voltage levels to represent logic 0 and logic 1, such as a positive level representing 1 and a low level representing 0. The difference between it and Return-to-zero (RZ) coding is that it does not need to return to zero, that is, one cycle can be used to transmit data, so that the transmission bandwidth can be fully utilized. Traditional digital signals mostly use NRZ signals, that is, two signal levels are used to represent the 1 and 0 information of digital logic signals, and each symbol period (or UI) can transmit 1 bit of logic information. For example, Figure 2 is a schematic diagram of NRZ coding. 3) Three-level pulse amplitude modulation (PAM-3) coding: 2 ternary level values ​​are used to represent 3 bits of logic information, that is, 3 bits of logic information can be transmitted every two symbol periods. For example, FIG3A is a schematic diagram of a PAM-3 coding, 3 bits have 8 combinations (i.e., 2 to the cube), and two level values ​​have 9 combinations (i.e., 3 to the square), so the latter can cover the former, so two levels can represent 3 bits of logic information, and each level actually contains 1.5 bits of information. Of course, in addition to PAM-3 encoding, there are also multi-level PAM encoding methods such as PAM-4 encoding, PAM-6 encoding, and PAM-8 encoding, which will not be introduced one by one here. 4) Chiplets, also known as core particles or small chips, refer to pre-manufactured chips with specific functions that can be combined and integrated. A type of bare chip (die) that meets specific functions can be packaged together with multiple module chips and underlying basic chips through die-to-die internal interconnection technology to form a system chip. Chips can be interconnected through multiple channels (the specific implementation of the channel can be input and output (IO or I / O) pins) and transmit data, achieving low cost and high yield while improving performance. 5) The terms "system" and "network" in the embodiments of the present application can be used interchangeably. "At least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, or b, or c, or a and b, or b and c, or a and c, or a and b and c. Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish multiple objects, and are not used to limit the order, timing, priority or importance of multiple objects. For example, the first priority criterion and the second priority criterion are only used to distinguish different criteria, and do not indicate the difference in the content, priority or importance of the two criteria. In addition, the terms "including" and "having" in the embodiments, claims and drawings of the present application are not exclusive. For example, a process, method, system, product or device including a series of steps or modules is not limited to the listed steps or modules, and may also include steps or modules that are not listed. See Figure 4, which is a schematic diagram of an application scenario provided in an embodiment of the present application. This scenario illustrates a core particle interconnection system, including at least two core particles. It can be understood that Figure 4 illustrates two core particles, namely core particle A and core particle B, but is not limited to this. Core particles can be interconnected and transmit data through one or more channels. For example, Figure 4 takes the example of core particle A sending data to core particle B, that is, core particle A is the sending end and core particle B is the receiving end. It can be understood that the interconnection channel between core particles is based on the channel within the package, which can achieve a lower bit error rate than the inter-chip interconnection channel. The industry generally defines the bit error probability (Bit Error Ratio, BER) before error correction as less than 1e-15. The transmission delay in the core particle interconnection system affects the overall performance of the system. When correcting the bit error, the impact on the transmission delay should be reduced. It is necessary to use the smallest possible implementation cost to improve the bit error rate of the interconnection transmission. In the chip interconnection system, multi-level coding can be used to encode data to increase the channel interconnection bandwidth. However, under the multi-level coding method, if an original bit error of 1UI occurs in the channel, multiple bit errors may be generated after decoding. For example, for PAM-3 coding, 3 bits of data are transmitted every 2 UI in the channel. If an original bit error of 1UI occurs in the channel, 2 to 3 bits of bit errors may be generated after decoding. See Figure 3B, which is a schematic diagram of a single UI error causing multiple bit errors after PAM-3 decoding. The receiving end samples the level of each UI, 00 represents a low level (-1), 01 represents an intermediate level (0), and 11 represents a high level (1). The levels of two consecutive UIs can restore three data bits. For example, the original data sent by the transmitting end is 010, and the correct levels of the two UIs should be 00 (low level) 01 (intermediate level). Assume that the level sampling error of the first UI becomes the intermediate level 01, that is, the intermediate level of the two UIs is received. At this time, it coincides with the code pattern of sending "101". PAM-3 will decode it as "101", which has a 3-bit error with the correct "010" data. Therefore, the receiving end needs to perform error correction to reduce the bit error rate of the interconnection interface. In one implementation, Reed-Solomon (RS) (450, 406) codes can be used to detect and correct errors in the chip interconnection system. In RS coding technology, 9 bits are used as a signal (symbol), and 44 symbol check bits are added to the original data of 406 symbols, supporting error correction of up to 22 symbol errors. At the transmitting end, 45 81-bit data blocks and 1 9-bit Operations Administration and Maintenance (OAM) information constitute 406 symbols. After RS ​​(450, 406) coding processing, 44 symbols are added, and a total of 450 symbol data is generated. At the receiving end, after the 450 symbol data is processed by RS (450, 406) decoding, the error-corrected original data of 406 symbols is output, and 45 81-bit data blocks and 1 9-bit OAM are restored. In this implementation method, the RS encoding and decoding process is complex, resulting in a large processing delay (in the order of dozens of ns), which cannot meet the low-delay requirements of the chiplet interface interconnection. In another implementation method, the BCH code (Bose-Chaudhuri-Hocquenghem codes) can be used to detect and correct errors in the data of the chiplet interconnection system. BCH encoding is often used to correct multiple random errors and can be designed according to the number of bits to be corrected and the length of the information bits. For BCH(n,k,t) encoding, n is the length of the codeword, t is the number of error-correcting bits, k is the number of information bits, n = 2^m - 1, and the number of parity bits to be added n - k = mt. Among them, the value of m is used to calculate the number of parity bits to be added in the primitive BCH code (the BCH code with a code length of n = is called the primitive BCH code) and the code length of the non-primitive BCH code (the BCH code with a code length as a factor is called the non-primitive BCH code). For example: Instance of primitive BCH code: BCH(8191, 7151, 80) means the code length n = 8191, the information bit k = 7151, and the correctable bit t = 80. Given n, t, and the primitive BCH code, the process of calculating t can be: Since 8191 = 2^13 – 1, that is, m = 13; the number of parity bits to be added n - k = mt = 13 * 80 = 1040; the effective information bit k = n – 1040 = 8191 – 1040 = 7151; Instance of non-primitive BCH code: BCH(9312, 8192, 80), which means the code length n = 9312, the information bit k = 8192, and the correctable bit t = 80. Given k, t, and the non-primitive BCH code, the process of calculating n is: First, determine m. Since k = 8192 = 2**13, generally speaking, n - k < k, and n <= 2**m - 1, it can be deduced that m = 14; the number of parity bits to be added n - k = mt = 14 * 80 = 1120; the effective information bit n = k + 1120 = 8192 + 1120 = 9312. For the chiplet interconnection system based on PAM-3 encoding, at least 2-bit errors need to be corrected. For example, BCH(255, 239, 2) can correct 2 bits, the number of information bits is 239, m = 8, and the added parity bits are 255 - 239 = 8 * 2 = 16. In this implementation method, at least 2-bit errors need to be corrected, the BCH decoding process is complex, and the processing delay is still relatively large (in the order of ns). In another implementation, when data transmission errors occur, data retransmission can be used to correct the errors. At the sending end, a sequence number and a cyclic redundancy check (CRC) are added to the data, and the sent data is stored in the sending buffer; after receiving the data, the receiving end verifies the data bits through CRC, and when the data is correct, it sends an acknowledgment (ACK) response to the sending end, and the sending end releases the data in the sending buffer; when the data is erroneous, the receiving end sends a negative acknowledgement (NACK) response to the sending end with the corresponding sequence number, and carries the corresponding sequence number information, and the sending end resends the message corresponding to the sequence number. In this implementation, each sent message needs to be cached, the receiving end needs to return ACK / NAK information in real time, a bidirectional link must be used, and the transmission bandwidth of the reverse path is occupied, the implementation cost and power consumption are high; and when data errors occur, the sending end needs to retransmit to correct the errors, and the processing delay is still large. It can be seen that the use of multi-bit error correction technology or retransmission technology for error correction has a large processing delay and cannot meet the low-latency requirements of chip interface interconnection. In view of this, a technical solution of an embodiment of the present application is provided for implementing error correction using single-bit error correction technology in a chip interconnection system, which has lower latency and smaller area power consumption than multi-bit error correction technology or retransmission technology. Referring to FIG. 5 , which is a schematic diagram of a data transmission system provided in an embodiment of the present application, the system includes a data transmission device 01 and a data transmission device 02 . The data transmission device 01 is a transmitting end or a device located at the transmitting end, such as the core A in the scenario shown in Figure 4. The data transmission device 01 includes an error correction code (ECC) encoder 11, an interleaver 12, an IO data distributor 13 and a PAM encoder 14. The data transmission device 02 is a receiving end or a device located at the receiving end, for example, the core B in the scenario shown in FIG4 . The data transmission device 02 includes a PAM decoder 21 , a first converger 22 , a deinterleaver 23 , and an ECC decoder 24 . The data transmission system also includes multiple IO pins, each IO pin includes multiple parts, one part is distributed in the data transmission device 01, one part is distributed in the data transmission device 02, and another part is connected between the data transmission device 01 and the data transmission device 02, serving as an interconnection channel between the data transmission device 01 and the data transmission device 02, and is used to transmit data sent by the data transmission device 01 to the data transmission device 02. The data transmission device 01 is used to perform single-bit ECC encoding, interleaving and PAM-N processing on the original data, and then transmit the processed data stream through the channel to the data transmission device 02. The data transmission device is used to perform PAM-N decoding, deinterleaving and single-bit ECC decoding on the received data to restore the original data. The data processing scheme in the data transmission device 01 is introduced below. See FIG. 6A , which is a schematic diagram of the data processing flow in the data transmission device 01 . S601A, the ECC encoder 11 performs single-bit error correction ECC encoding on N groups of data bit streams to obtain N groups of ECC encoded bit streams. The value of N is a positive integer greater than 2, for example, the value of N is any one of 3, 4, 6, 8 or 16. Each of the N groups of data bit streams includes M data bits, and the coded bits in each of the N groups of ECC coded bit streams include M data bits and P check bits. It can be understood that the number of groups of the data bit stream in step S601A (ie, N) corresponds to the encoding method of the PAM encoder 14 in step S604A. For example, if the encoding method of the PAM encoder 14 is PAM-3 encoding, then N=3, and if the encoding method of the PAM encoder 14 is PAM-4 encoding, then N=4. Optionally, the single-bit error correction ECC encoding includes an extended Hamming code for implementing single-error correction and double-error detecting (SEC-DED). For example, the optimal minimum odd-weighted column code, or other extended Hamming codes for implementing SEC-DED, are not limited in this application. Taking the optimal minimum odd-weighted column code as an example, the encoding method is PAM-3 encoding, and each group of data bit streams includes 120 data bits. Then, 8 bits of check bits can be provided for each group of data bit streams, and each group of ECC encoded bit streams outputs 128 bits. In the embodiment of the present application, different ECC coded bit streams (or data bit streams) correspond to different error correction codes, namely ECC (specifically, for example, an optimal minimum odd-weighted column code). Optionally, the number of ECC encoders 11 is N, as shown in FIG7 , and the N ECC encoders 11 are respectively used to perform single-bit error correction ECC encoding on N groups of data bit streams, and different ECC encoders 11 use different ECCs to implement different ECC encoding bit streams corresponding to different ECCs. For example, ECC encoder 11-1 is used to perform single-bit error correction ECC encoding on the first group of data bit streams to obtain the first group of ECC encoding bit streams, ECC encoder 11-2 is used to perform single-bit error correction ECC encoding on the second group of data bit streams to obtain the second group of ECC encoding bit streams, ..., ECC encoder 11-N is used to perform single-bit error correction ECC encoding on the Nth group of data bit streams to obtain the Nth group of ECC encoding bit streams. S602A: The interleaver 12 reads coded bits from N groups of ECC coded bit streams in a polling manner and reassembles them into a first coded bit stream. It can be understood that the interleaver 12 reads the coded bits from the N groups of ECC coded bit streams by polling, which means that multiple read operations are performed on the N groups of ECC coded bit streams, wherein the process in which the interleaver 12 performs a read operation on each group of ECC coded bit streams in the N groups of ECC coded bit streams is one round. Specifically, the interleaver 12 reads 1 bit of data from each group of ECC coded bit streams in the N groups of ECC coded bit streams in each round, that is, each round reads a total of N bits, and the N bits come from the N groups of ECC coded bit streams; when the interleaver 12 completes one round of reading operations, it performs the next round of reading operations until all the coded bits in the N groups of ECC coded bit streams are read. Optionally, the order in which the interleaver 12 reads the coded bits from the N groups of ECC coded bit streams in each round is the same, and this order can be called the first polling order. Taking N=3 as an example, for example, the first polling order is the first group of ECC coded bit streams, the second group of ECC coded bit streams, and the third group of ECC coded bit streams. Of course, this is only an example and not a limitation. Since the N bits read in each round come from N groups of ECC coded bit streams, the first coded bit stream can be composed of N coded bits as a unit in bit order, and the N coded bits in each unit come from different ECC coded bit streams. Taking N=3 as an example, the 1st to 3rd bits are a unit (the 1st to 3rd bits come from 3 groups of ECC encoded bit streams respectively), the 4th to 6th bits are a unit (the 4th to 6th bits come from 3 groups of ECC encoded bit streams respectively), and so on, and so on. Further optionally, the relative positions of the N coded bits read by the interleaver 12 in each round in the ECC coded bits to which they belong are the same. Referring to FIG8 , taking N=3, and the first polling order being the first group of ECC encoded bit streams, the second group of ECC encoded bit streams, and the third group of ECC encoded bit streams as an example: the first group of ECC encoded bit streams is A_0 / A_1 / A_2…, the second group of ECC encoded bit streams is B_0 / B_1 / B_2…, the third group of ECC encoded bit streams is C_0 / C_1 / C_2…. In the first round, the interleaver 12 sequentially reads the first bit (i.e., A_0) in the first group of ECC coded bit streams, the first bit (i.e., B_0) in the second group of ECC coded bit streams, and the first bit (i.e., C_0) in the third group of ECC coded bit streams; in the second round, the interleaver 12 sequentially reads the second bit (i.e., A_1) in the first group of ECC coded bit streams, the second bit (i.e., B_1) in the second group of ECC coded bit streams, the second bit (i.e., C_1) in the third group of ECC coded bit streams, ..., and repeats this cycle to finally obtain the first coded bit stream A_0 / B_0 / C_0 / A_1 / B_1 / C_1...A_N / B_N / C_N. It can be understood that the process of the interleaver reorganizing the coded bits read from N groups of ECC coded bit streams into the first coded bit stream is essentially a process of rearranging the coded bits, so this process can also be described as "interleaving". S603A, the IO data distributor 13 distributes each unit in the first coded bit stream to Q IO pins to obtain Q groups of IO data streams. It can be understood that the IO data distributor 13 distributes the bits in the first coded bit stream based on the unit granularity, so that it can be ensured that the N bits distributed to the Q IO pins (i.e., the N bits in each unit) come from different ECC coded bit data streams and correspond to different ECCs. Continuing with the first coded bit stream shown in FIG. 8 , FIG. 9 is a schematic diagram of distributing each unit in the first coded bit stream to Q IO pins. Optionally, the IO data distributor 13 evenly distributes each unit in the first coded bit stream to Q IO pins. In other words, the data lengths of each IO data stream in the Q groups of IO data streams are the same. In this way, the parallelism of data processing can be improved, and the data processing efficiency can be further improved. S604A, the PAM encoder 14 performs PAM-N encoding on the Q groups of IO data streams to obtain Q groups of PAM encoded bit streams. Specifically, the PAM encoder 14 encodes at a unit granularity. Taking N=3 as an example, each unit includes 3 bits, which come from three different ECC encoded data streams and correspond to different ECCs. The PAM-3 encoding method is adopted, and the 3-bit encoding of each unit can be represented by using 2 ternary level values. The specific encoding principle can refer to the relevant content shown in the previous Figure 3A, which will not be repeated here. Optionally, as shown in FIG10 , each IO pin corresponds to a PAM encoder 14 , that is, the number of IO pins is Q, the number of PAM encoders 14 is also Q, and each PAM encoder is used to perform PAM-N encoding on the IO data stream on the IO pin corresponding to the PAM encoder. Finally, Q groups of PAM encoded bit streams are sent out through Q IO pins respectively. It can be understood that N, M, P, and Q are all positive integers. Optionally, as shown in FIG. 11 , the data transmission device 01 further includes a data grouper 15 for grouping the original data bit stream to obtain N groups of data bit streams; and transmitting the N groups of data bit streams to the ECC encoder 11 . To understand the above process more clearly, here is another complete example: Taking 120*3=360 bits of original data as an example, the data transmission device 01 and the data transmission device 02 are interconnected through 64 IO pins (i.e., IO 0 to IO 63). The data transmission device 01 needs to perform grouping, ECC encoding, interleaving, IO data distribution, and PAM-3 encoding on the original data before sending the data. Referring to FIG. 12 , the specific processing flow is as follows: The data grouper 15 divides the 360-bit original data (represented as D[120*3-1:0] in Figure 12, referring to 360 bits of data from 0 to 120*3-1) into three groups on average, each with 120 bits, namely DA[119:0], DB[119:0], and DC[119:0]. Each grouped data corresponds to an ECC encoder 11, corresponding to ECC encoder A, ECC encoder B, and ECC encoder C, respectively. Each ECC encoder 11 uses the minimum odd-weight column code as the ECC encoding algorithm, adds 8-bit check bits (C[7:0]) to each group of 120-bit input data (D[119:0]), and outputs a total of 128 bits of data. The calculation formula of ECC encoding is: {C[7:0], D[119:0]} = D[119:0]*G, where G is a 120*128-bit matrix, which is composed of a 120*120 unit matrix I2 and a 8*120 transposed matrix H1, that is: G=[I2,H1 T ]; The interleaver 12 reorganizes the three groups of 128-bit data ({CC[7:0],DC[119:0]},{CB[7:0],DB[119:0]},{CA[7:0],DA[119:0]}) output by the three ECC encoders 11 into a group of parallel data, i.e., the first coded bit stream. The specific interleaving method is to poll the three groups of data and take 1 bit from the group each time, and so on. The final output data is: CC[7], CB[7], CA[7], ..., CC[0], CB[0], CA[0], DC

[0119] ,DB

[0119] ,DA

[0119] ,…,DC[1],DB[1],DA[1],DC[0],DB[0],DA[0]. The IO data distributor 13 distributes the interleaved data in units of 3 consecutive bits to the 64 IO pins in bit order, and each IO pin transmits 6 bits of IO data. For example: IO 0: DC

[0064] ,DB

[0064] ,DA

[0064] ,DC[0],DB[0],DA[0]; IO 1: DC

[0065] ,DB

[0065] ,DA

[0065] ,DC[0],DB[0],DA[0]; … IO 63: CC[7], CB[7], CA[7], DC

[0063] , DB

[0063] , DA

[0063] . It can be understood that the above distribution methods are only examples and not specific limitations. The PAM-3 encoder 14 performs PAM-3 encoding on the data in each IO pin, so that three data bits are transmitted using two UIs, thereby obtaining 64 groups of PAM encoded bit streams, each of which includes four bits. It should be noted that the above only describes several key components in the data transmission device 01 and the methods for executing the same. In practical applications, the data transmission device 01 may also include other components, and the data transmission device 01 may also perform other processing on the data before sending the data. For example, before executing PAM encoding, the data transmission device 01 may also perform scrambling, repairing, and other processing on the data before PAM encoding, and after executing PAM encoding, it may also perform parallel and serial processing on the data after PAM encoding, etc., and this application does not limit this. In addition, in actual applications, the positions of some components in the data transmission device 01 can also be swapped. For example, the IO data distributor 13 can also be set after the PAM encoder 14, that is, the data transmission device 01 can first perform PAM-N encoding on the first encoded bit stream, and then perform IO distribution on the PAM-N encoded data. The following introduces the data processing solution in the receiving end (ie, the data transmission device 02). See FIG. 6B , which is a schematic diagram of the data processing flow in the data transmission device 02 . S601B, the PAM decoder 21 performs PAM-N decoding on the Q groups of PAM encoded bit streams to obtain Q groups of IO data streams. Specifically, the PAM decoder 21 obtains Q groups of PAM coded bit streams from the Q IO pins respectively, and the Q groups of PAM coded bit streams are sent by the data transmission device 01 to the Q IO pins. S601B is the opposite process of S604A above. The decoding method of the PAM decoder 21 corresponds to the encoding method of the PAM encoder 14 in the data transmission device 01. The value of N is a positive integer greater than 2, for example, the value of N is any one of 3, 4, 6, 8 or 16. For example, if the encoding method of the PAM encoder 14 is PAM-3 encoding, then the decoding method of the PAM decoder 21 is PAM-3 decoding, that is, the level value of every 2 UI in the PAM encoded bit stream is decoded into 3 bits of data. The specific decoding principle can refer to the relevant content shown in Figure 3A above, which will not be repeated here. Optionally, as shown in FIG13 , each IO pin corresponds to a PAM decoder 21 , the number of IO pins is Q, the number of PAM decoders 21 is also Q, and each PAM decoder is used to perform PAM-N decoding on the IO data stream on the IO pin corresponding to the PAM decoder. Optionally, the lengths of each group of PAM coded bit streams in the Q groups of PAM coded bit streams are the same. S602B: The first aggregator 22 aggregates the Q groups of IO data streams to obtain a first coded bit stream, where every N coded bits in the first coded bit stream constitute a unit. S602B is the opposite process of S603A above. Specifically, the first aggregator 22 can take each Q group of IO data streams as a unit and sequentially reassemble the units in the Q group of IO data streams into the first coded bit stream, with each consecutive N coded bits as a unit. It can be understood that the order in which the first aggregator 22 reorganizes the units here corresponds to the order in which the IO data distributor 13 in the data transmission device 01 distributes the units. For example, when the order in which the IO data distributor 13 distributes the units in the first coded bit stream to the Q IO pins is the order shown in FIG9 , the order in which the first aggregator 22 reorganizes the units in the Q groups of IO data streams into the first coded bit stream is the order shown in FIG14 . This ensures that the bit order of the first coded bit stream output by the first aggregator 22 is the same as the bit order of the first coded bit stream input by the IO data distributor 13. Taking N=3 as an example, the 1st to 3rd bits in the first coded bit stream are a unit, the 4th to 6th bits are a unit, and so on, and so on. It can be understood that the order in which the first aggregator 22 reorganizes the units and the order in which the IO data distributor 13 distributes the units can be specified by a protocol, or configured by other control devices, or agreed upon in advance by the data transmission device 01 and the data transmission device 02, or configured by the data transmission device 01 and notified to the data transmission device 02, or configured by the data transmission device 02 and notified to the data transmission device 01, etc., and this application does not impose any restrictions. S603B: The deinterleaver 23 reads coded bits from each unit of the first coded bit stream and reorganizes them into N groups of ECC coded bit streams. S603B is the opposite process of S602A above, and this process may be called “de-interleaving”. It can be understood that, in order to correspond to S602A above and facilitate understanding, the process of the deinterleaver 23 reading the coded bits from each unit of the first coded bit stream can also be described in a polling manner, wherein the process of the deinterleaver 23 reading a unit in the first coded bit stream and allocating each bit in the unit to the ECC coded bit stream is one round. Specifically, the interleaver 12 reads one unit, that is, N consecutive bits, from the first coded bit stream in each round, and then allocates the N bits to N groups of ECC coded bit streams in the reading order; when the deinterleaver 23 completes one round of reading and allocation operations, it performs the next round of reading and allocation operations until all units in the first coded bit stream are read and allocated. Taking N=3 as an example, the 1st to 3rd bits in the first coded bit stream are a unit, and the 1st to 3rd bits are respectively allocated to 3 different ECC coded bit streams; the 4th to 6th bits in the first coded bit stream are a unit, and the 4th to 6th bits are respectively allocated to 3 different ECC coded bit streams, ..., and this cycle is repeated until the coded bits in the first coded bit stream are all allocated, and N groups of ECC coded bit streams are obtained. Correspondingly, the coded bits in each of the N groups of ECC coded bit streams include M data bits and P check bits. Optionally, the order in which the deinterleaver 23 reads and allocates the coded bits in each round is the same, and this order can be called the second polling order. It can be understood that the second polling order here corresponds to the first polling order mentioned above (i.e., the order in which the interleaver 12 reads the coded bits from the N groups of ECC coded bit streams in each round). For example, taking N=3 as an example, for example, the first polling order is the first group of ECC coded bit streams, the second group of ECC coded bit streams, and the third group of ECC coded bit streams, then the second polling order corresponds to the first coded bit in each unit (allocated to the first group of ECC coded bit streams), the second coded bit (allocated to the second group of ECC coded bit streams), and the third coded bit (allocated to the third group of ECC coded bit streams). Further optionally, the relative positions of the coded bits read by the deinterleaver 23 in each round in the allocated ECC coded bits are the same. Referring to FIG. 15 , N=3 is taken, and the second polling order is the first coded bit, the second coded bit, and the third coded bit in each unit as an example: in the first round, the deinterleaver 23 reads the first unit (i.e., the first to third bits) in the first coded bit stream, and allocates the first bit (i.e., A_0) in the first unit to the first group of ECC coded bit streams, allocates the second bit (i.e., B_0) in the first unit to the second group of ECC coded bit streams, and allocates the third bit (i.e., C_0) in the first unit to the third group of ECC coded bit streams; in the second round, the deinterleaver 23 reads the first unit (i.e., the first to third bits ... The device 23 reads the second unit (i.e., the 4th to 6th bits) in the first coded bit stream, allocates the first bit (i.e., A_1) in the second unit to the second group of ECC coded bit streams, allocates the second bit (i.e., B_1) in the second unit to the second group of ECC coded bit streams, allocates the third bit (i.e., C_1) in the second unit to the third group of ECC coded bit streams, ..., and repeats this cycle to finally obtain three groups of ECC coded bit streams: A_0 / A_1 / A_2..., B_0 / B_1 / B_2..., C_0 / C_1 / C_2.... S604B: The ECC decoder 24 performs single-bit error correction ECC decoding on the N groups of ECC encoded bit streams to obtain N groups of data bit streams. S604B is the opposite process of S601A above. The ECC decoding method used by the ECC decoder 24 corresponds to the ECC encoding method used by the ECC encoder 11 in the data transmission device 01. ECC is specifically, for example, an optimal minimum odd-weight column code or other extended Hamming code for implementing SEC-DED, which is not limited in this application. The ECC encoding and decoding method can be specifically specified by the protocol, or configured by other control devices, or agreed in advance by the data transmission device 01 and the data transmission device 02, or configured by the data transmission device 01 and notified to the data transmission device 02, or configured by the data transmission device 02 and notified to the data transmission device 01, etc., which is not limited in this application. Since the N bits in each unit correspond to different ECCs, when multiple bit errors occur in a unit, these errors will be dispersed to different ECCs, and multi-bit errors can be corrected based on single-bit error correction technology. Optionally, the number of ECC decoders 24 is N, as shown in FIG16, and the N decoders 24 are respectively used to perform single-bit error correction ECC decoding on N groups of ECC coded bit streams, and different N decoders 24 correspond to different ECCs. For example, the ECC decoder 24-1 is used to perform single-bit error correction ECC decoding on the first group of ECC coded bit streams to obtain the first group of data bit streams, the ECC decoder 24-2 is used to perform single-bit error correction ECC decoding on the second group of ECC coded bit streams to obtain the second group of data bit streams, ..., the ECC decoder 24-N is used to perform single-bit error correction ECC decoding on the Nth group of ECC coded bit streams to obtain the Nth group of data bit streams. Optionally, as shown in FIG. 17 , the data transmission device 02 further includes a second aggregator 25 for aggregating the Nth group of data bit streams to obtain an original data bit stream. To understand the above process more clearly, here is another complete example: Using the example of FIG12 , the original data has 120*3=360 bits, and the data transmission device 01 and the data transmission device 02 are interconnected through 64 IO pins (i.e., IO 0 to IO 63). The data transmission device 01 outputs 64 groups of PAM coded bit streams, and the data transmission device 02 receives the 64 groups of PAM coded bit streams and performs PAM-3 decoding, IO data aggregation, cross-linking, ECC decoding, etc. Referring to FIG18 , the specific processing flow is as follows: The PAM decoder 21 performs PAM-3 decoding on the 64 groups of PAM coded bit streams. The PAM-3 decoding is implemented to recover 3 data bits from the received data of 2 UIs of each IO, and obtain 64 groups of IO data streams: IO 0: DC

[0064] ,DB

[0064] ,DA

[0064] ,DC[0],DB[0],DA[0]; IO 1: DC

[0065] ,DB

[0065] ,DA

[0065] ,DC[0],DB[0],DA[0]; … IO 63: CC[7], CB[7], CA[7], DC

[0063] , DB

[0063] , DA

[0063] . The first aggregator 22 aggregates the 64 groups of IO data streams into one group of data streams, specifically taking 3 consecutive bits as a unit and taking 3 bits of data in sequence from IO 0 to IO 63 in the order of IO, and finally forming 384 bits of data: CC[7], CB[7], CA[7], …, CC[0], CB[0], CA[0], DC

[0119] , DB

[0119] , DA

[0119] , …, DC[1], DB[1], DA[1], DC[0], DB[0], DA[0]. The deinterleaver 23 divides the data output by the first aggregator 22 into three groups of 128-bit data, specifically in bit order, with 3 bits as a unit, taking 1 bit each time to form three groups of data: {CC[7:0],DC[119:0]}, {CB[7:0],DB[119:0]}, and {CA[7:0],DA[119:0]}. The 128-bit data {C[7:0], D[119:0]} received by ECC decoders A, B, and C respectively includes 120 bits of data and 8 bits of check bits. Each ECC decoder determines whether the received D[119:0] data needs error correction by calculating the syndrome S: S = {C[7:0], D[119:0]}*HT; Among them, H is 8*128 bits, consisting of an 8x120-bit H1 matrix and an 8x8-bit identity matrix I1: H = [H1, HI 1]; S has 8 bits in total. When S is 0, it means no error has occurred, and D[119:0] is directly output as decoded data. When S is not 0 and is equal to the value of a column in the H check matrix, it means that an error has occurred in the bit corresponding to the column, and the bit is inverted to restore the original data. After ECC decoding, the corrected 120-bit data D[119:0] is output. The second aggregator 25 combines the three groups of error-corrected 120-bit data into 360-bit data, and sequentially combines the 360-bit original data, namely, D[120*3-1:0]={DC[119:0], DB[119:0], DA[119:0]}. It should be noted that the above only describes several key components in the data transmission device 02 and the methods for executing the same. In practical applications, the data transmission device 02 may also include other components, and the data transmission device 02 may also perform other processing on the data. For example, before performing PAM decoding, the data transmission device 02 may also perform serial-to-parallel processing on the data before PAM decoding, and after PAM decoding, may also perform repair, descrambling, and other processing on the decoded data, etc., and this application does not limit this. In addition, in actual applications, the positions of some components in the data transmission device 02 can be swapped. For example, the first aggregator 22 can also be set before the PAM decoder 21, that is, the data transmission device 02 can first aggregate the data of each IO pin, and then uniformly perform PAM-N decoding on the aggregated data. Optionally, the Q IO pins described above belong to the same Lane, where lane refers to a collection of all physical layer pins that share the same on-link clock source. In other words, the method described above takes data transmission in one Lane as an example. However, in actual applications, the data transmission device 01 and the data transmission device 02 can transmit in multiple Lanes at the same time to increase the total bit width of the entire transmission interface. It can be understood that in the case of multiple Lane transmissions, the data processing flow corresponding to each lane can refer to the method flow described above. In an embodiment of the present application, the transmitting end performs single-bit ECC encoding on N groups of data bit streams, and then interleaves the encoded N groups of ECC encoded bit streams to ensure that the N bits in a unit in the interleaved bit stream correspond to different ECCs, and performs PAM encoding with the unit as the granularity. In this way, when a bit error occurs in a unit, the error will be dispersed to different ECCs, and then the receiving end can complete multi-bit error correction processing through a single-bit error correction method. For example, see Figure 19, which is a schematic diagram of error correction. Assume that an error occurs in one UI of IO_0 due to external interference, and other UIs and IOs are normal. For example, sending "010" is "101" after PAM-3 decoding at the receiving end, but these three bits correspond to ECCs respectively, and each ECC can correct 1 bit of error. Therefore, after ECC decoding, these three bits are corrected to "010", thereby achieving 3-bit error correction capability through a single-bit error correction method. It can be seen that the embodiments of the present application can implement error correction using single-bit error correction technology in a chip interconnection system, which can achieve lower latency and smaller area power consumption compared to multi-bit error correction technology or retransmission technology. Based on the same technical concept, an embodiment of the present application also provides a computer-readable storage medium, which is used to store instructions. When the instructions are executed, the method shown in Figure 6A or Figure 6B is implemented. Based on the same technical concept, an embodiment of the present application further provides a computer program product, in which instructions are stored. When the computer program product is run on a computer, the method shown in FIG. 6A or FIG. 6B is executed. Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code. The present application is described with reference to the flowchart and / or block diagram of the method, device (system), and computer program product according to the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the process and / or box in the flowchart and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the function specified in one process or multiple processes in the flowchart and / or one box or multiple boxes in the block diagram. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram. These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and / or one or more boxes in the block diagram. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the scope of protection of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A data transmission device, characterized in that: include: An error correction code (ECC) encoder is used to perform single-bit error correction ECC encoding on N groups of data bit streams to obtain N groups of ECC encoded bit streams; wherein each group of data bit streams in the N groups of data bit streams includes M data bits, and the encoded bits in each group of ECC encoded bit streams in the N groups of ECC encoded bit streams include M data bits and P check bits; An interleaver, configured to read coded bits from the N groups of ECC coded bit streams in a polling manner and reorganize them into a first coded bit stream; wherein each N coded bits in the first coded bit stream is a unit, and the N coded bits in each unit are from different ECC coded bit streams; An input / output IO data distributor, used to distribute each unit in the first coded bit stream to Q IO pins to obtain Q groups of IO data streams; A pulse amplitude modulation (PAM) encoder is used to perform PAM-N encoding on the Q groups of IO data streams to obtain Q groups of PAM encoded bit streams; The Q IO pins are respectively used to send the Q groups of PAM coded bit streams; Among them, N, M, P, and Q are positive integers.

2. The device according to claim 1, characterized in that The device also includes: The data grouper is used to group the original data bit stream to obtain the N groups of data bit streams; and transmit the N groups of data bit streams to the ECC encoder respectively.

3. The device according to claim 1 or 2, characterized in that The data lengths of the IO data streams in the Q group of IO data streams are the same.

4. The device according to any one of claims 1 to 3, characterized in that: The single-bit error-correcting ECC code includes an extended Hamming code for implementing single error correction and double error detection SEC-DED.

5. The device according to claim 4, characterized in that The extended Hamming code for implementing SEC-DED includes an optimal minimum odd-weight column code.

6. The device according to any one of claims 1 to 5, characterized in that: The value of N is any one of 3, 4, 6, 8 or 16.

7. A data transmission device, characterized in that: include: Q IO pins, each used to receive Q groups of PAM coded bit streams; A PAM decoder, used for performing PAM-N decoding on the Q groups of PAM encoded bit streams to obtain Q groups of IO data streams; A first aggregator, configured to aggregate the Q groups of IO data streams to obtain a first coded bit stream, wherein every N coded bits in the first coded bit stream constitute a unit; A deinterleaver, configured to read coded bits from each unit of the first coded bit stream and reorganize into N groups of ECC coded bit streams; wherein the N coded bits in each unit are respectively allocated to different ECC coded bit streams, and the coded bits in each group of the N groups of ECC coded bit streams include M data bits and P check bits; An ECC decoder, configured to perform single-bit error correction ECC decoding on the N groups of ECC encoded bit streams to obtain N groups of data bit streams; Among them, N, M, P, and Q are positive integers.

8. The device according to claim 7, characterized in that The device also includes: The second aggregator is used to aggregate the N groups of data bit streams into an original data bit stream.

9. The device according to claim 7 or 8, characterized in that The data lengths of the IO data streams in the Q group of IO data streams are the same.

10. The device according to any one of claims 7 to 9, characterized in that: The single-bit error-correcting ECC code includes an extended Hamming code for implementing SEC-DED.

11. The device according to claim 10, characterized in that The extended Hamming code for implementing SEC-DED includes an optimal minimum odd-weight column code.

12. The device according to any one of claims 7 to 11, characterized in that: The value of N is any one of 3, 4, 6, 8 or 16.

13. A data transmission method, characterized in that: include: Performing single-bit error correction ECC encoding on N groups of data bit streams to obtain N groups of ECC encoded bit streams; wherein each group of data bit streams in the N groups of data bit streams includes M data bits, and the encoded bits in each group of ECC encoded bit streams in the N groups of ECC encoded bit streams include M data bits and P check bits; Reading coded bits from the N groups of ECC coded bit streams in a polling manner and recombining them into a first coded bit stream; wherein each N coded bits in the first coded bit stream is a unit, and the N coded bits in each unit are from different ECC coded bit streams; Distribute each unit in the first coded bit stream to Q IO pins to obtain Q groups of IO data streams; Performing PAM-N encoding on the Q groups of IO data streams to obtain Q groups of PAM encoded bit streams; Sending the Q groups of PAM coded bit streams through the Q IO pins; Among them, N, M, P, and Q are positive integers.

14. The method according to claim 13, characterized in that The method further comprises: The original data bit streams are grouped to obtain the N groups of data bit streams.

15. The method according to claim 13 or 14, characterized in that The data lengths of the IO data streams in the Q group of IO data streams are the same.

16. The method according to any one of claims 13 to 15, characterized in that: The single-bit error-correcting ECC code includes an extended Hamming code for implementing SEC-DED.

17. The method according to claim 14, characterized in that The extended Hamming code for implementing SEC-DED includes an optimal minimum odd-weight column code.

18. The method according to any one of claims 13 to 17, characterized in that: The value of N is any one of 3, 4, 6, 8 or 16.

19. A data transmission method, characterized in that: include: Receive Q groups of PAM coded bit streams through Q IO pins; Performing PAM-N decoding on the Q groups of PAM encoded bit streams to obtain Q groups of IO data streams; Aggregating the Q groups of IO data streams to obtain a first coded bit stream, wherein every N coded bits in the first coded bit stream constitute a unit; Reading coded bits from each unit of the first coded bit stream and reorganizing them into N groups of ECC coded bit streams; wherein the N coded bits in each unit are respectively allocated to different ECC coded bit streams, and the coded bits in each group of the N groups of ECC coded bit streams include M data bits and P check bits; Performing single-bit error correction ECC decoding on the N groups of ECC encoded bit streams to obtain N groups of data bit streams; Among them, N, M, P, and Q are positive integers.

20. The method of claim 19, wherein: The method further comprises: The N groups of data bit streams are aggregated into an original data bit stream.

21. The method according to claim 19 or 20, characterized in that The data lengths of the IO data streams in the Q group of IO data streams are the same.

22. The method according to any one of claims 19 to 21, characterized in that: The single-bit error-correcting ECC code includes an extended Hamming code for implementing SEC-DED.

23. The method of claim 22, wherein: The extended Hamming code for implementing SEC-DED includes an optimal minimum odd-weight column code.

24. The method according to any one of claims 19 to 23, characterized in that The value of N is any one of 3, 4, 6, 8 or 16.

25. A computer-readable storage medium, characterized in that: The readable storage medium is used to store instructions, and when the instructions are executed, the method according to any one of claims 13 to 18 is implemented, or the method according to any one of claims 19 to 24 is implemented.

26. A computer program product, characterized in that The computer program product stores instructions, and when the computer program product is run on a computer, the method according to any one of claims 13 to 18 is executed, or the method according to any one of claims 19 to 24 is executed.

27. A data transmission system, characterized in that: It comprises the device as described in any one of claims 1 to 6 and the device as described in any one of claims 7 to 12.

Images