System and method for bonding semiconductor devices

Abstract

A method for manufacturing a semiconductor package. The method includes: providing a first semiconductor die including a plurality of metallization layers; completely covering the topmost metallization layer in the metallization layers with a barrier layer; completely covering the barrier layer with a stop layer and a laser lift-off layer in sequence; attaching a first side of the first semiconductor die to the first wafer through at least a laser lift-off layer; attaching a second side of the first semiconductor die to a second wafer; removing the first wafer from the first semiconductor die based on the laser lift-off layer; forming a plurality of connectors on the first side of the first semiconductor die to electrically couple to the topmost metallization layer; and bonding the first semiconductor die to a third wafer including the second semiconductor die.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of U.S. Non - Provisional Application No. 18 / 072,096, filed on November 30, 2022, which is hereby incorporated by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor devices and methods of bonding multiple semiconductor devices. Background Art

[0004] Due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, this increase in integration density comes from the continuous reduction of the minimum feature size, which allows more components to be integrated into a given area. With the recent growing demands for miniaturization, higher speed, greater bandwidth, and lower power consumption and latency, the demand for smaller and more innovative semiconductor die packaging technologies has also increased. Summary of the Invention

[0005] At least one aspect of this disclosure relates to a method for manufacturing a semiconductor package. The method includes: providing a first semiconductor die including a plurality of metallization layers; completely covering the top - most metallization layer among the metallization layers with a barrier layer; sequentially covering the barrier layer completely with a stop layer and a laser lift - off layer; attaching a first side of the first semiconductor die to a first wafer through at least the laser lift - off layer; attaching a second side of the first semiconductor die to a second wafer; removing the first wafer from the first semiconductor die through the laser lift - off layer; forming a plurality of connectors on the first side of the first semiconductor die to electrically couple to the top - most metallization layer; and bonding the first semiconductor die to a third wafer including a second semiconductor die.

[0006] In some embodiments, the second semiconductor die includes a plurality of second metallization layers and a plurality of second connectors. The step of bonding the first semiconductor die to the third wafer includes connecting at least one of the plurality of connectors to a corresponding second connector among the plurality of second connectors.

[0007] In some embodiments, before forming the plurality of connectors, the method further includes forming a plurality of vias that extend through the barrier layer to contact the top - most metallization layer. Each of the plurality of vias contacts a corresponding connector among the plurality of connectors.

[0008] In some embodiments, the step of removing the first wafer includes applying a laser to the first side of the first semiconductor die to cause thermochemical dissociation of the laser lift - off layer. The method further includes polishing away any remaining portion of the laser lift - off layer until the stop layer is exposed.

[0009] In some embodiments, the step of attaching the second side of the first semiconductor die to the second wafer includes forming a first bonding layer on the second side of the first semiconductor die; planarizing the first bonding layer using a laser; forming a second bonding layer on the second wafer; and bonding the first bonding layer to the second bonding layer. The step of forming the first bonding layer, the step of planarizing the first bonding layer, and the step of bonding the first bonding layer to the second bonding layer are each performed at an elevated temperature.

[0010] In some embodiments, the step of forming a plurality of connectors on the first side of the first semiconductor die is performed at a temperature not greater than about 250 °C.

[0011] At least another aspect of the present disclosure relates to a method for manufacturing a semiconductor package. The method includes: bonding a plurality of semiconductor dies to a first wafer on their respective first sides; bonding the plurality of semiconductor dies to a second wafer on their respective second sides; decoupling the first wafer from the plurality of semiconductor dies; forming a plurality of first connectors in electrical contact with the plurality of semiconductor dies disposed on the second wafer; and bonding the plurality of semiconductor dies to a third wafer by connecting the plurality of first connectors to a plurality of second connectors disposed on a third wafer, respectively.

[0012] In some embodiments, the step of forming a plurality of first connectors is performed after any one of the steps of bonding the plurality of semiconductor dies to the first wafer, bonding the plurality of semiconductor dies to the second wafer, or decoupling the first wafer from the plurality of semiconductor dies. Each of the steps of bonding the plurality of semiconductor dies to the first wafer, bonding the plurality of semiconductor dies to the second wafer, and decoupling the first wafer from the plurality of semiconductor dies is performed at an elevated temperature.

[0013] In some embodiments, the step of decoupling the first wafer from the plurality of semiconductor dies includes applying a laser through the first wafer on the first side of the semiconductor dies.

[0014] In some embodiments, prior to forming the plurality of first connectors, each semiconductor die among the semiconductor dies includes: a plurality of metallization layers; a barrier layer that completely covers the topmost metallization layer among the plurality of metallization layers; a dielectric layer that covers the barrier layer; a stop layer that covers the dielectric layer; and a laser lift-off layer that covers the stop layer. After decoupling the first wafer from the plurality of semiconductor dies, the method further includes: polishing from the first side of the semiconductor dies until the stop layer of at least one of the semiconductor dies is exposed; and forming a plurality of vias that extend through the barrier layer and the dielectric layer. The plurality of first connectors are electrically coupled to the topmost metallization layer through the plurality of vias, respectively.

[0015] In some embodiments, the step of bonding a plurality of semiconductor dies to the third wafer is performed by hybrid bonding technology.

[0016] Another aspect of the present disclosure relates to a method for manufacturing a semiconductor package. The method includes preparing a plurality of semiconductor dies, each of the plurality of semiconductor dies including, on its first side, a plurality of metallization layers, a dielectric layer completely covering the topmost metallization layer of the metallization layers, a stop layer covering the dielectric layer, and a laser lift-off layer covering the stop layer; bonding the plurality of semiconductor dies to a first wafer through their respective first sides; bonding the plurality of semiconductor dies to a second wafer through their respective second sides; decoupling the first wafer from the plurality of semiconductor dies based on thermochemical dissociation of the laser lift-off layer of each of the plurality of semiconductor dies; forming a plurality of vias that extend through the dielectric layer to contact the topmost metallization layer respectively; forming a plurality of first connectors that contact the plurality of vias respectively; and bonding the plurality of semiconductor dies to a third wafer by connecting the plurality of first connectors to a plurality of second connectors disposed on the third wafer respectively.

[0017] In some embodiments, each of the steps of bonding the plurality of semiconductor dies to the first wafer, bonding the plurality of semiconductor dies to the second wafer, and decoupling the first wafer from the plurality of semiconductor dies is performed at an elevated temperature.

[0018] In some embodiments, each of the steps of forming the plurality of vias and forming the plurality of first connectors is performed at a temperature not greater than about 250 °C.

[0019] These and other aspects and implementations are discussed in detail below. The above information and the following detailed description include illustrative examples of various aspects and implementations, and provide an overview or framework for understanding the nature and characteristics of the claimed aspects and implementations. The drawings provide an illustration and further understanding of the various aspects and implementations, and are incorporated into and constitute a part of this specification. The aspects can be combined, and it will be readily understood that the features described in the context of one aspect of the present invention can be combined with other aspects. The aspects can be implemented in any convenient form. As used in the specification and claims, unless the context clearly indicates otherwise, the singular forms "a / an" and "the" include plural referents. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings illustrate non-limiting embodiments of the present disclosure by way of example. The drawings are schematic and are not intended to be drawn to scale. Unless indicated as representing prior art, the drawings represent aspects of the present disclosure. For the purposes of clarity, not every element may be labeled in each drawing. In the drawings:

[0021] Figure 1 A flowchart showing an example method for manufacturing a semiconductor package in accordance with some embodiments is presented.

[0022] Figures 2 to 11 A semiconductor package manufactured by the method of Figure 1 is shown in respective cross-sectional views during various manufacturing stages. DETAILED DESCRIPTION

[0023] Reference will now be made to the illustrative embodiments depicted in the accompanying drawings, and specific language will be used herein to describe these embodiments. However, it is understood that no limitation of the scope of the claims or of the present disclosure is thereby intended. Changes and further modifications of the features of the invention shown herein, as well as additional applications of the principles of the subject matter shown herein, which would occur to those skilled in the relevant art and to those who have obtained knowledge of the present disclosure, will be considered to be within the scope of the subject matter disclosed herein. Other embodiments may be used and / or other changes may be made without departing from the spirit or scope of the present disclosure. The illustrative embodiments described in the detailed description are not meant to limit the subject matter presented.

[0024] As semiconductor technology has advanced further, stacked semiconductor devices (e.g., 3D integrated circuits (3DICs)) have emerged as an effective alternative for further reducing the physical size of semiconductor devices. In a stacked semiconductor device, active circuits (such as logic circuits, memory circuits, processor circuits, etc.) are fabricated on different semiconductor wafers. Two or more semiconductor wafers can be mounted on top of each other to further reduce the form factor of the semiconductor device.

[0025] Two semiconductor wafers or dies can be bonded together by suitable bonding techniques. Commonly used bonding techniques include direct bonding, chemical activation bonding, plasma activation bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reactive bonding, hybrid bonding, and / or similar bonding. Electrical connections can be provided between the stacked semiconductor wafers / dies (or stacked semiconductor devices). Stacked semiconductor devices can provide higher density at a smaller form factor and achieve improved performance and lower power consumption.

[0026] Of particular interest is hybrid bonding that does not require a specific high-temperature annealing process. In hybrid bonding technology, permanent bonds couple dielectric bonds (e.g., SiOx ) combined with one or more embedded metals (e.g., Cu) to form interconnects. Hybrid bonding extends fusion bonding through the embedded metal pads in the bonding interface, which allows face-to-face connection of different semiconductor wafers / die. However, in the prior art, the embedded metal pads of semiconductor devices are typically formed immediately after the topmost metallization layer of the semiconductor device (i.e., before the semiconductor device is processed for bonding to another semiconductor device). One or more of such process steps (e.g., fusion bonding to a carrier / sacrificial substrate, laser planarization, laser lift-off, etc.) typically require a high-temperature annealing process, which may damage the metal pads. Thus, in some aspects, the prior art for bonding different semiconductor devices is not entirely satisfactory.

[0027] The present disclosure provides various embodiments of a method for bonding semiconductor devices (e.g., die-to-wafer, wafer-to-wafer, die-to-die), which can advantageously circumvent the above problems. In one aspect of the present disclosure, instead of forming the metal pads immediately after the topmost metallization layer of the semiconductor device to be bonded, the method as disclosed herein may include forming the metal pads (and the corresponding via structures connecting the metal pads to the topmost metallization layer) only until the semiconductor device has advanced through the steps that require a high-temperature annealing process. For example, the semiconductor device may first be bonded to a first carrier / sacrificial wafer through a plurality of layers that completely cover the topmost metallization layer, bonded to a second carrier / sacrificial wafer through a bonding layer, and then released from the first carrier / sacrificial wafer. Each of these steps may include a high-temperature annealing process. By arranging the step of forming the metal pads after those high-temperature annealing processes, the metal pads can be advantageously protected from damage caused by the high-temperature annealing process. Thus, the disclosed method can solve the technical problems faced by the prior art.

[0028] Figure 1 A flowchart of an example method 100 for forming a semiconductor package having at least one reconfigured wafer is shown, the at least one reconfigured wafer having a plurality of semiconductor die bonded to another wafer by low-temperature hybrid bonding. It should be noted that method 100 is merely an example and is not intended to limit the present disclosure. Accordingly, it should be understood that additional operations may be provided before, during, and after Figure 1 method 100, and some other operations may be described only briefly herein.

[0029] In various embodiments, the operations of method 100 may be respectively associated with cross-sectional views of an example semiconductor package 200 at various manufacturing stages as shown in Figures 2 to 11 which will be discussed in further detail below. It should be understood that Figures 2 to 11The semiconductor package 200 shown can include a plurality of other devices, such as inductors, fuses, capacitors, coils, etc., while still being within the scope of the present disclosure.

[0030] Briefly, method 100 begins with operation 102 of providing a plurality of first semiconductor dies, each of the plurality of first semiconductor dies including a plurality of metallization layers formed on its first side. In various embodiments, the topmost metallization layer among the metallization layers of each first semiconductor die can be completely covered with at least a barrier layer, a stop layer, and a laser lift-off (LLO) layer. Method 100 proceeds to operation 104 of attaching the first semiconductor dies to a first (sacrificial) wafer on their first sides. Method 100 proceeds to operation 106 of thinning the first semiconductor dies from their respective second sides (e.g., back sides). Method 100 proceeds to operation 108 of covering the first semiconductor dies with an encapsulation layer. Method 100 proceeds to operation 110 of planarizing the encapsulation layer. Method 100 proceeds to operation 112 of attaching the first semiconductor dies to a second (support) wafer on their second sides. Method 100 proceeds to operation 114 of removing the first wafer based on the LLO layer. Method 100 proceeds to operation 116 of forming metal connectors on the first sides of each of the first semiconductor dies. Method 100 proceeds to operation 118 of bonding the first semiconductor dies to a third (semiconductor) wafer including a plurality of second semiconductor dies. In various embodiments of the present disclosure, any operation after operation 116 (e.g., operation 118) can be performed without an annealing process or at a substantially low temperature (e.g., not greater than about 250 °C).

[0031] Corresponding to Figure 1 Operation 102, Figure 2 is a cross-sectional view of an exemplary first semiconductor die 250 to be included in the semiconductor package 200 at one manufacturing stage among various manufacturing stages according to various embodiments.

[0032] As shown in the figure, the first semiconductor die 250 includes a substrate 252, a plurality of metallization layers 254 above the substrate 252, a barrier layer 256 above the topmost metallization layer in the metallization layers, an interlayer dielectric (ILD) or intermetallic dielectric (IMD) material 258 above the barrier layer 256, a stop layer 260 above the ILD material 258, and a laser lift-off (LLO) layer 262 above the stop layer 260. Each metallization layer in the metallization layers 254 disposed on the first side of the substrate 252 includes a plurality of interconnect structures, such as metal lines 270 and vias 272. The bottommost metallization layer in the metallization layers 254 is sometimes referred to as M0, the subsequent metallization layers are respectively referred to as M1, M2, etc., and the topmost metallization layer is sometimes referred to as Mx. In various embodiments of the present disclosure, the barrier layer 256 (and subsequent layers 258 to 262) may completely cover the topmost metallization layer Mx.

[0033] The substrate 252 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 252 may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a semiconductor material layer formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate 252 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0034] The substrate 252 includes a plurality of device features / structures 253 (e.g., transistors, diodes, resistors, etc., not shown for clarity) formed along the surface of the substrate 252. Above the surface of the substrate 252, a plurality of metallization layers 254 may be formed, each including a plurality of interconnect structures (e.g., metal lines 270 and vias 272). These interconnect structures across the metallization layers 254 are configured to electrically connect the device structures to each other to form an integrated circuit, which may be used as a logic device, a memory device, an input / output device, etc. (e.g., formed of a conductive material such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers, or combinations thereof) The interconnect structures may be embedded in one or more ILD or IMD materials (e.g., low-k dielectric materials such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiO x C y, spin-on glass, spin-on polymer, silicon carbide material, its compounds, its composites, its combinations, etc.).

[0035] Further, on the topmost metallization layer Mx, a barrier layer 256 is formed, and then an ILD / IMD material 258, a stop layer 260, and an LLO layer 262 are formed. As an example, the barrier layer 256 may include cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, titanium nitride, and / or combinations thereof, but alternatively, the barrier layer 256 may include other materials. The ILD / IMD material 258 may include one or more low-k dielectric materials, such as silicon oxide (SiO2). The stop layer 260 configured to stop at least one of an etching process or a polishing process may include a dielectric material, such as silicon nitride (SiN). The LLO layer 262 may be used as a bonding layer to attach the first semiconductor die 250 to the carrier wafer (to be shown in Figure 3 ). Further, the LLO layer 262 can be induced to undergo thermochemical dissociation when a laser is applied, thereby allowing the first semiconductor die 250 to be removed from the carrier wafer at a later time (which will be shown in Figure 8 ). In some embodiments, the LLO layer 262 may include a silicon-based dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxycarbide, its multi-layers, etc., and may be deposited or thermally grown.

[0036] Corresponding to Figure 1 operation 104, Figure 3 is a cross-sectional view of a semiconductor package 200 at a manufacturing stage in various manufacturing stages according to different embodiments, in which a plurality of first semiconductor dies 250 are bonded to a sacrificial wafer 300.

[0037] In some embodiments, the first semiconductor die 250 may be bonded to the sacrificial wafer 300 to form a reconstructed wafer. It should be noted that the reconstructed wafer at the current stage may not be fully completed, that is, one or more components will be removed or added. For example, in Figure 3In [the figure], each of the first semiconductor dies 250 is flipped and attached to the sacrificial wafer 300, with their respective metallization layers 254 and overcoat layers 256 to 262 therebetween. Further, the first semiconductor dies 250 can be bonded to the sacrificial wafer 300 through a fusion bonding process. The fusion bonding process can involve bringing the first semiconductor dies 250 and the sacrificial wafer 300 into close contact, which causes them to stay together due to atomic attraction (i.e., van der Waals forces). The first semiconductor dies 250 and the sacrificial wafer 300 can be subjected to an annealing process, after which a solid-state bond can be formed between the first semiconductor dies 250 and the sacrificial wafer 300. The temperature of the annealing process can be any suitable temperature, such as between about 250 °C and about 350 °C. The fusion bonding process can be produced by SiO2 (oxide) / Si bonding, Si / Si bonding, and / or other suitable bonding. In some embodiments, an optional bonding layer 320 (e.g., formed of silicon oxide) can be formed over the sacrificial wafer 300.

[0038] Corresponding to Figure 1 operation 106, Figure 4 is a cross-sectional view of the semiconductor package 200 at one of the manufacturing stages in various embodiments, where a polishing process 401 is performed from the back side of the first semiconductor die 250.

[0039] In the case where each of the first semiconductor dies 250 as shown in Figure 3 has a corresponding thickness (or height), the polishing process 401 can polish the first semiconductor die from the back side of the first semiconductor die 250. Thus, as shown in Figure 4 , a horizontal (virtual) surface can be formed by the corresponding polished bottom surfaces of the first semiconductor dies 250. In some embodiments, the polishing process 401 can include a chemical mechanical polishing (CMP) process.

[0040] Corresponding to Figure 1 operation 108, Figure 5 is a cross-sectional view of the semiconductor package 200 at one of the manufacturing stages in various embodiments, where an encapsulation layer 500 can be formed over the first semiconductor die 250.

[0041] The encapsulation layer 500 formed over the reconstructed wafer 300 can continuously surround each of the semiconductor dies 250. In some embodiments, the encapsulation layer 500, which can be deposited or thermally grown at an elevated temperature (e.g., above 250 °C), can include an epoxy resin, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or a combination thereof, with or without fillers embedded therein. The fillers can include carbon fillers or glass fillers. In some embodiments, the encapsulation layer 500 can include a silicon-based dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon oxycarbide, multi-layers thereof, etc.

[0042] Corresponding to Figure 1 operation 110, Figure 6 is a cross-sectional view of the semiconductor package 200 at one of the various manufacturing stages according to various embodiments, where a polishing process 601 can be performed on the encapsulation layer 500.

[0043] As Figure 5 shown, upon formation, the encapsulation layer 500 can present a non-uniform surface. To bond the reconstructed wafer to another wafer (e.g., the support wafer shown below), the polishing process 601 can be used to polish the non-uniform surface of the encapsulation layer 500. Accordingly, the surface of the encapsulation layer 500 opposite to the other surface that contacts the sacrificial wafer 300 can be planarized. In some embodiments, the polishing process 601 can include a laser polishing process. Such a laser polishing process can include applying a laser beam with a very high power density in the form of pulses, which is typically performed at an elevated temperature (e.g., above 250 °C).

[0044] Corresponding to Figure 1 operation 112, Figure 7 is a cross-sectional view of the semiconductor package 200 at one of the various manufacturing stages according to different embodiments, where the reconstructed wafer (including the first semiconductor die 250 bonded to the sacrificial wafer 300) is attached to the support wafer 700.

[0045] The reconstructed wafer can be bonded to the support wafer 700 through a fusion bonding process. The fusion bonding process can involve bringing the reconstructed wafer and the support wafer 700 into close contact, which causes them to remain together due to atomic attraction (i.e., van der Waals forces). The reconstructed wafer and the support wafer 700 can be subjected to an annealing process, after which a solid-state bond can be formed between the reconstructed wafer and the support wafer 700 (e.g., between the encapsulation layer 500 and the support wafer 700). The temperature of the annealing process can be any suitable temperature, such as between about 250 °C and about 350 °C. The fusion bonding process can be produced by SiO2 (oxide) / Si bonding, Si / Si bonding, and / or other suitable bonding. In some embodiments, an optional bonding layer 720 (e.g., formed of silicon oxide) can be formed between the encapsulation layer 500 and the support wafer 700.

[0046] Corresponding to Figure 1 operation 114, Figure 8 is a cross-sectional view of the semiconductor package 200 at one manufacturing stage in various manufacturing stages according to various embodiments, where the sacrificial wafer 300 is removed from the remaining portion of the reconstructed wafer.

[0047] The sacrificial wafer 300 can be removed by a laser lift-off (LLO) process. In such an LLO process, light energy (e.g., a laser beam) 810 irradiates the reconstructed wafer through the first surface of the sacrificial wafer 300, where the radiation passes through the sacrificial wafer 300 and reaches the interface between the second opposite surface of the sacrificial wafer 300 and the first semiconductor die 250 (e.g., between the second surface of the sacrificial wafer 300 and the LLO layer 262 ( Figure 2 ) disposed above each of the first semiconductor dies 250). In various embodiments, the sacrificial wafer 300 can be optically transparent to the wavelength of the light energy 810. As a non-limiting example, the laser radiation incident on the sacrificial wafer 300 can be 248 nm radiation from a KrF pulsed excimer laser with a pulse width of 38 ns. Then, the energy passing through the sacrificial wafer 300 is absorbed by the LLO layer 262, which causes thermochemical dissociation in the LLO layer 262. The first semiconductor dies 250 (while still bonded to the support wafer 700) can be released, disconnected, or otherwise decoupled from the sacrificial wafer 300. Accordingly, the LLO layer 262 can sometimes be referred to as a release layer. The LLO process can be performed in a vacuum, air, or other ambient environment, and is typically performed at an elevated temperature (e.g., above 250 °C).

[0048] Corresponding to Figure 1 operation 116, Figure 9A cross-sectional view of a semiconductor package 200 at one manufacturing stage among various manufacturing stages according to various embodiments, where a polishing process 901 can be performed on the first semiconductor dies 250 until their stop layer 260 is exposed.

[0049] In some embodiments, the polishing process 901 can include a chemical mechanical polishing (CMP) process, and this chemical mechanical polishing process can stop only until the stop layer 260 is exposed. For example, after decoupling from the sacrificial wafer 300 ( Figure 8 ), the corresponding remaining portions of the LLO layer 262 can still exist on the first semiconductor dies 250. The polishing process 901 can polish off such remaining portions until the stop layer 260 is exposed. Alternatively stated, the stop layer 260 can be configured to stop the polishing process 901. When exposed, the stop layer 260 can be removed to expose the ILD material 258. Next, a plurality of metal connectors (e.g., bond pads and corresponding vias) can be formed to extend through the ILD material 258 and the barrier layer 256 to contact the interconnect structures disposed in the topmost metallization layer Mx of each first semiconductor die 250, as Figure 10 shown.

[0050] Figure 10 A cross-sectional view of one of the first semiconductor dies 250 bonded to the support wafer 700 is shown, where a plurality of vias 1070 and a plurality of bond pads 1072 are formed on the topmost metallization layer Mx. The vias 1070 and the bond pads 1072 can each be formed of one or more conductive materials (such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers, or a combination thereof). The vias 1070 and the bond pads 1072 can be formed by performing one or more damascene processes on the ILD material 258 that is exposed again. After forming the bond pads 1072 (as Figure 10 ), the first semiconductor die 250 can have a bonding surface 1050 that includes both at least one dielectric material (e.g., the ILD material 258) and at least one metal material (e.g., the bond pads 1072). Such a hybrid bonding surface along each of the first semiconductor dies 250 allows the reconstructed wafer (the first semiconductor die 250 bonded to the support wafer 700) to be bonded to another wafer that can also include a plurality of (e.g., second) semiconductor dies through a hybrid bonding process typically performed at a relatively low temperature (e.g., not greater than 250 °C). In this way, the metal connectors can be protected from potential thermal damage.

[0051] Corresponding to Figure 1 operation 118, Figure 11FIG. 0 is a cross-sectional view of a semiconductor package 200 at one manufacturing stage among various manufacturing stages according to different embodiments, in which a first semiconductor die 250 is bonded to a semiconductor wafer 1100 that further includes a plurality of second semiconductor dies. For clarity, the second semiconductor dies bonded, attached, or otherwise integrated to the semiconductor wafer 1100 are not shown, but it should be understood that each of such second semiconductor dies is substantially similar to the first semiconductor die 250. For example, each of the second semiconductor dies may have a hybrid bonding surface (e.g., a combination of a dielectric material and a metal material) that together forms a bonding surface 1150. Thus, the bonding surface 1050 and the bonding surface 1150 may be connected (bonded) to each other through a hybrid bonding process.

[0052] In the foregoing description, specific details have been set forth, such as the specific geometry of a processing system and descriptions of various components and processes used therein. However, it should be understood that the techniques herein may be practiced in other embodiments that depart from these specific details, and such details are for purposes of explanation rather than limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. However, the embodiments may be practiced without such specific details. Components having substantially the same functional construction are denoted by like reference characters, and thus any redundant description may be omitted.

[0053] Various techniques have been described as a plurality of discrete operations to assist in understanding the various embodiments. The order of description should not be construed as implying that these operations necessarily depend on order. In fact, these operations do not need to be performed in the order presented. The described operations may be performed in an order different from the order of the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0054] As used herein, a "substrate" or "target substrate" generally refers to an object to be processed in accordance with the present invention. A substrate may include any material portion or structure of a device (especially a semiconductor or other electronic device), and may be, for example, a base substrate structure (such as a semiconductor wafer, a mask), or a layer on or overlying a base substrate structure (such as a thin film). Thus, a substrate is not limited to any particular base structure, underlying layer, or overlying layer that is patterned or unpatterned, but is envisioned to include any such layer or base structure, as well as any combination of layers and / or base structures. This description may refer to a particular type of substrate, but this is for illustrative purposes only.

[0055] Those skilled in the art will also understand that many variations can be made to the operation of the techniques explained above while still achieving the same objectives of the present invention. The scope of this disclosure is intended to cover such variations. Thus, the above description of the embodiments of the present invention is not intended to be limiting. On the contrary, any limitations of the embodiments of the present invention are presented in the appended claims.

Claims

1. A method for manufacturing a semiconductor package, the method comprising: Providing a first semiconductor die including a plurality of metallization layers; Covering the topmost layer of these metallization layers with a barrier layer; Covering the barrier layer with a stop layer and a laser lift-off layer in sequence; Attaching a first side of the first semiconductor die to a first wafer through at least the laser lift-off layer; Attaching a second side of the first semiconductor die to a second wafer; Removing the first wafer from the first semiconductor die through the laser lift-off layer; Forming a plurality of connectors on the first side of the first semiconductor die for electrical coupling to the topmost metallization layer; and Bonding the first semiconductor die to a third wafer including a second semiconductor die.

2. The method according to claim 1, wherein The second semiconductor die includes a plurality of second metallization layers and a plurality of second connectors.

3. The method according to claim 2, wherein, The step of bonding the first semiconductor die to the third wafer includes connecting at least one of the plurality of connectors to a corresponding second connector of the plurality of second connectors.

4. The method according to claim 1, before forming the plurality of connectors, the method further comprises forming a plurality of vias extending through the barrier layer to contact the topmost metallization layer, wherein, Each of the plurality of vias contacts a corresponding connector of the plurality of connectors.

5. The method according to claim 1, wherein, The step of removing the first wafer further includes applying a laser to the first side of the first semiconductor die to cause thermochemical dissociation of the laser lift-off layer.

6. The method according to claim 5, the method further comprising polishing away any remaining portion of the laser lift-off layer until the stop layer is exposed.

7. The method according to claim 1, wherein, The step of attaching the second side of the first semiconductor die to the second wafer further includes: Forming a first bonding layer on the second side of the first semiconductor die; Planarizing the first bonding layer using a laser; Forming a second bonding layer on the second wafer; and Bonding the first bonding layer to the second bonding layer.

8. The method according to claim 7, wherein, The step of forming the first bonding layer, the step of planarizing the first bonding layer, and the step of bonding the first bonding layer to the second bonding layer are each performed at an elevated temperature.

9. The method according to claim 1, wherein The step of attaching the first side of the first semiconductor die to the first wafer and the step of removing the first wafer from the first semiconductor die are each performed at an elevated temperature.

10. The method according to claim 1, wherein, The step of forming a plurality of connectors on the first side of the first semiconductor die is performed at a temperature not greater than about 250 °C.

11. A method for manufacturing a semiconductor package, the method comprising: Bonding a plurality of semiconductor dies to a first wafer on respective first sides of the plurality of semiconductor dies; Bonding the plurality of semiconductor dies to a second wafer on respective second sides of the plurality of semiconductor dies; Disconnecting the first wafer from the plurality of semiconductor dies; Forming a plurality of first connectors in electrical contact with the plurality of semiconductor dies placed on the second wafer; And Bonding the plurality of semiconductor dies to the third wafer by connecting the plurality of first connectors to a plurality of second connectors provided on a third wafer respectively.

12. The method according to claim 11, wherein, The step of forming a plurality of first connectors is performed after any one of the step of bonding a plurality of semiconductor dies to the first wafer, the step of bonding the plurality of semiconductor dies to the second wafer, or the step of disconnecting the first wafer from the plurality of semiconductor dies.

13. The method according to claim 12, wherein, Each of the steps of bonding a plurality of semiconductor dies to a first wafer, bonding the plurality of semiconductor dies to a second wafer, and decoupling the first wafer from the plurality of semiconductor dies is performed at an elevated temperature.

14. The method according to claim 11, wherein, The step of decoupling the first wafer from the plurality of semiconductor dies further comprises applying a laser through the first wafer on a first side of the semiconductor dies.

15. The method according to claim 11, wherein, Before forming the plurality of first connectors, each of the semiconductor dies among the plurality of semiconductor dies comprises: a plurality of metallization layers; a barrier layer that completely covers the topmost metallization layer among the plurality of metallization layers; a dielectric layer that covers the barrier layer; a stop layer that covers the dielectric layer; and a laser lift-off layer that covers the stop layer.

16. The method according to claim 15, after decoupling the first wafer from the plurality of semiconductor dies, the method further comprises: polishing from a first side of the semiconductor dies until the stop layer of at least one of the semiconductor dies is exposed; and forming a plurality of vias that extend through the barrier layer and the dielectric layer; wherein the plurality of first connectors are electrically coupled to the topmost metallization layer respectively through the plurality of vias.

17. The method according to claim 11, wherein, The step of bonding the plurality of semiconductor dies to a third wafer is performed by a hybrid bonding technique.

18. A method for manufacturing a semiconductor package, the method comprising: preparing a plurality of semiconductor dies, each of the plurality of semiconductor dies comprising on a first side of the semiconductor die a plurality of metallization layers, a dielectric layer that completely covers the topmost metallization layer among the metallization layers, a stop layer that covers the dielectric layer, and a laser lift-off layer that covers the stop layer; bonding the plurality of semiconductor dies to a first wafer through respective first sides; bonding the plurality of semiconductor dies to a second wafer through respective second sides of the plurality of semiconductor dies; decoupling the first wafer from the plurality of semiconductor dies based on thermochemical dissociation of the laser lift-off layer of each of the plurality of semiconductor dies; forming a plurality of vias that extend through the dielectric layer to contact the topmost metallization layer respectively; forming a plurality of first connectors that contact the plurality of vias respectively; and bonding the plurality of semiconductor dies to the third wafer by connecting the plurality of first connectors to a plurality of second connectors provided on the third wafer respectively.

19. The method according to claim 18, wherein, Each of the steps of bonding a plurality of semiconductor dies to a first wafer, bonding the plurality of semiconductor dies to a second wafer, and decoupling the first wafer from the plurality of semiconductor dies is performed at an elevated temperature.

20. The method according to claim 18, wherein, Each of the steps of forming a plurality of vias and forming a plurality of first connectors is performed at a temperature not greater than about 250 °C.

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