Semiconductor structure with etch stop layer and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure, a manufacturing method thereof and a using method thereof. The semiconductor structure includes a first substrate, a second substrate on the first substrate, a first bonding layer between the first substrate and the second substrate, and a first etch stop layer between the first bonding layer and the second substrate, and the first etch stop layer has high etch selectivity for the first bonding layer. Some embodiments of the present disclosure particularly relate to semiconductor structures having etch stop layers, methods of making the same, and methods of using the same.

Description

[0001] Cross References

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 382,726, filed on November 8, 2022, entitled "Structures and Processes Including an Etch Stop Layer", the entire content of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to semiconductor structures, methods of manufacturing the same, and methods of using the same. Some embodiments of the present disclosure particularly relate to semiconductor structures having an etch stop layer, methods of manufacturing the same, and methods of using the same. Background Art

[0004] The semiconductor industry faces the need to continuously increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). The increase in integration density can be achieved by repeatedly reducing the minimum feature size to integrate more components into a given chip area. However, the lithography process has its physical limits; on the other hand, when reducing the size of semiconductor devices and increasing the integration density, the distance between semiconductor devices also decreases. As the integration density increases, the device pitch becomes a key factor in device performance. When the pitch is too small, the components will interfere with each other. Therefore, a balance needs to be achieved between the feature size and the device pitch, and the performance of individual devices may also need to be optimized. When more devices are integrated into a single chip, the resistance-capacitance delay and chip power consumption of the circuit may also increase significantly due to the significant increase in the number and length of the interconnections between devices.

[0005] Due to the gradual reduction of the lateral dimensions of semiconductor devices in each process generation, it faces a bottleneck in increasing the integration density. Generally, semiconductor devices are usually manufactured on the front side of a substrate, and through-substrate vias (TSVs) may be used to connect devices and / or interconnect structures. However, there is still a need to improve the process to increase the integration density and device performance. Summary of the Invention

[0006] The present disclosure provides a semiconductor structure. The semiconductor structure includes a first substrate, a second substrate, a first bonding layer, and a first etch stop layer. The second substrate is located on the first substrate. The first bonding layer is located between the first substrate and the second substrate. The first etch stop layer is located between the first bonding layer and the second substrate. The first etch stop layer has a high etch selectivity with respect to the first bonding layer.

[0007] In one embodiment, the second substrate is made of silicon, germanium, silicon-germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN).

[0008] In one embodiment, the first bonding layer includes silicon oxide, and the first etch stop layer includes silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, or conductive metal compound.

[0009] In one embodiment, the first etch stop layer includes a dielectric material.

[0010] In one embodiment, the first etch stop layer has an etch selectivity greater than 5:1 with respect to the first bonding layer.

[0011] In one embodiment, the semiconductor structure further includes a second etch stop layer located between the first substrate and the first bonding layer. The second etch stop layer has a high etch selectivity with respect to the first substrate.

[0012] In one embodiment, the first substrate includes single-crystalline semiconductor material or glass, and the second etch stop layer includes silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, or conductive metal compound.

[0013] In one embodiment, the semiconductor structure further includes an intermediate layer located between the first etch stop layer and the second substrate.

[0014] In one embodiment, the intermediate layer includes doped semiconductor material, metal, or conductive metal compound.

[0015] In one embodiment, the first etch stop layer includes silicon nitride or silicon oxynitride.

[0016] In one embodiment, the intermediate layer is patterned.

[0017] In one embodiment, the intermediate layer includes silicon oxide or a high-k material.

[0018] In one embodiment, the first etch stop layer includes silicon nitride, silicon oxynitride, doped semiconductor material, metal, or conductive metal compound.

[0019] In one embodiment, the semiconductor structure further includes alignment marks disposed in the second substrate.

[0020] In one embodiment, the semiconductor structure further includes a second etch stop layer and a second bonding layer. The second etch stop layer is located between the first substrate and the first bonding layer. The second bonding layer is located between the first substrate and the second etch stop layer. The second etch stop layer has a high etch selectivity with respect to the second bonding layer.

[0021] In one embodiment, the second bonding layer includes silicon oxide, and the second etch stop layer includes silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, or conductive metal compound.

[0022] The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a first structure that includes a first substrate (step (a)). The method includes providing a second structure that includes a second substrate and a first etch stop layer on the second substrate, and the second substrate includes an implanted hydrogen ion layer (step (b)). The method includes bonding the first structure and the second structure with a bonding layer to form a bonded structure (step (c)). The method includes removing a portion of the second substrate from about the implanted hydrogen ion layer (step (d)).

[0023] In one embodiment, the second substrate is made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN).

[0024] In one embodiment, the bonding layer includes silicon oxide, and the first etch stop layer includes silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, or conductive metal compound.

[0025] In one embodiment, step (b) includes providing the second substrate (step (b1)), forming the first etch stop layer on the second substrate (step (b2)), and implanting the hydrogen ion layer into the second substrate (step (b3)).

[0026] In one embodiment, step (c) includes forming a first dielectric layer on the first substrate and forming a second dielectric layer on the first etch stop layer before bonding.

[0027] In one embodiment, the bonded structure further includes a second etch stop layer located between the first substrate and the bonding layer.

[0028] In one embodiment, step (a) includes providing the first substrate (step (a1)), and forming the second etch stop layer on the first substrate (step (a2)).

[0029] In one embodiment, step (c) includes forming a first dielectric layer on the second etch stop layer and forming a second dielectric layer on the first etch stop layer before bonding.

[0030] In one embodiment, the bonded structure further includes an intermediate layer located between the first etch stop layer and the second substrate.

[0031] In one embodiment, step (b) includes providing the second substrate (step (b1)), forming the intermediate layer on the second substrate (step (b2)), forming the first etch stop layer on the intermediate layer (step (b3)), and implanting the hydrogen ion layer into the second substrate (step (b4)).

[0032] In one embodiment, step (b2) further includes patterning the intermediate layer.

[0033] The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing a semiconductor structure that includes a first substrate, a second substrate on the first substrate, a bonding layer between the first substrate and the second substrate, and a first etch stop layer between the bonding layer and the second substrate (step (a)). The method includes forming a first portion of the semiconductor device (step (b)). The method includes attaching a third substrate to a first side of the second substrate, with the second substrate located between the third substrate and the first substrate (step (c)). The method includes removing the first substrate and the bonding layer of the semiconductor structure to expose the first etch stop layer (step (d)). The method includes removing at least a portion of the first etch stop layer (step (e)).

[0034] In one embodiment, the first portion of the semiconductor device includes a transistor or a diode.

[0035] In one embodiment, step (b) includes doping the second substrate or etching the second substrate.

[0036] In one embodiment, the method further includes forming a second portion of the semiconductor device on a second side of the second substrate (step (f)).

[0037] In one embodiment, the first portion of the semiconductor device includes a transistor that includes a source region, a drain region, a channel region, and a gate structure, and the second portion of the semiconductor device includes a capacitor that is electrically connected to the source region of the transistor.

[0038] In one embodiment, the first portion of the semiconductor device includes a transistor that includes a first source / drain region, a second source / drain region, a channel region, and a first gate structure, and the second portion of the semiconductor device includes a second gate structure that overlaps the channel region of the transistor.

[0039] In one embodiment, the method further includes forming a via on the second side of the second substrate, wherein the first gate structure is electrically connected to the second gate structure through the via.

[0040] In one embodiment, the method further includes forming a first interconnect structure on the first side of the second substrate before step (c).

[0041] In one embodiment, the method further includes forming a second interconnect structure on the second side of the second substrate after step (e).

[0042] In one embodiment, the semiconductor structure further includes an intermediate layer located between the first etch stop layer and the second substrate.

[0043] In one embodiment, step (e) includes removing at least a portion of the first etch stop layer to expose the intermediate layer.

[0044] In one embodiment, the intermediate layer is patterned.

[0045] In one embodiment, step (d) includes performing a first etching process by applying a first etchant.

[0046] In one embodiment, step (e) includes performing a second etching process by applying a second etchant.

[0047] In one embodiment, the semiconductor structure further includes alignment marks disposed in the second substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 FIG. is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0049] Figure 2 FIG. is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0050] Figure 3 FIG. is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0051] Figure 4 FIG. is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0052] Figure 5 FIG. is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0053] Figure 6 FIG. is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0054] Figure 7 FIG. is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0055] Figures 8A to 8D FIG. is a schematic diagram of an intermediate stage in manufacturing a semiconductor structure similar to Figure 1 as shown.

[0056] Figures 9A to 9D Schematic diagram of an intermediate stage of manufacturing a semiconductor structure similar to Figure 2 that shown.

[0057] Figures 10A to 10D Schematic diagram of an intermediate stage of manufacturing a semiconductor structure similar to Figure 4 that shown.

[0058] Figures 11A to 11D Schematic diagram of an intermediate stage of manufacturing a semiconductor structure similar to Figure 5 that shown.

[0059] Figures 12A to 12F Schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0060] Figures 13A to 13H Schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0061] Figure 14 Schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0062] Figures 15A to 15F Schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0063] Figure 16 Schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0064] Figures 17A to 17D Schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0065] Figures 18A to 18G Schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0066] Figure 19 Schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0067] Figure 20 Schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure. Detailed implementation manners

[0068] The terms used in this document are used to describe the details of specific embodiments of the present invention, and all terms should be interpreted in the broadest possible sense. Certain terms will be emphasized specifically below; any restrictive terms will be defined by specific embodiments. In the present invention, the components and functions of a semiconductor structure or device can be illustrated by the following figures and embodiments. However, the dimensions and shapes of the semiconductor structures or devices shown in the figures do not limit the technical features of the present invention.

[0069] The term "on" in this specification may mean direct contact or being indirectly located above an intermediate element or intermediate layer. Spatial relative terms such as "beneath", "below", "lower", "above", "upper" and other relative terms may be used herein to facilitate the description of the relationship between an element or feature in a figure and another (other) element or feature. In addition to the directions described in the figures, these spatial relative terms are intended to include different directions of use or operation of the device. For example, when the device in the figure is turned upside down, an element described as "below" or "beneath" other elements or features will become positioned "above" the other elements or features. Therefore, the term "below" in the example includes both upward and downward directions. These devices may be positioned in another way (rotated 90 degrees or in other directions), and thus the spatial relative signs used herein can be interpreted in the same way.

[0070] Figure 1 It is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. As Figure 1 shown, the semiconductor structure 100 includes a first substrate 10, a second substrate 40 located on the first substrate 10, a first bonding layer 20 located between the first substrate 10 and the second substrate 40, and a first etch stop layer 30 located between the first bonding layer 20 and the second substrate 40. The second substrate 40 of the semiconductor structure 100 can be used to fabricate various semiconductor devices, including but not limited to transistors, diodes, capacitors, and / or resistors.

[0071] In one embodiment, the first substrate 10 and the second substrate 40 may each be a wafer with a diameter of 6 inches, 8 inches, 12 inches, or 18 inches. In this case, the first substrate 10 may be a handle wafer and the second substrate 40 may be a device wafer. The first substrate 10 and the second substrate 40 may be single crystalline semiconductor substrates, such as those made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In other embodiments, the first substrate 10 may include glass, polysilicon, or ceramic. In one embodiment, the thickness of the second substrate 40 may be in the range of about 5 nanometers (nm) to about 0.2 micrometers (μm). These values are merely illustrative and are not intended to limit the present disclosure.

[0072] The first etch stop layer 30 has a high etch selectivity with respect to the first bonding layer 20. The etch selectivity of the first etch stop layer 30 with respect to the first bonding layer 20 may refer to the ratio of the etch rate of the first bonding layer 20 to the etch rate of the first etch stop layer 30 under the same etching conditions. Under the same etching conditions, when the etch rate of the first bonding layer 20 is substantially greater than the etch rate of the first etch stop layer 30, the first etch stop layer 30 may have a high etch selectivity with respect to the first bonding layer 20. In some embodiments, the etch selectivity of the first etch stop layer 30 with respect to the first bonding layer 20 may be greater than 5:1. In some embodiments, the etch selectivity of the first etch stop layer 30 with respect to the first bonding layer 20 may be greater than 10:1, 20:1, 30:1, 50:1, 80:1, 100:1, 200:1, or 300:1.

[0073] For example, in one embodiment, the first etch stop layer 30 includes silicon nitride, and the first bonding layer 20 includes silicon oxide. Under appropriate etching conditions, such as using diluted hydrofluoric acid (e.g., a weight ratio of water to hydrogen fluoride of about 100:1) as the etchant, the etch rate of the first etch stop layer 30 (e.g., silicon nitride) is about 1 angstrom per minute, and the etch rate of the first bonding layer 20 (e.g., silicon oxide) is about 30 angstroms per minute, resulting in an etch selectivity of about 30:1 (silicon oxide / silicon nitride). The present disclosure is not limited thereto.

[0074] In some embodiments, other materials may be used for the first etch stop layer 30 and the first bonding layer 20 to achieve high etch selectivity under appropriate etch conditions of a dry etch process or a wet etch process. The appropriate materials for the first etch stop layer and the first bonding layer, as well as the appropriate etch conditions, can be selected according to actual requirements and material properties. Through the design of the present disclosure, the embedded first etch stop layer can be pre-formed in the semiconductor structure, which can substantially stop the etching of the bonding layer to protect the structures in the second substrate of the semiconductor structure. In this way, the difficulty of fabricating semiconductor devices and / or interconnect structures on both sides of the second substrate can be reduced.

[0075] In some embodiments, the first bonding layer 20 includes an oxide such as silicon oxide, and the first etch stop layer 30 may include silicon nitride, silicon oxynitride, a doped semiconductor material, an undoped semiconductor material, a metal, a conductive metal compound, or a combination of the foregoing. The doped semiconductor material may be a semiconductor material containing p-type dopants, such as boron, aluminum, gallium, indium, analogs thereof, or a combination of the foregoing; or a semiconductor material containing n-type dopants, such as phosphorus, arsenic, antimony, bismuth, analogs thereof, or a combination of the foregoing. The undoped semiconductor material may be amorphous silicon, polysilicon, silicon germanium, analogs thereof, or a combination of the foregoing. The metal may be aluminum, gold, copper, tungsten, analogs thereof, or an alloy of the foregoing. The conductive metal compound may be a metal silicide, a metal carbide, a metal nitride, analogs thereof, or a combination of the foregoing, such as tungsten nitride (WN), tantalum nitride (TaN), tantalum silicide (TaSi), titanium nitride (TiN), titanium silicide (TiSi), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), molybdenum nitride (MoN), iridium oxide (IrOx), ruthenium oxide (RuOx), or ruthenium titanium nitride (RuTiN).

[0076] In some embodiments, the first etch stop layer 30 includes a dielectric material such as silicon nitride, silicon oxynitride, analogs thereof, or a combination of the foregoing. The present disclosure is not limited thereto. AsFigure 1 As shown, in some embodiments, the first etch stop layer 30 is in direct contact with the first bonding layer 20. In this way, the first etch stop layer 30 can act as an etch stop layer during the removal process of the first bonding layer 20. However, in some embodiments, intervening layers (not shown) may be present between the first etch stop layer and the first bonding layer, as long as the removal process of the first bonding layer 20 can be stopped at the first etch stop layer 30. In one embodiment, the thickness of the first bonding layer 20 can be in the range of about 0.2 nanometers to about 1000 nanometers. In one embodiment, the thickness of the first etch stop layer 30 can be in the range of about 0.2 nanometers to about 5 nanometers. These values are merely illustrative and are not intended to limit the present disclosure.

[0077] Figure 2 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. As Figure 2 shown, the semiconductor structure 200 can be substantially similar to Figure 1 the semiconductor structure 100, where the same element symbols indicate the same elements. The semiconductor structure 200 includes a first substrate 10, a second substrate 40 located on the first substrate 10, a first bonding layer 20 located between the first substrate 10 and the second substrate 40, a first etch stop layer 31 located between the first bonding layer 20 and the second substrate 40, and an intermediate layer 51 located between the first etch stop layer 31 and the second substrate 40.

[0078] The first etch stop layer 31 can be substantially similar to Figure 1 the first etch stop layer 30, for example, the first etch stop layer 31 has a high etch selectivity with respect to the first bonding layer 20. In some embodiments, the etch selectivity of the first etch stop layer 31 with respect to the first bonding layer 20 can be greater than 5 to 1. In some embodiments, the etch selectivity of the first etch stop layer 31 with respect to the first bonding layer 20 can be greater than 10 to 1, 20 to 1, 30 to 1, 50 to 1, 80 to 1, 100 to 1, 200 to 1, or 300 to 1. As applicable, all other descriptions of the semiconductor structure 100 can apply here.

[0079] In some embodiments, the intermediate layer 51 includes a doped semiconductor material, a metal, a conductive metal compound, or a combination of the foregoing. In these embodiments, the first etch stop layer 31 can include silicon nitride or silicon oxynitride, however, the present disclosure is not limited thereto. In one embodiment, the thickness of the intermediate layer 51 can be in the range of about 10 nanometers to about 200 nanometers. In one embodiment, the thickness of the first etch stop layer 31 can be in the range of about 0.2 nanometers to about 5 nanometers. These values are merely illustrative and are not intended to limit the present disclosure. The intermediate layer can be conductive or can include an electron-conducting layer, such as Figure 2The intermediate layer 51 of the semiconductor structure 200 shown. However, the intermediate layer can be non-conductive, such as Figure 3 The intermediate layer 52 of the semiconductor structure 300 shown. In some embodiments, the intermediate layer 51 can be patterned. The pre-formed patterned conductive layer in the intermediate layer 51 of the semiconductor structure 200 can have various applications for different manufacturing purposes. For example, a part of the device or a functional element of the device can be formed or partially formed in the intermediate layer 51. In some embodiments, the intermediate layer 51 can include a stack of sublayers, which can include at least one patterned conductive sublayer, and the patterned conductive sublayer includes a doped semiconductor material, a metal, and / or a conductive metal compound as described above, which can be formed as a part of the device or a functional element of the device. In some embodiments, a sublayer or an additional layer of one or more intermediate layers can be disposed between this patterned conductive sublayer and the second substrate. However, in some embodiments, according to actual requirements, this patterned conductive sublayer can be in contact with the second substrate. In some embodiments, the patterned intermediate layer 51 or the patterned conductive sublayer can be electrically connected to a semiconductor device that has been formed or will be formed subsequently in the second substrate 40. The pre-formed part or element and / or the pre-formed sublayer that sets the part or element can be formed to have better contact with each other and / or better contact with the second substrate.

[0080] In one embodiment, the semiconductor structure 200 can further include an alignment mark 53 disposed in the second substrate 40. The patterning process of the intermediate layer 51, the manufacturing of the device in the second substrate 40, and / or the manufacturing of features above and / or below the second substrate 40 can be performed according to the alignment mark 53. In this way, introducing the alignment mark can further reduce the difficulty of manufacturing semiconductor devices or interconnect structures on both sides of the second substrate.

[0081] Figure 3 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. As Figure 3 shown, the semiconductor structure 300 can be substantially similar to Figure 2 the semiconductor structure 200, where the same element symbols indicate the same elements. The semiconductor structure 300 includes a first substrate 10, a second substrate 40 located on the first substrate 10, a first bonding layer 20 located between the first substrate 10 and the second substrate 40, a first etch stop layer 32 located between the first bonding layer 20 and the second substrate 40, and an intermediate layer 52 located between the first etch stop layer 32 and the second substrate 40.

[0082] The first etch stop layer 32 can be substantially similar to Figure 1The first etch stop layer 30, for example, the first etch stop layer 32 has a high etch selectivity with respect to the first bonding layer 20. In some embodiments, the etch selectivity of the first etch stop layer 32 with respect to the first bonding layer 20 can be greater than 5 to 1. In some embodiments, the etch selectivity of the first etch stop layer 32 with respect to the first bonding layer 20 can be greater than 10 to 1, 20 to 1, 30 to 1, 50 to 1, 80 to 1, 100 to 1, 200 to 1, or 300 to 1. Where applicable, all other descriptions regarding semiconductor structures 100 and 200 can apply here.

[0083] In the embodiment as Figure 3 shown, the intermediate layer 52 can include silicon oxide, a high-k material (including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide), or a combination of the foregoing. In one embodiment, the thickness of the intermediate layer 52 can be in the range of about 10 nanometers to about 200 nanometers. The first etch stop layer 32 can include silicon nitride, silicon oxynitride, a doped semiconductor material, a metal, a conductive metal compound, or a combination of the foregoing. In one embodiment, the thickness of the first etch stop layer 32 can be in the range of about 0.2 nanometers to about 5 nanometers. These values are only illustrative and are not intended to limit the present disclosure. The intermediate layer 52 can be patterned or unpatterned. The patterned or unpatterned intermediate layer 52 can have various applications for different manufacturing purposes. For example, the intermediate layer 52 can be formed as a gate dielectric layer. The dielectric layer pre-formed in the intermediate layer 52 can have better quality and can have better contact with the second substrate 40.

[0084] Figure 4 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. As Figure 4 shown, the semiconductor structure 400 can be substantially similar to Figure 1 the semiconductor structure 100, where the same element symbols indicate the same elements. The semiconductor structure 400 includes a first substrate 10, a second substrate 40 located on the first substrate 10, a first bonding layer 20 located between the first substrate 10 and the second substrate 40, a first etch stop layer 30 located between the first bonding layer 20 and the second substrate 40, and a second etch stop layer 60 located between the first substrate 10 and the first bonding layer 20.

[0085] The second etch stop layer 60 has a high etch selectivity with respect to the first substrate 10, such that under the same etching conditions, the etching rate of the first substrate 10 is substantially greater than the etching rate of the second etch stop layer 60. In some embodiments, the etch selectivity of the second etch stop layer 60 with respect to the first substrate 10 can be greater than 5 to 1. In some embodiments, the etch selectivity of the second etch stop layer 60 with respect to the first substrate 10 can be greater than 10 to 1, 20 to 1, 30 to 1, 50 to 1, 80 to 1, 100 to 1, 200 to 1, or 300 to 1. The appropriate materials for the second etch stop layer and the first substrate, as well as the appropriate etching conditions, can be selected according to actual requirements and material properties. Where applicable, all other descriptions of the semiconductor structure 100 can apply here. By designing in this way, the embedded second etch stop layer can be pre-formed in the semiconductor structure, which can substantially stop the etching of the first substrate to protect the underlying structure and provide various manufacturing options.

[0086] In some embodiments, the first substrate 10 can include single-crystalline semiconductor material or glass, and the second etch stop layer 60 can include silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, conductive metal compound, or a combination of the foregoing. In one embodiment, the second etch stop layer 60 can include a material or combination of materials different from the first etch stop layer 30. In one embodiment, the thickness of the second etch stop layer 60 can be in the range of about 0.2 nanometers to about 5 nanometers. These values are merely illustrative and are not intended to limit the present disclosure.

[0087] Figure 5 Schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. As Figure 5 shown, the semiconductor structure 500 can be substantially similar to Figure 1 the semiconductor structure 100, where the same element symbols indicate the same elements. The semiconductor structure 500 further includes a second etch stop layer 60 between the first substrate 10 and the first bonding layer 20, and a second bonding layer 21 between the first substrate 10 and the second etch stop layer 60.

[0088] The second etch stop layer 60 has a high etch selectivity with respect to the second bonding layer 21, such that under the same etching conditions, the etching rate of the second bonding layer 21 is substantially greater than that of the second etch stop layer 60. In some embodiments, the etch selectivity of the second etch stop layer 60 with respect to the second bonding layer 21 can be greater than 5:1. In some embodiments, the etch selectivity of the second etch stop layer 60 with respect to the second bonding layer 21 can be greater than 10:1, 20:1, 30:1, 50:1, 80:1, 100:1, 200:1, or 300:1. The appropriate materials for the second etch stop layer and the second bonding layer, as well as the appropriate etching conditions, can be selected according to actual requirements and material properties. As applicable, all other descriptions regarding the semiconductor structure 100 can apply here. By designing in this way, the embedded second etch stop layer can be pre-formed in the semiconductor structure, which can substantially stop the etching of the second bonding layer to protect the underlying structure and provide diverse manufacturing options.

[0089] In some embodiments, the second bonding layer 21 can include an oxide such as silicon oxide, and the second etch stop layer 60 can include silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, conductive metal compound, or a combination of the foregoing. In one embodiment, the thickness of the second bonding layer 21 can be in the range of about 0.2 nanometers to about 1000 nanometers. In one embodiment, the thickness of the second etch stop layer 60 can be in the range of about 0.2 nanometers to about 5 nanometers. These values are only illustrative and are not intended to limit the present disclosure.

[0090] Figure 6 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. As Figure 6 shown, the semiconductor structure 600 can be substantially similar to Figure 2 the semiconductor structure 200, where the same element symbols indicate the same elements. The semiconductor structure 600 further includes a second etch stop layer 60 between the first substrate 10 and the first bonding layer 20, and a second bonding layer 21 between the first substrate 10 and the second etch stop layer 60. The second etch stop layer 60 of the semiconductor structure 600 can be similar to the second etch stop layer 60 of the semiconductor structure 500 described with reference to Figure 5 As applicable, all other descriptions regarding the semiconductor structures 200 and 500 can apply here.

[0091] Figure 7 A schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. As Figure 7 shown, the semiconductor structure 700 can be substantially similar to Figure 3The semiconductor structure 300, where the same component symbols indicate the same components. The semiconductor structure 700 further includes a second etch stop layer 60 located between the first substrate 10 and the first bonding layer 20, and a second bonding layer 21 located between the first substrate 10 and the second etch stop layer 60. The second etch stop layer 60 of the semiconductor structure 700 can be similar to the second etch stop layer 60 of the semiconductor structure 500 with reference to Figure 5 described. When applicable, all other descriptions regarding the semiconductor structures 300 and 500 can apply here.

[0092] Figures 8A to 8D is a schematic diagram of an intermediate stage of manufacturing a semiconductor structure similar to Figure 1 shown.

[0093] As Figure 8A shown, a first structure 100A and a second structure 100B are provided. The first structure 100A includes a first substrate 10. The second structure 100B includes a second substrate 40 having a hydrogen ion implanted layer 70 therein, and a first etch stop layer 30 located on the second substrate 40. As previously described, the first substrate 10 and the second substrate 40 can be single crystal semiconductor substrates, such as made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In other embodiments, the first substrate 10 can include glass, polysilicon, or ceramic.

[0094] The first etch stop layer 30 can include silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, conductive metal compound, or a combination of the foregoing, similar to the first etch stop layer 30 with reference to Figure 1 described. The thickness of the first etch stop layer 30 can be in the range of about 0.2 nanometers to about 5 nanometers. These values are only illustrative and not intended to limit the present disclosure. The first etch stop layer 30 can be formed on the second substrate 40. In one embodiment, the first etch stop layer 30 is formed by epitaxial growth or by deposition such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In one embodiment, the first etch stop layer 30 is formed by sputtering or evaporation.

[0095] The hydrogen ion implanted layer 70 is implanted into the second substrate 40 at a specific depth before bonding the first structure 100A and the second structure 100B. The implantation can be performed before or after the formation of the first etch stop layer 30, as long as the hydrogen ion implanted layer 70 is not damaged by subsequent processes. For example, if a high temperature is required to form the first etch stop layer 30, the hydrogen ions should be implanted after the formation of the first etch stop layer 30. In one embodiment, hydrogen ions are implanted into the second substrate 40 using a dose of 1×1016 ions / cm2 to 2×1017 ions / cm2 and an implantation energy of 50 keV to 150 keV. Larger substrates can use larger doses. The hydrogen ion implanted layer 70 can be formed at a depth of about 4×10-5 inches to about 8×10-5 inches (1 μm to 2 μm) from the upper surface of the second substrate 40. These values are for illustration only and are not intended to limit the present disclosure. In one embodiment, since the thicknesses of the first etch stop layer 30 and the second dielectric layer 82 are known, the peak of the implanted hydrogen ions can be made to appear at the desired depth below the first etch stop layer 30 by selecting an appropriate implantation voltage. In one embodiment, when the first etch stop layer 30 includes a metal, the implantation can be performed before the formation of the first etch stop layer 30.

[0096] As Figure 8B shown, before bonding the first structure 100A and the second structure 100B, a first dielectric layer 81 is formed on the first substrate 10, and a second dielectric layer 82 is formed on the first etch stop layer 30. In one embodiment, only one of the first dielectric layer 81 and the second dielectric layer 82 is formed before bonding the first structure 100A and the second structure 100B. In one embodiment, the first dielectric layer 81 and / or the second dielectric layer 82 is formed by thermal oxidation or by deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the first dielectric layer 81 and / or the second dielectric layer 82 includes silicon oxide. In some embodiments, the implantation for forming the hydrogen ion implanted layer 70 can be performed after the formation of the second dielectric layer 82.

[0097] As Figure 8CAs shown, the second structure 100B is flipped and bonded to the first structure 100A with the first bonding layer 20 to form a bonded structure 100C. For example, the second structure 100B can be bonded to the first structure 100A through a fusion bonding process, such as a hydrophilic fusion bonding process. In one embodiment, both the first dielectric layer 81 and the second dielectric layer 82 are cleaned with conventional cleaning techniques, such as the RCA wafer cleaning process. The cleaning process removes impurities and particles on the surfaces of the dielectric layers 81 and 82. In one embodiment, due to the presence of atomic charges, hydroxyl groups are formed on the surfaces to be bonded. Hydrogen bonds can be formed between the first dielectric layer 81 and the second dielectric layer 82, and an annealing process can be performed to form chemical bonds (such as silicon-oxygen bonds) between the surfaces of the first dielectric layer 81 and the second dielectric layer 82.

[0098] In the embodiment as Figure 8C shown, the first dielectric layer 81 and the second dielectric layer 82 are bonded to form the first bonding layer 20. In some embodiments, when only one of the first dielectric layer or the second dielectric layer is formed before bonding the first structure 100A and the second structure 100B, one of the first dielectric layer or the second dielectric layer forms the first bonding layer 20 of the bonded structure 100C. In one embodiment, the thickness of the first bonding layer 20 can be in the range of about 0.2 nanometers to about 1000 nanometers. These values are only illustrative and are not intended to limit the present disclosure.

[0099] As Figure 8D shown, at about the hydrogen ion implantation layer 70, a portion of the second substrate 40 is removed from the bonded structure 100C. A portion of the second substrate 40 can be removed by heating the bonded structure 100C to a first temperature. The first temperature is generally lower than about 400 degrees Celsius (400 °C) to avoid any damage to the semiconductor devices (if any) fabricated in the second substrate 40. In some embodiments, a portion of the second substrate 40 can be removed by other methods, as long as a portion of the second substrate 40 has been sufficiently weakened by the previous hydrogen ion implantation and some subsequent annealing. For example, a mechanical pressure can be applied to the second substrate 40, or the bonded structure 100C can be quenched by immersing it in liquid nitrogen to cleave the bonded structure 100C.

[0100] Depending on the implantation depth of the implanted hydrogen ion layer 70, the remaining portion of the second substrate 40 on the bonding structure 100C can be less than 3 micrometers. The thickness of the remaining portion of the second substrate 40 can also depend on the semiconductor manufacturing technology node used to fabricate various semiconductor devices. After removing a portion of the second substrate 40, the separation surface of the second substrate 40 often has a roughness of several hundred angstroms. This separation surface of the second substrate 40 can be polished by chemical mechanical polishing (CMP) to planarize the separation surface and minimize its non-uniformity. Other methods such as etching can be used for the same purpose. When using etching to planarize the separation surface of the second substrate 40 and minimize its non-uniformity, it may be necessary to pre-deposit another etch stop layer.

[0101] Figures 9A to 9D Is a schematic diagram of an intermediate stage for manufacturing a semiconductor structure similar to Figure 2 As shown.

[0102] As Figure 9A Shown, a first structure 100A and a second structure 200A are provided. The first structure 100A includes a first substrate 10. The second structure 200A includes a second substrate 40 having an implanted hydrogen ion layer 70 therein, an intermediate layer 51 located on the second substrate 40, and a first etch stop layer 31 located on the intermediate layer 51. As described above, the intermediate layer 51 can include a doped semiconductor material, a metal, a conductive metal compound, or a combination of the foregoing, and the first etch stop layer 31 can include silicon nitride, silicon oxynitride, or a combination of the foregoing. In one embodiment, the thickness of the intermediate layer 51 can be in the range of about 10 nanometers to about 200 nanometers. In one embodiment, the thickness of the first etch stop layer 31 can be in the range of about 0.2 nanometers to about 5 nanometers. These values are only illustrative and are not intended to limit the present disclosure. The intermediate layer 51 can be formed on the second substrate 40. The first etch stop layer 31 can be formed on the intermediate layer 51. In one embodiment, the intermediate layer 51 and / or the first etch stop layer 31 are formed by epitaxial growth or by deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In one embodiment, the intermediate layer 51 and / or the first etch stop layer 31 are formed by sputtering or evaporation.

[0103] In some embodiments, depending on the actual application and circuit design, the intermediate layer 51 may be formed as a patterned layer before bonding the second structure 200A to the first structure 100A. The patterned intermediate layer may be fabricated by any suitable process, such as a photolithography and etch process, a damascene process, a dual damascene process, or similar processes. In some embodiments, a dielectric material may be deposited on the second substrate 40. Trenches may then be formed in the dielectric material layer by appropriate photolithography and etch techniques. For example, a photosensitive material (photoresist) may be deposited over the dielectric material layer and selectively removed. The etch process uses the mask element formed by the photoresist to etch a portion of the dielectric layer to form trenches. Then, deposition of a conductive material is performed to fill the trenches to form the patterned intermediate layer. This process may be repeated to form multiple sub-layers of the intermediate layer, where each sub-layer may have the same or different patterns. The patterned intermediate layer may provide better contact with the second substrate for routing and layout.

[0104] In one embodiment, the second structure 200A may further include alignment marks 53 disposed in the second substrate 40. The alignment marks 53 may be fabricated by appropriate methods. The patterning process of the intermediate layer 51, and subsequent fabrication of semiconductor devices and / or conductive features in and / or over the second substrate 40 may be performed based on the alignment marks 53. By using the same alignment marks 53 in the process of the intermediate layer 51 and the fabrication of semiconductor devices and / or conductive features, semiconductor devices and / or interconnect structures may be fabricated on both sides of the second substrate 40. In some embodiments, it may be necessary to remove portions of layers (such as the intermediate layer and / or its sub-layers) over the alignment marks 53 to expose the alignment marks 53.

[0105] The hydrogen ion implantation layer 70 is implanted into the second substrate 40 to a specific depth before bonding the first structure 100A and the second structure 200A. Similarly, the implantation may be performed before or after the formation of the intermediate layer 51, the first etch stop layer 31, or the second dielectric layer 82 (as Figure 9B described), as long as the hydrogen ion implantation layer 70 is not damaged by subsequent processes. The previously described implantation process and its related details may be applicable here.

[0106] As Figure 9BAs shown, before bonding the first structure 100A and the second structure 200A, a first dielectric layer 81 is formed on the first substrate 10, and a second dielectric layer 82 is formed on the first etch stop layer 31. In one embodiment, before bonding the first structure 100A and the second structure 200A, only one of the first dielectric layer 81 and the second dielectric layer 82 is formed. The formation of the dielectric layers 81 and 82 and the related details described above can be applied here.

[0107] like Figure 9C As shown, the second structure 200A is flipped over and bonded to the first structure 100A with the first bonding layer 20 to form a bonded structure 200B. The bonding process and related details described above are applicable here.

[0108] like Figure 9D As shown, a portion of the second substrate 40 is removed from the bonded structure 200B at approximately the location of the hydrogen ion implantation layer 70. The removal process and related details described previously may be applied here.

[0109] Forming something similar to Figure 3 The various intermediate stages of the semiconductor structure shown may be substantially similar to those described above. Figures 9A to 9D process. For example, the intermediate layer 51 and the first etch stop layer 31 are replaced by the intermediate layer 52 and the first etch stop layer 32, respectively. As described above, the intermediate layer 52 may include silicon oxide, a high dielectric constant material (including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide) or a combination of the foregoing. In one embodiment, the thickness of the intermediate layer 52 may be in the range of about 10 nanometers to about 200 nanometers. The first etch stop layer 32 may include silicon nitride, silicon oxynitride, a doped semiconductor material, a metal, a conductive metal compound or a combination of the foregoing. In one embodiment, the thickness of the first etch stop layer 32 may be in the range of about 0.2 nanometers to about 5 nanometers. These values ​​are only illustrative and are not intended to limit the content of the present disclosure. The intermediate layer 52 may be formed on the second substrate 40. The first etch stop layer 32 may be formed on the intermediate layer 52. In one embodiment, the intermediate layer 52 and / or the first etch stop layer 32 are formed by epitaxial growth or by deposition such as chemical vapor deposition, physical vapor deposition or atomic layer deposition. In one embodiment, the intermediate layer 52 and / or the first etching stop layer 32 are formed by sputtering or evaporation. Figures 9A to 9D The process and related details are applicable here.

[0110] Figures 10A to 10D According to an embodiment of the present disclosure, a similar Figure 4 Schematic diagram of an intermediate stage of a semiconductor structure shown.

[0111] like Figure 10AAs shown, a first structure 400A and a second structure 100B are provided. The first structure 400A includes a first substrate 10 and a second etch stop layer 60 located on the first substrate 10. The second structure 100B includes a second substrate 40 having an implanted hydrogen ion layer 70 therein and a first etch stop layer 30 located on the second substrate 40. As previously described, the second etch stop layer 60 may include silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, conductive metal compound, or a combination of the foregoing. In one embodiment, the second etch stop layer 60 may include a material or combination of materials different from the first etch stop layer 30. In one embodiment, the thickness of the second etch stop layer 60 may be in the range of about 0.2 nanometers to about 5 nanometers. These values are merely illustrative and are not intended to limit the present disclosure. The second etch stop layer 60 may be formed on the first substrate 10. In one embodiment, the second etch stop layer 60 is formed by epitaxial growth or by deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In one embodiment, the second etch stop layer 60 is formed by sputtering or evaporation. The previously described fabrication of the second structure 100B and its related details are applicable herein.

[0112] As Figure 10B shown, before bonding the first structure 400A and the second structure 100B, a first dielectric layer 81 is formed on the second etch stop layer 60, and a second dielectric layer 82 is formed on the first etch stop layer 30. In one embodiment, before bonding the first structure 400A and the second structure 100B, only one of the first dielectric layer 81 and the second dielectric layer 82 is formed. In one embodiment, the first dielectric layer 81 and / or the second dielectric layer 82 is formed by thermal oxidation or by deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the first dielectric layer 81 and / or the second dielectric layer 82 includes silicon oxide.

[0113] As Figure 10C shown, the second structure 100B is flipped and bonded to the first structure 400A with a first bonding layer 20 to form a bonded structure 400B. The previously described bonding process and its related details are applicable herein.

[0114] As Figure 10D shown, at about the implanted hydrogen ion layer 70, a portion of the second substrate 40 is removed from the bonded structure 400B. The previously described removal process and its related details are applicable herein.

[0115] Figures 11A to 11D is a schematic diagram of an intermediate stage of manufacturing a semiconductor structure similar to Figure 5 shown according to an embodiment of the present disclosure.

[0116] As Figure 11AAs shown, a first structure 500A and a second structure 100B are provided. The first structure 500A includes a first substrate 10, a second bonding layer 21 located on the first substrate 10, and a second etch stop layer 60 located on the second bonding layer 21. The second structure 100B includes a second substrate 40 having an implanted hydrogen ion layer 70 therein, and a first etch stop layer 30 located on the second substrate 40. As previously described, the second bonding layer 21 may include an oxide such as silicon oxide, and the second etch stop layer 60 may include silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, conductive metal compound, or a combination of the foregoing. In one embodiment, the thickness of the second bonding layer 21 may be in the range of about 0.2 nanometers to about 1000 nanometers. In one embodiment, the thickness of the second etch stop layer 60 may be in the range of about 0.2 nanometers to about 5 nanometers. These values are merely illustrative and are not intended to limit the present disclosure. The second bonding layer 21 may be formed on the first substrate 10. In one embodiment, the second bonding layer 21 is formed by thermal oxidation or by deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The second etch stop layer 60 may be formed on the second bonding layer 21. In one embodiment, the second etch stop layer 60 is formed by epitaxial growth or by deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In one embodiment, the second etch stop layer 60 is formed by sputtering or evaporation. The previously described manufacture of the second structure 100B and its related details are applicable herein.

[0117] As Figure 11B shown, before bonding the first structure 500A and the second structure 100B, a first dielectric layer 81 is formed on the second etch stop layer 60, and a second dielectric layer 82 is formed on the first etch stop layer 30. In one embodiment, before bonding the first structure 500A and the second structure 100B, only one of the first dielectric layer 81 and the second dielectric layer 82 is formed. In one embodiment, the first dielectric layer 81 and / or the second dielectric layer 82 is formed by thermal oxidation or by deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In some embodiments, the first dielectric layer 81 and / or the second dielectric layer 82 includes silicon oxide.

[0118] As Figure 11C shown, the second structure 100B is flipped and bonded to the first structure 500A with a first bonding layer 20 to form a bonded structure 500B. The previously described bonding process and its related details are applicable herein.

[0119] As Figure 11D shown, at about the implanted hydrogen ion layer 70, a portion of the second substrate 40 is removed from the bonded structure 500B. The previously described removal process and its related details are applicable herein.

[0120] Formed similar to Figure 6Various intermediate stages of the semiconductor structure shown may be substantially similar to those described above Figures 11A to 11D In one embodiment, the second structure 200A shown is flipped and bonded to the first structure 500A shown with a first bonding layer 20 to form a bonded structure. Then, at approximately the hydrogen ion implantation layer 70, a portion of the second substrate 40 is removed from the bonded structure to form a semiconductor structure similar to that shown in Figure 9A Figure 11A The processes described above and their related details may be applicable here Figure 6 Figures 11A to 11D

[0121] Various intermediate stages of forming a semiconductor structure similar to that shown in Figure 7 may be substantially similar to those described above Figures 11A to 11D For example, the intermediate layer 51 and the first etch stop layer 31 of the second structure 200A shown are respectively replaced with an intermediate layer 52 and a first etch stop layer 32. Then the second structure is flipped and bonded to the first structure 500A shown with a first bonding layer 20 to form a bonded structure. Then, at approximately the hydrogen ion implantation layer 70, a portion of the second substrate 40 is removed from the bonded structure to form a semiconductor structure similar to that shown in Figure 9A Figure 11A The intermediate layer 52 and the first etch stop layer 32 may respectively include similar materials to the intermediate layer 52 and the first etch stop layer 32 described above, and the forming method is also the same Figure 7

[0122] In other methods of manufacturing a semiconductor structure similar to that shown in Figure 2 , Figure 3 , Figure 5 , Figure 6 or Figure 7 , the intermediate layer 51 or 52 or the second bonding layer 21 may be used to bond the second structure to the first structure. In any embodiment, the layers below the specific layer used for bonding are formed on the first substrate 10 of the first structure. The layers above the specific layer used for bonding are formed on the second substrate 40 of the second structure. The specific layer used for bonding (such as the intermediate layer 51 or 52 or the second bonding layer 21) may be partially or fully formed on one or both of the first substrate 10 and the second substrate 40 before bonding. Other processes described above may be applicable to this manufacturing method

[0123] For example, manufacturing a semiconductor structure similar to that shown in Figure 5 ​​​​​The semiconductor structure shown provides a first structure and a second structure. The first structure includes a first substrate 10. The second structure includes a second substrate 40 having a hydrogen ion implanted layer 70 therein, a first etch stop layer 30 located on the second substrate 40, a first bonding layer 20 located on the first etch stop layer 30, and a second etch stop layer 60 located on the first bonding layer 20. Dielectric layers similar to the aforementioned first dielectric layer 81 and second dielectric layer 82 may be formed on one or both of the first structure and the second structure before bonding.

[0124] The second structure is flipped and bonded to the first structure with a second bonding layer 21 to form a bonded structure 500B, wherein the dielectric layers formed on the first structure and the second structure are bonded to form the second bonding layer 21. In one embodiment, the dielectric layers formed on the first structure and the second structure are bonded to form the second bonding layer 21. In another embodiment, when only one dielectric layer is formed on the first structure or the second structure before bonding, the dielectric layer forms the second bonding layer 21 of the bonded structure 500B. Then, at about the hydrogen ion implanted layer 70, a portion of the second substrate 40 is removed from the bonded structure to form a semiconductor structure similar to Figure 5 the one shown.

[0125] The above semiconductor structure can be used to manufacture various types of semiconductor devices, such as transistors, diodes, capacitors, and / or resistors. Transistors can include bipolar transistors (bipolar junction transistors, BJTs), field-effect transistors (FETs), and / or insulated-gate bipolar transistors (IGBTs). Field-effect transistors can include planar FETs, finFETs, and / or gate-all-around FETs (GAAFETs). Multiple embodiments of the process for manufacturing semiconductor devices are described below.

[0126] Figures 12A to 12F It is a schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0127] As Figure 12A shown, a semiconductor structure 101 is provided (step (a)). The semiconductor structure 101 can be similar to the aforementioned Figure 1 semiconductor structure 100. In Figure 12AIn the illustrated embodiment, the semiconductor structure 101 includes a first substrate 10, a second substrate 40 located on the first substrate 10, a first bonding layer 20 located between the first substrate 10 and the second substrate 40, and a first etch stop layer 30 located between the first bonding layer 20 and the second substrate 40. In one embodiment, the first etch stop layer 30 has a high etch selectivity with respect to the first bonding layer 20. All other descriptions regarding the semiconductor structure 100 are applicable herein.

[0128] As Figure 12A shown, a first portion of the semiconductor device is formed (step (b)). In some embodiments, the first portion of the semiconductor device may include device elements, such as transistors, diodes, capacitors, and / or resistors. The transistor may be a bipolar transistor (bipolar junction transistor), a field effect transistor, and / or an insulated gate bipolar transistor. The field effect transistor may be a planar field effect transistor, a fin field effect transistor, and / or a gate-all-around field effect transistor. In some embodiments, the first portion of the semiconductor device may include components of the device elements, such as the gate structure of a transistor, the dielectric layer of a transistor or capacitor, or the conductive component of a capacitor. The first portion of the semiconductor device may be formed in the second substrate 40 and / or on the first side 40a of the second substrate 40.

[0129] In as Figure 12A shown embodiment, the first portion of the semiconductor device includes a transistor 110, such as a planar metal oxide semiconductor field effect transistor (planar MOSFET). As Figure 12A shown, the transistor 110 is formed. The transistor 110 includes a source region 111 (source region), a drain region 112 (drain region), a channel region 113 (channel region) located between the source region 111 and the drain region 112, a gate structure 114 (gate structure) and a gate dielectric 115 (gate dielectric). The source region 111, the drain region 112, and the channel region 113 are formed in the second substrate 40. The source region 111 and the drain region 112 may include a first type of dopant (e.g., n-type dopant), and the channel region 113 may include a second type of dopant different from the first type of dopant (e.g., p-type dopant). As Figure 12A shown, the source region 111 and the drain region 112 of the transistor 110 may extend through the thickness of the second substrate 40. The source region 111 and the drain region 112 may be in contact with the first etch stop layer 30. The gate dielectric 115 and the gate structure 114 are formed above the channel region 113.

[0130] The transistor 110 can be formed by any suitable method. In one embodiment, the second substrate 40 can be etched to form trenches and define active regions, and an isolation structure 42 including a dielectric material (such as shallow trench isolation (STI)) can be formed in the trenches. The gate dielectric 115 and the gate structure 114 are formed on the active regions. Specifically, a stack of a gate dielectric layer (not shown) and a gate conductor layer (not shown) can be formed on the second substrate 40 and patterned and etched by lithography. The gate dielectric layer can include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, high-k materials (including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide), any suitable material, or a combination of the foregoing. The gate dielectric layer can be formed by thermal oxidation, deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, sputtering, evaporation, other suitable methods, and / or a combination of the foregoing. The gate conductor layer can be formed on the gate dielectric layer. The gate conductor layer can include a semiconductor material (such as polysilicon), a metal material (such as a metal or a conductive metal compound), any suitable material, or a combination of the foregoing. In some embodiments, a stack of a semiconductor material layer and a metal material layer can form the gate conductor layer. The gate conductor layer can be formed by epitaxial growth, deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, sputtering, evaporation, other suitable methods, and / or a combination of the foregoing. In some embodiments, a gate replacement process can be performed subsequently.

[0131] In one embodiment, forming the transistor 110 includes doping the second substrate 40. For example, in an embodiment where a source region 111 and a drain region 112 include a first type of dopant (such as an n-type dopant), and a channel region 113 includes a second type of dopant different from the first type of dopant (such as a p-type dopant), a selected type of dopant (such as the foregoing n-type dopant or p-type dopant) can be implanted into the second substrate 40 to form the source region 111, the drain region 112, and / or the channel region 113. In one embodiment, forming the transistor 110 includes etching the second substrate 40. For example, a portion of the second substrate 40 can be etched, and a subsequent epitaxy process can be performed to form the source region 111 and the drain region 112 of the transistor 110.

[0132] In an embodiment as Figure 12A shown, the first portion of the semiconductor device can further include a first capacitor 90. As Figure 12AAs shown, a first capacitor 90 is formed on a first side 40a of a second substrate 40 and is electrically connectable to a source region 111 of a transistor 110. The first capacitor 90 includes a first internal conductive component 91, a first external conductive component 93, and a first capacitive dielectric 92 located between the first internal conductive component 91 and the first external conductive component 93. The first internal conductive component 91 and the first external conductive component 93 may each include at least one conductive material, including but not limited to metals (such as tungsten (W), nickel (Ni), tantalum (Ta), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al), molybdenum (Mo), titanium (Ti), iridium (Ir), or ruthenium (Ru)); doped semiconductor materials (such as doped polysilicon, doped germanium); conductive metal compounds (such as metal silicides, metal carbides, or metal nitrides, such as tungsten nitride, tantalum nitride, tantalum silicide, titanium nitride, titanium silicide, titanium silicon nitride, titanium aluminum nitride, molybdenum nitride, iridium oxide, ruthenium oxide, or titanium ruthenium nitride). The first capacitive dielectric 92 may include silicon oxide, high-k materials (including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide), any suitable materials, and / or combinations of the foregoing. The first capacitor 90 may be formed by any suitable method.

[0133] In other embodiments, under appropriate etching conditions, for example, hot phosphoric acid may be used as an etchant. In one embodiment, when the first etch stop layer 30 includes tungsten and the first bonding layer 20 includes silicon oxide, trifluoromethane (CHF3) may be used as an etching gas to perform dry etching by reactive-ion etching. In one embodiment, when the first etch stop layer 30 includes tungsten in the first etch stop layer 30 (such as tungsten and silicon nitride), trifluoromethane may be used as an etching gas to perform dry etching by reactive-ion etching. In one embodiment, when the first etch stop layer 30 includes polysilicon and the first bonding layer 20 includes silicon oxide, nitrogen trifluoride (NF3) may be used as an etching gas to perform dry etching by remote plasma. In another embodiment, when the first etch stop layer 30 includes silicon nitride and the first bonding layer 20 includes silicon oxide, a mixed gas of chlorine trifluoride (ClF3) and hydrogen (H2) may be used to perform dry etching by reactive-ion etching of a decoupled plasma source.

[0134] As Figure 12BAs shown, a drain contact 117, a gate contact (not shown), and a dielectric layer 118 are formed. The dielectric layer 118 may include one or more stacked dielectric layers. The drain contact 117 is physically and electrically connected to the drain region 112 and is formed through one or more dielectric layers 118. The gate contact is physically and electrically connected to the gate structure 114 and is formed through one or more dielectric layers 118. A first interconnect structure 120 and a dielectric layer 121 are formed above the dielectric layer 118. The first interconnect structure 120 may include conductive features (such as wires and vias) electrically connected to a first portion of the semiconductor device. In an embodiment as shown in Figure 12B As shown, the first interconnect structure 120 may be physically and electrically connected to the drain contact 117 and / or the gate contact. In some embodiments, one of the wires of the first interconnect structure 120 may be a word line electrically connected to the gate structure 114. The dielectric layer 121 may include one or more stacked dielectric layers. As shown in Figure 12B As shown, the first interconnect structure 120 is formed on a first side 40a of the second substrate 40. The dielectric layer 118 and the dielectric layer 121 may include an interlayer dielectric (ILD) and / or an inter-metal dielectric (IMD), and may include dielectric materials such as silicon oxide, silicon oxynitride, low-k material, combinations of the foregoing, and / or other suitable materials, and may be formed by deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, spin coating, or any suitable method. The drain contact 117 and the gate contact may include titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, copper, some other suitable materials, or combinations of the foregoing, and may be formed in the dielectric layer 118 by an inlay process, a dual inlay process, or any suitable method. The first interconnect structure 120 may include titanium nitride, tantalum nitride, tungsten, ruthenium, aluminum, copper, some other suitable materials, or combinations of the foregoing, and may be formed in the dielectric layer 121 by an inlay process, a dual inlay process, or any suitable method.

[0135] As shown in Figure 12C As shown, an additional third substrate 130 is attached to the first side 40a of the second substrate 40, where the second substrate 40 is located between the third substrate 130 and the first substrate 10 (step (c)). In some embodiments, the first interconnect structure 120 may be located between the second substrate 40 and the third substrate 130. As shown in Figures 12A to 12C As shown, a first portion of the semiconductor device (such as the transistor 110) and the first interconnect structure 120 are formed before attaching the third substrate 130.

[0136] In one embodiment, the third substrate 130 may be a wafer with a diameter of 6 inches, 8 inches, 12 inches, or 18 inches. The third substrate 130 may be an operating wafer or a device wafer. In one embodiment, the third substrate 130 may include glass, polysilicon, or ceramic. In other embodiments, the third substrate 130 may be a single crystal semiconductor substrate, such as made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN). In one embodiment, the thickness of the third substrate 130 may be in the range of about 20 microns to about 700 microns. These values are merely illustrative and are not intended to limit the present disclosure. The third substrate 130 may include semiconductor devices, including but not limited to transistors, diodes, capacitors, and / or resistors. In one embodiment, the interconnect structure or semiconductor devices (not shown) of the third substrate 130 may be electrically connected to the first interconnect structure 120. In some embodiments, the third substrate 130 may be formed by epitaxial growth, chemical vapor deposition, physical vapor deposition, or atomic layer deposition. In one embodiment, the third substrate 130 may be bonded to the second substrate 40 by performing an appropriate process, such as adhesive bonding or direct bonding. The third substrate 130 may provide mechanical support for the semiconductor structure to avoid forming fractures and cracks during the process of manufacturing semiconductor devices.

[0137] As Figure 12DAs shown, the first substrate 10 and the first bonding layer 20 are removed to expose the first etch stop layer 30 (step (d)). The first substrate 10 and the first bonding layer 20 can be removed by performing appropriate processes, such as grinding, chemical mechanical polishing, and etching processes. The first etching process can be performed by applying a first etchant to remove the first substrate 10 and / or the first bonding layer 20. In one embodiment, the first substrate 10 is removed by a grinding and / or chemical mechanical polishing process, and the first bonding layer 20 can be removed by applying a first etchant, such as the aforementioned diluted hydrofluoric acid (e.g., a weight ratio of water to hydrogen fluoride of about 100 to 1). In one embodiment, when diluted hydrofluoric acid is used as the etchant, the etching rate of the first etch stop layer 30 (e.g., silicon nitride) is about 1 angstrom per minute, and the etching rate of the first bonding layer 20 (e.g., silicon oxide) is about 30 angstroms per minute, such that the etching selectivity is about 30 to 1 (silicon oxide / silicon nitride). In another embodiment, the first bonding layer 20 (e.g., silicon oxide) can be removed by applying a first etchant, such as buffered hydrofluoric acid (a mixture of hydrogen fluoride and a buffer such as ammonium fluoride). In one embodiment, when buffered hydrofluoric acid (e.g., an aqueous solution containing 6.6 wt% hydrogen fluoride (HF) and 35.7 wt% ammonium fluoride (NH4F)) is used as the etchant, the etching rate of the first etch stop layer 30 (e.g., silicon oxynitride) is about 24.5 nanometers per minute, and the etching rate of the first bonding layer 20 (e.g., silicon oxide) is about 305.7 nanometers per minute, such that the etching selectivity is about 12.5 to 1 (silicon oxide / silicon oxynitride). It should be noted that the etching conditions can be adjusted according to the actual application, and the present disclosure is not limited thereto. The materials of the first etch stop layer 30 and the first bonding layer 20 can be selected such that the first etch stop layer 30 can serve as an etch stop layer with high etching selectivity for the first bonding layer 20 and / or can serve as an etch stop layer under more appropriate etching conditions. The material of the first etch stop layer 30 can be selected such that in subsequent steps (as described below), the etch stop layer can be easily removed to expose the second substrate 40 and / or the intermediate layer (if present). In some embodiments, as discussed previously, the first etch stop layer 30 can include a dielectric material such that at least a portion of the first etch stop layer 30 can remain on the second substrate 40 to provide electrical insulation between the elements of the device (as described below).

[0138] The first etch stop layer 30 is exposed after step (d). In the embodiment as shown in Figure 12D the first etch stop layer 30 can protect the transistor 110 and the insulating structure 42 during the etching process. This can reduce the difficulty of fabricating semiconductor devices and / or interconnect structures on both sides of the second substrate.

[0139] As shown in Figure 12EAs shown, at least a portion of the first etch stop layer 30 is removed (step (e)). The first etch stop layer 30 can be removed by oxide etching, plasma retching, hydrogen peroxide etching, similar methods, or any suitable method. The second etching process can be performed by applying a second etchant to remove the first etch stop layer 30. In one embodiment, the first etch stop layer 30 including silicon nitride can be removed by applying a second etchant (such as hot phosphoric acid). However, the present disclosure is not limited thereto. At least a portion of the second substrate 40 is exposed after removing the first etch stop layer 30. Introducing the etch stop layer 30 can ensure the planarity of the exposed surface of the second substrate 40, and the etch stop layer 30 can be used to monitor the etch endpoint. In the embodiment as Figure 12E shown, the first etch stop layer 30 is completely removed (or at least the first etch stop layer 30 overlapping with the transistor 110 and the isolation structure 42 is completely removed). However, in other embodiments, only a portion of the first etch stop layer 30 can be removed by a suitable method (such as a lithographic etching process). For example, when the first etch stop layer 30 includes silicon nitride and the first bonding layer 20 has been removed, nitrogen trifluoride can be used as the etch gas, and dry etching can be performed by remote plasma to remove only a portion of the first etch stop layer 30, and the first etch stop layer 30 (such as silicon nitride) can have etch selectivities of 60 (silicon nitride / silicon dioxide) and 100 (silicon nitride / silicon) relative to silicon dioxide and silicon, respectively.

[0140] As Figure 12F shown, a second portion of the semiconductor device is formed on the second side 40b of the second substrate 40 (step (f)). The second portion of the semiconductor device can include device elements, such as transistors, diodes, capacitors, and / or resistors. In some embodiments, the second portion of the semiconductor device can include components of device elements, such as the gate structure of a transistor, the dielectric layer of a transistor or capacitor, or the conductive components of a capacitor. In some embodiments, the second portion of the semiconductor device may not be directly formed on the second substrate 40. For example, a dielectric layer (not shown) can be formed on the exposed surface of the second substrate 40, and the second portion of the semiconductor device is formed on the dielectric layer.

[0141] In the embodiment as Figure 12F shown, the second portion of the semiconductor device includes a second capacitor 94. As Figure 12FAs shown, the second capacitor 94 is formed on the second side 40b of the second substrate 40, and the second capacitor 94 includes a second internal conductive component 95, a second external conductive component 97 and a second capacitor dielectric 96 located between the second internal conductive component 95 and the second external conductive component 97. The second capacitor 94 can be electrically connected to the source region 111 of the transistor 110. The second capacitor 94 can be formed by any suitable method. The semiconductor device 1200 can be formed by forming a first portion of the semiconductor device (e.g., the transistor 110 and the first capacitor 90) on the first side 40a of the second substrate 40 and / or in the second substrate 40, and forming a second portion of the semiconductor device (e.g., the second capacitor 94) on the second side 40b of the second substrate 40. In an embodiment where only a portion of the first etch stop layer is removed, the second capacitor 94 can be formed on the remaining portion of the etch stop layer and can be electrically connected to the source region 111 of the transistor 110 through a contact structure extending through the first etch stop layer. In such an embodiment, the second capacitor 94 can be electrically connected to the source region 111 of the transistor 110 through a contact structure extending through the first etch stop layer. Figure 12F In the illustrated embodiment, the semiconductor device 1200 may be a memory cell, including but not limited to a memory cell of a dynamic random access memory (DRAM).

[0142] Advantages of the process disclosed herein include increasing the capacitance of the capacitor in the memory cell. First, additional capacitors (e.g., second capacitor 94) can be formed to increase the equivalent capacitance of the capacitor in the memory cell. Second, due to the increase in available area, the additional capacitors (e.g., second capacitor 94) fabricated on the second side 40b of the second substrate 40 can have a larger size, so the capacitance of the additional capacitors (e.g., second capacitor 94) can also be increased. In addition, the process disclosed herein helps to reduce the die size, thereby increasing the unit density.

[0143] Figures 13A to 13H FIG. 4 is a schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0144] like Figure 13A As shown, a semiconductor structure 102 is provided (step (a)). The semiconductor structure 102 may be similar to the aforementioned Figure 1 The semiconductor structure 100. Figure 13A In the illustrated embodiment, the semiconductor structure 102 includes a first substrate 10, a second substrate 40 located on the first substrate 10, a first bonding layer 20 located between the first substrate 10 and the second substrate 40, and a first etch stop layer 30 located between the first bonding layer 20 and the second substrate 40. In one embodiment, the first etch stop layer 30 has a high etching selectivity with respect to the first bonding layer 20. All other descriptions regarding the semiconductor structure 100 are applicable here.

[0145] As shown Figure 13A in, the first part of the semiconductor device is formed (step (b)). In the embodiment as shown Figure 13A in, the first part of the semiconductor device includes a fin field-effect transistor 140. A fin field-effect transistor 140 is formed, which includes a first source / drain region 141, a second source / drain region 142, a channel region 143 located between the first source / drain region 141 and the second source / drain region 142, a first gate structure 144, and a first gate dielectric 145. The first source / drain region 141, the second source / drain region 142, and the channel region 143 are formed in the second substrate 40. Specifically, the first source / drain region 141, the second source / drain region 142, and the channel region 143 may be formed in the fin structure of the second substrate 40. In the embodiment as shown Figure 13A in, the first source / drain region 141 and the second source / drain region 142 of the fin field-effect transistor 140 may extend through the second substrate 40 and contact the first etch stop layer 30. The channel region 143 is wrapped around by the first gate structure 144 and the first gate dielectric 145, such that the first source / drain region 141, the second source / drain region 142, the channel region 143, and the first gate structure 144 may together serve as a fin field-effect transistor. The length direction of the first gate structure 144 may be substantially perpendicular to the length direction of the fin structure.

[0146] The fin field-effect transistor 140 can be formed by any suitable method. The second substrate 40 can be etched to define a fin structure. The first gate dielectric 145 and the first gate structure 144 are formed on the fin structure. The first gate dielectric 145 can include silicon oxide, silicon nitride, high-k materials (including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide), combinations of the foregoing, or multilayer structures of the foregoing. The first gate structure 144 can include semiconductor materials (such as polysilicon), metal materials (such as metals or conductive metal compounds), combinations of the foregoing, or multilayer structures of the foregoing. In some embodiments, the first gate dielectric material layer and the first gate structure material layer can be deposited or thermally grown, and then lithographically patterned and etched according to applicable techniques to form the first gate dielectric 145 and the first gate structure 144. In some embodiments, a gate replacement process can be performed subsequently. In one embodiment, forming the fin field-effect transistor 140 includes etching the second substrate 40. For example, in one embodiment, the first source / drain region 141 and the second source / drain region 142 can be formed by etching the fin structure of the second substrate 40 and epitaxially growing a suitable material. In one embodiment, forming the fin field-effect transistor 140 includes doping the second substrate 40. For example, in an embodiment where the first source / drain region 141 and the second source / drain region 142 include a first type of dopant (such as an n-type dopant), and the channel region 143 includes a second type of dopant different from the first type of dopant (such as a p-type dopant), a selected type of dopant (such as the foregoing n-type dopant or p-type dopant) can be implanted into the second substrate 40 to form the first source / drain region 141, the second source / drain region 142, and / or the channel region 143.

[0147] As Figure 13B shown, the first source / drain contact 146, the second source / drain contact 147, the first gate contact 150 (shown in Figure 13H ) and the dielectric layer 118 are formed. The dielectric layer 118 can include one or more stacked dielectric layers. The first source / drain contact 146 and the second source / drain contact 147 are physically and electrically connected to the first source / drain region 141 and the second source / drain region 142, respectively, and are formed through one or more dielectric layers 118. The first gate contact 150 is physically and electrically connected to the first gate structure 144, and is formed through one or more dielectric layers 118. The first interconnect structure 120 and the dielectric layer 121 are formed above the dielectric layer 118 on the first side 40a of the second substrate 40. The first interconnect structure 120 can include conductive features (such as wires and vias) electrically connected to a first portion of the semiconductor device. In such as Figure 13B and Figure 13HIn the illustrated embodiment, the first interconnect structure 120 may be physically and electrically connected to the first source / drain contact 146, the second source / drain contact 147, and / or the first gate contact 150. In one embodiment, the first interconnect structure 120 may also be electrically connected to a second portion of a semiconductor device formed on the second side 40b of the second substrate 40. The wires of the first interconnect structure 120 may extend in different directions. The dielectric layer 121 may include one or more stacked dielectric layers. The dielectric layer 118 and the dielectric layer 121 may include an interlayer dielectric layer and / or an intermetallic dielectric layer. The materials and processes for forming the dielectric layer 118 and the dielectric layer 121 may be similar to those of the dielectric layer 118 and the dielectric layer 121 as described in Figure 12B The first source / drain contact 146, the second source / drain contact 147, and the first gate contact 150 may include materials similar to the previously discussed drain contact 117 and may be formed in the dielectric layer 118 by an inlay process, a dual inlay process, or other suitable methods. The first interconnect structure 120 may include materials similar to those of the first interconnect structure 120 as described in Figure 12B and may be formed in the dielectric layer 121 by an inlay process, a dual inlay process, or any suitable method.

[0148] As Figure 13C shown, an additional third substrate 130 is added to the first side 40a of the second substrate 40, where the second substrate 40 is located between the third substrate 130 and the first substrate 10 (step (c)). As Figures 13A to 13C shown, a first portion of the semiconductor device (e.g., the fin field effect transistor 140) and the first interconnect structure 120 are formed before adding the third substrate 130. The addition of the third substrate 130 may be substantially similar to the process as described in Figure 12C and the related description is omitted for simplicity.

[0149] As Figure 13D shown, the first substrate 10 and the first bonding layer 20 are removed to expose the first etch stop layer 30 (step (d)). The removal of the first substrate 10 and the first bonding layer 20 may be substantially similar to the process as described in Figure 12D and the related description is omitted for simplicity.

[0150] As Figure 13E shown, at least a portion of the first etch stop layer 30 is removed (step (e)). The removal of the first etch stop layer 30 may be substantially similar to the process as described in Figure 12E and the related description is omitted for simplicity. In the embodiment as shown in Figure 13E , the first etch stop layer 30 is completely removed (or at least the portion of the first etch stop layer 30 overlapping with the fin field effect transistor 140 is completely removed). However, in other embodiments (e.g., Figure 14 and Figure 16In the illustrated embodiment, only a portion of the first etch stop layer 30 can be removed.

[0151] As Figure 13F illustrated, a second portion of the semiconductor device is formed on a second side 40b of the second substrate 40 (step (f)). In an embodiment as Figure 13F illustrated, the second portion of the semiconductor device may include a second gate dielectric 148 and / or a second gate structure 149. The second gate structure 149 overlaps a channel region 143 of the fin field effect transistor 140. In an embodiment as Figure 13F illustrated, a length direction of the second gate structure 149 may be substantially perpendicular to a length direction of the fin structure. However, the length direction of the second gate structure 149 can be adjusted according to actual applications. The second gate dielectric 148 may include a material similar to the previously discussed first gate dielectric 145, and the second gate structure 149 may include a material similar to the previously discussed first gate structure 144. In some embodiments, a stack (not shown) of a second gate dielectric layer and a second gate conductor layer may be deposited or thermally grown on the second side 40b of the second substrate 40. The stack of material layers may then be lithographically patterned and etched according to applicable techniques to form the second gate dielectric 148 and the second gate structure 149. By forming a first portion of the semiconductor device (e.g., the fin field effect transistor 140) on a first side 40a of the second substrate 40 and / or in the second substrate 40, and forming a second portion of the semiconductor device (e.g., the second gate dielectric 148 and the second gate structure 149) on the second side 40b of the second substrate 40, the semiconductor device 1300 can be formed.

[0152] Figure 13H is Figure 13G a schematic cross-sectional view of the semiconductor structure along line A-A'. As Figure 13G and 13H illustrated, a second gate contact 151 and a dielectric layer 119 can be formed. The dielectric layer 119 may include one or more stacked dielectric layers. The second gate contact 151 physically and electrically connects to the second gate structure 149 and is formed through one or more dielectric layers 119. A second interconnect structure 122 and a dielectric layer 123 are formed above the dielectric layer 119 on the second side 40b of the second substrate 40. The second interconnect structure 122 may include conductive features (e.g., wires and vias) electrically connected to the second portion of the semiconductor device. In an embodiment as Figure 13H illustrated, the second interconnect structure 122 may physically and electrically connect to the second gate contact 151. In one embodiment, the second interconnect structure 122 may also be electrically connected to the first portion of the semiconductor device (e.g., the fin field effect transistor 140), at Figure 19A more detailed description is provided therein. The dielectric layer 123 may include one or more stacked dielectric layers. The dielectric layer 119 and the dielectric layer 123 may include an interlayer dielectric layer and / or an intermetallic dielectric layer. The materials and processes for forming the dielectric layer 119 and the dielectric layer 123 may be similar to those of the dielectric layer 118 and the dielectric layer 121 as described in Figure 12B The second gate contact 151 may include materials similar to the previously discussed drain contact 117 and may be formed in the dielectric layer 119 by an inlay process, a dual inlay process, or any suitable method. The second interconnect structure 122 may include materials similar to those of the first interconnect structure 120 as described in Figure 12B and may be formed in the dielectric layer 123 by an inlay process, a dual inlay process, or any suitable method. In this way, the second interconnect structure 122 may be formed on the second side 40b of the second substrate 40 after removing the first substrate 10 and the first bonding layer 20 and after removing the first etch stop layer 30. The processes disclosed herein can be used to fabricate interconnect structures on both sides of the second substrate, which can provide additional wiring options and can reduce the size of the circuit and / or improve the performance of the semiconductor device. In the embodiments as shown in Figure 13G and Figure 13H the first gate structure 144 and the second gate structure 149 may extend across a plurality of fin structures, and the gate contacts 150 and 151 may not overlap with the channel region 143 of the fin field effect transistor 140.

[0153] Figure 14 is a schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0154] As shown in Figure 14 a semiconductor device 1400 is provided. The semiconductor device 1400 may be similar to the semiconductor device 1300 as described in Figure 13F wherein the same element symbols indicate the same elements. The process for manufacturing the semiconductor device 1400 may be substantially similar to the process as described in Figures 13A to 13H In the embodiment as shown in Figure 14 the first etch stop layer 30 of the semiconductor structure 102 provided in step (a) may include a dielectric material such as silicon nitride, silicon oxynitride, a high-k material (including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide), or a combination of the foregoing. As shown in Figure 14 at least one layer of the first etch stop layer 30 may remain on the second side 40b of the second substrate 40 instead of completely removing the first etch stop layer 30 (as shown in Figure 13EIn the embodiment shown in the figure), the first etch stop layer 30 may become the second gate dielectric 148 of the semiconductor device 1400. In one embodiment, at least a portion of the first etch stop layer 30 may be removed (step (e)) to reduce the thickness of the first etch stop layer 30 to provide a second gate dielectric 148 having a desired thickness. Figure 13G and Figure 13H The second gate contact 151 and the second gate contact (not shown) and the second interconnect structure (not shown) of the second interconnect structure 122. The process disclosed herein can provide a gate dielectric with better contact with the second substrate and can reduce the difficulty of forming a high-quality gate dielectric on the substrate, especially on the second side of the substrate.

[0155] Figures 15A to 15F FIG. 4 is a schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0156] like Figure 15A As shown, a semiconductor structure 301 is provided (step (a)). The semiconductor structure 301 may be similar to the aforementioned Figure 3 The semiconductor structure 300. Figure 15A In the illustrated embodiment, the semiconductor structure 301 includes a first substrate 10, a second substrate 40 located on the first substrate 10, a first bonding layer 20 located between the first substrate 10 and the second substrate 40, a first etch stop layer 32 located between the first bonding layer 20 and the second substrate 40, and an intermediate layer 52 located between the first etch stop layer 32 and the second substrate 40. In one embodiment, the first etch stop layer 32 has a high etching selectivity to the first bonding layer 20. The intermediate layer 52 may include silicon oxide, a high dielectric constant material (including but not limited to hafnium silicate, zirconium silicate, hafnium dioxide, zirconium dioxide), or a combination thereof. All other descriptions regarding the semiconductor structure 300 may apply here.

[0157] like Figure 15B As shown, the first part of the semiconductor device is formed (step (b)). Figure 15B In the illustrated embodiment, the first portion of the semiconductor device includes a fin field effect transistor 140. The fin field effect transistor 140 may be similar to the fin field effect transistor 140 described above. Figure 13A The fin field effect transistor 140, wherein the same reference numerals indicate the same elements, and can be similar to the above Figure 13A In the method of Figure 15B In the embodiment shown, a similar Figure 13B The first source / drain contact 146 , the second source / drain contact 147 , the dielectric layer 118 , the first interconnect structure 120 and the dielectric layer 121 .

[0158] likeFigure 15C As shown, an additional third substrate 130 is attached to the first side 40a of the second substrate 40, where the second substrate 40 is located between the third substrate 130 and the first substrate 10 (step (c)). Attaching the third substrate 130 can be substantially similar to the process as Figure 12C and Figure 13C described, and the related description is omitted for simplicity.

[0159] As Figure 15D shown, the first substrate 10 and the first bonding layer 20 are removed to expose the first etch stop layer 32 (step (d)). Removing the first substrate 10 and the first bonding layer 20 can be substantially similar to the process as Figure 12D and Figure 13D described, and the related description is omitted for simplicity.

[0160] As Figure 15E shown, at least a portion of the first etch stop layer 32 is removed to expose the intermediate layer 52 (step (e)). The first etch stop layer 32 can be removed by oxide etching, plasma etching, hydrogen peroxide etching, similar methods, or any suitable method. The second etching process can be performed by applying a second etchant to remove the first etch stop layer 32. In one embodiment, the first etch stop layer 32 including silicon nitride can be removed by applying a second etchant (such as the aforementioned hot phosphoric acid). However, the present disclosure is not limited thereto. At least a portion of the intermediate layer 52 is exposed after removing the first etch stop layer 32. In the embodiment as Figure 15E shown, the first etch stop layer 32 is completely removed (or at least the portion of the first etch stop layer 32 overlapping with the fin field effect transistor 140 is completely removed). However, in other embodiments (such as Figure 16 shown in the embodiment), only a portion of the first etch stop layer 32 can be removed by a suitable method (such as a lithographic etching process).

[0161] As Figure 15F shown, a second portion of the semiconductor device is formed on the second side 40b of the second substrate 40 (step (f)). In the embodiment as Figure 15F shown, the second portion of the semiconductor device includes a second gate structure 149. The second gate structure 149 can be similar to the second gate structure 149 as described above Figure 13F and can be formed by a similar method as described above. As Figure 15FAs shown, the second gate structure 149 is formed on the exposed surface of the intermediate layer 52 on the second side 40b of the second substrate 40. In this way, the intermediate layer 52 of the semiconductor structure 301 can include silicon oxide or a high-k material, which can serve as the second gate dielectric 148 of the semiconductor device 1500. In some embodiments, at least a portion of the intermediate layer 52 can be removed to reduce the thickness of the intermediate layer 52 to provide a second gate dielectric 148 with a desired thickness. In some other embodiments, the intermediate layer 52 of the semiconductor structure (such as the semiconductor structure 301) can be formed to have a desired thickness, and the step of subsequently removing the intermediate layer 52 can be omitted. A second gate contact 151 and a second gate contact (not shown) of a second interconnect structure 122 and a second interconnect structure (not shown) similar to those described as Figure 13G and Figure 13H can also be formed. The processes disclosed herein can provide a gate dielectric made of a desired material and having better contact with the second substrate, and can reduce the difficulty of forming a high-quality gate dielectric on the substrate, especially on the second side of the substrate.

[0162] Figure 16 FIG. is a schematic diagram of an intermediate stage in manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0163] As Figure 16 shown, a semiconductor device 1600 is provided. The semiconductor device 1600 can be similar to the semiconductor device 1500 described as Figure 15F , where like element symbols indicate like elements. For example, the intermediate layer 52 of the semiconductor structure (such as the semiconductor structure 301) can serve as the second gate dielectric 148 of the semiconductor device 1600. In the embodiment shown as Figure 16 , only a portion of the first etch stop layer 32 is removed, rather than completely removing the first etch stop layer 32 (as in the embodiment shown as Figure 15E ). Specifically, the first etch stop layer 32 can be partially removed by an appropriate method (such as a lithographic etching process) to form trenches and / or openings and expose at least a portion of the intermediate layer 52. The second gate structure 149 can be formed by filling the trenches and / or openings with a semiconductor material (such as polysilicon) and / or a metal material (such as a metal or a conductive metal compound), and the filling material outside the trenches and / or openings can be removed by an appropriate method, such as grinding, chemical mechanical polishing, and etching processes. The filling material can be formed by epitaxial growth, deposition such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, sputtering, evaporation, other appropriate methods, and / or a combination of the foregoing. A second gate contact 151 and a second gate contact (not shown) of a second interconnect structure 122 and a second interconnect structure (not shown) similar to those described as Figure 13G and Figure 13H can also be formed.

[0164] Figures 17A to 17D FIG. 4 is a schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0165] like Figure 17A As shown, a semiconductor structure 201 is provided (step (a)). The semiconductor structure 201 may be similar to the aforementioned Figure 2 A semiconductor structure 200, wherein the same reference numerals indicate the same elements. Figure 17A In the illustrated embodiment, the semiconductor structure 201 includes a first substrate 10, a second substrate 40 located on the first substrate 10, a first bonding layer 20 located between the first substrate 10 and the second substrate 40, a first etch stop layer 31 located between the first bonding layer 20 and the second substrate 40, and an intermediate layer 51 located between the first etch stop layer 31 and the second substrate 40. In one embodiment, the first etch stop layer 31 has a high etching selectivity with respect to the first bonding layer 20.

[0166] In such Figure 17A In the illustrated embodiment, the intermediate layer 51 includes a multilayer structure including a first intermediate layer 51a and a second intermediate layer 51b located between the first etch stop layer 31 and the second substrate 40. The first intermediate layer 51a may include a conductive material, such as a doped semiconductor material, a metal, a conductive metal compound, or a combination thereof. In some embodiments, the first intermediate layer 51a may be patterned. In some embodiments, the patterning process of the first intermediate layer 51a may be performed based on the alignment mark 53 disposed in the second substrate 40. The formation of the first intermediate layer 51a may be similar to the above-mentioned Figure 2 and Figure 9A The second intermediate layer 51b may include silicon oxide, a high dielectric constant material, or a combination thereof, and may be formed by deposition or any other appropriate method before forming the first intermediate layer 51a. All other descriptions of the semiconductor structure 200 are applicable here.

[0167] like Figure 17B As shown, the first portion of the semiconductor device (FinFET 140) is formed (step (b)). The FinFET 140 can be similar to the above-mentioned Figure 13A The fin field effect transistor 140, wherein the same reference numerals indicate the same elements, and can be similar to the above Figure 13A It can also be formed by a method similar to Figure 13B The first source / drain contact 146, the second source / drain contact 147, the dielectric layer 118, the first interconnect structure 120 and the dielectric layer 121. The fabrication of the FinFET 140, the contacts 146 and 147 and / or the first interconnect structure 120 may be performed based on the alignment mark 53.

[0168] like Figure 17C As shown, the third substrate 130 is attached to the first side 40a of the second substrate 40 (step (c)), and then the first substrate 10 and the first bonding layer 20 are removed to expose the first etching stop layer 31 (step (d)). Figures 12A to 12D , Figures 13C to 13D and Figures 15C to 15D The description of the process can be applied here.

[0169] like Figure 17D As shown, at least a portion of the first etching stop layer 31 is removed (step (e)). At least a portion of the first intermediate layer 51a is exposed after the first etching stop layer 31 is removed. Figure 17D In the embodiment shown, the first etch stop layer 31 is completely removed (or at least the first etch stop layer 31 overlapping the fin field effect transistor 140 is completely removed). However, in other embodiments, only a portion of the first etch stop layer 31 may be removed by a suitable method (e.g., a photolithography etching process). Figure 13G and Figure 13H The second gate contact 151 and the second gate contact (not shown) and the second interconnect structure (not shown) of the second interconnect structure 122 are connected to each other. Thus, a semiconductor device 1700 similar to the aforementioned semiconductor devices 1300, 1400, 1500 and / or 1600 is provided, wherein the same reference numerals indicate the same elements. Figure 17D In the illustrated embodiment, the first intermediate layer 51a may become the second gate structure 149 of the semiconductor device 1700, and the second intermediate layer 51b may become the second gate dielectric 148 of the semiconductor device 1700. The process disclosed herein may provide a gate structure and / or gate dielectric having better quality and better contact with the second substrate, thereby reducing the difficulty of forming the gate structure and / or gate dielectric on the second side of the substrate.

[0170] Figures 18A to 18G FIG. 1 is a schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure. Figures 18A to 18G , except for the changes described here, the steps are similar to Figures 13A to 13H and / or Figures 15A to 15F The steps described.

[0171] like Figure 18A As shown, a semiconductor structure 401 is provided (step (a)). The semiconductor structure 401 may be similar to the aforementioned Figure 4 The semiconductor structure 400. Figure 18AIn the illustrated embodiment, the semiconductor structure 401 includes a first substrate 10, a second substrate 40 located on the first substrate 10, a first bonding layer 20 located between the first substrate 10 and the second substrate 40, a first etch stop layer 30 located between the first bonding layer 20 and the second substrate 40, and a second etch stop layer 60 located between the first substrate 10 and the first bonding layer 20. In one embodiment, the second etch stop layer 60 has a high etch selectivity with respect to the first substrate 10. The second etch stop layer 60 may include silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, conductive metal compound, or a combination of the foregoing. All other descriptions regarding the semiconductor structure 400 are applicable herein.

[0172] As Figure 18B shown, a first portion of the semiconductor device (fin field effect transistor 140) is formed (step (b)). The fin field effect transistor 140 may be similar to the fin field effect transistor 140 as described above, where the same element symbols indicate the same elements, and may be formed by a method similar to the foregoing. Figure 13A Also, a first source / drain contact 146, a second source / drain contact 147, a dielectric layer 118, a first interconnect structure 120, and a dielectric layer 121 similar to those Figure 13A described may be formed. Figure 13B

[0173] As Figure 18C shown, a third substrate 130 is attached to the first side 40a of the second substrate 40 (step (c)). Attaching the third substrate 130 may be substantially similar to the process as Figure 12C and Figure 13C described, and related descriptions are omitted for brevity.

[0174] As Figure 18D shown, the first substrate 10 is removed to expose the second etch stop layer 60. The first substrate 10 may be removed by performing an appropriate process, such as grinding, chemical mechanical polishing, and etching processes.

[0175] As Figure 18E shown, after removing the first substrate 10, the second etch stop layer 60 is removed to expose the first bonding layer 20. The second etch stop layer 60 may be removed by oxide etching, plasma etching, hydrogen peroxide etching, similar methods, or any appropriate method. The third etching process may be performed by applying a third etchant to remove the second etch stop layer 60. In one embodiment, the second etch stop layer 60 including silicon nitride may be removed by applying a third etchant (such as hot phosphoric acid). However, the present disclosure is not limited thereto.

[0176] As Figure 18FAs shown, the first bonding layer 20 is removed to expose the first etch stop layer 30. In one embodiment, the exposed first bonding layer 20 can be removed by a grinding and / or chemical mechanical polishing process, and the remaining first bonding layer 20 can be removed by a first etching process. In an embodiment where the first bonding layer 20 comprises silicon oxide, the first etching process can be performed by applying a first etchant (such as the aforementioned diluted hydrofluoric acid).

[0177] As Figure 18G shown, at least a portion of the first etch stop layer 30 is removed (step (e)), and a second portion of the semiconductor device is formed on the second side 40b of the second substrate 40 (step (f)). Where applicable, all other descriptions regarding Figures 13E to 13F the process can apply herein. In this way, a semiconductor device 1800 similar to the aforementioned semiconductor devices 1300, 1400, 1500, 1600, and / or 1700 is provided, where the same element symbols indicate the same elements. In the process disclosed herein, the exposure of the second etch stop layer 60 can indicate the removal end point of the first substrate 10, so introducing the second etch stop layer 60 can make the removal of the first substrate 10 more controllable, and thus make the removal of the first bonding layer 20 more controllable. In this way, the manufacturing difficulties caused by uneven removal and / or over-removal of the first substrate 10 and / or the first bonding layer 20 can be alleviated.

[0178] Figure 19 is a schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0179] As Figure 19 shown, a semiconductor device 1900 is provided. The semiconductor device 1900 can be similar to Figure 13G the semiconductor device described, where the same element symbols indicate the same elements. The process of manufacturing the semiconductor device 1900 can be substantially similar to the process as Figures 13A to 13H described. In the embodiment as Figure 19 shown, the second source / drain contact 147 can be formed on the second side 40b of the second substrate 40 after removing the first substrate 10 and the first bonding layer 20, and after removing the first etch stop layer 30. The second source / drain contact 147 is physically and electrically connected to the second source / drain region 142, and is formed through one or more dielectric layers 119 and through the second gate dielectric 148. The second source / drain contact 147 can comprise a material similar to the previously discussed drain contact 117, and can be formed in the dielectric layer 119 by an inlay process, a dual inlay process, or any suitable method. In the embodiment as Figure 19In the illustrated embodiment, the second interconnect structure 122 is physically and electrically connected to the second source / drain contact 147, such that the second interconnect structure 122 can be electrically connected to the first part of the semiconductor device (e.g., the fin field effect transistor 140) through the second source / drain contact 147. In some embodiments, at least one or both of the first source / drain contact 146 and the second source / drain contact 147 can be formed on the second side 40b of the second substrate 40 and electrically connected to the second interconnect structure 122. The processes disclosed herein can provide additional wiring options and can reduce the size of the circuit and / or improve the performance of the semiconductor device.

[0180] Figure 20 FIG. is a schematic diagram of an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0181] As Figure 20 shown, a semiconductor device 2000 is provided. The semiconductor device 2000 can be similar to Figure 13G the semiconductor device described, where like element symbols indicate like elements. The process of manufacturing the semiconductor device 2000 can be substantially similar to the process described above, for example, as Figures 13A to 13H , Figure 14 or Figures 15A to 15F described. In the embodiment shown in Figure 20 , vias 160 can be formed on the second side 40b of the second substrate 40 after removing the first substrate 10 and the first bonding layer 20, and after removing at least a portion of the first etch stop layer 30. The vias 160 are formed through the second gate dielectric 148. As Figures 13A to 13H , Figure 14 and Figures 15A to 15F described, in some embodiments, the second gate dielectric 148 can be a dielectric layer formed after removing the first etch stop layer. In some embodiments, the second gate dielectric 148 can include a layer of the first etch stop layer. In some embodiments, the second gate dielectric 148 can include a portion of an intermediate layer that is exposed after removing the first etch stop layer.

[0182] The vias 160 are physically and electrically connected to the first gate structure 144. The vias 160 can include materials similar to the drain contact 117 discussed previously and can be formed in the second gate dielectric 148 by a damascene process, a dual damascene process, or any suitable method. The second gate structure 149 can be formed by a method similar to that described with reference to Figure 13F and can be physically and electrically connected to the vias 160. Thus, the first gate structure 144 can be electrically connected to the second gate structure 149 through the vias 160.

[0183] In the embodiment shown in Figure 20In the illustrated embodiment, the second interconnect structure 122 is formed to be physically and electrically connected to the second gate contact 151. In this way, the line for controlling the gate voltage can be disposed on the second side 40b of the second substrate 40, which can provide additional wiring options and can reduce the size of the circuit and / or improve the performance of the semiconductor device. However, in other embodiments, the first gate structure 144 can be electrically connected to an interconnect structure disposed on the first side 40a of the second substrate 40, such as an interconnect structure similar to Figure 13H the illustrated first interconnect structure 120, rather than being electrically connected to the second interconnect structure 122 located on the second side 40b of the second substrate 40.

[0184] The process described herein can provide a quasi-GAAFET (quasi-gate-all-around field-effect transistor), in which the first gate structure 144 and the second gate structure 149 overlap the channel region 143 of the fin field-effect transistor 140, and the combination of the first gate structure 144 and the second gate structure 149 surrounds the channel region 143 of the fin field-effect transistor 140 on all four sides. The process described herein can provide an easy-to-implement manufacturing method for the quasi-GAAFET structure. In addition, by using an etch stop layer as described above, the complexity of the wiring can be alleviated and the space required for metal wires can be reduced.

[0185] The above semiconductor structure having an etch stop layer and its manufacturing method, the etch stop layer having a high etch selectivity for the bonding layer, has one or more of the following advantages.

[0186] 1. The semiconductor structure according to the present disclosure may include an etch stop layer located between the bonding layer and the second substrate, the etch stop layer having a high etch selectivity for the bonding layer. In this way, the etch stop layer can protect device elements (such as transistors, diodes, capacitors, and resistors), components of device elements (such as gate structures of transistors, dielectric layers of transistors or capacitors, or conductive components of capacitors), isolation structures (such as shallow trench isolation, silicon oxide, etc.), and / or interconnect structures in the second substrate during the etching process. In this way, the difficulty of manufacturing semiconductor devices and / or interconnect structures on both sides of the second substrate can be reduced. Introducing the etch stop layer can ensure the flatness of the exposed surface of the second substrate, and the etch stop layer can be used to monitor the etch end point.

[0187] 2. The semiconductor structure according to the present disclosure may further include alignment marks in the second substrate. In this way, introducing alignment marks can further reduce the difficulty of manufacturing semiconductor devices or interconnect structures on both sides of the second substrate.

[0188] III. The semiconductor structure according to the present disclosure may include an intermediate layer located between the etch stop layer and the second substrate. In some embodiments, the intermediate layer may be patterned. The patterned intermediate layer may provide wirings and layouts with better contact with the second substrate. In some embodiments, the intermediate layer of the semiconductor structure may include silicon oxide or a high-k material and may serve as the gate dielectric of the semiconductor device. The process disclosed herein may provide a gate dielectric made of a desired material and having better contact with the second substrate, and may reduce the difficulty of forming a high-quality gate dielectric on the substrate, especially on the second side of the substrate.

[0189] IV. The semiconductor structure according to the present disclosure may further include a second etch stop layer located between the first substrate and the bonding layer, and the second etch stop layer has a high etch selectivity with respect to the first substrate. In the process disclosed herein, the exposure of the second etch stop layer may indicate the removal end point of the first substrate. Therefore, introducing the second etch stop layer may make the removal of the first substrate more controllable, so that the removal of the first bonding layer can be made more controllable. In this way, the manufacturing difficulties caused by uneven removal and / or over-removal of the first substrate and / or the first bonding layer can be alleviated.

[0190] V. A method for manufacturing a semiconductor structure is provided according to the present disclosure, and a person of ordinary skill in the art can fabricate the semiconductor structure as described above through this method. In this way, the semiconductor structure can be fabricated cost-effectively.

[0191] VI. The method for manufacturing a semiconductor device according to the present disclosure may include forming a first part of the semiconductor device and removing at least a part of the first etch stop layer. In some embodiments, the method further includes forming a second part of the semiconductor device on the second side of the second substrate. In some embodiments, the first etch stop layer may be completely removed to expose the layer under the first etch stop layer (such as the second substrate or the intermediate layer). In some embodiments, the first etch stop layer may be partially removed by an appropriate method (such as a lithography etching process) to form trenches and / or openings and expose at least a part of the second substrate or the intermediate layer. When the first etch stop layer includes silicon oxide or a high-k material, at least one layer of the first etch stop layer may remain on the second substrate, and this layer of the first etch stop layer may serve as the gate dielectric of the semiconductor device. In this way, the first etch stop layer can be completely or partially removed according to actual requirements and material properties.

[0192] VII. Through the process provided by the method of manufacturing a semiconductor device according to the present disclosure, it is possible to achieve manufacturing semiconductor devices and / or interconnect structures on both sides of a second substrate. In one embodiment, a first portion of the semiconductor device on a first side of the second substrate includes transistors, and a second portion of the semiconductor device on a second side of the second substrate includes a capacitor electrically connected to the source region of the transistor. The semiconductor device may be a memory cell, including but not limited to memory cells of DRAM. In one embodiment, a first portion of the semiconductor device on a first side of the second substrate includes fin field-effect transistors, and a second portion of the semiconductor device on a second side of the second substrate includes a second gate structure. In some embodiments, a first interconnect structure located on a first side of the second substrate and a second interconnect structure located on a second side of the second substrate may be formed. In some embodiments, the first interconnect structure is electrically connected to the first portion of the semiconductor device, and the second interconnect structure is electrically connected to the second portion of the semiconductor device. In one embodiment, the first interconnect structure may also be electrically connected to the second portion of the semiconductor device, and the second interconnect structure may also be electrically connected to the first portion of the semiconductor device. In one embodiment, the first portion of the semiconductor device may be electrically connected to the second portion of the semiconductor device through vias.

[0193] The above description of the embodiments can be used by those of ordinary skill in the art to implement the present subject matter. Various modifications to the embodiments will be apparent to those of ordinary skill in the art, and the basic principles determined herein can be applied to other embodiments without creative effort. Therefore, the claimed subject matter is not limited only to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein. Other embodiments are contemplated to be within the spirit and scope of the present disclosure. Therefore, the present invention is intended to cover modifications and variations within the scope of the appended patent claims and their equivalents.

Claims

1. A semiconductor structure, comprising: A first substrate, A second substrate located on the first substrate, A first bonding layer located between the first substrate and the second substrate, A first etch stop layer located between the first bonding layer and the second substrate, wherein the first etch stop layer has a high etch selectivity with respect to the first bonding layer.

2. The semiconductor structure of claim 1, wherein the second substrate is made of silicon, germanium, silicon germanium, gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), or gallium nitride (GaN).

3. The semiconductor structure of claim 1, wherein the first bonding layer comprises silicon oxide, and the first etch stop layer comprises silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, or conductive metal compound.

4. The semiconductor structure of claim 1, wherein the first etch stop layer comprises a dielectric material.

5. The semiconductor structure of claim 1, wherein the first etch stop layer has an etch selectivity greater than 5:1 with respect to the first bonding layer.

6. The semiconductor structure of claim 1, further comprising: A second etch stop layer located between the first substrate and the first bonding layer, wherein the second etch stop layer has a high etch selectivity with respect to the first substrate.

7. The semiconductor structure of claim 6, wherein the first substrate comprises single crystal semiconductor material or glass, and the second etch stop layer comprises silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, or conductive metal compound.

8. The semiconductor structure of claim 1, further comprising: An intermediate layer located between the first etch stop layer and the second substrate.

9. The semiconductor structure of claim 8, wherein the intermediate layer comprises doped semiconductor material, metal, or conductive metal compound.

10. The semiconductor structure of claim 9, wherein the first etch stop layer comprises silicon nitride or silicon oxynitride.

11. The semiconductor structure of claim 9, wherein the intermediate layer is patterned.

12. The semiconductor structure of claim 8, wherein the intermediate layer comprises silicon oxide or high-k material.

13. The semiconductor structure of claim 12, wherein the first etch stop layer comprises silicon nitride, silicon oxynitride, doped semiconductor material, metal, or conductive metal compound.

14. The semiconductor structure of claim 1, further comprising alignment marks disposed in the second substrate.

15. The semiconductor structure of claim 1, further comprising: A second etch stop layer located between the first substrate and the first bonding layer; And A second bonding layer located between the first substrate and the second etch stop layer, wherein the second etch stop layer has a high etch selectivity with respect to the second bonding layer.

16. The semiconductor structure of claim 15, wherein the second bonding layer comprises silicon oxide, and the second etch stop layer comprises silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, or conductive metal compound.

17. A method of manufacturing a semiconductor structure, comprising: (a) Providing a first structure, the first structure comprising a first substrate; (b) Provide a second structure, which includes a second substrate and a first etch stop layer located on the second substrate, wherein the second substrate includes an implanted hydrogen ion layer; (c) Bond the first structure and the second structure with a bonding layer to form a bonded structure; and (d) Remove a portion of the second substrate from approximately the implanted hydrogen ion layer.

18. The method of claim 17, wherein the second substrate is made of silicon, germanium, silicon germanium, gallium arsenide GaAs, indium phosphide InP, silicon carbide SiC, or gallium nitride GaN.

19. The method of claim 17, wherein the bonding layer includes silicon oxide, and the first etch stop layer includes silicon nitride, silicon oxynitride, doped semiconductor material, undoped semiconductor material, metal, or conductive metal compound.

20. The method of claim 17, wherein step (b) includes: (b1) Provide the second substrate; (b2) Form the first etch stop layer on the second substrate; and (b3) Implant the hydrogen ion layer into the second substrate.

21. The method of claim 17, wherein step (c) includes forming a first dielectric layer on the first substrate and a second dielectric layer on the first etch stop layer before bonding.

22. The method of claim 17, wherein the bonded structure further includes: A second etch stop layer, located between the first substrate and the bonding layer.

23. The method of claim 22, wherein step (a) includes: (a1) Provide the first substrate; and (a2) Form the second etch stop layer on the first substrate.

24. The method of claim 23, wherein step (c) includes forming a first dielectric layer on the second etch stop layer and a second dielectric layer on the first etch stop layer before bonding.

25. The method of claim 17, wherein the bonded structure further includes: An intermediate layer, located between the first etch stop layer and the second substrate.

26. The method of claim 25, wherein step (b) includes: (b1) Provide the second substrate; (b2) Form the intermediate layer on the second substrate; (b3) Form the first etch stop layer on the intermediate layer; and (b4) Implant the hydrogen ion layer into the second substrate.

27. The method of claim 26, wherein step (b2) further includes patterning the intermediate layer.

28. A method of manufacturing a semiconductor device, including: (a) Provide a semiconductor structure, which includes a first substrate, a second substrate located on the first substrate, a bonding layer located between the first substrate and the second substrate, and a first etch stop layer located between the bonding layer and the second substrate; (b) Form a first portion of the semiconductor device; (c) Attach a third substrate to a first side of the second substrate, wherein the second substrate is located between the third substrate and the first substrate; (d) Remove the first substrate and the bonding layer of the semiconductor structure to expose the first etch stop layer; and (e) Remove at least a portion of the first etch stop layer.

29. The method of claim 28, wherein the first portion of the semiconductor device includes a transistor or a diode.

30. The method of claim 28, wherein step (b) comprises doping the second substrate or etching the second substrate.

31. The method of claim 28, further comprising: (f) forming a second portion of the semiconductor device on a second side of the second substrate.

32. The method of claim 31, wherein the first portion of the semiconductor device comprises a transistor, the transistor comprising a source region, a drain region, a channel region, and a gate structure, and the second portion of the semiconductor device comprises a capacitor, the capacitor being electrically connected to the source region of the transistor.

33. The method of claim 31, wherein the first portion of the semiconductor device comprises a transistor, the transistor comprising a first source / drain region, a second source / drain region, a channel region, and a first gate structure, and the second portion of the semiconductor device comprises a second gate structure, the second gate structure overlapping the channel region of the transistor.

34. The method of claim 33, further comprising: (g) forming a via on the second side of the second substrate, wherein the first gate structure is electrically connected to the second gate structure through the via.

35. The method of claim 28, further comprising forming a first interconnect structure on a first side of the second substrate before step (c).

36. The method of claim 28, further comprising forming a second interconnect structure on a second side of the second substrate after step (e).

37. The method of claim 28, wherein the semiconductor structure further comprises: an intermediate layer located between the first etch stop layer and the second substrate.

38. The method of claim 37, wherein step (e) comprises removing at least a portion of the first etch stop layer to expose the intermediate layer.

39. The method of claim 37, wherein the intermediate layer is patterned.

40. The method of claim 28, wherein step (d) comprises performing a first etching process by applying a first etchant.

41. The method of claim 28, wherein step (e) comprises performing a second etching process by applying a second etchant.

42. The method of claim 28, wherein the semiconductor structure further comprises alignment marks disposed in the second substrate.

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