Component carrier having rows of equidistant wiring elements at different heights connected to mutually spaced conductive regions and further wiring elements

Abstract

A component carrier (100) comprising: a stack (102) comprising at least two electrically insulating layer structures (106, 106 ', 106' ') and at least one electrically conductive layer structure (104, 104', 104 ''); a plurality of wiring elements (108) disposed in one of the at least two electrically insulating layer structures (106), the plurality of wiring elements (108) being arranged in a wiring plane (162) to form a first row (110) of equidistant wiring elements (108) and a second row (112) of equidistant wiring elements (108), the equidistant wiring elements of the first row are arranged in a linear direction in the wiring plane (162), and the equidistant wiring elements of the second row are arranged in a linear direction in the wiring plane (162); a plurality of further wiring elements (108 '), which are arranged in a further electrically insulating layer structure (106') of the at least two electrically insulating layer structures; wherein the at least one electrically conductive layer structure (104, 104 ', 104' ') comprises a plurality of conductive regions (111) electrically insulated from each other, each of the conductive regions (111) being connected to at least one of the plurality of wiring elements (108) and to at least one further wiring element of the plurality of further wiring elements (108'); and wherein each of the conductive regions (111) of the at least one electrically conductive layer structure (104, 104 ', 104' ') is spaced apart from a respective conductive region (111) connected to an adjacent wiring element (108, 108') by a distance (d), and wherein the distance (d) is at least 5% of a diameter (D1) of the wiring element (108, 108 ').

Description

Field of the Invention

[0001] The present invention relates to a component carrier and a method for manufacturing a component carrier. Background Art

[0002] Against the background of the increasing product functionality of component carriers equipped with one or more electronic components, the ever-increasing miniaturization of such electronic components, and the increasing number of electronic components to be mounted on component carriers such as printed circuit boards, more and more powerful array-shaped components or packages with multiple electronic components are being employed. The array-shaped components or packages have multiple contact parts or connection parts, and the pitch between these contact parts is getting smaller and smaller. Removing the heat generated by such electronic components and the component carrier itself during operation has become an ever-increasing problem. At the same time, the component carrier should be mechanically stable and electrically reliable so as to be able to operate even under harsh conditions.

[0003] It may be difficult to design a component carrier to meet one or more target requirements, such as those defined by specifications, especially when at least one powerful electronic component is surface-mounted on the upper surface of the component carrier. Summary of the Invention

[0004] The object of the present invention is to enable the manufacture of a component carrier that meets one or more target requirements.

[0005] To achieve the above object, a component carrier and a method for manufacturing a component carrier according to the independent claims are provided.

[0006] According to an exemplary embodiment of the present invention, there is provided a component carrier, which includes: a stack including at least two electrically insulating layer structures and at least one electrically conductive layer structure (preferably a plurality of electrically conductive layer structures); a plurality of wiring elements disposed in one of the at least two electrically insulating layer structures, the plurality of wiring elements being arranged in a wiring plane to form an equidistant row of wiring elements in a first row and an equidistant row of wiring elements in a second row, the equidistant row of wiring elements in the first row being arranged in a straight-line direction in the wiring plane, and the equidistant row of wiring elements in the second row being arranged in the wiring plane along the straight-line direction; a plurality of additional wiring elements disposed in the other of the at least two electrically insulating layer structures, wherein the at least one electrically conductive layer structure includes a plurality of conductive regions electrically insulated from each other (the plurality of conductive regions may be planar, such as pads), each of the conductive regions being connected to at least one of the plurality of wiring elements and being connected to at least one of the plurality of additional wiring elements, and wherein each of the conductive regions of the at least one electrically conductive layer structure is spaced apart from a corresponding conductive region connected to an adjacent wiring element by a distance, wherein the distance is at least 5% (preferably at least 10%) of the diameter of the wiring element (especially the wiring element of the wiring plane having the first row and the second row).

[0007] According to another exemplary embodiment of the present invention, there is provided a method of manufacturing a component carrier, wherein the method includes: providing a stack including at least two electrically insulating layer structures and at least one electrically conductive layer structure (preferably a plurality of electrically conductive layer structures); forming a plurality of wiring elements in one of the at least two electrically insulating layer structures, the plurality of wiring elements being arranged in a wiring plane to form an equidistant row of wiring elements in a first row and an equidistant row of wiring elements in a second row, the equidistant row of wiring elements in the first row being arranged in a straight-line direction in the wiring plane, and the equidistant row of wiring elements in the second row being arranged in the wiring plane along the straight-line direction; forming a plurality of additional wiring elements in the other of the at least two electrically insulating layer structures; forming the at least one electrically conductive layer structure to include a plurality of conductive regions electrically insulated from each other, each of the conductive regions being connected to at least one of the plurality of wiring elements and being connected to at least one of the plurality of additional wiring elements; and forming each of the conductive regions of the at least one electrically conductive layer structure to be spaced apart from a corresponding conductive region connected to an adjacent wiring element by a distance, wherein the distance is at least 5% (preferably at least 10%) of the diameter of the wiring element (especially the wiring element of the wiring plane having the first row and the second row).

[0008] In the context of the present application, the term "component carrier" may in particular denote any support structure capable of accommodating one or more components thereon and / or therein to provide mechanical support and / or electrical connection. In other words, the component carrier may be configured as a mechanical and / or electronic carrier for components. In particular, the component carrier may be one of a printed circuit board, an organic interposer, and an IC (integrated circuit) substrate. The component carrier may also be a hybrid board combining different types of component carriers of the above-mentioned types of component carriers.

[0009] In the context of the present application, the term "stack" may in particular denote a sequence of two or more layer structures formed on top of each other. For example, the layer structures of the stack may be connected by lamination, i.e., by applying heat and / or pressure. Preferably, the stacked layer structures may be arranged parallel to each other.

[0010] In the context of the present application, the term "layer structure" may in particular denote a continuous layer, a patterned layer, or a plurality of non-continuous island-shaped elements in a common plane.

[0011] In the context of the present application, the term "routing element" may in particular denote an electrically conductive element forming part of a routing or electrical interconnection within the dielectric matrix of a stack. The routing element may be formed within an electrically insulating layer structure and be part of an electrically conductive layer structure. The routing element may include vertical vias for creating vertical electrical interconnections between different layer structures of the stack. The routing element may include electrically conductive vias that extend through the thickness of one or more layer structures and / or the stack, preferably from one major surface of the one or more layer structures and / or the stack to the opposite major surface and / or in a direction perpendicular or inclined with respect to one of the major surfaces of the one or more layer structures and / or the stack. Such vias may be through-holes, such as laser-drilled metal through-holes, mechanically drilled metal through-holes, sleeve-shaped through-holes, all-metal through-holes, metal pillars, etc. The routing element may also include horizontal electrically conductive structures, such as traces and / or pads. Additionally, the routing element may have a linear shape and / or a tapered shape, such as a cylindrical shape or a frustoconical shape.

[0012] In the context of the present application, the term "aligned equidistant wiring elements" may denote a set of wiring elements arranged along a straight line direction and having a constant mutual spacing between each pair of adjacent wiring elements in the row. In other words, for every two adjacent wiring elements belonging to the set, the mutual spacing may be the same. For example, only the equidistant wiring elements of the row may be arranged along the straight line direction. Alternatively, one or more additional wiring elements may also be arranged between the equidistant wiring elements of the row along the straight line direction. For example, the aligned equidistant wiring elements may be a sequence of at least three wiring elements, in particular a sequence of at least ten wiring elements, wherein these wiring elements have the same mutual spacing with respect to one or more adjacent wiring elements in the set. Those skilled in the art will understand that in forming the equidistant wiring elements, technical tolerances (especially manufacturing tolerances) may inevitably occur, which may result in very small deviations from the exactly same distance between adjacent wiring elements in the row. However, when designing a component carrier for subsequent manufacturing, the equidistant wiring elements (e.g., in the design document) may be defined as having the same mutual target distance from each other. For example, the actually manufactured equidistant wiring elements may have a mutual spacing or distance from each other that may deviate from the same target distance by no more than the diameter of the wiring element. For example, the actually manufactured equidistant wiring elements may have a mutual spacing or distance from each other that may deviate from the same target distance by less than 5%, in particular less than 2%. Due to technical tolerances, the dimensions (e.g., diameter) of the equidistant wiring elements may also inevitably vary, although in an embodiment the equidistant wiring elements may be configured (e.g., in the design document) to have the same dimensions (such as diameter). The length between two mutual wiring elements may be measured by measuring the distance between the center of the first wiring element and the center of the second wiring element (closest along the straight line direction).

[0013] In the context of the present application, the term "conductive region" can particularly denote a structure of an electrically conductive material, which is particularly a metal such as copper, and the structure of the electrically conductive material is arranged to serve as an electrical conductive connection between wiring elements of different wiring planes located at different vertical heights of a component carrier stack. In particular, such a conductive region can be a flat or planar structure. The conductive region can be configured as a pad, which can also be denoted as a pad. The corresponding conductive region can cover or surround the wiring element to increase the extension or connection area of the wiring element in the horizontal plane, thereby simplifying the connection with additional wiring elements arranged at another vertical height. For example, the conductive region can have an annular or circular shape. The thickness of the conductive region can be equal to the thickness of the electrically conductive layer structure. Additionally or alternatively, the thickness of the conductive region can be different from the thickness of the electrically conductive layer structure.

[0014] In the context of the present application, the term "wiring plane" can particularly denote a common plane provided with rows (i.e., a first row and a second row) of wiring elements. The common plane can be defined from a plan view perpendicular to one of the main surfaces of the layer structure and / or the stack. The common plane can be defined as a plane parallel to the main surface of the layer structure and / or the stack, preferably, the common plane corresponds to the main surface of the layer structure and / or the stack.

[0015] In the context of the present application, the term "diameter of the wiring element" can particularly denote the constant diameter of the wiring element when implemented with a vertical sidewall, particularly implemented as a cylindrical structure (e.g., a metal-filled mechanical via). Alternatively, in the case of an irregular (non-constant) diameter, the term "diameter of the wiring element" can denote the minimum measured value of the diameter of the wiring element, particularly the minimum measured value of the diameter of the wiring element measured from a direction perpendicular to the axis of the wiring element. When implemented as a tapered structure (e.g., a metal-filled laser via), the diameter can be, for example, the minimum diameter of the tapered wiring element having a frustoconical shape. When implemented as a hollow structure (e.g., a via located in a stack having a plated sidewall and a remaining hollow core), the diameter of the wiring element can be the outer diameter of the wiring element.

[0016] According to an exemplary embodiment of the present invention, there is provided a stacked-layer type component carrier, which includes wiring elements located in a wiring plane, and these wiring elements form rows of equally spaced wiring elements arranged along a straight-line direction. In addition, additional wiring elements are provided in another wiring plane. Furthermore, a plurality of mutually insulated conductive regions (such as pads) can be provided, and each conductive region is connected to the wiring elements located in this wiring plane and the additional wiring elements located in another wiring plane, so that the corresponding conductive region can be used as a wiring element interface. Advantageously, adjacent conductive regions connected to adjacent wiring elements can be spaced apart by a distance that is at least 5% of the diameter of the correspondingly connected wiring element. This design can achieve a simple, reliable, and compact interconnection of wiring elements located in different wiring planes, while maintaining a sufficient safety distance between adjacent conductive regions. This can reliably prevent unwanted electrical breakdown and destructive discharges as well as unnecessary short circuits.

[0017] In the following, further exemplary embodiments of the component carrier and the method will be described.

[0018] In an embodiment, each of the conductive regions in the conductive region of the at least one electrically conductive layer structure is spaced apart from the corresponding conductive region connected to an adjacent wiring element by a distance that is not greater than 30% (preferably, not greater than 20%) of the diameter of the wiring element. This upper limit can ensure a compact design of the component carrier. In addition, this design rule can facilitate compliance with strict requirements in terms of the current-carrying capacity of circuit elements and the resulting current density (i.e., the current-carrying capacity per unit area), such as 0.5 A / mm 2 to 15 A / mm 2 aspect.

[0019] In an embodiment, the wiring elements in the second row are arranged with an offset in a straight-line direction relative to the wiring elements in the first row. In the context of the present application, the term "offsetting rows of wiring elements" can specifically mean that the rows of wiring elements are arranged such that there is a spatial shift in the straight-line direction between the equally spaced wiring elements in the first row and the equally spaced wiring elements in the second row, and the wiring elements in the first row and the wiring elements in the second row are also arranged along the straight-line direction. More specifically, the equally spaced wiring elements in the second row can be shifted as a whole relative to the equally spaced wiring elements in the first row in the straight-line direction. Due to the non-zero offset, the wiring elements in the first row may not be aligned with the wiring elements in the second row in the straight-line direction. In addition, the wiring elements in the first row and the wiring elements in the second row may or may not be spaced apart or offset from each other in another direction perpendicular to the straight-line direction. The above two directions (i.e., the straight-line direction and the other direction) can be located within a common wiring plane. Arranging rows of wiring elements in an offset manner can facilitate meeting target requirements, such as one or more target current values to be achieved and / or the density of wiring elements within a specific surface, without the risk of destructive discharge occurring between adjacent wiring elements.

[0020] In an alternative embodiment, the wiring elements in the second row can be arranged without an offset in a straight-line direction relative to the wiring elements in the first row.

[0021] In an embodiment, the offset value of the offset of the equally spaced wiring elements in the second row relative to the equally spaced wiring elements in the first row in the straight-line direction is 1 / 2 of the mutual spacing between adjacent equally spaced wiring elements in the first row (for example, see Figure 2 ). In terms of the straight-line direction, the design rule can correspond to: the wiring elements in the second row are arranged in the middle between two corresponding wiring elements in the first row. In particular, such an embodiment can relate to a configuration in which the first row and the second row are also vertically shifted, i.e., also shifted along a direction perpendicular to the straight-line direction. This can ensure reliable electrical insulation between different wiring elements in different rows.

[0022] In another embodiment, the offset value of the offset of the equally spaced wiring elements in the second row relative to the equally spaced wiring elements in the first row in the straight-line direction is 1 / 3 of the mutual spacing between adjacent equally spaced wiring elements in the first row (for example, see Figure 4)。In terms of the straight-line direction, the design rule can correspond to: the wiring elements in the second row are arranged to be closer to the other of the two corresponding wiring elements in the first row than to one of the two corresponding wiring elements in the first row, where the distance ratio can be 2:1. In particular, this embodiment can relate to such a configuration: in this configuration, the first row and the second row are not vertically displaced, that is, all are arranged along the straight-line direction without being vertically spaced from the straight-line direction. Therefore, the design rule can correspond to such a configuration: in this configuration, the equally spaced wiring elements in the first row and the equally spaced wiring elements in the second row are at the same horizontal level in the wiring plane. In other words, the first row and the second row can extend along the same straight-line direction without being displaced from each other perpendicular to the common straight-line direction. The design rule can allow a large number of wiring elements to be arranged with less space consumption. Alternatively, a non-displacement along the vertical direction between the first row and the second row can be provided in an embodiment where the offset value corresponds to 1 / 2 of the mutual spacing between adjacent equally spaced wiring elements in the first row, and / or a displacement along the vertical direction between the first row and the second row can be provided in an embodiment where the offset value corresponds to 1 / 3 of the mutual spacing between adjacent equally spaced wiring elements in the first row.

[0023] In an embodiment, at least some of the wiring elements are arranged at the central part of the hexagonal virtual cells of the wiring plane, and each of the hexagonal virtual cells in the hexagonal virtual cells is adjacent to each other and shares the corresponding sides of the corresponding hexagons with the corresponding adjacent hexagons. Therefore, the plane of the wiring elements of the component carrier can be configured according to the Voronoi cells with hexagonal contours. Therefore, the wiring plane or the region of interest of the wiring plane can be virtually divided into a plurality of hexagonal virtual cells, and the plurality of hexagonal virtual cells can be directly connected to each other along the corresponding sides. For example, the wiring elements can be arranged in the central part of these hexagonal virtual cells and / or at the corners of these hexagonal virtual cells. The regular pattern of such virtual hexagonal virtual cells can be transformed into a highly symmetric wiring pattern, thereby forming a well-defined power distribution system. Therefore, no free space and gaps are left between adjacent hexagonal virtual cells. As an alternative to the hexagonal virtual cells, other embodiments can also implement cells with another contour, such as cells of regular triangles or rectangles (preferably squares). Subdividing the wiring plane into Voronoi cells has proven to be an effective means to achieve the electrical target requirements, such as target current-related values, in the constructed component carrier while ensuring electrical safety.

[0024] In an embodiment, the wiring elements are arranged such that the mutual distance between adjacent equally spaced wiring elements in the first row is equal to the mutual distance between adjacent equally spaced wiring elements in the second row. In other words, the pitch between adjacent equally spaced wiring elements in the first row of equally spaced wiring elements may be the same as the mutual distance between adjacent equally spaced wiring elements in the second row of equally spaced wiring elements. This can provide a high degree of symmetry and can thus contribute to a high current-carrying capacity and high electrical reliability.

[0025] In an embodiment, the plurality of additional wiring elements are arranged in an additional wiring plane parallel to the wiring plane, and the plurality of additional wiring elements are arranged according to a wiring element pattern corresponding to the wiring elements of the first row and the second row but with a different wiring element density from the wiring elements of the first row and the second row. For example, the above-described arrangement structure of the wiring elements may relate to a core having metallized vias (i.e., metal-filled mechanical drill vias), while the additional wiring elements may relate to a stack-up layer located on top of or at the bottom of the core and may include metallized laser vias (or vice versa). For example, compared to a core having larger metallized vias and a smaller number of wiring elements per unit area or volume, the wiring plane having wiring elements including metallized laser vias may have smaller-sized wiring elements and a higher number of wiring elements per unit area or volume. Although the density of the wiring elements may be different for the different wiring planes, the regularity of the patterns of the wiring elements in these different wiring planes may be corresponding. The wiring elements and the additional wiring elements may be electrically coupled to each other partially or entirely. For example, a plurality of additional wiring elements (e.g., metal-filled laser vias) may be electrically coupled to one wiring element (e.g., metal-filled mechanical drill holes) by connecting the additional wiring elements to corresponding conduction regions such as pads formed around the wiring element. In particular, at least one of the plurality of additional wiring elements may be connected to the surface (especially the main surface) of the conduction region, and at least one of the wiring elements may be connected to the other opposite surface (especially the main surface) of the conduction region.

[0026] In an embodiment, the wiring elements and the additional wiring elements are arranged in a shadow region of a component that is surface-mounted on a stack-up of component carriers. The shadow region of the surface-mounted component may correspond to the following spatial region in the stack-up: in this spatial region, electrical connections for the component should be arranged. For example, the shadow region may taper from the interior of the stack-up towards the surface-mounted component. Such tapering may reflect the fact that the integration density may be greater closer to the surface-mounted component compared to parts of the stack-up that are further away from the surface-mounted component. Such tapering may correspond to the redistribution function of the wiring elements and the additional wiring elements.

[0027] The shadow region of the surface-mounted component described above can be the projection of the surface-mounted component onto the wiring plane of the stack-up, in which wiring elements and additional wiring elements are arranged. In particular, the region directly below the component may be the most important in terms of electrical interconnection. For this purpose, specifically, the shadow region below a surface-mounted component (e.g., having a large number of I / O pads) can be a favorable region for arranging wiring elements and additional wiring elements in the above-described manner. The shadow region can extend vertically into the stack-up, or the shadow region can extend vertically such that the shadow region tapers towards the surface-mounted component. Such a tapering measure can reflect the layout structure of the redistribution structure below the surface-mounted component in order to achieve a larger pitch that conforms to the mounting base (e.g., a mounting base implemented as a printed circuit board) below the stack-up.

[0028] Thus, the component carrier can include at least one surface-mounted component, such as a semiconductor chip, and in particular, the at least one surface-mounted component is a power semiconductor chip or a processor chip. Multiple electronic components can also be surface-mounted on the stack-up. Additionally or alternatively, one or more electronic components can be embedded in the stack-up, and wiring elements can also provide services in terms of the electrical interconnection of one or more electronic components.

[0029] In an embodiment, the wiring elements are arranged in the core of the component carrier. Additionally, additional wiring elements can be arranged in a stack-up that is located on such a core of the component carrier. Thus, the component carrier can have a stack-up that has a central core made of a fully cured dielectric material, the central core having a relatively large thickness and having metallization holes extending through the central core. For example, the thickness of the core can be in the range of 500 μm to 2 mm. The stack-up can be formed on one or both of the two main opposite surfaces of such a core and can have a higher density of wiring elements, which can be implemented as metal-filled laser vias. The core can play a crucial role in power and signal distribution and can thus be designed according to the equidistant wiring element rows described above. However, the ingenious interconnection between the wiring elements of the core and the additional wiring elements of the stack-up can be achieved through the design of the above-described conduction regions and the interconnection of the above-described conduction regions with the wiring elements and additional wiring elements.

[0030] In an embodiment, the wiring element is a mechanical drill hole that is at least partially filled with metal, while the further wiring element is a laser drill hole that is at least partially filled with metal. According to this configuration, the wiring element can have straight sidewalls. For example, the wiring element can have a cylindrical shape or a hollow cylindrical shape. Correspondingly, the further wiring element can have tapered sidewalls. For example, the further wiring element can have a frustoconical shape that is completely filled with metal or that includes only a sleeve-shaped hollow metal filling.

[0031] In an embodiment, at least a portion of the conduction region is a pad. The pad can be a flat structure surrounding the connected wiring element to increase the contact surface for a further wiring element connected to the pad.

[0032] In an embodiment, at least a portion of the conduction region has a planar annular shape surrounding the respective wiring element in the wiring elements. Such an annular or ring-shaped structure can be formed around the flange face of the wiring element and be in direct contact with the wiring element.

[0033] In an embodiment, at least a portion of the conduction region is circular (in particular having a circular profile) and is aligned coaxially with the axis of the respective wiring element. Furthermore, in such a configuration of the conduction region, a direct physical contact can be established between the continuous conduction region and the flange face of the wiring element. This embodiment can achieve a high degree of symmetry and thus electrical reliability. In an example, the wiring element or the further wiring element can be in direct physical contact with one conduction region. In another example, the wiring element or the further wiring element can be in direct physical contact with two conduction regions, each conduction region being located at the opposite end portions of the (in particular further) wiring element, respectively.

[0034] In an embodiment, adjacent wiring elements of the electrically insulating layer structure have different cross-sectional areas. Thus, the diameter of the wiring element and thus the cross-sectional area of the wiring element can be used as individually adjustable design parameters to fine-tune the electrical characteristics of the component carrier. This can increase the design flexibility.

[0035] Correspondingly, adjacent further wiring elements of the further electrically insulating layer structure can have different cross-sectional areas. Thus, also in the further wiring plane, the diameters of different further wiring elements and thus the cross-sectional areas of different further wiring elements can be used as individually adjustable design parameters for locally adjusting the electrical characteristics of the component carrier. This can allow for taking into account local characteristics in one or more stack layers.

[0036] In another embodiment, adjacent wiring elements of the electrically insulating layer structure have the same cross-sectional area. In such an embodiment, all the wiring elements of a common wiring plane can have the same diameter and thus the same cross-sectional area. This can give the wiring plane a high degree of symmetry and enable a simplified design. In yet another embodiment, adjacent wiring elements of the electrically insulating layer structure have different cross-sectional areas (see, for example, Figure 27 ). This can allow for the achievement of a specific target current transmission or allow for a mix between a power transmission network and signal management.

[0037] Thus, adjacent additional wiring elements of the other electrically insulating layer structure can have the same cross-sectional area. However, the cross-sectional area of the additional wiring elements can be different from the cross-sectional area of the wiring elements. In this way, the core can be designed in a different manner than one or more of the stack designs.

[0038] In an embodiment, additional wiring elements connected to corresponding conduction regions have the same cross-sectional area as additional wiring elements connected to conduction regions to which adjacent wiring elements are connected. Alternatively, additional wiring elements connected to corresponding conduction regions have a different cross-sectional area from additional wiring elements connected to conduction regions to which adjacent wiring elements are connected.

[0039] In an embodiment, at least one of the conduction regions is electrically connected to at least two of the additional wiring elements. In this preferred embodiment, at least two of the additional wiring elements assigned to an additional wiring plane are all connected to the same conduction region in a directly physically contacting manner, in particular, at least two of the additional wiring elements assigned to an additional wiring plane are all connected to the same annular pad of the wiring elements of this wiring plane; preferably, at least three of the additional wiring elements assigned to an additional wiring plane are all connected to the same conduction region in a directly physically contacting manner, in particular, at least three of the additional wiring elements assigned to an additional wiring plane are all connected to the same annular pad of the wiring elements of this wiring plane. This can achieve a highly compact design and can allow for a more complex electronic connection architecture. Figure 5 A corresponding embodiment is shown in

[0040] In an embodiment, at least one of the conduction regions is connected to only one of the wiring elements. Thus, the corresponding conduction region can be assigned to exactly one wiring element of the central wiring plane.

[0041] In an embodiment, the number of additional wiring elements connected to the respective conduction regions connected to the wiring elements in the first row is higher than the number of additional wiring elements connected to the respective conduction regions connected to the wiring elements in the second row. Thus, equidistant wiring elements in different rows can be achieved by different configurations of the connected conduction regions and additional wiring elements. This can provide greater freedom in design and thus improve the flexibility of the design.

[0042] In an embodiment, the number of additional wiring elements connected to a larger conduction region is higher than the number of additional wiring elements connected to a smaller conduction region. Thus, when there is a larger conduction region, the larger conduction region can be used to connect more additional wiring elements than the additional wiring elements connected to the smaller conduction region.

[0043] In an embodiment, the number of additional wiring elements connected to the respective conduction regions connected to the wiring elements in the first row is the same as the number of additional wiring elements connected to the respective conduction regions connected to the wiring elements in the second row. In particular, the conduction regions may have the same area value. In such a configuration, equidistant rows of wiring elements can be connected to the respective additional wiring elements in the same way through the respective conduction regions.

[0044] In an embodiment, one conduction region in the conduction regions in a row (particularly the first row or the second row) is arranged such that it is spaced from another conduction region connected to the closest adjacent wiring element in another row (particularly the second row or the first row) by a distance that is at least 5% of the diameter of the wiring element. Thus, a 5% design rule can be applied to equidistant wiring elements in different rows.

[0045] In an embodiment, one conduction region in the conduction regions in a row (particularly the first row or the second row) is arranged such that it is spaced from another conduction region connected to an adjacent wiring element in the same row by a distance that is at least 5% of the diameter of the wiring element. Thus, a 5% design rule can be achieved for different wiring elements and conduction regions of equidistant wiring elements in the same row.

[0046] In an embodiment, an additional wiring element has a smaller size compared to a larger size of a wiring element, in particular, an additional wiring element has a smaller diameter compared to a larger diameter of a wiring element. Different regions of the stack may be provided with different wiring element densities, i.e., different numbers of wiring elements per unit volume or area. For example, such a density in the core may be less than that in the stack. In regions with a higher integration density, in particular in the stack located on the core, the size of each additional wiring element may be smaller than the size of the wiring element in a region with a lower integration density, in particular in the core. For example, an additional wiring element of a smaller size may be formed as a metal-filled laser via, while a wiring element of a larger size may be formed as a metal-filled mechanical drill hole.

[0047] In an embodiment, the sum of the cross-sectional areas of the additional wiring elements connected to the same conduction region is equal to or greater than the cross-sectional area of the wiring element connected to the same conduction region. Thus, even though the cross-sectional area of each additional wiring element of an additional wiring plane may be smaller than the cross-sectional area of the connected wiring element of this wiring plane, a higher integration density of the additional wiring plane compared to this wiring plane may result in the total metal cross-sectional area of the additional wiring plane being the same as or even higher compared to this wiring plane.

[0048] In an embodiment, different regions of the component carrier have different distributions of wiring elements. Thus, the distribution of the wiring elements in the wiring plane may be non-uniform. This may allow taking into account local characteristics in different regions of the stack or different requirements for wiring. For example, the wiring element density in the wafer shadow region may be greater compared to other regions of the stack. This may reduce the manufacturing effort while fully meeting the functional requirements of the component carrier in the design.

[0049] In an embodiment, the component carrier includes a plurality of still other wiring elements, which are provided in other electrical insulation layer structures of the at least two electrical insulation layer structures and are located on a side of the electrical insulation layer structure opposite to the other electrical insulation layer structure. Some conduction regions may be connected to at least one of the plurality of still other wiring elements, wherein each of the some conduction regions may be spaced apart from a corresponding conduction region connected to an adjacent still other wiring element by a distance, and wherein the distance may be at least 5% of the diameter of the still other wiring element. Thus, a wiring plane having wiring elements may be connected at one side to the above-mentioned other wiring plane including additional wiring elements through the above-mentioned conduction regions. In addition, the wiring plane may be connected at its opposite other side to still other wiring elements of other wiring planes through conduction regions. In short, the interconnection of the still other wiring elements and the wiring elements through other conduction regions may be achieved in a manner corresponding to the interconnection manner of the additional wiring elements. Thus, a symmetric stack may be obtained. The wiring elements may be assigned to the core, while the additional wiring elements and the still other wiring elements may form parts of the stack located on two opposite main surfaces of the core.

[0050] In a corresponding manner, each of the some conduction regions may also be spaced apart from a corresponding conduction region connected to an adjacent wiring element by a distance. The distance may be at least 5% of the diameter of the wiring element.

[0051] In an embodiment, a wiring element having a first function has a different function from an adjacent wiring element. This heterogeneous interaction enables wiring elements with different functions to be distributed in a predetermined distribution order, thereby allowing optimization of the wiring elements with specific functions and corresponding conduction regions (i.e., increasing the diameter / area for power distribution) without affecting adjacent wiring elements and / or conduction regions with different functions (i.e., reducing the diameter / area for signal distribution and / or reference potential). In a preferred embodiment, in the case of the hexagonal virtual cell as described above, the wiring element / conduction region provided at the central portion of one cell in (each) cell has a different function from one or more wiring elements / conduction regions provided at one or more corners of the cell; for example, the wiring element / conduction region located at the central portion may have the function of distributing power in the component carrier, while the three wiring elements / conduction regions located at the corners may have the function of providing a ground potential, and the other three wiring elements / conduction regions located at the other three corners may have a voltage level different from the voltage level of the central wiring element. This means that for adjacent wiring elements / conduction regions, the two wiring elements / conduction regions are only divided planar by an overlying layer plane, in other words, there are no one or more additional wiring elements / conduction regions between the two wiring elements / conduction regions, and in particular, there are no one or more additional wiring elements / conduction regions extending along the same plane between the two wiring elements / conduction regions.

[0052] In an embodiment, a plurality of wiring elements are provided with different functions from each other, such that different functions can be distributed in a predetermined order, thereby allowing optimization of the wiring elements / conduction regions with specific functions without affecting adjacent wiring elements / conduction regions with different functions.

[0053] In an embodiment, a plurality of wiring elements / conduction regions are provided with different electrical functions from each other. In particular, the plurality of wiring elements / conduction regions are assigned different voltage levels and / or are assigned different sizes and / or are assigned different current-carrying capacities.

[0054] In an embodiment, a plurality of wiring elements / conduction regions on the same wiring plane in the at least one electrically insulating layer structure are provided with at least two different functions.

[0055] In an embodiment, a plurality of wiring elements / conduction regions on the same wiring plane in the at least one electrically insulating layer structure have at least three different functions. This provides the following advantage: the plurality of different functions can be distributed orderly and predictably, thereby avoiding negative impacts between different (adjacent) wiring elements in advance, even in the same planar layer.

[0056] In an embodiment, the wiring elements / conduction regions are used to distribute electrical power in the component carrier. This can be particularly advantageous for high-performance computing applications, artificial intelligence applications, processor applications, and applications that require a large amount of electrical energy during operation.

[0057] In an embodiment, some of the wiring elements / conduction regions in the wiring elements / conduction regions are used to distribute signals in the component carrier. The arrangement of the wiring elements in rows of equidistant wiring elements in the wiring plane can also support reliable signal transmission.

[0058] In an embodiment, some of the wiring elements / conduction regions in the wiring elements / conduction regions are used to provide a reference potential, in particular a ground potential, in the component carrier. In addition, it may also be necessary to have a ground potential or a similar potential to operate surface-mounted components. Some further wiring elements in the wiring elements can be used for heat dissipation.

[0059] In an embodiment, some of the wiring elements for distributing electrical power or electrical signals or providing a reference potential (such as a ground potential) are arranged on the wiring elements in the first row or the second row or the third row. Some of the wiring elements with different functions can also be arranged in another row among the first row, the second row, or the third row. For example, each row among the respective rows can have a separate function. The wiring elements in the first row can provide a first electrical function, while the wiring elements in the second row can provide another electrical function. If there are wiring elements in the third row, the wiring elements in the third row can provide a third electrical function, and so on.

[0060] In an embodiment, the wiring elements are arranged in the wiring plane according to Voronoi cells. In mathematics, a Voronoi cell can represent a region or partition of a plane (currently the wiring plane) that includes all points on the plane that are closer to a specific object on the plane (in this case, a mechanical drill-through hole) than to any other object. A set of Voronoi cells defines a Voronoi diagram. Voronoi cells can provide a good basis for determining the arrangement of the wiring elements in the wiring plane of the stack-up. Voronoi cells have a high degree of symmetry, and there can be no gaps between Voronoi cells. The high degree of symmetry of the corresponding arrangement of the wiring elements can be translated into well-defined and highly suitable electrical characteristics.

[0061] In an embodiment, the Voronoi cells are hexagonal virtual cells. In particular, each Voronoi cell is bounded by a regular hexagon. However, the Voronoi cells can also be triangular cells, rectangular cells, or other polygonal Voronoi cells.

[0062] In an embodiment, the method includes arranging routing elements to adjust the number of routing elements in a routing plane to comply with a predetermined specification. The specification may generally define attributes related to the electrical function of the routing plane or the component carrier to be designed. The routing elements may then be arranged in a first row, a second row, and optionally in additional rows to comply with the specification. This process may be performed manually or preferably automatically (e.g., by executing a fitting program and / or by applying artificial intelligence).

[0063] In an embodiment, the method includes arranging routing elements to adjust the current-carrying capacity of the routing elements in a routing plane. When designing the arrangement of the routing elements, a predetermined current density of the routing elements (i.e., the conduction current per cross-sectional metal area), e.g., from 0.5 A / mm 2 to 15 A / mm 2 value can be regarded as a boundary condition that the arrangement of the routing elements to be designed should satisfy.

[0064] In an embodiment, the method includes determining at least one of the spatial distribution, pad diameter, drill diameter, and / or functional grouping of the routing elements to satisfy a predetermined specification. Other parameters may also be considered in the design of the routing elements.

[0065] In an embodiment, the method includes arranging the routing elements according to the Voronoi cells of hexagons surrounding each routing element and by combining the grouped routing elements of adjacent Voronoi cells of hexagons into quadrilateral blocks, particularly parallelogram blocks (e.g., see Figure 26 ). The Voronoi cells can provide a virtual distribution of directly connected cells without gaps therebetween and can provide a suitable basis for a symmetric arrangement structure of the routing elements. The definition of the quadrilateral blocks, particularly parallelogram blocks, can further refine the designed arrangement of the routing elements.

[0066] In a further embodiment, the area of the conduction region (such as a pad) can be greater than 50% of the area of the entire routing plane. In particular, the area of the conduction region (such as a pad) can be greater than 70% of the area of the entire routing plane, at least in a part of the routing plane. In yet another embodiment, additional routing elements can be in contact with the peripheral portion of the conduction region. Additionally or alternatively, additional routing elements can be in contact with the central portion of the conduction region.

[0067] In an embodiment, the component carrier includes a stack-up which includes at least one electrically insulating layer structure and at least one electrically conductive layer structure. For example, the component carrier can be a laminate of the one or more electrically insulating layer structures and the one or more electrically conductive layer structures mentioned, in particular a laminate of the one or more electrically insulating layer structures and the one or more electrically conductive layer structures formed by applying mechanical pressure and / or thermal energy. The stack-up mentioned can provide a plate-shaped component carrier which can provide a large mounting surface for other components and is still very thin and compact.

[0068] In an embodiment, the component carrier is shaped as a plate. This contributes to a compact design in which, nevertheless, the component carrier still provides a large substrate for the mounting components on the component carrier. In addition, in particular, a die, as an example of an embedded electronic component, can be conveniently embedded in a thin plate such as a printed circuit board due to its small thickness.

[0069] In an embodiment, the component carrier is configured as one of a printed circuit board, a substrate (in particular an IC substrate), and an interposer.

[0070] In the context of the present application, the term "printed circuit board (PCB)" can particularly denote a plate-shaped component carrier formed by laminating a plurality of electrically conductive layer structures and a plurality of electrically insulating layer structures, for example by applying pressure and / or by supplying thermal energy. As a preferred material for PCB technology, the electrically conductive layer structures are made of copper, while the electrically insulating layer structures can include resin and / or glass fibers, so-called prepregs, or FR4 material. The individual electrically conductive layer structures can be connected to each other in a desired manner by forming holes through the laminate, for example by laser drilling or mechanical drilling, and by partially or completely filling these holes with an electrically conductive material (in particular copper), thereby forming vias or any other through-hole connections. The filled holes connect the entire stack-up (i.e., through-hole connections extending through multiple layers or the entire stack-up), or the filled holes connect at least two electrically conductive layers, i.e., so-called vias. Similarly, optical interconnects can be formed through the individual layers of the stack-up to accommodate an electro-optical circuit board (EOCB). In addition to the one or more components that can be embedded in the printed circuit board, the printed circuit board is generally configured to accommodate the one or more components on one surface or on the two opposite surfaces of the plate-shaped printed circuit board. The one or more components can be connected to the respective main surfaces by soldering. The dielectric part of the PCB can include a resin with reinforcing fibers (such as glass fibers).

[0071] In the context of the present application, the term "substrate" may specifically denote a small component carrier. Relative to a PCB, a substrate may be a relatively small component carrier on which one or more components can be mounted, and which can serve as a connection medium between one or more chips and another PCB. For example, a substrate may have approximately the same size as the components (especially electronic components) to be mounted on the substrate (e.g., in the case of a chip scale package (CSP)). More specifically, a substrate can be understood as such a carrier: a carrier for electrical connectors or electrical grids, and a component carrier comparable to a printed circuit board (PCB) but having a relatively high density of lateral and / or vertical connections. Lateral connections are, for example, conduction paths, while vertical connections can be, for example, drilled holes. These lateral and / or vertical connections are arranged within the substrate and can be used to provide electrical, thermal, and / or mechanical connections for accommodated or non-accommodated components (such as wafers), especially IC chips, to a printed circuit board or an intermediate printed circuit board. Thus, the term "substrate" also includes "IC substrate". The dielectric portion of the substrate may include a resin having reinforcing particles (such as reinforcing spheres, especially glass spheres).

[0072] The substrate or the interposer may include or be constituted of layers of at least one of the following: glass; silicon (Si) and / or photoimageable or dry-etchable organic materials, such as epoxy-based stack materials (such as epoxy-based stack films); or polymer compounds (the polymer compounds may or may not include photosensitive and / or thermosensitive molecules), such as polyimide or polybenzoxazole.

[0073] In an embodiment, the at least one electrically insulating layer structure comprises at least one of the following: a resin or polymer, such as an epoxy resin, a cyanate resin, a benzocyclobutene resin, a bismaleimide-triazine resin, a polyphenylene derivative (e.g., based on polyphenylene ether, PPE), a polyimide (PI), a polyamide (PA), a liquid crystal polymer (LCP), polytetrafluoroethylene (PTFE), and / or a combination thereof. Reinforcement structures such as meshes, fibers, spherical pieces, or other kinds of filler particles made of, for example, glass (multi-layer glass) can also be used to form a composite. A semi-cured resin in combination with a reinforcement, for example, a fiber impregnated with the above resin, is called a prepreg. These prepregs are usually named after their properties, such as FR4 or FR5, and the properties of these prepregs describe their flame retardant properties. Although prepregs, especially FR4, are generally preferred for rigid PCBs, other materials, especially epoxy-based stacked materials (such as stacked films) or photosensitive dielectric materials, can also be used. For high-frequency applications, high-frequency materials such as polytetrafluoroethylene, liquid crystal polymers, and / or cyanate resins can be preferred. In addition to these polymers, low-temperature co-fired ceramics (LTCC) or other low, very low, or ultra-low DK materials can be used as the electrically insulating structure in the component carrier.

[0074] In an embodiment, the at least one electrically conductive layer structure comprises at least one of the following: copper, aluminum, nickel, silver, gold, palladium, tungsten, and magnesium. Although copper is generally preferred, other materials or their coated variants, especially variants coated with a superconducting material or a conductive polymer, are also possible, the superconducting material or conductive polymer being, for example, graphene or poly(3,4-ethylenedioxythiophene) (PEDOT), respectively.

[0075] At least one additional component can be embedded in the stack-up and / or surface-mounted on the stack-up. The component and / or the at least one additional component can be selected from at least one of the following: a non-conductive inlay, a conductive inlay (such as a metal inlay, preferably including copper or aluminum), a heat transfer unit (e.g., a heat pipe), an optical guiding element (e.g., an optical waveguide or an optical conductor connection), an electronic component, or a combination thereof. The inlay can be, for example, a metal block (IMS-inlay) with or without an insulating material coating, which can be embedded or surface-mounted for the purpose of promoting heat dissipation. Suitable materials are defined according to the thermal conductivity of the material, and the thermal conductivity should be at least 2 W / mK. Such materials are generally based on but not limited to metals, metal oxides, and / or ceramics, such as copper, aluminum oxide (Al2O3), or aluminum nitride (AlN). In order to improve the heat exchange capacity, other geometries with an increased surface area are also often used. In addition, the component can be an active electronic component (implementing at least one p-n junction), a passive electronic component such as a resistor, an inductor, or a capacitor, an electronic chip, a storage device (e.g., DRAM or other data memories), a filter, an integrated circuit (such as a field programmable gate array (FPGA), a programmable array logic (PAL), a generic array logic (GAL), and a complex programmable logic device (CPLD)), a signal processing component, a power management component (such as a field effect transistor (FET), a metal oxide semiconductor field effect transistor (MOSFET), a complementary metal oxide semiconductor (CMOS), a junction field effect transistor (JFET), or an insulated gate field effect transistor (IGFET), all of which are based on semiconductor materials, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), gallium oxide (Ga2O3), indium gallium arsenide (InGaAs), and / or any other suitable inorganic compound), an optoelectronic interface element, a light-emitting diode, an optical coupler, a voltage converter (e.g., a DC / DC converter or an AC / DC converter), a cryptographic component, a transmitter and / or a receiver, an electromechanical transducer, a sensor, an actuator, a microelectromechanical system (MEMS), a microprocessor, a capacitor, a resistor, an inductor, a battery, a switch, a camera, an antenna, a logic chip, and an energy harvesting unit. However, other components can also be embedded on the component carrier. For example, a magnetic element can be used as a component. Such a magnetic element can be a permanent magnetic element (such as a ferromagnetic element, an antiferromagnetic element, a multiferroic element, or a ferrimagnetic element, such as a ferrite core) or can be a paramagnetic element. However, the component can also be an IC substrate, an interposer, or another component carrier, for example, in a board-in-board configuration. The component can be surface-mounted on the component carrier and / or can be embedded inside the component carrier.In addition, other components, in particular components that generate and emit electromagnetic radiation and / or are sensitive to electromagnetic radiation propagating from the environment, can be used as components.

[0076] In an embodiment, the component carrier is a laminated component carrier. In such an embodiment, the component carrier is a composite of a multi-layer structure that is stacked and joined together by applying pressure and / or heat.

[0077] After processing the internal layer structure of the component carrier, one or more additional electrically insulating layer structures and / or electrically conductive layer structures (in particular, by lamination) can symmetrically or asymmetrically cover one major surface or the opposite two major surfaces of the processed layer structure. In other words, stacking can continue until the desired number of layers is obtained.

[0078] After the formation of the stack having the electrically insulating layer structure and the electrically conductive layer structure is completed, the obtained layer structure or component carrier can be surface-treated.

[0079] In particular, in terms of surface treatment, an electrically insulating solder resist can be applied to one major surface or the opposite two major surfaces of the layer stack or component carrier. For example, such a solder resist can be formed over the entire major surface and then the layer of the solder resist can be patterned to expose one or more electrically conductive surface portions that will be used to electrically couple the component carrier to electronic peripherals. The surface portions of the component carrier that are kept covered by the solder resist, in particular the surface portions containing copper, can be effectively protected against oxidation or corrosion.

[0080] In terms of surface treatment, a surface finish can also be selectively applied to the exposed electrically conductive surface portions of the component carrier. Such a surface finish can be an electrically conductive covering material on the exposed electrically conductive layer structure (such as pads, conductive traces, etc., in particular including or consisting of copper) on the surface of the component carrier. If the exposed electrically conductive layer structure is not protected, the exposed electrically conductive component carrier material (especially copper) will be oxidized, resulting in a lower reliability of the component carrier. In addition, the surface finish can be formed as, for example, a joint between a surface-mounted component and the component carrier. The surface finish has the function of protecting the exposed electrically conductive layer structure (especially the copper circuit), and the surface finish can be used to achieve the joining process with one or more components, for example, by soldering. Examples of suitable materials for the surface finish are organic solderability preservatives (OSP), electroless nickel immersion gold (ENIG), electroless nickel immersion palladium immersion gold (ENIPIG), gold (especially hard gold), chemical tin, nickel gold, nickel palladium, etc.

[0081] In an embodiment, the body associated with the component carrier is a laminated component carrier. In this embodiment, the component carrier is a composite of a plurality of layer structures which are stacked and joined together by applying pressure and / or heat.

[0082] The above-defined aspects and further aspects of the invention become apparent by way of example of embodiments which will be described hereinafter and will be elucidated with reference to the examples of these embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1 A cross-sectional view of a component carrier according to an exemplary embodiment of the invention is shown.

[0084] Figure 2 Shows according to Figure 1 A plan view of a wiring plane of the component carrier.

[0085] Figure 3 A plan view of a wiring plane of a component carrier according to an exemplary embodiment of the invention is shown.

[0086] Figure 4 A plan view of a wiring plane of a component carrier according to an exemplary embodiment of the invention is shown.

[0087] Figure 5 A cross-sectional view of a part of a component carrier according to an exemplary embodiment of the invention is shown.

[0088] Figure 6 Shows according to Figure 5 A plan view of a part of a wiring plane of the component carrier.

[0089] Figure 7 Parts of a computer-based system for defining the distribution of wiring elements for a component carrier to be designed are shown, and a table with parameters for defining the structure and properties of a component carrier according to an exemplary embodiment of the invention is shown.

[0090] Figure 8 A plan view of wiring elements of a detail of a wiring plane of a component carrier according to an exemplary embodiment of the invention is shown.

[0091] Figure 9 A plan view of a part of a wiring plane of a component carrier according to an exemplary embodiment of the invention is shown, showing a mechanical drill-through via of a core and a laser drill-through via of a stack.

[0092] Figure 10 A plan view of a wiring plane of a component carrier according to an exemplary embodiment of the invention is shown.

[0093] Figure 11 Shows a cross-sectional view of a component carrier according to an exemplary embodiment of the present invention and a plan view of a wiring plane of the component carrier.

[0094] Figure 12 Shows according to Figure 11 A plan view of another wiring plane of the component carrier.

[0095] Figure 13 Shows Figure 11 And Figure 12 A plan view of a cladding of the wiring plane.

[0096] Figure 14 Shows a plan view of a part of a wiring plane of a component carrier according to an exemplary embodiment of the present invention.

[0097] Figure 15 Shows a cross-sectional view of a part of a component carrier according to an exemplary embodiment of the present invention.

[0098] Figure 16 Shows a plan view of a part of a wiring plane of a component carrier according to an exemplary embodiment of the present invention.

[0099] Figure 17 Shows a plan view of different wiring planes of a component carrier according to an exemplary embodiment of the present invention.

[0100] Figure 18 Shows a view similar to Figure 17 Indicating additional conduction regions around the wiring elements.

[0101] Figure 19 Shows Figure 18 Details of.

[0102] Figure 20 Shows a plan view of a wiring plane of a component carrier with additional wiring elements added according to an exemplary embodiment of the present invention.

[0103] Figure 21 Shows a plan view of a conventional wiring plane of a component carrier.

[0104] Figure 22 Shows a plan view of different wiring planes of a component carrier according to an exemplary embodiment of the present invention.

[0105] Figure 23 Shows a plan view of a wiring plane of a component carrier according to an exemplary embodiment of the present invention.

[0106] Figure 24A plan view of a wiring plane of a component carrier according to an exemplary embodiment of the present invention is shown.

[0107] Figure 25 A plan view of a wiring plane of a component carrier according to an exemplary embodiment of the present invention is shown.

[0108] Figure 26 A plan view of different wiring planes of a component carrier according to an exemplary embodiment of the present invention is shown.

[0109] Figure 27 A plan view of a wiring plane of a component carrier according to an exemplary embodiment of the present invention is shown. Detailed Description

[0110] The illustrations in the figures are schematic. In different figures, similar or identical elements are provided with the same reference numerals.

[0111] Before the exemplary embodiments will be described in more detail with reference to the figures, some basic considerations on which the exemplary embodiments of the present invention are based will be summarized.

[0112] According to an exemplary embodiment of the present invention, a (preferably laminated) component carrier is provided, which has an array of wiring elements in a wiring plane. The wiring plane may form a first row of equally spaced wiring elements arranged in a straight line direction within the wiring plane, and a second row of equally spaced wiring elements arranged in a straight line direction within the wiring plane. In addition, additional wiring elements may be provided in another wiring plane. In addition, at least one (preferably a plurality of) electrically conductive layer structures of a stack of component carriers may include a plurality of conductive regions (descriptively speaking, the conductive regions may be pads of wiring elements), and these conductive regions may be electrically insulated from each other. Each conductive region may be connected to a corresponding wiring element among the wiring elements and to a corresponding other wiring element among the other wiring elements. In addition, each of the conductive regions may extend in such a way that it is spaced apart from a conductive region connected to an adjacent wiring element by a distance (i.e., spaced apart from this conductive region): The distance is at least 5% of the value of the diameter of the wiring element. In an example, the distance between adjacent conductive regions may be 30 μm, while the diameter of the wiring element connected to the conductive region may be 400 μm (for example, when the wiring element is a metal-filled mechanical drill through hole located in a core). Thus, the above example corresponds to a ratio of 30 μm / 400 μm = 7.5%. The minimum distance of 5% can ensure reliable electrical decoupling of adjacent conductive regions and reliable electrical decoupling of adjacent wiring elements. This can effectively suppress adverse phenomena such as electrical short circuits, electrical breakdowns, or destructive discharges inside the component carrier.

[0113] In a preferred embodiment, the axes of the respective conduction regions can be coaxial with the axes of the corresponding wiring elements. It can also be preferred that each conduction region has a diameter such that the distance between the periphery of the conduction region and the periphery of the conduction region connected to an adjacent wiring element is at least 5% of the value of the diameter of the corresponding wiring element (e.g., 30 μm / 400 μm = 7.5%).

[0114] In one embodiment, the conduction areas of adjacent wiring elements have different area values. Alternatively, the conduction areas of adjacent wiring elements can also have the same area value.

[0115] For example, a plurality of additional wiring elements are provided in the respective conduction regions. In other words, one conduction region can be in direct physical contact with two or more additional wiring elements. For example, these additional wiring elements can be spatially distributed along a circumferential member that forms the conduction region and surrounds the wiring element.

[0116] In one embodiment, the number of additional wiring elements connected to the respective conduction regions connected to the wiring elements in the first row is higher than the number of additional wiring elements connected to the respective conduction regions connected to the wiring elements in the second row.

[0117] Furthermore, the number of additional wiring elements connected to a larger conduction region (i.e., a conduction region having a larger connection surface) can be higher than the number of additional wiring elements connected to a smaller conduction region (i.e., a conduction region having a smaller connection surface).

[0118] For example, the number of additional wiring elements connected to the respective conduction regions connected to the wiring elements in the first row is the same as the number of additional wiring elements connected to the respective conduction regions connected to the wiring elements in the second row. In particular, the conduction regions of adjacent wiring elements can have the same area value.

[0119] Preferably, the wiring elements in the second row can be offset relative to the wiring elements in the first row in a linear direction. In one embodiment, the offset of the equally spaced wiring elements in the second row relative to the equally spaced wiring elements in the first row in the linear direction is 1 / 2 of the mutual spacing between adjacent equally spaced wiring elements in the first row. In other embodiments, the offset of the equally spaced wiring elements in the second row relative to the equally spaced wiring elements in the first row in the linear direction is 1 / 3 of the mutual spacing between adjacent equally spaced wiring elements in the first row.

[0120] In an embodiment, the conduction region connected to a wiring element extends in such a way that it is spaced apart from the conduction region of the closest adjacent wiring element in another row by a distance that is at least 5% (e.g., at least 7.5%) of the value of the diameter of this wiring element. Additionally or alternatively, the conduction region connected to a wiring element extends in such a way that it is spaced apart from the conduction region connected to an adjacent wiring element in the same row by a distance that is at least 5% (e.g., at least 7.5%) of the diameter of this wiring element.

[0121] Preferably, the additional wiring element has a smaller size (especially a smaller diameter) relative to the size (especially the diameter) of the wiring element.

[0122] The sum of the cross-sectional metal areas of the additional wiring elements connected to the same conduction region can be equal to or greater than the cross-sectional metal area of the corresponding wiring element.

[0123] Preferably, the additional wiring element has the same pattern as the pattern of the wiring element, but is descaled.

[0124] In an embodiment, different distribution regions can be provided on the component carrier.

[0125] Using the above method, for example, a high-performance computing (HPC) substrate core can be designed. The power supply of the component carrier can be defined by the design of the wiring elements of the corresponding wiring plane.

[0126] Figure 1 A cross-sectional view of a component carrier 100 according to an exemplary embodiment of the present invention is shown. Figure 2 Shown according to Figure 1 A plan view of the wiring plane 162 of the component carrier 100.

[0127] The component carrier 100 can be an integrated circuit (IC) substrate or a printed circuit board (PCB). The component carrier 100 can include a laminated stack 102 that includes one or more electrically conductive layer structures 104 and one or more electrically insulating layer structures 106 in a core 122 (e.g., the core 122 can be a multi-layer core). For example, the one or more electrically conductive layer structures 104 can include a patterned metal layer (such as a patterned copper foil or a patterned deposited copper layer) and vertical vias, such as copper-filled vias, which can be created by drilling and plating. The one or more electrically insulating layer structures 106 can include corresponding resins (e.g., corresponding epoxy resins), preferably with reinforcing particles (such as glass fibers or glass spheres) included in the resins. For example, the one or more electrically insulating layer structures 106 can be made of FR4. The one or more electrically insulating layer structures 106 can also include resin layers that are free of glass (especially glass fibers).

[0128] As shown, a plurality of through-holes are formed in the central core 122 of the stack 102, e.g., by mechanical drilling. The through-holes in the core 122 can be partially or fully filled with an electrically conductive material such as copper, e.g., the through-holes in the core 122 can be partially or fully filled with an electrically conductive material such as copper by plating. A plurality of wiring elements 108 are disposed inside the central electrically insulating layer structure 106, and the plurality of wiring elements 108 form part of the central electrically conductive layer structure 104.

[0129] Also as Figure 1 shown, an upper stack 150 and a lower stack 152 are respectively formed on the top and bottom of the core 122. The stack 152 on the bottom side can be constructed in a similar manner to the stack 150 on the top side.

[0130] The upper stack 150 includes a plurality of additional electrically conductive layer structures 104' and a plurality of additional electrically insulating layer structures 106'. A plurality of additional wiring elements 108' are disposed inside the additional electrically insulating layer structures 106', and these additional wiring elements 108' form part of the additional electrically conductive layer structures 104'.

[0131] Correspondingly, the lower stack 152 includes a plurality of additional electrically conductive layer structures 104'' and electrically insulating layer structures 106''. A plurality of additional wiring elements 108'' are disposed inside the additional electrically insulating layer structures 106'', and these additional wiring elements 108'' form part of the additional electrically conductive layer structures 104''.

[0132] More specifically, a plurality of metal-filled laser vias are provided in each of the stacked members 150 and 152, thereby forming the additional wiring elements 108' and 108". Compared with the metal-filled mechanical drill vias that extend through the core 122 and form the wiring element 108, the additional wiring elements 108' and 108" have a higher density (i.e., a greater number of wiring elements per unit area or volume) and a smaller size. Preferably, the wiring element 108 has a cylindrical shape, and the additional wiring elements 108' and 108" have a frustum-conical shape.

[0133] By an attachment technique such as soldering, thermocompression bonding, hybrid bonding, wire bonding, adhesive bonding, or other intermetallic diffusion techniques, surface-mounted components 118 are mounted on top of the upper stacked member 150 and thus on the upper main surface of the stacked member 102. For example, the component 118 is a semiconductor chip or a semiconductor package, such as including at least one power semiconductor chip, a microprocessor, a central processing unit, a graphics processing unit, an artificial intelligence chip, and / or another electronic component having high electronic performance. The surface-mounted component 118 is connected to the stacked member 102 by a solder structure 154. A plurality of surface-mounted components 118 may also be mounted on the stacked member 102.

[0134] At the bottom of the stacked member 152 on the bottom side, the stacked member 102 is mounted on a mounting base component 160 such as a printed circuit board (PCB) by another solder structure 158, or the stacked member 102 is mounted into a socket by using grid array pads, and the socket is carried by a PCB, for example. The dimension of the another solder structure 158 in at least one direction may be greater than the corresponding dimension of the solder structure 154 in at least one direction.

[0135] Electric power and electrical signals can be guided through the core 122 and the stacked members 150, 152 and thus between the mounting base component 160 and the surface-mounted component 118. The electricity transmitted through the stacked member 102 and thus through the core 122 may include electric power and / or electrical signals. In addition, at least one reference potential (e.g., ground potential) may be provided at one or more wiring elements 108 that extend through the core 122.

[0136] As can be seen from the above description, the electrical interconnection and supply of the component carrier 100 can be very challenging, especially when a high current density (e.g., from 0.5 A / mm 2 to 15 A / mm 2This is especially true when the current density is high (e.g., at least 10 or even at least 50 I / O connections). In order to meet these challenging requirements in terms of electrical performance of the component carrier 100, the following reference may be made to Figure 2 The wiring elements 108, 108', 108" in any of the electrically insulating layer structures 106, 106', 106" can be modeled and designed in the manner described in the subsequent figures. In short, corresponding planar wiring layers can be defined, in particular, the wiring plane 162 extending through the core 122. In addition or alternatively, at least one other wiring plane can be designed, such as a wiring plane 164 in the upper stack 150 and / or a corresponding wiring plane 165 in the lower stack 152.

[0137] Hereinafter, the wiring plane 162 will be taken as an example to describe how to design the wiring element 108 of the wiring plane 162 according to an exemplary embodiment of the present invention. This will be explained for the wiring plane 162 of the core 122, wherein the wiring plane 164 in the upper stack 150 and / or the wiring plane 165 in the lower stack 152 can be designed accordingly.

[0138] Now refer to Figure 2 , showing a cross-sectional view through the wiring plane 162 Figure 1 In the cross section of FIG. 1 , the corresponding electrically conductive layer structure 104 comprises a plurality of wiring elements 108 . The wiring elements 108 are arranged in a wiring plane 162 and embedded in a dielectric matrix provided by the corresponding electrically insulating layer structure 106 .

[0139] like Figure 2 As shown in FIG. 1 , the first group of wiring elements 108 are arranged along a first row 110 of equidistant wiring elements 108, wherein the equidistant wiring elements 108 of the first row 110 are arranged along a straight line direction (according to FIG. 1 ) in the wiring plane 162. Figure 2 More specifically, the distances b between adjacent equally spaced wiring elements 108 in the first row 110 are the same. Figure 2 As shown in FIG. 1 , the second group of wiring elements 108 are arranged along the equally spaced wiring elements 108 of the second row 112, and the equally spaced wiring elements 108 of the second row 112 are arranged in the wiring plane 162 along the same straight line direction as the wiring elements 108 in the first row 110 (according to FIG. 1 ). Figure 2is arranged in the horizontal direction). More specifically, the mutual distance b between adjacent equally spaced wiring elements 108 in the second row 112 is the same for each. Thus, for the first row 110 and the second row 112, the distance or spacing b can be the same. Accordingly, the mutual distance b between adjacent equally spaced wiring elements 108 in the first row 110 is equal to the mutual distance b between adjacent equally spaced wiring elements 108 in the second row 112.

[0140] However, the equally spaced wiring elements 108 of the second row 112 are offset by an offset value f in a linear direction with respect to the wiring elements 108 in the first row 110. Descriptively, if the wiring elements 108 in the second row 112 are shifted by the offset value f in the horizontal linear direction, the wiring elements 108 will be aligned with the sequence of wiring elements 108 in the first row 110. Additionally, the offset value f of the equally spaced wiring elements 108 in the second row 112 with respect to the equally spaced wiring elements 108 in the first row 110 in the linear direction is 1 / 2 of the mutual spacing b between adjacent equally spaced wiring elements in the first row 110 or adjacent equally spaced wiring elements 108 in the second row 112.

[0141] Furthermore, the second row 112 is spaced apart by a dimension h from the first row 110 along another linear direction perpendicular to the horizontal linear direction. In Figure 2 this case, the said another linear direction extends vertically. In other words, the second row 112 can be aligned in a manner parallel to the first row 110.

[0142] In addition to the wiring elements 108 in the first row 110 and the wiring elements 108 in the second row 112, Figure 2 the wiring plane 162 also includes a third row 114 adjacent to the second row 112, and the wiring elements 108 of the third row 114 are arranged in the same manner as the first row 110. Additionally, a fourth row 116 is arranged adjacent to the third row 114, and the wiring elements 108 of the fourth row 116 are arranged in the same manner as the second row 112. Thus, equally spaced wiring elements 108 are arranged in a highly symmetric manner in the wiring plane 162.

[0143] Although only some of the wiring elements 108 in the first row 110, the second row 112, the third row 114, and the fourth row 116 are shown in Figure 2 this figure, the said sequence of wiring elements 108 can continue according to the above sorting scheme. Additionally, additional rows (not shown) can be provided.

[0144] Referring again to Figure 2, all the wiring elements 108 are arranged at the central part of the hexagonal virtual cells 126, and the wiring plane 162 can be virtually divided into the hexagonal virtual cells. As shown, each of the hexagonal virtual cells 126 in the hexagonal virtual cells is adjacent to each other, and there is no gap between the respective hexagonal virtual cells. Therefore, adjacent hexagonal virtual cells 126 share corresponding sides. Descriptively speaking, the entire wiring plane 162 can be subdivided into hexagonal virtual cells 126 arranged side by side, and there is no gap between the hexagonal virtual cells 126. Each of the hexagonal virtual cells 126 is defined by a regular hexagon having six angles β, where each angle is 120°. The hexagonal virtual cells 126 form a Voronoi diagram.

[0145] For example, the wiring elements 108 of the wiring plane 162 can be used to distribute electric power in the component carrier 100, more specifically in the core 122 of the component carrier 100. This electric power can be used to operate the surface-mounted components 118. For example, some of the wiring elements 108 can be used to distribute electrical signals in the component carrier 100. For example, the signals can be signals for driving the surface-mounted components 118 and / or signals provided by the surface-mounted components 118. Other wiring elements among the wiring elements 108 can be used to provide a reference potential, in particular a ground potential, in the component carrier. Other wiring elements among the wiring elements 108 can be used for heat dissipation. In order to correctly operate the surface-mounted electronic components 118, it may also be necessary to provide a ground potential or a return current path. In an embodiment, the wiring elements 108 for distributing electric power or signals or ground potential can be the wiring elements provided on the first row 110 or the second row 112 or the third row 114 or the fourth row 116. Other wiring elements with different functions among the wiring elements 108 can be provided on another one of the first row 110 or the second row 112 or the third row 114 or the fourth row 116.

[0146] When designing the component carrier 100, the wiring elements 108 can be arranged to conform to a predetermined specification, for example, a predetermined specification in terms of current-carrying capacity or ampere capacity. In this case, the above parameters (such as b, f, h) and / or other parameters and / or attributes (for example, the design of the virtual cells 126) can be appropriately selected to achieve a specification or requirement that conforms to at least one target attribute, function, or characteristic of the component carrier 100. For example, this can be done by computer fitting or manually.

[0147] In short, Figure 2 shows Figure 1A plan view of the wiring plane 162 shown therein. Each wiring plane 162, 164, 165... can be subdivided into a plurality of Voronoi cells, which are implemented herein as hexagonal virtual cells 126. As shown, the regular hexagonal virtual cell 126 has six sides, wherein the mutual angles between the six sides are 120°, and the regular hexagonal virtual cell 126 is in direct contact with adjacent cells. Therefore, no empty space or area is created between the regular hexagonal virtual cells 126. By virtually dividing each wiring plane 162, 164, 165 into virtual cells 126, the entire area or a partial area of each wiring plane 162, 164, 165 can be covered. The wiring elements 108, 108', 108” of the conduction layer structures 104, 104', 104” of each wiring plane 162, 164, 165 can all be arranged in the central part of the regular hexagonal virtual cell 126. By taking this measure, a regular pattern can be obtained, thereby allowing the minimum distance between adjacent wiring elements 108, 108', 108” to be maintained, which may be required for electrical safety purposes according to the specifications to be met. Through the arrangement in each row 110, 112, 114, 116 and through the mutual offset f between adjacent rows 110, 112, 114, 116, a highly symmetric pattern can be achieved, so that the electrical requirements of a specific application can be satisfied simultaneously. To optimize the design, the positions of the wiring elements 108, 108', 108” and / or the sizes and positions of the virtual cells 126 can be fitted to achieve a suitable or even optimal result. For example, the fitting parameters can be the length of the sides of the regular hexagonal virtual cell 126, the area of the wiring elements 108, 108', 108” in the corresponding wiring planes 162, 164, 165, the offset value f, etc.

[0148] Although not shown in Figure 1 it, a surface treatment part, such as a gold layer and / or a solder mask layer, can be provided.

[0149] In addition, in Figure 1In embodiments, one or more components may also be embedded in the stack 102, and in particular, one or more components may be embedded in the core 122. Thus, the patterned wirings 108, 108', 108'' may include at least one empty position or void. Even if the embedding is for strategic considerations to avoid interfering with the power distribution network of the wiring elements 108, 108', 108'', the embedded components may still be part of the power distribution network itself. Thus, there may be empty positions, especially in the linear arrangement of the vertical structure. Even if the embedding is for strategic considerations to avoid interfering with the power distribution network of the wiring elements 108, 108', 108'', the embedded components may still be part of the power distribution network itself. Thus, there may be empty positions, especially in the linear arrangement of the vertical structure.

[0150] Figure 3 A plan view of a wiring plane 162 of a component carrier 100 according to an exemplary embodiment of the present invention is shown. Figure 3 Auxiliary lines 166 extending from the respective wiring elements 108 to the corners 170 or sides 171 of the hexagonal virtual cells 126 are also shown. These parameters may also be design parameters for designing a component carrier 100 that meets predetermined target electrical characteristics.

[0151] Figure 4 A plan view of a wiring plane 162 of a component carrier 100 according to another exemplary embodiment of the present invention is shown.

[0152] In addition to the wiring elements 108 located in the central portions of the respective hexagonal virtual cells 126, Figure 4 An embodiment is also shown in which another part of the wiring elements 108 is arranged at the corners 170 of the hexagonal virtual cells 126. For example, a part of the wiring elements 108 arranged at the central portions of the hexagonal virtual cells 126 may provide a first electrical function (e.g., a power supply function), while another part of the wiring elements 108 arranged at the corners 170 of the hexagonal virtual cells 126 may provide a second electrical function different from the first electrical function (e.g., a signal transmission function).

[0153] In Figure 4 both the equally spaced wiring elements 108 of the first row 110 and the equally spaced wiring elements 108 of the second row 112 extend along the same horizontal straight line direction, but are also aligned with respect to another straight line direction perpendicular to the horizontal straight line direction. In Figure 4In the example of, rows 110 and 112 are defined by the following order of the wiring elements 108: the wiring element 108 from the first row 110, then the wiring element 108 from the second row 112, then the wiring element 108 from the first row 110, then the wiring element 108 from the second row 112, and so on. Therefore, in order to map the wiring element 108 in the second row 112 onto the wiring element 108 in the first row 110, it is sufficient to shift the wiring element 108 in the second row 112 relative to the wiring element 108 in the first row 110 by an offset value f in the direction of the horizontal line towards Figure 4 the left - hand side. In the illustrated embodiment, the wiring elements 108 located in the central part of the hexagonal virtual cell 126 may form the first row 110, and the wiring elements 108 located at the corners 170 of the hexagonal virtual cell 126 may form the second row 112. Here, the offset value f of the equally - spaced wiring elements 108 in the second row 112 relative to the equally - spaced wiring elements 108 in the first row 110 in the straight - line direction is 1 / 3 of the mutual pitch b between adjacent equally - spaced wiring elements 108 in the first row 110 or 1 / 3 of the mutual pitch b between adjacent equally - spaced wiring elements 108 in the second row 112.

[0154] As shown, the minimum distance between the wiring element 108 in the second row 112 and the wiring element 108 in the first row 110 (in the illustrated embodiment, this minimum distance is equal to the offset value f) is 1 / 3 of the mutual pitch b between adjacent equally - spaced wiring elements 108 in the first row 110 or 1 / 3 of the mutual pitch b between adjacent equally - spaced wiring elements 108 in the second row 112.

[0155] In Figure 4 , the second row 112 is aligned with the first row 110. The third row 114 and the fourth row 116 are also aligned with each other, but are spaced apart by an offset value h from the first row 110 and the second row 112 in the vertical straight - line direction.

[0156] The wiring elements 108 of the wiring plane 162 of Figure 4 can also be grouped into a plurality of wiring - element groups having different electrical functions (the plurality of wiring - element groups corresponding to the respective rows 110, 112, 114, 116). For example, Figure 4 the wiring elements 108 of the wiring plane 162 of

[0157] are assigned different voltage levels and / or different current - carrying capacities, as described above. Figure 4The wiring elements 108 therein are arranged not only in the central part of the hexagonal virtual cell 126 but also at the corners 170 of the hexagonal virtual cell 126. For example, the wiring element 108 located in the central part may have a first electrical function, while the wiring element 108 located at the corner 170 may have another second electrical function. For example, the wiring element 108 located in the central part and the wiring element 108 located in the corner 170 may have different potentials. It is also possible that the wiring element 108 located in the central part supplies power, while the wiring element 108 located in the corner 170 supplies a reference potential or a signal (or vice versa).

[0158] Figure 5 Fig. shows a sectional view of a part of the component carrier 100 according to an exemplary embodiment of the present invention. Figure 6 Fig. shows according to Figure 5 a plan view of a part of the wiring plane 162 of the component carrier 100.

[0159] Referring to Figure 5 , details of the connection part of the core 122 and the stacks 150, 152 are shown. In particular, the conduction regions 111 - the conduction regions 111 may also be referred to as lands or land pads - are provided for interconnecting the wiring elements 108, 108', 108". Figure 5 Also shown is the respective distance d between adjacent conduction regions 111 of the respective wiring planes (designated by reference numerals 162, 164, 165 in a similar manner to Figure 1 ).

[0160] Furthermore, the diameters of the wiring elements 108, 108', 108" are denoted by the reference numeral D1. As shown, the wiring element 108 having a vertical sidewall and a cylindrical design in the wiring plane 162 has a constant diameter D1 along the vertical extension direction of the wiring element 108. The additional and other wiring elements 108', 108" of the wiring planes 164, 165 have inclined sidewalls and a frustum - cone shape, and the minimum diameter of the additional and other wiring elements 108', 108" of the wiring planes 164, 165 is denoted as the diameter D1. Of course, the respective diameters D1 of the individual wiring elements 108, 108', 108" may be different. In particular, the diameter D1 of the wiring element 108 (the wiring element 108 may be a metal - filled mechanical drill - through via) may be greater than the diameter D1 of the additional / other wiring elements 108', 108" (the additional / other wiring elements 108', 108" may be metal - filled laser vias).

[0161] In addition, the diameter of the pad or conduction region 111 is shown by reference numeral D2. Different conduction regions 111 may have the same or different diameters D2.

[0162] As Figure 5 shown, the upper conduction region 111 of the wiring element 108 assigned to the Figure 5 right - hand side is connected to a plurality of additional wiring elements 108'. Thus, the additional wiring elements 108' can also be directly connected to the annular conduction region 111 in an efficient manner. In Figure 5 an embodiment, each of the other conduction regions 111 in the other conduction regions is connected to only a single assigned additional wiring element 108' or 108". More specifically, the lower conduction region 111 of the wiring element 108 assigned to the Figure 5 right - hand side is connected to a single other wiring element 108". In addition to this, the upper conduction region 111 of the wiring element 108 assigned to the Figure 5 left - hand side is connected to a single additional wiring element 108'. Further, the lower conduction region 111 of the wiring element 108 assigned to the Figure 5 left - hand side is also connected to only a single other wiring element 108".

[0163] Still referring to Figure 5 , the upper conduction regions 111 shown are coplanar and are provided with a lateral mutual spacing d. Correspondingly, the lower conduction regions 111 shown are also coplanar and are provided with a lateral mutual spacing d. The upper conduction regions 111 and the lower conduction regions 111 are vertically spaced from each other by a spacing corresponding to the length of the wiring element 108.

[0164] Now referring to Figure 6 , a plan view of the wiring elements 108 of a wiring plane (e.g., 162) arranged side - by - side is shown. In addition to the respective wiring elements 108, the corresponding pads or conduction regions 111 are also shown. The pads or conduction regions 111 may be circular or annular structures that extend laterally beyond the assigned wiring elements 108. Adjacent wiring elements 108 having pads or conduction regions 111 are spaced apart by a distance d. The diameter of each wiring element 108 is denoted as D1. The diameter of the corresponding pad or conduction region 111 is denoted as D2. Parameter values such as D1, D2, and d can be used as design parameters or fitting parameters for optimizing the electrical performance of the wiring plane 162.

[0165] When designing the component carrier 100, this may include: determining the spatial distribution of the wiring elements 108 and the pads or conduction areas 111, the pad diameter D2, the hole (in particular, drill hole) diameter D1, and the functional grouping of the wiring elements 108 that conforms to a predetermined specification (e.g., a design document). In other words, the specification may define the target characteristics of the component carrier 100 to be designed and subsequently manufactured. Then, the distribution of the wiring elements 108 including the pads or conduction areas 111, the parameters d, D1, and D2, and the grouping of the wiring elements 108 may be adjusted accordingly in order to provide a specific function (in particular, an electrical function) within the framework of the component carrier 100. The spacing d between adjacent pads or conduction areas 111 of adjacent wiring elements 108 may be an additional design parameter to be adjusted herein. In addition, the minimum distance Md and / or the pitch P for the virtual unit 126 of the hexagon may also be introduced during the determination process. The pitch P may define the center-to-center distance between adjacent wiring elements 108. Therefore, the above factors may be considered when defining the core drill hole settings. By performing the core drilling accordingly and at least partially filling the electroconductive material (e.g., metal) to form the wiring elements 108, the target ampacity of the component carrier 100 may be achieved, for example.

[0166] Refer to Figure 6 , the following formula is applied:

[0167] Md = 1 / 2D2 + d + D2 + d + 1 / 2D2

[0168] P = 1 / 2D2 + d + 1 / 2D2.

[0169] The resulting minimum geometry can be solved by modifying some of the same rules that control the pitch. For example, it can be solved by modifying the possibility of differentiating the diameter of the mechanically drilled through holes. Then, the final pitch can be modified to further achieve other significant changes, such as enlarging some holes relative to others. This may have a differential impact on the overall characteristics of the substrate.

[0170] According to a preferred embodiment, the component carrier 100 may be designed to have, for example, a configuration of the stack-up 102 according to Figure 1 or Figure 5 . For example, the corresponding wiring planes 162, 164, 165 may be configured according to the equidistant wiring elements 108, 108', 108” of the rows 110, 112..., where these equidistant wiring elements are offset or not offset from each other. For example, the wiring elements 108, 108', 108” may be arranged according to Figure 2 or Figure 4The Voronoi diagram is used. The wiring elements 108, 108', 108'' can be interconnected using the conduction regions 111, as shown, for example, Figure 5 or Figure 6 as shown in.

[0171] According to a particularly preferred design rule, each conduction region 111 in the conduction regions 111 of the respective electrical conduction layer structures 104, 104', 104'' connected to at least two wiring elements 108, 108', 108'' is spaced apart from the respective other conduction regions 111 connected to adjacent wiring elements 108, 108', 108'' by a distance d, such that the distance d is at least 5% (preferably at least 10%, for example not more than 30%) of the diameter D1 of the respective wiring elements 108, 108', 108''. In other words, the ratio between the distance d between adjacent pad-shaped conduction regions 111 at the same vertical height and the (in particular constant or minimum) diameter D1 of at least one connected wiring element 108, 108', 108'' of at least one wiring plane 162, 164, 165 should be at least 5%. In particular, the at least 5% ratio can be the ratio between the distance d between adjacent conduction regions 111 at the same vertical height and the diameter D1 of the wiring element 108 (in particular corresponding to a metal-filled mechanical drill-through via) of the wiring plane 162 (in particular the wiring plane 162 associated with the core 122) connected to one of the conduction regions 111. By this design rule, reliable electrical separation between different conduction regions 111 and the connected wiring elements 108, 108', 108'' can be ensured, even when conducting high-value currents. Therefore, high electrical reliability can be combined with high electrical performance.

[0172] Figure 7 shows components of a computer-based system 199 for defining the distribution of the wiring elements 108 for the component carrier 100 to be designed, and shows a table 197 that has parameters defining the structure and performance of the component carrier 100 according to an exemplary embodiment of the present invention. When designing the component carrier 100 according to Figure 7 the models, parameters, and properties in Figure 5 and Figure 6 can be considered. In particular, the above "at least 5% distance" design rule can be considered for designing and subsequent manufacturing of the component carrier 100.

[0173] Now refer more specifically to Figure 7, when designing the subsequent component carrier 100 to be manufactured, the distribution of the wiring elements 108 can be defined by the processor 113 according to specific requirements. The requirements can be associated with some of the parameter values in Table 197, and these parameter values can be stored in the database 119 (the database 119 can be implemented by a mass storage device such as a hard disk). The processor 113 can form a part of a computer (not shown), and the processor 113 can execute calculations for virtual design of the component carrier 100. In order to define the distribution of the wiring elements 108 for the component carrier design with the support of the processor 113, a suitable fitting algorithm can be executed. The fitting algorithm can change multiple degrees of freedom, but can keep the target current-related values such as the target ampacity of the designed component carrier 100 fixed. A set of predetermined parameters and fixed boundary conditions for fitting can be considered. In order to support the processor 113 during virtual design of the component carrier 100, the artificial intelligence module 115 (for example, the artificial intelligence module 115 can include a neural network) can be used to determine the distribution of the wiring elements 108 according to the above requirements. As shown, the computer-based system 199 can also include an input / output unit 121 (such as a user interface), and a human operator such as a design engineer can input the parameters to be considered for design or fitting through the input / output unit. In addition, the output parameters of the design or fitting can be output to the human operator through the input / output unit 121. When the design for the component carrier 100 has been defined according to one or more target current-related values (such as the target ampacity) and meets additional possible input definitions (such as the above-mentioned "at least 5%" design rule), the computer-based system 199 can output the correspondingly constructed design file 123, so as to summarize all the parameters required for manufacturing the component carrier 100. The design file 123 can be sent (especially after approval by the human operator) to the component carrier manufacturing device 125 to physically manufacture the component carrier 100 according to the exported design. Therefore, the component carrier 100 can be manufactured according to the design file 123 including the defined distribution of the wiring elements 108.

[0174] Figure 8 A plan view of the wiring element 108 showing details of the wiring plane 162 of the component carrier 100 according to an exemplary embodiment of the present invention is shown. Briefly, Figure 8 is shown in connection with Figure 6 a similar scenario, where Figure 8 a central wiring element 108 having a size larger than the size of the external wiring elements 108 is shown.

[0175] Figure 9A plan view of portions of overlapping wiring planes 162, 164 of a component carrier 100 according to an exemplary embodiment of the present invention is shown, thereby showing the density per unit area of the mechanically drilled vias 190 of the core 122 and the density per same unit area of the laser drilled vias 192 of the stack 150. Thus, Figure 9 a geometric comparison can be made between the mechanically drilled vias 190 and the laser vias, i.e., the laser drilled vias 192. Comparing the laser via dimensions with the dimensions of the plated vias in the core 122 of the substrate-type component carrier 100 shows significant differences. In the example shown, the diameter of the laser via pad is 60 μm. In contrast, in the example shown, the diameter of the pad of the plated mechanical via is 350 μm (relative to a 150 μm drill). As Figure 9 shown, there can be significant differences between the different geometries and even densities of the vertical metal structures within the substrate layer.

[0176] The entry point can be implemented with small features but carry lower current and higher voltage. The central part of the substrate (i.e., the core 122 of the substrate) can handle the conversion to lower voltage and higher current. In the upper section, the distribution or feeding of the current value to the semiconductor interconnects can be accomplished. This may involve concentrating the design into a specific area corresponding to the shadow area 120 of the semiconductor component 118 itself.

[0177] Figure 10 A plan view of the wiring plane 162 of the component carrier 100 according to an exemplary embodiment of the present invention is shown.

[0178] In Figure 10 the embodiment, the shadow area 120 of the surface-mounted component 118 is drawn. In this shadow area 120, for example, in the projection of the contour of the surface-mounted electronic component 118 in the stack 102, an appropriate wiring distribution may be particularly important because such a surface-mounted component 118 may have a large number of I / O pads with electrical functions that must be routed vertically through the stack 102. Thus, when the component 118 is surface-mounted on the stack 102, the wiring elements 108 having the above-described pattern can be arranged in the shadow area 120 of the surface-mounted component 118. Although not shown in Figure 10 the shadow area 120 can taper from inside the stack 102 towards the surface-mounted component 118.

[0179] Within the above-described shadow area 120, power voltage and ground potential can be provided. Thus, power supply can be achieved by performing optimized geometric calculations on the distribution and configuration of the wiring elements 108.

[0180] The distribution of the power characteristics required for a predetermined current transfer value can be accomplished by an analytical approach. Then, regions of interest in terms of power supply can be used to place the structures according to the concept of tessellation, e.g., thereby creating corresponding regions for each power structure. In Figure 11 the concept of creating Voronoi cells and positioning the power supply via mechanical drill vias as seeds for each Voronoi cell is shown:

[0181] Figure 11 A cross-sectional view of a component carrier 100 and a plan view of a wiring plane 162 of the component carrier 100 according to an exemplary embodiment of the invention are shown.

[0182] One can select Figure 11 the honeycomb structure of the virtual cells 126 for defining hexagons in

[0183] Figure 12 to determine the equalization structure of the intermediate layer in the core structure, thereby achieving a uniform contribution to the power delivery to the points determined to be closer to the load point, which is represented by the power connection of the surface-mounted component 118. The core structure can have at least one additional layer (e.g., made of prepreg), and the at least one additional layer can be used to more finely distribute (e.g., stack) the starting vertical structure of the laser vias. Figure 11 A plan view of another wiring plane 164 of the component carrier 100 according to

[0184] is shown. Another wiring plane 164 corresponds to the upper stack 150 and has a higher integration density than the integration density of the core 122. More specifically, the number of wiring elements 108' per unit area or volume in the upper stack 150 can be higher than the number of wiring elements 108 in the core 122. This may result in the size of the virtual cells 126 of the hexagons in the upper stack 150 being smaller than the size of the virtual cells 126 of the hexagons in the core 122. Figure 11 and Figure 12 it can be seen that the honeycomb tessellation structure can be scaled based on the available minimum geometry of the power supply structure. While according to Figure 11 the honeycomb tessellation structure is built into a part of the core 122, according to Figure 12 the honeycomb tessellation structure can also be (even partially) applied to the above-mentioned layers of the stack 150 and with a much smaller size (scaling).

[0185] Figure 13 is shown Figure 11 and Figure 12 a plan view of the overlay of the wiring planes 162, 164.

[0186] The sizing operation for determining the size of the Voronoi cells can be driven by the functional requirements of the specific structure of the component carrier to be designed. In the case of mechanical through-holes, there may be limitations imposed by the structural factors of the core, such as the overall aspect ratio between the drill diameter and the depth of the hole (the thickness of the drill). Technical implementations may be governed by the physical limitations of the steps required to achieve the desired result. In the case of mechanical through-holes, the final overall aspect ratio may limit the ability to plate the internal part of the vertical hole, thereby forming a conductive copper deposit on the walls of the hole. These limitations can be summarized in the design rules to be used in the design of the structure. Examples are the minimum distance between holes (pad-to-pad) or the minimum drill diameter that can be compatible with the overall thickness of the core. These geometries may determine other geometric dimensions, such as the maximum density (pitch) of the structure. The possible maximum density can be determined based on the individual capabilities of the individual structures to determine the maximum contribution of these structures.

[0187] Referring again to Figure 12 , the additional conductive layer structure 104' of the stack 102 includes a plurality of additional wiring elements 108', which are arranged in an additional plane 164 parallel to the wiring plane 162, and these additional wiring elements 108' have a pattern corresponding to the pattern of the conductive layer structure 104 of the wiring elements 108 having the first row 110 and the second row 112 of wiring elements 108, but having a wiring element density different from the wiring element density of the conductive layer structure 104 of the wiring elements 108 having the first row 110 and the second row 112 of wiring elements 108, as Figure 11 shown. The wiring plane 162 corresponds to a cross-section through the core 122, while the wiring plane 164 corresponds to a cross-section through the upper stack 150. Figure 11 and Figure 12 show the mosaic structure of the wafer shadow region 120. An influence region can be created for each power domain. Figure 11 and Figure 12 show that: the different wiring planes 162 and 164 can be subdivided into virtual cells 126 (or Voronoi cells having other geometries) that are hexagons with different cell sizes. The sizes of the hexagon virtual cells 126 in the different wiring planes 162 and 164 can reflect different integration densities in the different wiring planes 162 and 164 (e.g., different numbers of wiring elements 108 per unit area or volume). In the illustrated embodiment, the integration density of the wiring plane 162 is less than the integration density of the wiring plane 164. This may be due to redistribution layers or structures inside the stack 102.

[0188] Therefore, Figure 11 and Figure 12It is shown that the described mosaic structure is scalable. Thus, the described techniques can be adapted to specific power delivery objectives and available space.

[0189] Still referring to Figure 11 and Figure 12 , two different wiring planes 162 ( Figure 11 ) and 164 ( Figure 12 ) are shown. Figure 11 The wiring plane 162 in Figure 12 is associated with the core 122 and has a relatively small number of wiring elements 108 per unit area. In contrast, Figure 12 corresponds to a layer of the respective stack 150 (or 152) that has a larger number of wiring elements 108' (or 108”) per unit area or volume. According to a preferred embodiment, the combined arrangement of the wiring elements 108, 108' and pads (see

[0190] Figure 14 ) can be adjusted such that the wiring planes 162 and 164 can be electrically interconnected correctly. Figure 14 shows a plan view of a part of the wiring plane 162 of the component carrier 100 according to an exemplary embodiment of the present invention. In principle, Figure 6 shows a larger part of the wiring plane 162 in

[0191] Figure 15 shows a cross-sectional view of a part of the component carrier 100 according to an exemplary embodiment of the present invention. Figure 16 shows a plan view of a part of the wiring plane 162 of the component carrier 100 according to an exemplary embodiment of the present invention. Figure 15 The embodiment of Figure 5 differs from the embodiment of Figure 15 particularly in that, according to

[0192] , each conduction region in the conduction region 111 is only connected to a single assigned additional wiring element 108' or 108”. Figure 16 shows some possible combinations, where the redundancy of the reference structure (especially the ground structure) may be higher than that of the power supply structure and can be maintained at a smaller diameter, while making the diameter of the power supply structure larger. Thus, a larger conductor cross-section can be obtained with a small increment in pitch. The small increment in pitch allows maintaining or achieving the required density level within the design.

[0193] Figure 17 shows plan views of different wiring planes 162, 162' of the component carrier 100 according to an exemplary embodiment of the present invention.

[0194] Figure 17 The affected area 187 is shown. In addition, Figure 17 various types of wiring elements 108 in different wiring planes 162 and 162' are also shown, namely, the first type of wiring element 108A in the wiring plane 162 and the second type of wiring element 108B in the wiring plane 162'. In the example shown, the first type of wiring element 108A may be configured to provide a ground potential, while the second type of wiring element 108B may be configured to provide a power voltage. Each point in space is served by the second type of wiring element 108B corresponding to the power domain. More specifically, each second type of wiring element 108B that provides power is served by three first type of redundant wiring elements 108A (with a possibly smaller hole or drilling diameter) that provide an electrical reference or ground potential.

[0195] More generally, the determination method according to an exemplary embodiment of the present invention can link a wiring element in one wiring plane to multiple wiring elements in the next adjacent wiring plane.

[0196] Figure 17 The portions of the wiring planes 162, 162' denoted by the reference numeral 187 are highlighted. Such sub-portions can be subject to optimization, fitting, or adjustment.

[0197] In a double matrix, it may not be necessary to fill all vertices. If the requirement is to fill all vertices, some vertices can be reserved for use. On the other hand, a strategic tessellation structure can also be used to divide the distribution according to the mapping of the power domain. Empty vertices can provide positions for additional power domains.

[0198] The affected area 187 has an advantage in terms of placing and / or defining the starting point of the tessellation structure. The affected area 187 also geometrically defines a potential area for expanding the landing area for connecting laser vias to mechanical vias associated with the wiring elements 108 of the core 122, where the laser vias are placed into the prepreg layer (balancing layer) of the core 122. Figure 22 An enlarged view of the landing area is shown.

[0199] Figure 18 Shows related to Figure 17 A similar view shows additional conduction areas 111 around the wiring element 108. Figure 19 Shows Figure 18 Details of

[0200] Figure 20A plan view of a wiring plane 162 of a component carrier 100 according to an exemplary embodiment of the present invention is shown, with a second type of additional wiring element 108B added to the wiring plane 162. Figure 20 The inlay structure of the wafer shadow region 120 is again shown. In particular, Figure 20 It shows how to create an influence area for each power domain. As shown, a second type of additional wiring element 108B is added to the power distribution of the first type 108A of wiring elements.

[0201] Figure 20 It is again shown that when designing the component carrier 100, pads or conduction regions 111 connected to the corresponding wiring elements 108 can also be considered.

[0202] Figure 21 A plan view of a conventional wiring plane of a component carrier is shown.

[0203] Figure 21 It relates to power voltage and ground laser landing areas. For example, the area around the wiring element can be used for laser via landing.

[0204] The position (pitch and rules) of the mechanical drill through holes can solve the placement problem of the laser vias on the annular ring of the mechanical drill through holes. Thus, the position of the structure can reach the relevant semiconductor.

[0205] If one or more shadow regions of one or more semiconductor components are projected onto the core, the area in the core can promote the distribution of the feeding current through some design practices:

[0206] a) Divide the area into a uniform pattern of mechanical drill through holes.

[0207] b) Separate the positioning of the power laser vias in the stack layers from the positioning of the mechanical drill through holes for power supply in the core. This can be achieved by adding a prepreg layer in the core structure so as to feed directly through the vertical via stack as much as possible.

[0208] c) Use different drill diameters for the mechanical drill through holes for power supply compared with the mechanical drill through holes for transmitting signals and providing ground potential.

[0209] d) By using thick copper layers and redundant parallel connections of vertical structures in the core structure, allow sufficient redundancy to protect the power grid circuit from current transients.

[0210] e) Use stack layers assigned to power supply for a hybrid configuration and provide a ground potential to assist in the final delivery design.

[0211] The division of the shadow region can be carried out on the coordinate grid at the central part of the selected (and optional) mechanically drilled through - holes.

[0212] The dimensions of these coordinate grids can be adjusted based on the level of the target current density per required unit surface area (e.g., square millimeters).

[0213] Figure 21 A conventional method is shown, which randomly places structures without an exact pre - coordinated plan, resulting in random placement positions and no exact relationship between the incoming - structure current and the outgoing - structure current - carrying capacity. Figure 21 The enlarged view shows that when the equalization layer is missing in the structure of the core, the area available for the laser via to land on the top surface of the covered mechanical through - hole is limited.

[0214] versus Figure 21 the conventional method, the embodiments of the present invention described below enable the area available for the power laser via to land to be greatly extended and standardized by an equalization layer, which helps to place the laser via stack in the vertical direction to reach the bump pads of the semiconductor (see Figure 22 the reference numeral 154 in Figure 1 ).

[0215] Figure 22 A plan view shows different wiring planes 162, 162' of a component carrier 100 according to an exemplary embodiment of the present invention.

[0216] According to Figure 22 , the supply of the power voltage and the provision of the reference potential (e.g., ground potential) can be achieved by the inlaid cladding of the wiring element 108 in different wiring planes 162 and 162'. In the shown distribution scheme, the power laser vias on the top prepreg / bottom prepreg can be placed in any area of the illustrated solid regions to align with the stacked via stack.

[0217] Figure 22 A view shows the areas within the prepreg that have a higher probability of aligning with the required vertical stack of laser vias constructed in the stack layer, so as to directly reach the semiconductor bumps with an optimized structure and the best possible ampere capacity.

[0218] Figure 23 , Figure 24 and Figure 25Plan views of corresponding wiring planes 162 of a component carrier 100 according to exemplary embodiments of the present invention are shown. In all three embodiments, a matrix-like arrangement of wiring elements 108 is shown, thereby solving the problem of different current or signal transmission density levels between stacked layers according to defined product specifications and interface interconnection mappings.

[0219] Figure 26 Plan views of different wiring planes 162, 162' of a component carrier 100 according to exemplary embodiments of the present invention are shown. Figure 26 A distribution method of wiring elements 108 is shown, which may include: arranging the wiring elements 108 according to the hexagonal Voronoi cells 126 surrounding each wiring element 108 and by combining the grouped wiring elements 108 of adjacent hexagonal Voronoi cells 126 into quadrilateral blocks 124. The quadrilateral blocks 124 may be blocks of the parallelogram type. Figure 26 The arrangement conforms to the 10 A / mm 2 ampacity target. Figure 26 The coverage of the wafer shadow region 120 is shown.

[0220] Each point in space can be served by a power domain. Six hexagons (e.g., having a side length of 447 μm) are shown with their mechanically drilled through-holes (e.g., having a drilling diameter of 225 μm) and filled with an electrically conductive material. Copper paste can carry a current of about 10 A at an area of 1.192 mm 2 and a temperature difference state of 10 °C. The current density is shown by different geometric space tessellations per 1 mm 2 unit surface area.

[0221] Figure 27 A plan view of a wiring plane 162 of a component carrier 100 according to an exemplary embodiment of the present invention is shown. Figure 27 It is shown that different wiring elements 108 located at the central part, corners or other positions relative to the hexagonal virtual cells 126 may also have different sizes. The cross-sectional area of the wiring element 108 may affect, for example, the current-carrying capacity of the wiring element 108.

[0222] It should be noted that the term "comprising" does not exclude other elements or steps, and "a" or "an" does not exclude a plurality. Also, elements described in connection with different embodiments may be combined.

[0223] It should also be noted that the reference signs in the claims should not be construed as limiting the scope of the claims.

[0224] The implementation of the present invention is not limited to the preferred embodiments shown in the drawings and described above. On the contrary, even in the case of fundamentally different embodiments, it is possible to use the solutions shown and various variants based on the principles of the present invention.

Claims

1. A component carrier (100), the component carrier (100) comprising: A stack (102), the stack (102) comprising at least two electrically insulating layer structures (106, 106', 106”) and at least one electrically conductive layer structure (104, 104', 104”); A plurality of wiring elements (108), the plurality of wiring elements (108) being provided in one of the at least two electrically insulating layer structures (106), the plurality of wiring elements (108) being arranged in a wiring plane (162) to form: A first row (110) of equally spaced wiring elements (108), the first row (110) of equally spaced wiring elements (108) being arranged in a straight-line direction within the wiring plane (162); And A second row (112) of equally spaced wiring elements (108), the second row (112) of equally spaced wiring elements (108) being arranged in the straight-line direction within the wiring plane (162); A plurality of further wiring elements (108'), the plurality of further wiring elements (108') being provided in the other electrically insulating layer structure (106') of the at least two electrically insulating layer structures; Wherein the at least one electrically conductive layer structure (104, 104', 104”) comprises a plurality of conductive regions (111) electrically insulated from each other, each of the conductive regions (111) being connected to at least one of the plurality of wiring elements (108) and being connected to at least one of the plurality of further wiring elements (108'); and Wherein each of the conductive regions (111) of the at least one electrically conductive layer structure (104, 104', 104”) is spaced apart from a corresponding conductive region (111) connected to an adjacent wiring element (108, 108') by a distance (d), wherein the distance (d) is at least 5% of the diameter (D1) of the wiring elements (108, 108').

2. The component carrier (100) according to claim 1, wherein, The wiring elements (108) in the second row (112) are offset in the straight-line direction relative to the wiring elements (108) in the first row (110).

3. The component carrier (100) according to claim 2, wherein, The offset value (f) of the offset of the equally spaced wiring elements (108) in the second row (112) relative to the equally spaced wiring elements (108) in the first row (110) in the straight-line direction is 1 / 2 of the mutual spacing (b) between adjacent equally spaced wiring elements (108) in the first row (110).

4. The component carrier (100) according to claim 2, wherein, The offset value (f) of the offset of the equally spaced wiring elements (108) in the second row (112) relative to the equally spaced wiring elements (108) in the first row (110) in the straight-line direction is 1 / 3 of the mutual spacing (b) between adjacent equally spaced wiring elements (108) in the first row (110).

5. The component carrier (100) according to any one of claims 1 to 4, wherein, At least some of the wiring elements (108) are arranged at the central part of the hexagonal virtual cells (126) of the wiring plane (162). Each of the hexagonal virtual cells (126) is adjacent to each other and shares the corresponding sides of the corresponding hexagons with the corresponding adjacent hexagons.

6. The component carrier (100) according to any one of claims 1 to 5, wherein, The wiring elements (108) are arranged such that the mutual distance (b) between adjacent equally spaced wiring elements (108) in the first row (110) is equal to the mutual distance (b) between adjacent equally spaced wiring elements (108) in the second row (112).

7. The component carrier (100) according to any one of claims 1 to 6, wherein, A plurality of the additional wiring elements (108') are arranged in an additional wiring plane (164) parallel to the wiring plane (162), and the plurality of the additional wiring elements (108') are arranged according to a wiring element pattern corresponding to the wiring elements (108) of the first row (110) and the wiring elements (108) of the second row (112) but with a wiring element density different from that of the wiring elements (108) of the first row (110) and the wiring elements (108) of the second row (112).

8. The component carrier (100) according to any one of claims 1 to 7, wherein, The wiring elements (108) and the additional wiring elements (108') are arranged in the shadow region (120) of the component (118), and the component (118) is surface-mounted on the stack (102) of the component carrier (100).

9. The component carrier (100) according to any one of claims 1 to 8, wherein, The wiring elements (108) are arranged in the core (122) of the component carrier (100).

10. The component carrier (100) according to any one of claims 1 to 9, wherein, The additional wiring elements (108') are arranged in a stack (150) located on the core (122) of the component carrier (100).

11. The component carrier (100) according to any one of claims 1 to 10, wherein, The wiring elements (108) are at least partially metal-filled mechanical drill holes, and the additional wiring elements (108') are at least partially metal-filled laser drill holes.

12. The component carrier (100) according to any one of claims 1 to 11, wherein, At least a part of the conduction regions (111) are pads.

13. The component carrier (100) according to any one of claims 1 to 12, wherein, At least a part of the conduction regions (111) have a planar annular shape surrounding the corresponding one of the wiring elements (108).

14. The component carrier (100) according to any one of claims 1 to 13, wherein, At least a part of the conduction regions (111) are circular and are coaxially aligned with the axis of the corresponding wiring element (108).

15. The component carrier (100) according to claim 14, wherein, The corresponding circular conduction regions (111) have a diameter (D2) such that the distance (d) between the circumference of the conduction region (111) and the circumference of the conduction region (111) connected to the adjacent wiring elements (108, 108') is at least 5% of the value of the diameter (D1) of the corresponding wiring elements (108, 108').

16. The component carrier (100) according to any one of claims 1 to 15, the component carrier (100) comprising at least one of the following features: The adjacent wiring elements (108) of the electrically insulating layer structure (106) have different cross-sectional areas; Adjacent wiring elements (108) of the electrical insulation layer structure (106) have the same cross-sectional area; Adjacent additional wiring elements (108') of the other electrical insulation layer structure (106') have different cross-sectional areas; Adjacent additional wiring elements (108') of the other electrical insulation layer structure (106') have the same cross-sectional area; The additional wiring elements (108') connected to the corresponding conduction regions (111) have the same cross-sectional area as the additional wiring elements (108') connected to the conduction regions (111) connected to adjacent wiring elements (108); The additional wiring elements (108') connected to the corresponding conduction regions (111) have different cross-sectional areas from the additional wiring elements (108') connected to the conduction regions (111) connected to adjacent wiring elements (108); 17. The component carrier (100) according to any one of claims 1 to 16, wherein, At least one conduction region in the conduction regions (111) is electrically connected to at least two of the additional wiring elements (108'); 18. The component carrier (100) according to any one of claims 1 to 17, wherein, At least one conduction region in the conduction regions (111) is connected to only one of the wiring elements (108); 19. The component carrier (100) according to any one of claims 1 to 18, wherein, The number of additional wiring elements (108') connected to the corresponding conduction regions (111) connected to the wiring elements (108) in the first row (110) is higher than the number of additional wiring elements (108') connected to the corresponding conduction regions (111) connected to the wiring elements (108) in the second row (112); 20. The component carrier (100) according to any one of claims 1 to 19, wherein, The number of additional wiring elements (108') connected to the larger conduction regions (111) is higher than the number of additional wiring elements (108') connected to the smaller conduction regions (111); 21. The component carrier (100) according to any one of claims 1 to 20, wherein, The number of additional wiring elements (108') connected to the corresponding conduction regions (111) connected to the wiring elements (108) in the first row (110) is the same as the number of additional wiring elements (108') connected to the corresponding conduction regions (111) connected to the wiring elements (108) in the second row (112), particularly where The conduction regions (111) have the same area value.

22. The component carrier (100) according to any one of claims 1 to 21, wherein, One conduction region in the conduction regions (111) of a row (110, 112) is arranged such that it is spaced apart from another conduction region connected to the closest adjacent wiring element (108) in the other row (110, 112) of the conduction regions (111) by a distance that is at least 5% of the diameter (D1) of the wiring element (108); 23. The component carrier (100) according to any one of claims 1 to 22, wherein, One conduction region in the conduction regions (111) of a row (110, 112) is arranged such that it is spaced apart from another conduction region connected to an adjacent wiring element (108) in the same row (110, 112) of the conduction regions (111) by a distance that is at least 5% of the diameter (D1) of the wiring element (108); 24. The component carrier (100) according to any one of claims 1 to 23, wherein, Compared to the larger dimensions of the wiring element (108), the additional wiring element (108') has smaller dimensions. In particular, compared to the larger diameter (D1) of the wiring element (108), the additional wiring element (108') has a smaller diameter (D1).

25. The component carrier (100) according to any one of claims 1 to 24, wherein, The sum of the cross-sectional areas of the additional wiring elements (108') connected to the same conduction region (111) is equal to or greater than the cross-sectional area of the wiring elements (108) connected to the same conduction region (111).

26. The component carrier (100) according to any one of claims 1 to 25, wherein, Different regions of the component carrier (100) have different distributions of the wiring elements (108, 108').

27. The component carrier (100) according to any one of claims 1 to 26, The component carrier (100) includes a plurality of other wiring elements (108''), and the plurality of other wiring elements (108'') are disposed in another electrical insulation layer structure (106'') among the at least two electrical insulation layer structures and on a side of the electrical insulation layer structure (106) opposite to the other electrical insulation layer structure (106'). Among them, Some conduction regions (111) are connected to at least one of the plurality of wiring elements (108) and are connected to at least one of the plurality of other wiring elements (108''). And wherein each of the some conduction regions (111) is spaced apart from a corresponding conduction region (111) connected to an adjacent wiring element (108) by a distance (d), and the distance (d) is at least 5% of the diameter (D1) of the wiring element (108).

28. A method of manufacturing a component carrier (100), wherein, The method includes: providing a stack (102) including at least two electrical insulation layer structures (106, 106', 106'') and at least one electrical conduction layer structure (104, 104', 104''); forming a plurality of wiring elements (108) in one of the at least two electrical insulation layer structures (106), and the plurality of wiring elements (108) are arranged in a wiring plane (162) to form: a first row (110) of equally spaced wiring elements (108), and the first row (110) of equally spaced wiring elements (108) is arranged in a straight-line direction within the wiring plane (162); and a second row (112) of equally spaced wiring elements (108), and the second row (112) of equally spaced wiring elements (108) is arranged in the straight-line direction within the wiring plane (162); forming a plurality of additional wiring elements (108') in another electrical insulation layer structure (106') among the at least two electrical insulation layer structures; Form the at least one electroconductive layer structure (104, 104', 104'') to include a plurality of conductive regions (111) that are electrically insulated from each other, each of the conductive regions (111) being connected to at least one of the plurality of wiring elements (108) and to at least one of the plurality of additional wiring elements (108'); and Form each of the conductive regions (111) of the at least one electroconductive layer structure (104, 104', 104'') to be spaced apart by a distance (d) from a corresponding conductive region (111) connected to an adjacent wiring element (108, 108'), where the distance (d) is at least 5% of the diameter (D1) of the wiring element (108, 108').

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